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5fafdf24 | 1 | /* |
e69954b9 PB |
2 | * ARM RealView Baseboard System emulation. |
3 | * | |
a1bb27b1 | 4 | * Copyright (c) 2006-2007 CodeSourcery. |
e69954b9 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
e69954b9 PB |
8 | */ |
9 | ||
2e9bdce5 | 10 | #include "sysbus.h" |
87ecb68b PB |
11 | #include "arm-misc.h" |
12 | #include "primecell.h" | |
13 | #include "devices.h" | |
14 | #include "pci.h" | |
18e08a55 | 15 | #include "usb-ohci.h" |
87ecb68b PB |
16 | #include "net.h" |
17 | #include "sysemu.h" | |
18 | #include "boards.h" | |
eee48504 | 19 | #include "bitbang_i2c.h" |
2446333c | 20 | #include "blockdev.h" |
35e87820 | 21 | #include "exec-memory.h" |
e69954b9 | 22 | |
0ef849d7 | 23 | #define SMP_BOOT_ADDR 0xe0000000 |
078758d0 | 24 | #define SMP_BOOTREG_ADDR 0x10000030 |
eee48504 PB |
25 | |
26 | typedef struct { | |
27 | SysBusDevice busdev; | |
35e87820 | 28 | MemoryRegion iomem; |
eee48504 PB |
29 | bitbang_i2c_interface *bitbang; |
30 | int out; | |
31 | int in; | |
32 | } RealViewI2CState; | |
33 | ||
35e87820 AK |
34 | static uint64_t realview_i2c_read(void *opaque, target_phys_addr_t offset, |
35 | unsigned size) | |
eee48504 PB |
36 | { |
37 | RealViewI2CState *s = (RealViewI2CState *)opaque; | |
38 | ||
39 | if (offset == 0) { | |
40 | return (s->out & 1) | (s->in << 1); | |
41 | } else { | |
42 | hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset); | |
43 | return -1; | |
44 | } | |
45 | } | |
46 | ||
47 | static void realview_i2c_write(void *opaque, target_phys_addr_t offset, | |
35e87820 | 48 | uint64_t value, unsigned size) |
eee48504 PB |
49 | { |
50 | RealViewI2CState *s = (RealViewI2CState *)opaque; | |
51 | ||
52 | switch (offset) { | |
53 | case 0: | |
54 | s->out |= value & 3; | |
55 | break; | |
56 | case 4: | |
57 | s->out &= ~value; | |
58 | break; | |
59 | default: | |
60 | hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset); | |
61 | } | |
62 | bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0); | |
63 | s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0); | |
64 | } | |
65 | ||
35e87820 AK |
66 | static const MemoryRegionOps realview_i2c_ops = { |
67 | .read = realview_i2c_read, | |
68 | .write = realview_i2c_write, | |
69 | .endianness = DEVICE_NATIVE_ENDIAN, | |
eee48504 PB |
70 | }; |
71 | ||
72 | static int realview_i2c_init(SysBusDevice *dev) | |
73 | { | |
74 | RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev); | |
75 | i2c_bus *bus; | |
eee48504 PB |
76 | |
77 | bus = i2c_init_bus(&dev->qdev, "i2c"); | |
78 | s->bitbang = bitbang_i2c_init(bus); | |
35e87820 AK |
79 | memory_region_init_io(&s->iomem, &realview_i2c_ops, s, |
80 | "realview-i2c", 0x1000); | |
750ecd44 | 81 | sysbus_init_mmio(dev, &s->iomem); |
eee48504 PB |
82 | return 0; |
83 | } | |
84 | ||
999e12bb AL |
85 | static void realview_i2c_class_init(ObjectClass *klass, void *data) |
86 | { | |
87 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
88 | ||
89 | k->init = realview_i2c_init; | |
90 | } | |
91 | ||
39bffca2 AL |
92 | static TypeInfo realview_i2c_info = { |
93 | .name = "realview_i2c", | |
94 | .parent = TYPE_SYS_BUS_DEVICE, | |
95 | .instance_size = sizeof(RealViewI2CState), | |
96 | .class_init = realview_i2c_class_init, | |
eee48504 PB |
97 | }; |
98 | ||
83f7d43a | 99 | static void realview_register_types(void) |
eee48504 | 100 | { |
39bffca2 | 101 | type_register_static(&realview_i2c_info); |
eee48504 PB |
102 | } |
103 | ||
e69954b9 PB |
104 | /* Board init. */ |
105 | ||
f93eb9ff | 106 | static struct arm_boot_info realview_binfo = { |
0ef849d7 | 107 | .smp_loader_start = SMP_BOOT_ADDR, |
078758d0 | 108 | .smp_bootreg_addr = SMP_BOOTREG_ADDR, |
f93eb9ff AZ |
109 | }; |
110 | ||
f7c70325 | 111 | /* The following two lists must be consistent. */ |
c988bfad PB |
112 | enum realview_board_type { |
113 | BOARD_EB, | |
0ef849d7 | 114 | BOARD_EB_MPCORE, |
f7c70325 PB |
115 | BOARD_PB_A8, |
116 | BOARD_PBX_A9, | |
117 | }; | |
118 | ||
d05ac8fa | 119 | static const int realview_board_id[] = { |
f7c70325 PB |
120 | 0x33b, |
121 | 0x33b, | |
122 | 0x769, | |
123 | 0x76d | |
c988bfad PB |
124 | }; |
125 | ||
c227f099 | 126 | static void realview_init(ram_addr_t ram_size, |
3023f332 | 127 | const char *boot_device, |
e69954b9 | 128 | const char *kernel_filename, const char *kernel_cmdline, |
c988bfad PB |
129 | const char *initrd_filename, const char *cpu_model, |
130 | enum realview_board_type board_type) | |
e69954b9 | 131 | { |
c988bfad | 132 | CPUState *env = NULL; |
35e87820 AK |
133 | MemoryRegion *sysmem = get_system_memory(); |
134 | MemoryRegion *ram_lo = g_new(MemoryRegion, 1); | |
135 | MemoryRegion *ram_hi = g_new(MemoryRegion, 1); | |
136 | MemoryRegion *ram_alias = g_new(MemoryRegion, 1); | |
137 | MemoryRegion *ram_hack = g_new(MemoryRegion, 1); | |
03a0e944 | 138 | DeviceState *dev, *sysctl, *gpio2, *pl041; |
c988bfad | 139 | SysBusDevice *busdev; |
fe7e8758 PB |
140 | qemu_irq *irqp; |
141 | qemu_irq pic[64]; | |
26883c69 | 142 | qemu_irq mmc_irq[2]; |
e69954b9 PB |
143 | PCIBus *pci_bus; |
144 | NICInfo *nd; | |
eee48504 | 145 | i2c_bus *i2c; |
e69954b9 | 146 | int n; |
0ef849d7 | 147 | int done_nic = 0; |
9ee6e8bb | 148 | qemu_irq cpu_irq[4]; |
f7c70325 PB |
149 | int is_mpcore = 0; |
150 | int is_pb = 0; | |
26e92f65 | 151 | uint32_t proc_id = 0; |
0ef849d7 PB |
152 | uint32_t sys_id; |
153 | ram_addr_t low_ram_size; | |
e69954b9 | 154 | |
f7c70325 PB |
155 | switch (board_type) { |
156 | case BOARD_EB: | |
157 | break; | |
158 | case BOARD_EB_MPCORE: | |
159 | is_mpcore = 1; | |
160 | break; | |
161 | case BOARD_PB_A8: | |
162 | is_pb = 1; | |
163 | break; | |
164 | case BOARD_PBX_A9: | |
165 | is_mpcore = 1; | |
166 | is_pb = 1; | |
167 | break; | |
168 | } | |
c988bfad | 169 | for (n = 0; n < smp_cpus; n++) { |
9ee6e8bb PB |
170 | env = cpu_init(cpu_model); |
171 | if (!env) { | |
172 | fprintf(stderr, "Unable to find CPU definition\n"); | |
173 | exit(1); | |
174 | } | |
fe7e8758 PB |
175 | irqp = arm_pic_init_cpu(env); |
176 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; | |
aaed909a | 177 | } |
26e92f65 | 178 | if (arm_feature(env, ARM_FEATURE_V7)) { |
f7c70325 PB |
179 | if (is_mpcore) { |
180 | proc_id = 0x0c000000; | |
181 | } else { | |
182 | proc_id = 0x0e000000; | |
183 | } | |
26e92f65 PB |
184 | } else if (arm_feature(env, ARM_FEATURE_V6K)) { |
185 | proc_id = 0x06000000; | |
186 | } else if (arm_feature(env, ARM_FEATURE_V6)) { | |
187 | proc_id = 0x04000000; | |
188 | } else { | |
189 | proc_id = 0x02000000; | |
190 | } | |
aaed909a | 191 | |
21a88941 PB |
192 | if (is_pb && ram_size > 0x20000000) { |
193 | /* Core tile RAM. */ | |
194 | low_ram_size = ram_size - 0x20000000; | |
195 | ram_size = 0x20000000; | |
c5705a77 AK |
196 | memory_region_init_ram(ram_lo, "realview.lowmem", low_ram_size); |
197 | vmstate_register_ram_global(ram_lo); | |
35e87820 | 198 | memory_region_add_subregion(sysmem, 0x20000000, ram_lo); |
21a88941 PB |
199 | } |
200 | ||
c5705a77 AK |
201 | memory_region_init_ram(ram_hi, "realview.highmem", ram_size); |
202 | vmstate_register_ram_global(ram_hi); | |
0ef849d7 PB |
203 | low_ram_size = ram_size; |
204 | if (low_ram_size > 0x10000000) | |
205 | low_ram_size = 0x10000000; | |
e69954b9 | 206 | /* SDRAM at address zero. */ |
35e87820 AK |
207 | memory_region_init_alias(ram_alias, "realview.alias", |
208 | ram_hi, 0, low_ram_size); | |
209 | memory_region_add_subregion(sysmem, 0, ram_alias); | |
0ef849d7 PB |
210 | if (is_pb) { |
211 | /* And again at a high address. */ | |
35e87820 | 212 | memory_region_add_subregion(sysmem, 0x70000000, ram_hi); |
0ef849d7 PB |
213 | } else { |
214 | ram_size = low_ram_size; | |
215 | } | |
e69954b9 | 216 | |
0ef849d7 | 217 | sys_id = is_pb ? 0x01780500 : 0xc1400400; |
26883c69 PM |
218 | sysctl = qdev_create(NULL, "realview_sysctl"); |
219 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); | |
26883c69 | 220 | qdev_prop_set_uint32(sysctl, "proc_id", proc_id); |
7a65c8cc | 221 | qdev_init_nofail(sysctl); |
26883c69 | 222 | sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000); |
9ee6e8bb | 223 | |
c988bfad | 224 | if (is_mpcore) { |
96eacf64 | 225 | target_phys_addr_t periphbase; |
f7c70325 | 226 | dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore"); |
c988bfad PB |
227 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); |
228 | qdev_init_nofail(dev); | |
229 | busdev = sysbus_from_qdev(dev); | |
f7c70325 | 230 | if (is_pb) { |
96eacf64 | 231 | periphbase = 0x1f000000; |
f7c70325 | 232 | } else { |
96eacf64 | 233 | periphbase = 0x10100000; |
f7c70325 | 234 | } |
96eacf64 | 235 | sysbus_mmio_map(busdev, 0, periphbase); |
c988bfad PB |
236 | for (n = 0; n < smp_cpus; n++) { |
237 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
238 | } | |
96eacf64 PM |
239 | sysbus_create_varargs("l2x0", periphbase + 0x2000, NULL); |
240 | /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ | |
241 | realview_binfo.gic_cpu_if_addr = periphbase + 0x100; | |
9ee6e8bb | 242 | } else { |
0ef849d7 PB |
243 | uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; |
244 | /* For now just create the nIRQ GIC, and ignore the others. */ | |
245 | dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]); | |
fe7e8758 PB |
246 | } |
247 | for (n = 0; n < 64; n++) { | |
067a3ddc | 248 | pic[n] = qdev_get_gpio_in(dev, n); |
9ee6e8bb PB |
249 | } |
250 | ||
03a0e944 PM |
251 | pl041 = qdev_create(NULL, "pl041"); |
252 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); | |
253 | qdev_init_nofail(pl041); | |
254 | sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000); | |
255 | sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[19]); | |
256 | ||
86394e96 PB |
257 | sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); |
258 | sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); | |
e69954b9 | 259 | |
a7d518a6 PB |
260 | sysbus_create_simple("pl011", 0x10009000, pic[12]); |
261 | sysbus_create_simple("pl011", 0x1000a000, pic[13]); | |
262 | sysbus_create_simple("pl011", 0x1000b000, pic[14]); | |
263 | sysbus_create_simple("pl011", 0x1000c000, pic[15]); | |
e69954b9 PB |
264 | |
265 | /* DMA controller is optional, apparently. */ | |
b4496b13 | 266 | sysbus_create_simple("pl081", 0x10030000, pic[24]); |
e69954b9 | 267 | |
6a824ec3 PB |
268 | sysbus_create_simple("sp804", 0x10011000, pic[4]); |
269 | sysbus_create_simple("sp804", 0x10012000, pic[5]); | |
e69954b9 | 270 | |
26883c69 PM |
271 | sysbus_create_simple("pl061", 0x10013000, pic[6]); |
272 | sysbus_create_simple("pl061", 0x10014000, pic[7]); | |
273 | gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]); | |
274 | ||
acb9b722 | 275 | sysbus_create_simple("pl111", 0x10020000, pic[23]); |
e69954b9 | 276 | |
26883c69 PM |
277 | dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL); |
278 | /* Wire up MMC card detect and read-only signals. These have | |
279 | * to go to both the PL061 GPIO and the sysctl register. | |
280 | * Note that the PL181 orders these lines (readonly,inserted) | |
281 | * and the PL061 has them the other way about. Also the card | |
282 | * detect line is inverted. | |
283 | */ | |
284 | mmc_irq[0] = qemu_irq_split( | |
285 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), | |
286 | qdev_get_gpio_in(gpio2, 1)); | |
287 | mmc_irq[1] = qemu_irq_split( | |
288 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), | |
289 | qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); | |
290 | qdev_connect_gpio_out(dev, 0, mmc_irq[0]); | |
291 | qdev_connect_gpio_out(dev, 1, mmc_irq[1]); | |
a1bb27b1 | 292 | |
a63bdb31 | 293 | sysbus_create_simple("pl031", 0x10017000, pic[10]); |
7e1543c2 | 294 | |
0ef849d7 | 295 | if (!is_pb) { |
7d6e771f PM |
296 | dev = qdev_create(NULL, "realview_pci"); |
297 | busdev = sysbus_from_qdev(dev); | |
298 | qdev_init_nofail(dev); | |
299 | sysbus_mmio_map(busdev, 0, 0x61000000); /* PCI self-config */ | |
300 | sysbus_mmio_map(busdev, 1, 0x62000000); /* PCI config */ | |
301 | sysbus_mmio_map(busdev, 2, 0x63000000); /* PCI I/O */ | |
302 | sysbus_connect_irq(busdev, 0, pic[48]); | |
303 | sysbus_connect_irq(busdev, 1, pic[49]); | |
304 | sysbus_connect_irq(busdev, 2, pic[50]); | |
305 | sysbus_connect_irq(busdev, 3, pic[51]); | |
0ef849d7 PB |
306 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); |
307 | if (usb_enabled) { | |
a67ba3b6 | 308 | usb_ohci_init_pci(pci_bus, -1); |
0ef849d7 PB |
309 | } |
310 | n = drive_get_max_bus(IF_SCSI); | |
311 | while (n >= 0) { | |
312 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
313 | n--; | |
314 | } | |
e69954b9 PB |
315 | } |
316 | for(n = 0; n < nb_nics; n++) { | |
317 | nd = &nd_table[n]; | |
0ae18cee | 318 | |
e6b3c8ca PM |
319 | if (!done_nic && (!nd->model || |
320 | strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) { | |
0ef849d7 PB |
321 | if (is_pb) { |
322 | lan9118_init(nd, 0x4e000000, pic[28]); | |
323 | } else { | |
324 | smc91c111_init(nd, 0x4e000000, pic[28]); | |
325 | } | |
326 | done_nic = 1; | |
e69954b9 | 327 | } else { |
07caea31 | 328 | pci_nic_init_nofail(nd, "rtl8139", NULL); |
e69954b9 PB |
329 | } |
330 | } | |
331 | ||
eee48504 PB |
332 | dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL); |
333 | i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c"); | |
334 | i2c_create_slave(i2c, "ds1338", 0x68); | |
335 | ||
e69954b9 PB |
336 | /* Memory map for RealView Emulation Baseboard: */ |
337 | /* 0x10000000 System registers. */ | |
338 | /* 0x10001000 System controller. */ | |
eee48504 | 339 | /* 0x10002000 Two-Wire Serial Bus. */ |
e69954b9 PB |
340 | /* 0x10003000 Reserved. */ |
341 | /* 0x10004000 AACI. */ | |
342 | /* 0x10005000 MCI. */ | |
343 | /* 0x10006000 KMI0. */ | |
344 | /* 0x10007000 KMI1. */ | |
0ef849d7 | 345 | /* 0x10008000 Character LCD. (EB) */ |
e69954b9 PB |
346 | /* 0x10009000 UART0. */ |
347 | /* 0x1000a000 UART1. */ | |
348 | /* 0x1000b000 UART2. */ | |
349 | /* 0x1000c000 UART3. */ | |
350 | /* 0x1000d000 SSPI. */ | |
351 | /* 0x1000e000 SCI. */ | |
352 | /* 0x1000f000 Reserved. */ | |
353 | /* 0x10010000 Watchdog. */ | |
354 | /* 0x10011000 Timer 0+1. */ | |
355 | /* 0x10012000 Timer 2+3. */ | |
356 | /* 0x10013000 GPIO 0. */ | |
357 | /* 0x10014000 GPIO 1. */ | |
358 | /* 0x10015000 GPIO 2. */ | |
0ef849d7 | 359 | /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ |
7e1543c2 | 360 | /* 0x10017000 RTC. */ |
e69954b9 PB |
361 | /* 0x10018000 DMC. */ |
362 | /* 0x10019000 PCI controller config. */ | |
363 | /* 0x10020000 CLCD. */ | |
364 | /* 0x10030000 DMA Controller. */ | |
0ef849d7 PB |
365 | /* 0x10040000 GIC1. (EB) */ |
366 | /* 0x10050000 GIC2. (EB) */ | |
367 | /* 0x10060000 GIC3. (EB) */ | |
368 | /* 0x10070000 GIC4. (EB) */ | |
e69954b9 | 369 | /* 0x10080000 SMC. */ |
0ef849d7 PB |
370 | /* 0x1e000000 GIC1. (PB) */ |
371 | /* 0x1e001000 GIC2. (PB) */ | |
372 | /* 0x1e002000 GIC3. (PB) */ | |
373 | /* 0x1e003000 GIC4. (PB) */ | |
e69954b9 PB |
374 | /* 0x40000000 NOR flash. */ |
375 | /* 0x44000000 DoC flash. */ | |
376 | /* 0x48000000 SRAM. */ | |
377 | /* 0x4c000000 Configuration flash. */ | |
378 | /* 0x4e000000 Ethernet. */ | |
379 | /* 0x4f000000 USB. */ | |
380 | /* 0x50000000 PISMO. */ | |
381 | /* 0x54000000 PISMO. */ | |
382 | /* 0x58000000 PISMO. */ | |
383 | /* 0x5c000000 PISMO. */ | |
384 | /* 0x60000000 PCI. */ | |
385 | /* 0x61000000 PCI Self Config. */ | |
386 | /* 0x62000000 PCI Config. */ | |
387 | /* 0x63000000 PCI IO. */ | |
388 | /* 0x64000000 PCI mem 0. */ | |
389 | /* 0x68000000 PCI mem 1. */ | |
390 | /* 0x6c000000 PCI mem 2. */ | |
391 | ||
7ffab4d7 PB |
392 | /* ??? Hack to map an additional page of ram for the secondary CPU |
393 | startup code. I guess this works on real hardware because the | |
394 | BootROM happens to be in ROM/flash or in memory that isn't clobbered | |
395 | until after Linux boots the secondary CPUs. */ | |
c5705a77 AK |
396 | memory_region_init_ram(ram_hack, "realview.hack", 0x1000); |
397 | vmstate_register_ram_global(ram_hack); | |
35e87820 | 398 | memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); |
7ffab4d7 | 399 | |
f93eb9ff AZ |
400 | realview_binfo.ram_size = ram_size; |
401 | realview_binfo.kernel_filename = kernel_filename; | |
402 | realview_binfo.kernel_cmdline = kernel_cmdline; | |
403 | realview_binfo.initrd_filename = initrd_filename; | |
c988bfad | 404 | realview_binfo.nb_cpus = smp_cpus; |
f7c70325 | 405 | realview_binfo.board_id = realview_board_id[board_type]; |
21a88941 | 406 | realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); |
f93eb9ff | 407 | arm_load_kernel(first_cpu, &realview_binfo); |
e69954b9 PB |
408 | } |
409 | ||
c988bfad PB |
410 | static void realview_eb_init(ram_addr_t ram_size, |
411 | const char *boot_device, | |
412 | const char *kernel_filename, const char *kernel_cmdline, | |
413 | const char *initrd_filename, const char *cpu_model) | |
414 | { | |
415 | if (!cpu_model) { | |
416 | cpu_model = "arm926"; | |
417 | } | |
418 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
419 | initrd_filename, cpu_model, BOARD_EB); | |
420 | } | |
421 | ||
422 | static void realview_eb_mpcore_init(ram_addr_t ram_size, | |
423 | const char *boot_device, | |
424 | const char *kernel_filename, const char *kernel_cmdline, | |
425 | const char *initrd_filename, const char *cpu_model) | |
426 | { | |
427 | if (!cpu_model) { | |
428 | cpu_model = "arm11mpcore"; | |
429 | } | |
430 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
431 | initrd_filename, cpu_model, BOARD_EB_MPCORE); | |
432 | } | |
433 | ||
0ef849d7 PB |
434 | static void realview_pb_a8_init(ram_addr_t ram_size, |
435 | const char *boot_device, | |
436 | const char *kernel_filename, const char *kernel_cmdline, | |
437 | const char *initrd_filename, const char *cpu_model) | |
438 | { | |
439 | if (!cpu_model) { | |
440 | cpu_model = "cortex-a8"; | |
441 | } | |
442 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
443 | initrd_filename, cpu_model, BOARD_PB_A8); | |
444 | } | |
445 | ||
f7c70325 PB |
446 | static void realview_pbx_a9_init(ram_addr_t ram_size, |
447 | const char *boot_device, | |
448 | const char *kernel_filename, const char *kernel_cmdline, | |
449 | const char *initrd_filename, const char *cpu_model) | |
450 | { | |
451 | if (!cpu_model) { | |
452 | cpu_model = "cortex-a9"; | |
453 | } | |
454 | realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, | |
455 | initrd_filename, cpu_model, BOARD_PBX_A9); | |
456 | } | |
457 | ||
c988bfad PB |
458 | static QEMUMachine realview_eb_machine = { |
459 | .name = "realview-eb", | |
c9b1ae2c | 460 | .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", |
c988bfad PB |
461 | .init = realview_eb_init, |
462 | .use_scsi = 1, | |
463 | }; | |
464 | ||
465 | static QEMUMachine realview_eb_mpcore_machine = { | |
466 | .name = "realview-eb-mpcore", | |
467 | .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)", | |
468 | .init = realview_eb_mpcore_init, | |
c9b1ae2c | 469 | .use_scsi = 1, |
c988bfad | 470 | .max_cpus = 4, |
e69954b9 | 471 | }; |
f80f9ec9 | 472 | |
0ef849d7 PB |
473 | static QEMUMachine realview_pb_a8_machine = { |
474 | .name = "realview-pb-a8", | |
475 | .desc = "ARM RealView Platform Baseboard for Cortex-A8", | |
476 | .init = realview_pb_a8_init, | |
f7c70325 PB |
477 | }; |
478 | ||
479 | static QEMUMachine realview_pbx_a9_machine = { | |
480 | .name = "realview-pbx-a9", | |
481 | .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9", | |
482 | .init = realview_pbx_a9_init, | |
0ef849d7 | 483 | .use_scsi = 1, |
f7c70325 | 484 | .max_cpus = 4, |
0ef849d7 PB |
485 | }; |
486 | ||
f80f9ec9 AL |
487 | static void realview_machine_init(void) |
488 | { | |
c988bfad PB |
489 | qemu_register_machine(&realview_eb_machine); |
490 | qemu_register_machine(&realview_eb_mpcore_machine); | |
0ef849d7 | 491 | qemu_register_machine(&realview_pb_a8_machine); |
f7c70325 | 492 | qemu_register_machine(&realview_pbx_a9_machine); |
f80f9ec9 AL |
493 | } |
494 | ||
495 | machine_init(realview_machine_init); | |
83f7d43a | 496 | type_init(realview_register_types) |