[mirror_qemu.git] / hw / remote / proxy.c

/*
 * Copyright © 2018, 2021 Oracle and/or its affiliates.
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 *
 */

#include "qemu/osdep.h"
#include "qemu-common.h"

#include "hw/remote/proxy.h"
#include "hw/pci/pci.h"
#include "qapi/error.h"
#include "io/channel-util.h"
#include "hw/qdev-properties.h"
#include "monitor/monitor.h"
#include "migration/blocker.h"
#include "qemu/sockets.h"
#include "hw/remote/mpqemu-link.h"
#include "qemu/error-report.h"
#include "hw/remote/proxy-memory-listener.h"
#include "qom/object.h"
#include "qemu/event_notifier.h"
#include "sysemu/kvm.h"
#include "util/event_notifier-posix.c"

static void probe_pci_info(PCIDevice *dev, Error **errp);
static void proxy_device_reset(DeviceState *dev);

static void proxy_intx_update(PCIDevice *pci_dev)
{
    PCIProxyDev *dev = PCI_PROXY_DEV(pci_dev);
    PCIINTxRoute route;
    int pin = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;

    if (dev->virq != -1) {
        kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq);
        dev->virq = -1;
    }

    route = pci_device_route_intx_to_irq(pci_dev, pin);

    dev->virq = route.irq;

    if (dev->virq != -1) {
        kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &dev->intr,
                                           &dev->resample, dev->virq);
    }
}

static void setup_irqfd(PCIProxyDev *dev)
{
    PCIDevice *pci_dev = PCI_DEVICE(dev);
    MPQemuMsg msg;
    Error *local_err = NULL;

    event_notifier_init(&dev->intr, 0);
    event_notifier_init(&dev->resample, 0);

    memset(&msg, 0, sizeof(MPQemuMsg));
    msg.cmd = MPQEMU_CMD_SET_IRQFD;
    msg.num_fds = 2;
    msg.fds[0] = event_notifier_get_fd(&dev->intr);
    msg.fds[1] = event_notifier_get_fd(&dev->resample);
    msg.size = 0;

    if (!mpqemu_msg_send(&msg, dev->ioc, &local_err)) {
        error_report_err(local_err);
    }

    dev->virq = -1;

    proxy_intx_update(pci_dev);

    pci_device_set_intx_routing_notifier(pci_dev, proxy_intx_update);
}

static void pci_proxy_dev_realize(PCIDevice *device, Error **errp)
{
    ERRP_GUARD();
    PCIProxyDev *dev = PCI_PROXY_DEV(device);
    uint8_t *pci_conf = device->config;
    int fd;

    if (!dev->fd) {
        error_setg(errp, "fd parameter not specified for %s",
                   DEVICE(device)->id);
        return;
    }

    fd = monitor_fd_param(monitor_cur(), dev->fd, errp);
    if (fd == -1) {
        error_prepend(errp, "proxy: unable to parse fd %s: ", dev->fd);
        return;
    }

    if (!fd_is_socket(fd)) {
        error_setg(errp, "proxy: fd %d is not a socket", fd);
        close(fd);
        return;
    }

    dev->ioc = qio_channel_new_fd(fd, errp);

    error_setg(&dev->migration_blocker, "%s does not support migration",
               TYPE_PCI_PROXY_DEV);
    migrate_add_blocker(dev->migration_blocker, errp);

    qemu_mutex_init(&dev->io_mutex);
    qio_channel_set_blocking(dev->ioc, true, NULL);

    pci_conf[PCI_LATENCY_TIMER] = 0xff;
    pci_conf[PCI_INTERRUPT_PIN] = 0x01;

    proxy_memory_listener_configure(&dev->proxy_listener, dev->ioc);

    setup_irqfd(dev);

    probe_pci_info(PCI_DEVICE(dev), errp);
}

static void pci_proxy_dev_exit(PCIDevice *pdev)
{
    PCIProxyDev *dev = PCI_PROXY_DEV(pdev);

    if (dev->ioc) {
        qio_channel_close(dev->ioc, NULL);
    }

    migrate_del_blocker(dev->migration_blocker);

    error_free(dev->migration_blocker);

    proxy_memory_listener_deconfigure(&dev->proxy_listener);

    event_notifier_cleanup(&dev->intr);
    event_notifier_cleanup(&dev->resample);
}

static void config_op_send(PCIProxyDev *pdev, uint32_t addr, uint32_t *val,
                           int len, unsigned int op)
{
    MPQemuMsg msg = { 0 };
    uint64_t ret = -EINVAL;
    Error *local_err = NULL;

    msg.cmd = op;
    msg.data.pci_conf_data.addr = addr;
    msg.data.pci_conf_data.val = (op == MPQEMU_CMD_PCI_CFGWRITE) ? *val : 0;
    msg.data.pci_conf_data.len = len;
    msg.size = sizeof(PciConfDataMsg);

    ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
    if (local_err) {
        error_report_err(local_err);
    }

    if (ret == UINT64_MAX) {
        error_report("Failed to perform PCI config %s operation",
                     (op == MPQEMU_CMD_PCI_CFGREAD) ? "READ" : "WRITE");
    }

    if (op == MPQEMU_CMD_PCI_CFGREAD) {
        *val = (uint32_t)ret;
    }
}

static uint32_t pci_proxy_read_config(PCIDevice *d, uint32_t addr, int len)
{
    uint32_t val;

    config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGREAD);

    return val;
}

static void pci_proxy_write_config(PCIDevice *d, uint32_t addr, uint32_t val,
                                   int len)
{
    /*
     * Some of the functions access the copy of remote device's PCI config
     * space which is cached in the proxy device. Therefore, maintain
     * it updated.
     */
    pci_default_write_config(d, addr, val, len);

    config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGWRITE);
}

static Property proxy_properties[] = {
    DEFINE_PROP_STRING("fd", PCIProxyDev, fd),
    DEFINE_PROP_END_OF_LIST(),
};

static void pci_proxy_dev_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->realize = pci_proxy_dev_realize;
    k->exit = pci_proxy_dev_exit;
    k->config_read = pci_proxy_read_config;
    k->config_write = pci_proxy_write_config;

    dc->reset = proxy_device_reset;

    device_class_set_props(dc, proxy_properties);
}

static const TypeInfo pci_proxy_dev_type_info = {
    .name          = TYPE_PCI_PROXY_DEV,
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIProxyDev),
    .class_init    = pci_proxy_dev_class_init,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static void pci_proxy_dev_register_types(void)
{
    type_register_static(&pci_proxy_dev_type_info);
}

type_init(pci_proxy_dev_register_types)

static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr,
                                bool write, hwaddr addr, uint64_t *val,
                                unsigned size, bool memory)
{
    MPQemuMsg msg = { 0 };
    long ret = -EINVAL;
    Error *local_err = NULL;

    msg.size = sizeof(BarAccessMsg);
    msg.data.bar_access.addr = mr->addr + addr;
    msg.data.bar_access.size = size;
    msg.data.bar_access.memory = memory;

    if (write) {
        msg.cmd = MPQEMU_CMD_BAR_WRITE;
        msg.data.bar_access.val = *val;
    } else {
        msg.cmd = MPQEMU_CMD_BAR_READ;
    }

    ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
    if (local_err) {
        error_report_err(local_err);
    }

    if (!write) {
        *val = ret;
    }
}

static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val,
                            unsigned size)
{
    ProxyMemoryRegion *pmr = opaque;

    send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size,
                        pmr->memory);
}

static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size)
{
    ProxyMemoryRegion *pmr = opaque;
    uint64_t val;

    send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size,
                        pmr->memory);

    return val;
}

const MemoryRegionOps proxy_mr_ops = {
    .read = proxy_bar_read,
    .write = proxy_bar_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .impl = {
        .min_access_size = 1,
        .max_access_size = 8,
    },
};

static void probe_pci_info(PCIDevice *dev, Error **errp)
{
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
    uint32_t orig_val, new_val, base_class, val;
    PCIProxyDev *pdev = PCI_PROXY_DEV(dev);
    DeviceClass *dc = DEVICE_CLASS(pc);
    uint8_t type;
    int i, size;

    config_op_send(pdev, PCI_VENDOR_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
    pc->vendor_id = (uint16_t)val;

    config_op_send(pdev, PCI_DEVICE_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
    pc->device_id = (uint16_t)val;

    config_op_send(pdev, PCI_CLASS_DEVICE, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
    pc->class_id = (uint16_t)val;

    config_op_send(pdev, PCI_SUBSYSTEM_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
    pc->subsystem_id = (uint16_t)val;

    base_class = pc->class_id >> 4;
    switch (base_class) {
    case PCI_BASE_CLASS_BRIDGE:
        set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
        break;
    case PCI_BASE_CLASS_STORAGE:
        set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
        break;
    case PCI_BASE_CLASS_NETWORK:
        set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
        break;
    case PCI_BASE_CLASS_INPUT:
        set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
        break;
    case PCI_BASE_CLASS_DISPLAY:
        set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
        break;
    case PCI_BASE_CLASS_PROCESSOR:
        set_bit(DEVICE_CATEGORY_CPU, dc->categories);
        break;
    default:
        set_bit(DEVICE_CATEGORY_MISC, dc->categories);
        break;
    }

    for (i = 0; i < PCI_NUM_REGIONS; i++) {
        config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
                       MPQEMU_CMD_PCI_CFGREAD);
        new_val = 0xffffffff;
        config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
                       MPQEMU_CMD_PCI_CFGWRITE);
        config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
                       MPQEMU_CMD_PCI_CFGREAD);
        size = (~(new_val & 0xFFFFFFF0)) + 1;
        config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
                       MPQEMU_CMD_PCI_CFGWRITE);
        type = (new_val & 0x1) ?
                   PCI_BASE_ADDRESS_SPACE_IO : PCI_BASE_ADDRESS_SPACE_MEMORY;

        if (size) {
            g_autofree char *name;
            pdev->region[i].dev = pdev;
            pdev->region[i].present = true;
            if (type == PCI_BASE_ADDRESS_SPACE_MEMORY) {
                pdev->region[i].memory = true;
            }
            name = g_strdup_printf("bar-region-%d", i);
            memory_region_init_io(&pdev->region[i].mr, OBJECT(pdev),
                                  &proxy_mr_ops, &pdev->region[i],
                                  name, size);
            pci_register_bar(dev, i, type, &pdev->region[i].mr);
        }
    }
}

static void proxy_device_reset(DeviceState *dev)
{
    PCIProxyDev *pdev = PCI_PROXY_DEV(dev);
    MPQemuMsg msg = { 0 };
    Error *local_err = NULL;

    msg.cmd = MPQEMU_CMD_DEVICE_RESET;
    msg.size = 0;

    mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
    if (local_err) {
        error_report_err(local_err);
    }

}
Commit	Line	Data
9f811207 EU	1	/*
	2	* Copyright © 2018, 2021 Oracle and/or its affiliates.
	3	*
	4	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*
	7	*/
	8
	9	#include "qemu/osdep.h"
	10	#include "qemu-common.h"
	11
	12	#include "hw/remote/proxy.h"
	13	#include "hw/pci/pci.h"
	14	#include "qapi/error.h"
	15	#include "io/channel-util.h"
	16	#include "hw/qdev-properties.h"
	17	#include "monitor/monitor.h"
	18	#include "migration/blocker.h"
	19	#include "qemu/sockets.h"
11ab8725 EU	20	#include "hw/remote/mpqemu-link.h"
11ab8725 EU	21	#include "qemu/error-report.h"
c746b74a JR	22	#include "hw/remote/proxy-memory-listener.h"
c746b74a JR	23	#include "qom/object.h"
bd36adb8 JR	24	#include "qemu/event_notifier.h"
	25	#include "sysemu/kvm.h"
	26	#include "util/event_notifier-posix.c"
	27
1bec145c	28	static void probe_pci_info(PCIDevice dev, Error *errp);
b6cc02d9	29	static void proxy_device_reset(DeviceState *dev);
1bec145c	30
bd36adb8 JR	31	static void proxy_intx_update(PCIDevice *pci_dev)
	32	{
	33	PCIProxyDev *dev = PCI_PROXY_DEV(pci_dev);
	34	PCIINTxRoute route;
	35	int pin = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
	36
	37	if (dev->virq != -1) {
	38	kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq);
	39	dev->virq = -1;
	40	}
	41
	42	route = pci_device_route_intx_to_irq(pci_dev, pin);
	43
	44	dev->virq = route.irq;
	45
	46	if (dev->virq != -1) {
	47	kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &dev->intr,
	48	&dev->resample, dev->virq);
	49	}
	50	}
	51
	52	static void setup_irqfd(PCIProxyDev *dev)
	53	{
	54	PCIDevice *pci_dev = PCI_DEVICE(dev);
	55	MPQemuMsg msg;
	56	Error *local_err = NULL;
	57
	58	event_notifier_init(&dev->intr, 0);
	59	event_notifier_init(&dev->resample, 0);
	60
	61	memset(&msg, 0, sizeof(MPQemuMsg));
	62	msg.cmd = MPQEMU_CMD_SET_IRQFD;
	63	msg.num_fds = 2;
	64	msg.fds[0] = event_notifier_get_fd(&dev->intr);
	65	msg.fds[1] = event_notifier_get_fd(&dev->resample);
	66	msg.size = 0;
	67
	68	if (!mpqemu_msg_send(&msg, dev->ioc, &local_err)) {
	69	error_report_err(local_err);
	70	}
	71
	72	dev->virq = -1;
	73
	74	proxy_intx_update(pci_dev);
	75
	76	pci_device_set_intx_routing_notifier(pci_dev, proxy_intx_update);
	77	}
9f811207 EU	78
	79	static void pci_proxy_dev_realize(PCIDevice device, Error *errp)
	80	{
	81	ERRP_GUARD();
	82	PCIProxyDev *dev = PCI_PROXY_DEV(device);
1bec145c	83	uint8_t *pci_conf = device->config;
9f811207 EU	84	int fd;
	85
	86	if (!dev->fd) {
	87	error_setg(errp, "fd parameter not specified for %s",
	88	DEVICE(device)->id);
	89	return;
	90	}
	91
	92	fd = monitor_fd_param(monitor_cur(), dev->fd, errp);
	93	if (fd == -1) {
	94	error_prepend(errp, "proxy: unable to parse fd %s: ", dev->fd);
	95	return;
	96	}
	97
	98	if (!fd_is_socket(fd)) {
	99	error_setg(errp, "proxy: fd %d is not a socket", fd);
	100	close(fd);
	101	return;
	102	}
	103
	104	dev->ioc = qio_channel_new_fd(fd, errp);
	105
	106	error_setg(&dev->migration_blocker, "%s does not support migration",
	107	TYPE_PCI_PROXY_DEV);
	108	migrate_add_blocker(dev->migration_blocker, errp);
	109
	110	qemu_mutex_init(&dev->io_mutex);
	111	qio_channel_set_blocking(dev->ioc, true, NULL);
c746b74a	112
1bec145c JR	113	pci_conf[PCI_LATENCY_TIMER] = 0xff;
	114	pci_conf[PCI_INTERRUPT_PIN] = 0x01;
	115
c746b74a	116	proxy_memory_listener_configure(&dev->proxy_listener, dev->ioc);
bd36adb8 JR	117
bd36adb8 JR	118	setup_irqfd(dev);
1bec145c JR	119
1bec145c JR	120	probe_pci_info(PCI_DEVICE(dev), errp);
9f811207 EU	121	}
	122
	123	static void pci_proxy_dev_exit(PCIDevice *pdev)
	124	{
	125	PCIProxyDev *dev = PCI_PROXY_DEV(pdev);
	126
	127	if (dev->ioc) {
	128	qio_channel_close(dev->ioc, NULL);
	129	}
	130
	131	migrate_del_blocker(dev->migration_blocker);
	132
	133	error_free(dev->migration_blocker);
c746b74a JR	134
c746b74a JR	135	proxy_memory_listener_deconfigure(&dev->proxy_listener);
bd36adb8 JR	136
	137	event_notifier_cleanup(&dev->intr);
	138	event_notifier_cleanup(&dev->resample);
9f811207 EU	139	}
9f811207 EU	140
11ab8725 EU	141	static void config_op_send(PCIProxyDev pdev, uint32_t addr, uint32_t val,
	142	int len, unsigned int op)
	143	{
	144	MPQemuMsg msg = { 0 };
	145	uint64_t ret = -EINVAL;
	146	Error *local_err = NULL;
	147
	148	msg.cmd = op;
	149	msg.data.pci_conf_data.addr = addr;
	150	msg.data.pci_conf_data.val = (op == MPQEMU_CMD_PCI_CFGWRITE) ? *val : 0;
	151	msg.data.pci_conf_data.len = len;
	152	msg.size = sizeof(PciConfDataMsg);
	153
	154	ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
	155	if (local_err) {
	156	error_report_err(local_err);
	157	}
	158
	159	if (ret == UINT64_MAX) {
	160	error_report("Failed to perform PCI config %s operation",
	161	(op == MPQEMU_CMD_PCI_CFGREAD) ? "READ" : "WRITE");
	162	}
	163
	164	if (op == MPQEMU_CMD_PCI_CFGREAD) {
	165	*val = (uint32_t)ret;
	166	}
	167	}
	168
	169	static uint32_t pci_proxy_read_config(PCIDevice *d, uint32_t addr, int len)
	170	{
	171	uint32_t val;
	172
	173	config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGREAD);
	174
	175	return val;
	176	}
	177
	178	static void pci_proxy_write_config(PCIDevice *d, uint32_t addr, uint32_t val,
	179	int len)
	180	{
	181	/*
	182	* Some of the functions access the copy of remote device's PCI config
	183	* space which is cached in the proxy device. Therefore, maintain
	184	* it updated.
	185	*/
	186	pci_default_write_config(d, addr, val, len);
	187
	188	config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGWRITE);
	189	}
	190
9f811207 EU	191	static Property proxy_properties[] = {
	192	DEFINE_PROP_STRING("fd", PCIProxyDev, fd),
	193	DEFINE_PROP_END_OF_LIST(),
	194	};
	195
	196	static void pci_proxy_dev_class_init(ObjectClass klass, void data)
	197	{
	198	DeviceClass *dc = DEVICE_CLASS(klass);
	199	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	200
	201	k->realize = pci_proxy_dev_realize;
	202	k->exit = pci_proxy_dev_exit;
11ab8725 EU	203	k->config_read = pci_proxy_read_config;
	204	k->config_write = pci_proxy_write_config;
	205
b6cc02d9 EU	206	dc->reset = proxy_device_reset;
b6cc02d9 EU	207
9f811207 EU	208	device_class_set_props(dc, proxy_properties);
	209	}
	210
	211	static const TypeInfo pci_proxy_dev_type_info = {
	212	.name = TYPE_PCI_PROXY_DEV,
	213	.parent = TYPE_PCI_DEVICE,
	214	.instance_size = sizeof(PCIProxyDev),
	215	.class_init = pci_proxy_dev_class_init,
	216	.interfaces = (InterfaceInfo[]) {
	217	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	218	{ },
	219	},
	220	};
	221
	222	static void pci_proxy_dev_register_types(void)
	223	{
	224	type_register_static(&pci_proxy_dev_type_info);
	225	}
	226
	227	type_init(pci_proxy_dev_register_types)
7ee3f823 JR	228
	229	static void send_bar_access_msg(PCIProxyDev pdev, MemoryRegion mr,
	230	bool write, hwaddr addr, uint64_t *val,
	231	unsigned size, bool memory)
	232	{
	233	MPQemuMsg msg = { 0 };
	234	long ret = -EINVAL;
	235	Error *local_err = NULL;
	236
	237	msg.size = sizeof(BarAccessMsg);
	238	msg.data.bar_access.addr = mr->addr + addr;
	239	msg.data.bar_access.size = size;
	240	msg.data.bar_access.memory = memory;
	241
	242	if (write) {
	243	msg.cmd = MPQEMU_CMD_BAR_WRITE;
	244	msg.data.bar_access.val = *val;
	245	} else {
	246	msg.cmd = MPQEMU_CMD_BAR_READ;
	247	}
	248
	249	ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
	250	if (local_err) {
	251	error_report_err(local_err);
	252	}
	253
	254	if (!write) {
	255	*val = ret;
	256	}
	257	}
	258
	259	static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val,
	260	unsigned size)
	261	{
	262	ProxyMemoryRegion *pmr = opaque;
	263
	264	send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size,
	265	pmr->memory);
	266	}
	267
	268	static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size)
	269	{
	270	ProxyMemoryRegion *pmr = opaque;
	271	uint64_t val;
	272
	273	send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size,
	274	pmr->memory);
	275
	276	return val;
	277	}
	278
	279	const MemoryRegionOps proxy_mr_ops = {
	280	.read = proxy_bar_read,
	281	.write = proxy_bar_write,
	282	.endianness = DEVICE_NATIVE_ENDIAN,
	283	.impl = {
	284	.min_access_size = 1,
	285	.max_access_size = 8,
	286	},
	287	};
1bec145c JR	288
	289	static void probe_pci_info(PCIDevice dev, Error *errp)
	290	{
	291	PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
	292	uint32_t orig_val, new_val, base_class, val;
	293	PCIProxyDev *pdev = PCI_PROXY_DEV(dev);
	294	DeviceClass *dc = DEVICE_CLASS(pc);
	295	uint8_t type;
	296	int i, size;
	297
	298	config_op_send(pdev, PCI_VENDOR_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
	299	pc->vendor_id = (uint16_t)val;
	300
	301	config_op_send(pdev, PCI_DEVICE_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
	302	pc->device_id = (uint16_t)val;
	303
	304	config_op_send(pdev, PCI_CLASS_DEVICE, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
	305	pc->class_id = (uint16_t)val;
	306
	307	config_op_send(pdev, PCI_SUBSYSTEM_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
	308	pc->subsystem_id = (uint16_t)val;
	309
	310	base_class = pc->class_id >> 4;
	311	switch (base_class) {
	312	case PCI_BASE_CLASS_BRIDGE:
	313	set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
	314	break;
	315	case PCI_BASE_CLASS_STORAGE:
	316	set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
	317	break;
	318	case PCI_BASE_CLASS_NETWORK:
	319	set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
	320	break;
	321	case PCI_BASE_CLASS_INPUT:
	322	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
	323	break;
	324	case PCI_BASE_CLASS_DISPLAY:
	325	set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
	326	break;
	327	case PCI_BASE_CLASS_PROCESSOR:
	328	set_bit(DEVICE_CATEGORY_CPU, dc->categories);
	329	break;
	330	default:
	331	set_bit(DEVICE_CATEGORY_MISC, dc->categories);
	332	break;
	333	}
	334
	335	for (i = 0; i < PCI_NUM_REGIONS; i++) {
	336	config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
	337	MPQEMU_CMD_PCI_CFGREAD);
	338	new_val = 0xffffffff;
	339	config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
	340	MPQEMU_CMD_PCI_CFGWRITE);
	341	config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
	342	MPQEMU_CMD_PCI_CFGREAD);
	343	size = (~(new_val & 0xFFFFFFF0)) + 1;
	344	config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
	345	MPQEMU_CMD_PCI_CFGWRITE);
	346	type = (new_val & 0x1) ?
	347	PCI_BASE_ADDRESS_SPACE_IO : PCI_BASE_ADDRESS_SPACE_MEMORY;
	348
	349	if (size) {
	350	g_autofree char *name;
	351	pdev->region[i].dev = pdev;
352	pdev->region[i].present = true;
353	if (type == PCI_BASE_ADDRESS_SPACE_MEMORY) {
354	pdev->region[i].memory = true;
355	}
356	name = g_strdup_printf("bar-region-%d", i);
357	memory_region_init_io(&pdev->region[i].mr, OBJECT(pdev),
358	&proxy_mr_ops, &pdev->region[i],
359	name, size);
360	pci_register_bar(dev, i, type, &pdev->region[i].mr);
361	}
362	}
363	}
b6cc02d9 EU	364
	365	static void proxy_device_reset(DeviceState *dev)
	366	{
	367	PCIProxyDev *pdev = PCI_PROXY_DEV(dev);
	368	MPQemuMsg msg = { 0 };
	369	Error *local_err = NULL;
	370
	371	msg.cmd = MPQEMU_CMD_DEVICE_RESET;
	372	msg.size = 0;
	373
	374	mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
	375	if (local_err) {
	376	error_report_err(local_err);
	377	}
	378
	379	}