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0ac24d56 AF |
1 | /* |
2 | * QEMU RISC-V Boot Helper | |
3 | * | |
4 | * Copyright (c) 2017 SiFive, Inc. | |
5 | * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2 or later, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
2c65db5e | 21 | #include "qemu/datadir.h" |
0ac24d56 AF |
22 | #include "qemu/units.h" |
23 | #include "qemu/error-report.h" | |
24 | #include "exec/cpu-defs.h" | |
12e9493d | 25 | #include "hw/boards.h" |
0ac24d56 AF |
26 | #include "hw/loader.h" |
27 | #include "hw/riscv/boot.h" | |
dc144fe1 | 28 | #include "hw/riscv/boot_opensbi.h" |
0ac24d56 | 29 | #include "elf.h" |
43cf723a | 30 | #include "sysemu/device_tree.h" |
75ea2529 | 31 | #include "sysemu/qtest.h" |
ad40be27 | 32 | #include "sysemu/kvm.h" |
64c75db3 | 33 | #include "sysemu/reset.h" |
0ac24d56 | 34 | |
43cf723a AP |
35 | #include <libfdt.h> |
36 | ||
a8259b53 | 37 | bool riscv_is_32bit(RISCVHartArrayState *harts) |
c4077842 | 38 | { |
db23e5d9 | 39 | return harts->harts[0].env.misa_mxl_max == MXL_RV32; |
c4077842 AF |
40 | } |
41 | ||
bf357e1d AF |
42 | /* |
43 | * Return the per-socket PLIC hart topology configuration string | |
44 | * (caller must free with g_free()) | |
45 | */ | |
46 | char *riscv_plic_hart_config_string(int hart_count) | |
47 | { | |
48 | g_autofree const char **vals = g_new(const char *, hart_count + 1); | |
49 | int i; | |
50 | ||
51 | for (i = 0; i < hart_count; i++) { | |
52 | CPUState *cs = qemu_get_cpu(i); | |
53 | CPURISCVState *env = &RISCV_CPU(cs)->env; | |
54 | ||
ad40be27 YJ |
55 | if (kvm_enabled()) { |
56 | vals[i] = "S"; | |
57 | } else if (riscv_has_ext(env, RVS)) { | |
bf357e1d AF |
58 | vals[i] = "MS"; |
59 | } else { | |
60 | vals[i] = "M"; | |
61 | } | |
62 | } | |
63 | vals[i] = NULL; | |
64 | ||
65 | /* g_strjoinv() obliges us to cast away const here */ | |
66 | return g_strjoinv(",", (char **)vals); | |
67 | } | |
68 | ||
a8259b53 | 69 | target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, |
38bc4e34 | 70 | target_ulong firmware_end_addr) { |
3ed2b8ac | 71 | if (riscv_is_32bit(harts)) { |
38bc4e34 AF |
72 | return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); |
73 | } else { | |
74 | return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); | |
75 | } | |
76 | } | |
77 | ||
9d3f7108 DHB |
78 | const char *riscv_default_firmware_name(RISCVHartArrayState *harts) |
79 | { | |
80 | if (riscv_is_32bit(harts)) { | |
81 | return RISCV32_BIOS_BIN; | |
82 | } | |
83 | ||
84 | return RISCV64_BIOS_BIN; | |
85 | } | |
86 | ||
8f619626 | 87 | static char *riscv_find_bios(const char *bios_filename) |
808faef7 DHB |
88 | { |
89 | char *filename; | |
90 | ||
8f619626 | 91 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename); |
808faef7 DHB |
92 | if (filename == NULL) { |
93 | if (!qtest_enabled()) { | |
94 | /* | |
95 | * We only ship OpenSBI binary bios images in the QEMU source. | |
96 | * For machines that use images other than the default bios, | |
97 | * running QEMU test will complain hence let's suppress the error | |
98 | * report for QEMU testing. | |
99 | */ | |
8f619626 BM |
100 | error_report("Unable to find the RISC-V BIOS \"%s\"", |
101 | bios_filename); | |
808faef7 DHB |
102 | exit(1); |
103 | } | |
104 | } | |
105 | ||
106 | return filename; | |
107 | } | |
108 | ||
8f619626 BM |
109 | char *riscv_find_firmware(const char *firmware_filename, |
110 | const char *default_machine_firmware) | |
fdd1bda4 | 111 | { |
8f619626 | 112 | char *filename = NULL; |
fdd1bda4 | 113 | |
8f619626 | 114 | if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) { |
fdd1bda4 | 115 | /* |
087a4246 BM |
116 | * The user didn't specify -bios, or has specified "-bios default". |
117 | * That means we are going to load the OpenSBI binary included in | |
118 | * the QEMU source. | |
fdd1bda4 | 119 | */ |
8f619626 BM |
120 | filename = riscv_find_bios(default_machine_firmware); |
121 | } else if (strcmp(firmware_filename, "none")) { | |
122 | filename = riscv_find_bios(firmware_filename); | |
fdd1bda4 AF |
123 | } |
124 | ||
8f619626 BM |
125 | return filename; |
126 | } | |
127 | ||
128 | target_ulong riscv_find_and_load_firmware(MachineState *machine, | |
129 | const char *default_machine_firmware, | |
130 | hwaddr firmware_load_addr, | |
131 | symbol_fn_t sym_cb) | |
132 | { | |
133 | char *firmware_filename; | |
134 | target_ulong firmware_end_addr = firmware_load_addr; | |
135 | ||
136 | firmware_filename = riscv_find_firmware(machine->firmware, | |
137 | default_machine_firmware); | |
138 | ||
3aa9004f | 139 | if (firmware_filename) { |
fdd1bda4 | 140 | /* If not "none" load the firmware */ |
e66c531e AF |
141 | firmware_end_addr = riscv_load_firmware(firmware_filename, |
142 | firmware_load_addr, sym_cb); | |
fdd1bda4 AF |
143 | g_free(firmware_filename); |
144 | } | |
e66c531e AF |
145 | |
146 | return firmware_end_addr; | |
fdd1bda4 AF |
147 | } |
148 | ||
b3042223 | 149 | target_ulong riscv_load_firmware(const char *firmware_filename, |
02777ac3 AP |
150 | hwaddr firmware_load_addr, |
151 | symbol_fn_t sym_cb) | |
b3042223 | 152 | { |
af975131 JI |
153 | uint64_t firmware_entry, firmware_end; |
154 | ssize_t firmware_size; | |
b3042223 | 155 | |
1db0c57a DHB |
156 | g_assert(firmware_filename != NULL); |
157 | ||
02777ac3 | 158 | if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, |
e66c531e | 159 | &firmware_entry, NULL, &firmware_end, NULL, |
02777ac3 | 160 | 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { |
e66c531e | 161 | return firmware_end; |
b3042223 AF |
162 | } |
163 | ||
e66c531e | 164 | firmware_size = load_image_targphys_as(firmware_filename, |
82e69054 PB |
165 | firmware_load_addr, |
166 | current_machine->ram_size, NULL); | |
e66c531e AF |
167 | |
168 | if (firmware_size > 0) { | |
169 | return firmware_load_addr + firmware_size; | |
b3042223 AF |
170 | } |
171 | ||
172 | error_report("could not load firmware '%s'", firmware_filename); | |
173 | exit(1); | |
174 | } | |
175 | ||
60c1f05e | 176 | target_ulong riscv_load_kernel(MachineState *machine, |
38bc4e34 AF |
177 | target_ulong kernel_start_addr, |
178 | symbol_fn_t sym_cb) | |
0ac24d56 | 179 | { |
60c1f05e | 180 | const char *kernel_filename = machine->kernel_filename; |
7e322a7f | 181 | uint64_t kernel_load_base, kernel_entry; |
0ac24d56 | 182 | |
1db0c57a DHB |
183 | g_assert(kernel_filename != NULL); |
184 | ||
7e322a7f JC |
185 | /* |
186 | * NB: Use low address not ELF entry point to ensure that the fw_dynamic | |
187 | * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL | |
188 | * behaviour, as well as fw_dynamic with a raw binary, all of which jump to | |
189 | * the (expected) load address load address. This allows kernels to have | |
190 | * separate SBI and ELF entry points (used by FreeBSD, for example). | |
191 | */ | |
6478dd74 | 192 | if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, |
7e322a7f | 193 | NULL, &kernel_load_base, NULL, NULL, 0, |
6478dd74 | 194 | EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { |
7e322a7f | 195 | return kernel_load_base; |
0ac24d56 AF |
196 | } |
197 | ||
395fd695 AF |
198 | if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, |
199 | NULL, NULL, NULL) > 0) { | |
200 | return kernel_entry; | |
201 | } | |
202 | ||
38bc4e34 | 203 | if (load_image_targphys_as(kernel_filename, kernel_start_addr, |
82e69054 | 204 | current_machine->ram_size, NULL) > 0) { |
38bc4e34 | 205 | return kernel_start_addr; |
395fd695 AF |
206 | } |
207 | ||
208 | error_report("could not load kernel '%s'", kernel_filename); | |
209 | exit(1); | |
0ac24d56 AF |
210 | } |
211 | ||
1f991461 | 212 | void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) |
0ac24d56 | 213 | { |
1f991461 DHB |
214 | const char *filename = machine->initrd_filename; |
215 | uint64_t mem_size = machine->ram_size; | |
216 | void *fdt = machine->fdt; | |
b9a65476 | 217 | hwaddr start, end; |
af975131 | 218 | ssize_t size; |
0ac24d56 | 219 | |
1db0c57a DHB |
220 | g_assert(filename != NULL); |
221 | ||
0ac24d56 AF |
222 | /* |
223 | * We want to put the initrd far enough into RAM that when the | |
224 | * kernel is uncompressed it will not clobber the initrd. However | |
225 | * on boards without much RAM we must ensure that we still leave | |
226 | * enough room for a decent sized initrd, and on boards with large | |
227 | * amounts of RAM we must avoid the initrd being so far up in RAM | |
228 | * that it is outside lowmem and inaccessible to the kernel. | |
229 | * So for boards with less than 256MB of RAM we put the initrd | |
230 | * halfway into RAM, and for boards with 256MB of RAM or more we put | |
231 | * the initrd at 128MB. | |
232 | */ | |
b9a65476 | 233 | start = kernel_entry + MIN(mem_size / 2, 128 * MiB); |
0ac24d56 | 234 | |
b9a65476 | 235 | size = load_ramdisk(filename, start, mem_size - start); |
0ac24d56 | 236 | if (size == -1) { |
b9a65476 | 237 | size = load_image_targphys(filename, start, mem_size - start); |
0ac24d56 AF |
238 | if (size == -1) { |
239 | error_report("could not load ramdisk '%s'", filename); | |
240 | exit(1); | |
241 | } | |
242 | } | |
243 | ||
b9a65476 DHB |
244 | /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ |
245 | if (fdt) { | |
246 | end = start + size; | |
247 | qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); | |
248 | qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); | |
249 | } | |
0ac24d56 | 250 | } |
43cf723a | 251 | |
bc2c0153 DHB |
252 | /* |
253 | * The FDT should be put at the farthest point possible to | |
254 | * avoid overwriting it with the kernel/initrd. | |
255 | * | |
256 | * This function makes an assumption that the DRAM is | |
257 | * contiguous. It also cares about 32-bit systems and | |
258 | * will limit fdt_addr to be addressable by them even for | |
259 | * 64-bit CPUs. | |
260 | * | |
261 | * The FDT is fdt_packed() during the calculation. | |
262 | */ | |
263 | uint64_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, | |
264 | void *fdt) | |
66b1205b | 265 | { |
bc2c0153 | 266 | uint64_t temp; |
66b1205b | 267 | hwaddr dram_end = dram_base + mem_size; |
909f7da6 DHB |
268 | int ret = fdt_pack(fdt); |
269 | int fdtsize; | |
66b1205b | 270 | |
909f7da6 DHB |
271 | /* Should only fail if we've built a corrupted tree */ |
272 | g_assert(ret == 0); | |
273 | ||
274 | fdtsize = fdt_totalsize(fdt); | |
66b1205b AP |
275 | if (fdtsize <= 0) { |
276 | error_report("invalid device-tree"); | |
277 | exit(1); | |
278 | } | |
279 | ||
280 | /* | |
281 | * We should put fdt as far as possible to avoid kernel/initrd overwriting | |
282 | * its content. But it should be addressable by 32 bit system as well. | |
ec2c62da | 283 | * Thus, put it at an 2MB aligned address that less than fdt size from the |
1a475d39 | 284 | * end of dram or 3GB whichever is lesser. |
66b1205b | 285 | */ |
faee5441 | 286 | temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; |
bc2c0153 DHB |
287 | |
288 | return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); | |
289 | } | |
290 | ||
291 | /* | |
292 | * 'fdt_addr' is received as hwaddr because boards might put | |
293 | * the FDT beyond 32-bit addressing boundary. | |
294 | */ | |
295 | void riscv_load_fdt(hwaddr fdt_addr, void *fdt) | |
296 | { | |
297 | uint32_t fdtsize = fdt_totalsize(fdt); | |
66b1205b | 298 | |
66b1205b AP |
299 | /* copy in the device tree */ |
300 | qemu_fdt_dumpdtb(fdt, fdtsize); | |
301 | ||
302 | rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, | |
303 | &address_space_memory); | |
64c75db3 JD |
304 | qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, |
305 | rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); | |
66b1205b AP |
306 | } |
307 | ||
78936771 AF |
308 | void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, |
309 | hwaddr rom_size, uint32_t reset_vec_size, | |
310 | uint64_t kernel_entry) | |
dc144fe1 AP |
311 | { |
312 | struct fw_dynamic_info dinfo; | |
313 | size_t dinfo_len; | |
314 | ||
78936771 AF |
315 | if (sizeof(dinfo.magic) == 4) { |
316 | dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); | |
317 | dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); | |
318 | dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); | |
319 | dinfo.next_addr = cpu_to_le32(kernel_entry); | |
320 | } else { | |
321 | dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); | |
322 | dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); | |
323 | dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); | |
324 | dinfo.next_addr = cpu_to_le64(kernel_entry); | |
325 | } | |
dc144fe1 AP |
326 | dinfo.options = 0; |
327 | dinfo.boot_hart = 0; | |
328 | dinfo_len = sizeof(dinfo); | |
329 | ||
330 | /** | |
331 | * copy the dynamic firmware info. This information is specific to | |
332 | * OpenSBI but doesn't break any other firmware as long as they don't | |
333 | * expect any certain value in "a2" register. | |
334 | */ | |
335 | if (dinfo_len > (rom_size - reset_vec_size)) { | |
336 | error_report("not enough space to store dynamic firmware info"); | |
337 | exit(1); | |
338 | } | |
339 | ||
340 | rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, | |
341 | rom_base + reset_vec_size, | |
342 | &address_space_memory); | |
343 | } | |
344 | ||
a8259b53 | 345 | void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, |
3ed2b8ac | 346 | hwaddr start_addr, |
78936771 AF |
347 | hwaddr rom_base, hwaddr rom_size, |
348 | uint64_t kernel_entry, | |
6934f15b | 349 | uint64_t fdt_load_addr) |
43cf723a AP |
350 | { |
351 | int i; | |
8590f536 | 352 | uint32_t start_addr_hi32 = 0x00000000; |
faee5441 | 353 | uint32_t fdt_load_addr_hi32 = 0x00000000; |
43cf723a | 354 | |
3ed2b8ac | 355 | if (!riscv_is_32bit(harts)) { |
78936771 | 356 | start_addr_hi32 = start_addr >> 32; |
faee5441 | 357 | fdt_load_addr_hi32 = fdt_load_addr >> 32; |
78936771 | 358 | } |
43cf723a | 359 | /* reset vector */ |
66b1205b | 360 | uint32_t reset_vec[10] = { |
dc144fe1 AP |
361 | 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ |
362 | 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ | |
43cf723a | 363 | 0xf1402573, /* csrr a0, mhartid */ |
78936771 AF |
364 | 0, |
365 | 0, | |
43cf723a | 366 | 0x00028067, /* jr t0 */ |
43cf723a | 367 | start_addr, /* start: .dword */ |
8590f536 | 368 | start_addr_hi32, |
66b1205b | 369 | fdt_load_addr, /* fdt_laddr: .dword */ |
faee5441 | 370 | fdt_load_addr_hi32, |
dc144fe1 | 371 | /* fw_dyn: */ |
43cf723a | 372 | }; |
3ed2b8ac | 373 | if (riscv_is_32bit(harts)) { |
78936771 AF |
374 | reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ |
375 | reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ | |
376 | } else { | |
377 | reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ | |
378 | reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ | |
379 | } | |
43cf723a | 380 | |
32c435a1 AF |
381 | if (!harts->harts[0].cfg.ext_icsr) { |
382 | /* | |
383 | * The Zicsr extension has been disabled, so let's ensure we don't | |
384 | * run the CSR instruction. Let's fill the address with a non | |
385 | * compressed nop. | |
386 | */ | |
387 | reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ | |
388 | } | |
389 | ||
43cf723a | 390 | /* copy in the reset vector in little_endian byte order */ |
66b1205b | 391 | for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { |
43cf723a AP |
392 | reset_vec[i] = cpu_to_le32(reset_vec[i]); |
393 | } | |
394 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
395 | rom_base, &address_space_memory); | |
78936771 | 396 | riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), |
dc144fe1 | 397 | kernel_entry); |
43cf723a | 398 | } |
ad40be27 YJ |
399 | |
400 | void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) | |
401 | { | |
402 | CPUState *cs; | |
403 | ||
404 | for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { | |
405 | RISCVCPU *riscv_cpu = RISCV_CPU(cs); | |
406 | riscv_cpu->env.kernel_addr = kernel_addr; | |
407 | riscv_cpu->env.fdt_addr = fdt_addr; | |
408 | } | |
409 | } | |
a5b0249d S |
410 | |
411 | void riscv_setup_firmware_boot(MachineState *machine) | |
412 | { | |
413 | if (machine->kernel_filename) { | |
414 | FWCfgState *fw_cfg; | |
415 | fw_cfg = fw_cfg_find(); | |
416 | ||
417 | assert(fw_cfg); | |
418 | /* | |
419 | * Expose the kernel, the command line, and the initrd in fw_cfg. | |
420 | * We don't process them here at all, it's all left to the | |
421 | * firmware. | |
422 | */ | |
423 | load_image_to_fw_cfg(fw_cfg, | |
424 | FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | |
425 | machine->kernel_filename, | |
426 | true); | |
427 | load_image_to_fw_cfg(fw_cfg, | |
428 | FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | |
429 | machine->initrd_filename, false); | |
430 | ||
431 | if (machine->kernel_cmdline) { | |
432 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | |
433 | strlen(machine->kernel_cmdline) + 1); | |
434 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | |
435 | machine->kernel_cmdline); | |
436 | } | |
437 | } | |
438 | } |