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Commit | Line | Data |
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2c44220d MAL |
1 | riscv_ss = ss.source_set() |
2 | riscv_ss.add(files('boot.c')) | |
3 | riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) | |
4 | riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) | |
5 | riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) | |
6 | riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c')) | |
7 | riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c')) | |
8 | riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c')) | |
9 | riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) | |
10 | riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) | |
11 | riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) | |
12 | riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c')) | |
13 | riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) | |
14 | riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c')) | |
15 | riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c')) | |
16 | riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) | |
17 | riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) | |
18 | ||
19 | hw_arch += {'riscv': riscv_ss} |