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fe0fe473 AF |
1 | /* |
2 | * QEMU RISC-V Board Compatible with OpenTitan FPGA platform | |
3 | * | |
4 | * Copyright (c) 2020 Western Digital | |
5 | * | |
6 | * Provides a board compatible with the OpenTitan FPGA platform: | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2 or later, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
91b1fbdc | 22 | #include "qemu/cutils.h" |
fe0fe473 AF |
23 | #include "hw/riscv/opentitan.h" |
24 | #include "qapi/error.h" | |
cc37d98b | 25 | #include "qemu/error-report.h" |
fe0fe473 AF |
26 | #include "hw/boards.h" |
27 | #include "hw/misc/unimp.h" | |
28 | #include "hw/riscv/boot.h" | |
888c9af2 | 29 | #include "qemu/units.h" |
b9fc5135 | 30 | #include "sysemu/sysemu.h" |
fe0fe473 | 31 | |
5379c1d0 WM |
32 | /* |
33 | * This version of the OpenTitan machine currently supports | |
34 | * OpenTitan RTL version: | |
7ae71462 | 35 | * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47> |
5379c1d0 WM |
36 | * |
37 | * MMIO mapping as per (specified commit): | |
38 | * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h | |
39 | */ | |
73261285 | 40 | static const MemMapEntry ibex_memmap[] = { |
7ae71462 WM |
41 | [IBEX_DEV_ROM] = { 0x00008000, 0x8000 }, |
42 | [IBEX_DEV_RAM] = { 0x10000000, 0x20000 }, | |
43 | [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 }, | |
44 | [IBEX_DEV_UART] = { 0x40000000, 0x40 }, | |
45 | [IBEX_DEV_GPIO] = { 0x40040000, 0x40 }, | |
46 | [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 }, | |
47 | [IBEX_DEV_I2C] = { 0x40080000, 0x80 }, | |
48 | [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 }, | |
49 | [IBEX_DEV_TIMER] = { 0x40100000, 0x200 }, | |
50 | [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 }, | |
51 | [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 }, | |
52 | [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 }, | |
53 | [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 }, | |
54 | [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 }, | |
55 | [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 }, | |
56 | [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 }, | |
57 | [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 }, | |
58 | [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 }, | |
59 | [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, | |
60 | [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 }, | |
61 | [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 }, | |
62 | [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 }, | |
63 | [IBEX_DEV_AES] = { 0x41100000, 0x100 }, | |
64 | [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, | |
65 | [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, | |
66 | [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 }, | |
67 | [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 }, | |
68 | [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 }, | |
69 | [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 }, | |
70 | [IBEX_DEV_EDNO] = { 0x41170000, 0x80 }, | |
71 | [IBEX_DEV_EDN1] = { 0x41180000, 0x80 }, | |
72 | [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 }, | |
73 | [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 }, | |
74 | [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 }, | |
75 | [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, | |
fe0fe473 AF |
76 | }; |
77 | ||
9b29697f | 78 | static void opentitan_machine_init(MachineState *machine) |
fe0fe473 | 79 | { |
91b1fbdc | 80 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
a828ba9d | 81 | OpenTitanState *s = OPENTITAN_MACHINE(machine); |
73261285 | 82 | const MemMapEntry *memmap = ibex_memmap; |
fe0fe473 | 83 | MemoryRegion *sys_mem = get_system_memory(); |
91b1fbdc BM |
84 | |
85 | if (machine->ram_size != mc->default_ram_size) { | |
86 | char *sz = size_to_str(mc->default_ram_size); | |
87 | error_report("Invalid RAM size, should be %s", sz); | |
88 | g_free(sz); | |
89 | exit(EXIT_FAILURE); | |
90 | } | |
fe0fe473 AF |
91 | |
92 | /* Initialize SoC */ | |
93 | object_initialize_child(OBJECT(machine), "soc", &s->soc, | |
9fc7fc4d | 94 | TYPE_RISCV_IBEX_SOC); |
8f972e5b | 95 | qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); |
fe0fe473 | 96 | |
fe0fe473 | 97 | memory_region_add_subregion(sys_mem, |
91b1fbdc | 98 | memmap[IBEX_DEV_RAM].base, machine->ram); |
fe0fe473 | 99 | |
fe0fe473 | 100 | if (machine->firmware) { |
30c717cb | 101 | riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL); |
fe0fe473 AF |
102 | } |
103 | ||
104 | if (machine->kernel_filename) { | |
62c5bc34 | 105 | riscv_load_kernel(machine, &s->soc.cpus, |
487d73fc DHB |
106 | memmap[IBEX_DEV_RAM].base, |
107 | false, NULL); | |
fe0fe473 AF |
108 | } |
109 | } | |
110 | ||
8696b74a | 111 | static void opentitan_machine_class_init(ObjectClass *oc, void *data) |
fe0fe473 | 112 | { |
8696b74a PMD |
113 | MachineClass *mc = MACHINE_CLASS(oc); |
114 | ||
fe0fe473 | 115 | mc->desc = "RISC-V Board compatible with OpenTitan"; |
9b29697f | 116 | mc->init = opentitan_machine_init; |
fe0fe473 AF |
117 | mc->max_cpus = 1; |
118 | mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; | |
91b1fbdc BM |
119 | mc->default_ram_id = "riscv.lowrisc.ibex.ram"; |
120 | mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size; | |
fe0fe473 AF |
121 | } |
122 | ||
89494462 | 123 | static void lowrisc_ibex_soc_init(Object *obj) |
fe0fe473 AF |
124 | { |
125 | LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); | |
126 | ||
db873cc5 | 127 | object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); |
b9fc5135 | 128 | |
ef631006 | 129 | object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC); |
cc411260 AF |
130 | |
131 | object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); | |
3ef64344 AF |
132 | |
133 | object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); | |
9972479f WM |
134 | |
135 | for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) { | |
136 | object_initialize_child(obj, "spi_host[*]", &s->spi_host[i], | |
137 | TYPE_IBEX_SPI_HOST); | |
138 | } | |
fe0fe473 AF |
139 | } |
140 | ||
89494462 | 141 | static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) |
fe0fe473 | 142 | { |
73261285 | 143 | const MemMapEntry *memmap = ibex_memmap; |
9972479f WM |
144 | DeviceState *dev; |
145 | SysBusDevice *busdev; | |
fe0fe473 AF |
146 | MachineState *ms = MACHINE(qdev_get_machine()); |
147 | LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); | |
148 | MemoryRegion *sys_mem = get_system_memory(); | |
e5cc6aae | 149 | int i; |
fe0fe473 | 150 | |
5325cc34 | 151 | object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, |
fe0fe473 | 152 | &error_abort); |
5325cc34 | 153 | object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, |
fe0fe473 | 154 | &error_abort); |
a06fded8 | 155 | object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec, |
bf8803c6 | 156 | &error_abort); |
91a3387d | 157 | sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); |
fe0fe473 AF |
158 | |
159 | /* Boot ROM */ | |
160 | memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", | |
30c717cb | 161 | memmap[IBEX_DEV_ROM].size, &error_fatal); |
fe0fe473 | 162 | memory_region_add_subregion(sys_mem, |
30c717cb | 163 | memmap[IBEX_DEV_ROM].base, &s->rom); |
fe0fe473 AF |
164 | |
165 | /* Flash memory */ | |
166 | memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", | |
30c717cb | 167 | memmap[IBEX_DEV_FLASH].size, &error_fatal); |
bb7e0cde AF |
168 | memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), |
169 | "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0, | |
170 | memmap[IBEX_DEV_FLASH_VIRTUAL].size); | |
30c717cb | 171 | memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, |
fe0fe473 | 172 | &s->flash_mem); |
bb7e0cde AF |
173 | memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base, |
174 | &s->flash_alias); | |
fe0fe473 | 175 | |
b9fc5135 | 176 | /* PLIC */ |
ef631006 | 177 | qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); |
ef631006 AF |
178 | qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); |
179 | qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); | |
ef631006 AF |
180 | qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); |
181 | qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); | |
0df470c3 | 182 | qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); |
9b144ed4 AF |
183 | qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); |
184 | qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); | |
ef631006 AF |
185 | qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); |
186 | ||
668f62ec | 187 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { |
b9fc5135 AF |
188 | return; |
189 | } | |
30c717cb | 190 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); |
b9fc5135 | 191 | |
e5cc6aae AF |
192 | for (i = 0; i < ms->smp.cpus; i++) { |
193 | CPUState *cpu = qemu_get_cpu(i); | |
194 | ||
ef631006 | 195 | qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i, |
e5cc6aae AF |
196 | qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); |
197 | } | |
198 | ||
cc411260 AF |
199 | /* UART */ |
200 | qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); | |
668f62ec | 201 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { |
cc411260 AF |
202 | return; |
203 | } | |
30c717cb | 204 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); |
cc411260 AF |
205 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), |
206 | 0, qdev_get_gpio_in(DEVICE(&s->plic), | |
d4cad544 | 207 | IBEX_UART0_TX_WATERMARK_IRQ)); |
cc411260 AF |
208 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), |
209 | 1, qdev_get_gpio_in(DEVICE(&s->plic), | |
d4cad544 | 210 | IBEX_UART0_RX_WATERMARK_IRQ)); |
cc411260 AF |
211 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), |
212 | 2, qdev_get_gpio_in(DEVICE(&s->plic), | |
d4cad544 | 213 | IBEX_UART0_TX_EMPTY_IRQ)); |
cc411260 AF |
214 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), |
215 | 3, qdev_get_gpio_in(DEVICE(&s->plic), | |
d4cad544 | 216 | IBEX_UART0_RX_OVERFLOW_IRQ)); |
cc411260 | 217 | |
3ef64344 AF |
218 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { |
219 | return; | |
220 | } | |
221 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base); | |
222 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), | |
223 | 0, qdev_get_gpio_in(DEVICE(&s->plic), | |
224 | IBEX_TIMER_TIMEREXPIRED0_0)); | |
57a3a622 AF |
225 | qdev_connect_gpio_out(DEVICE(&s->timer), 0, |
226 | qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), | |
227 | IRQ_M_TIMER)); | |
3ef64344 | 228 | |
9972479f WM |
229 | /* SPI-Hosts */ |
230 | for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) { | |
231 | dev = DEVICE(&(s->spi_host[i])); | |
232 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) { | |
233 | return; | |
234 | } | |
235 | busdev = SYS_BUS_DEVICE(dev); | |
236 | sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base); | |
237 | ||
238 | switch (i) { | |
239 | case OPENTITAN_SPI_HOST0: | |
240 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), | |
241 | IBEX_SPI_HOST0_ERR_IRQ)); | |
242 | sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic), | |
243 | IBEX_SPI_HOST0_SPI_EVENT_IRQ)); | |
244 | break; | |
245 | case OPENTITAN_SPI_HOST1: | |
246 | sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), | |
247 | IBEX_SPI_HOST1_ERR_IRQ)); | |
248 | sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic), | |
249 | IBEX_SPI_HOST1_SPI_EVENT_IRQ)); | |
250 | break; | |
251 | } | |
252 | } | |
253 | ||
fe0fe473 | 254 | create_unimplemented_device("riscv.lowrisc.ibex.gpio", |
30c717cb | 255 | memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); |
aecabd50 WM |
256 | create_unimplemented_device("riscv.lowrisc.ibex.spi_device", |
257 | memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size); | |
d31e970a AF |
258 | create_unimplemented_device("riscv.lowrisc.ibex.i2c", |
259 | memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); | |
260 | create_unimplemented_device("riscv.lowrisc.ibex.pattgen", | |
261 | memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); | |
d31e970a AF |
262 | create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", |
263 | memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); | |
264 | create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", | |
265 | memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); | |
bf8803c6 WM |
266 | create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl", |
267 | memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size); | |
fe0fe473 | 268 | create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", |
30c717cb | 269 | memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); |
fe0fe473 | 270 | create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", |
30c717cb | 271 | memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); |
fe0fe473 | 272 | create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", |
30c717cb | 273 | memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); |
d31e970a AF |
274 | create_unimplemented_device("riscv.lowrisc.ibex.pinmux", |
275 | memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); | |
aefd1108 WM |
276 | create_unimplemented_device("riscv.lowrisc.ibex.aon_timer", |
277 | memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size); | |
d31e970a AF |
278 | create_unimplemented_device("riscv.lowrisc.ibex.usbdev", |
279 | memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); | |
280 | create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", | |
281 | memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); | |
fe0fe473 | 282 | create_unimplemented_device("riscv.lowrisc.ibex.aes", |
30c717cb | 283 | memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); |
fe0fe473 | 284 | create_unimplemented_device("riscv.lowrisc.ibex.hmac", |
30c717cb | 285 | memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); |
d31e970a AF |
286 | create_unimplemented_device("riscv.lowrisc.ibex.kmac", |
287 | memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size); | |
288 | create_unimplemented_device("riscv.lowrisc.ibex.keymgr", | |
289 | memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size); | |
290 | create_unimplemented_device("riscv.lowrisc.ibex.csrng", | |
291 | memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size); | |
292 | create_unimplemented_device("riscv.lowrisc.ibex.entropy", | |
293 | memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size); | |
294 | create_unimplemented_device("riscv.lowrisc.ibex.edn0", | |
295 | memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size); | |
296 | create_unimplemented_device("riscv.lowrisc.ibex.edn1", | |
297 | memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); | |
fe0fe473 | 298 | create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", |
30c717cb | 299 | memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); |
7ae71462 WM |
300 | create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl", |
301 | memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size); | |
d31e970a AF |
302 | create_unimplemented_device("riscv.lowrisc.ibex.otbn", |
303 | memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); | |
7ae71462 WM |
304 | create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg", |
305 | memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size); | |
fe0fe473 AF |
306 | } |
307 | ||
a06fded8 AF |
308 | static Property lowrisc_ibex_soc_props[] = { |
309 | DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400), | |
310 | DEFINE_PROP_END_OF_LIST() | |
311 | }; | |
312 | ||
89494462 | 313 | static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) |
fe0fe473 AF |
314 | { |
315 | DeviceClass *dc = DEVICE_CLASS(oc); | |
316 | ||
a06fded8 | 317 | device_class_set_props(dc, lowrisc_ibex_soc_props); |
89494462 | 318 | dc->realize = lowrisc_ibex_soc_realize; |
fe0fe473 AF |
319 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
320 | dc->user_creatable = false; | |
321 | } | |
322 | ||
e0782b11 PMD |
323 | static const TypeInfo open_titan_types[] = { |
324 | { | |
325 | .name = TYPE_RISCV_IBEX_SOC, | |
326 | .parent = TYPE_DEVICE, | |
327 | .instance_size = sizeof(LowRISCIbexSoCState), | |
328 | .instance_init = lowrisc_ibex_soc_init, | |
329 | .class_init = lowrisc_ibex_soc_class_init, | |
8696b74a PMD |
330 | }, { |
331 | .name = TYPE_OPENTITAN_MACHINE, | |
332 | .parent = TYPE_MACHINE, | |
a828ba9d | 333 | .instance_size = sizeof(OpenTitanState), |
8696b74a | 334 | .class_init = opentitan_machine_class_init, |
e0782b11 | 335 | } |
fe0fe473 AF |
336 | }; |
337 | ||
e0782b11 | 338 | DEFINE_TYPES(open_titan_types) |