[mirror_qemu.git] / hw / riscv / sifive_clint.c

/*
 * SiFive CLINT (Core Local Interruptor)
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
 * Copyright (c) 2017 SiFive, Inc.
 *
 * This provides real-time clock, timer and interprocessor interrupts.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
#include "hw/qdev-properties.h"
#include "hw/riscv/sifive_clint.h"
#include "qemu/timer.h"

static uint64_t cpu_riscv_read_rtc(void)
{
    return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
        SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
}

/*
 * Called when timecmp is written to update the QEMU timer or immediately
 * trigger timer interrupt if mtimecmp <= current timer value.
 */
static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
{
    uint64_t next;
    uint64_t diff;

    uint64_t rtc_r = cpu_riscv_read_rtc();

    cpu->env.timecmp = value;
    if (cpu->env.timecmp <= rtc_r) {
        /* if we're setting an MTIMECMP value in the "past",
           immediately raise the timer interrupt */
        riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
        return;
    }

    /* otherwise, set up the future timer interrupt */
    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
    diff = cpu->env.timecmp - rtc_r;
    /* back to ns (note args switched in muldiv64) */
    next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
        muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
    timer_mod(cpu->env.timer, next);
}

/*
 * Callback used when the timer set using timer_mod expires.
 * Should raise the timer interrupt line
 */
static void sifive_clint_timer_cb(void *opaque)
{
    RISCVCPU *cpu = opaque;
    riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
}

/* CPU wants to read rtc or timecmp register */
static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
{
    SiFiveCLINTState *clint = opaque;
    if (addr >= clint->sip_base &&
        addr < clint->sip_base + (clint->num_harts << 2)) {
        size_t hartid = (addr - clint->sip_base) >> 2;
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            error_report("clint: invalid timecmp hartid: %zu", hartid);
        } else if ((addr & 0x3) == 0) {
            return (env->mip & MIP_MSIP) > 0;
        } else {
            error_report("clint: invalid read: %08x", (uint32_t)addr);
            return 0;
        }
    } else if (addr >= clint->timecmp_base &&
        addr < clint->timecmp_base + (clint->num_harts << 3)) {
        size_t hartid = (addr - clint->timecmp_base) >> 3;
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            error_report("clint: invalid timecmp hartid: %zu", hartid);
        } else if ((addr & 0x7) == 0) {
            /* timecmp_lo */
            uint64_t timecmp = env->timecmp;
            return timecmp & 0xFFFFFFFF;
        } else if ((addr & 0x7) == 4) {
            /* timecmp_hi */
            uint64_t timecmp = env->timecmp;
            return (timecmp >> 32) & 0xFFFFFFFF;
        } else {
            error_report("clint: invalid read: %08x", (uint32_t)addr);
            return 0;
        }
    } else if (addr == clint->time_base) {
        /* time_lo */
        return cpu_riscv_read_rtc() & 0xFFFFFFFF;
    } else if (addr == clint->time_base + 4) {
        /* time_hi */
        return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
    }

    error_report("clint: invalid read: %08x", (uint32_t)addr);
    return 0;
}

/* CPU wrote to rtc or timecmp register */
static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
        unsigned size)
{
    SiFiveCLINTState *clint = opaque;

    if (addr >= clint->sip_base &&
        addr < clint->sip_base + (clint->num_harts << 2)) {
        size_t hartid = (addr - clint->sip_base) >> 2;
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            error_report("clint: invalid timecmp hartid: %zu", hartid);
        } else if ((addr & 0x3) == 0) {
            riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));
        } else {
            error_report("clint: invalid sip write: %08x", (uint32_t)addr);
        }
        return;
    } else if (addr >= clint->timecmp_base &&
        addr < clint->timecmp_base + (clint->num_harts << 3)) {
        size_t hartid = (addr - clint->timecmp_base) >> 3;
        CPUState *cpu = qemu_get_cpu(hartid);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            error_report("clint: invalid timecmp hartid: %zu", hartid);
        } else if ((addr & 0x7) == 0) {
            /* timecmp_lo */
            uint64_t timecmp_hi = env->timecmp >> 32;
            sifive_clint_write_timecmp(RISCV_CPU(cpu),
                timecmp_hi << 32 | (value & 0xFFFFFFFF));
            return;
        } else if ((addr & 0x7) == 4) {
            /* timecmp_hi */
            uint64_t timecmp_lo = env->timecmp;
            sifive_clint_write_timecmp(RISCV_CPU(cpu),
                value << 32 | (timecmp_lo & 0xFFFFFFFF));
        } else {
            error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
        }
        return;
    } else if (addr == clint->time_base) {
        /* time_lo */
        error_report("clint: time_lo write not implemented");
        return;
    } else if (addr == clint->time_base + 4) {
        /* time_hi */
        error_report("clint: time_hi write not implemented");
        return;
    }

    error_report("clint: invalid write: %08x", (uint32_t)addr);
}

static const MemoryRegionOps sifive_clint_ops = {
    .read = sifive_clint_read,
    .write = sifive_clint_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static Property sifive_clint_properties[] = {
    DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
    DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
    DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
    DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
    DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void sifive_clint_realize(DeviceState *dev, Error **errp)
{
    SiFiveCLINTState *s = SIFIVE_CLINT(dev);
    memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_clint_ops, s,
                          TYPE_SIFIVE_CLINT, s->aperture_size);
    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
}

static void sifive_clint_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    dc->realize = sifive_clint_realize;
    device_class_set_props(dc, sifive_clint_properties);
}

static const TypeInfo sifive_clint_info = {
    .name          = TYPE_SIFIVE_CLINT,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(SiFiveCLINTState),
    .class_init    = sifive_clint_class_init,
};

static void sifive_clint_register_types(void)
{
    type_register_static(&sifive_clint_info);
}

type_init(sifive_clint_register_types)


/*
 * Create CLINT device.
 */
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
    uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
    bool provide_rdtime)
{
    int i;
    for (i = 0; i < num_harts; i++) {
        CPUState *cpu = qemu_get_cpu(i);
        CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
        if (!env) {
            continue;
        }
        if (provide_rdtime) {
            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc);
        }
        env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                  &sifive_clint_timer_cb, cpu);
        env->timecmp = 0;
    }

    DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT);
    qdev_prop_set_uint32(dev, "num-harts", num_harts);
    qdev_prop_set_uint32(dev, "sip-base", sip_base);
    qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
    qdev_prop_set_uint32(dev, "time-base", time_base);
    qdev_prop_set_uint32(dev, "aperture-size", size);
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
    return dev;
}
Commit	Line	Data
1c77c410 MC	1	/*
	2	* SiFive CLINT (Core Local Interruptor)
	3	*
	4	* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
	5	* Copyright (c) 2017 SiFive, Inc.
	6	*
	7	* This provides real-time clock, timer and interprocessor interrupts.
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms and conditions of the GNU General Public License,
	11	* version 2 or later, as published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	16	* more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along with
	19	* this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#include "qemu/osdep.h"
3e80f690	23	#include "qapi/error.h"
1c77c410	24	#include "qemu/error-report.h"
0b8fa32f	25	#include "qemu/module.h"
1c77c410 MC	26	#include "hw/sysbus.h"
1c77c410 MC	27	#include "target/riscv/cpu.h"
a27bd6c7	28	#include "hw/qdev-properties.h"
1c77c410 MC	29	#include "hw/riscv/sifive_clint.h"
	30	#include "qemu/timer.h"
	31
1c77c410 MC	32	static uint64_t cpu_riscv_read_rtc(void)
1c77c410 MC	33	{
2a8756ed MC	34	return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
2a8756ed MC	35	SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
1c77c410 MC	36	}
	37
	38	/*
	39	* Called when timecmp is written to update the QEMU timer or immediately
	40	* trigger timer interrupt if mtimecmp <= current timer value.
	41	*/
	42	static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
	43	{
	44	uint64_t next;
	45	uint64_t diff;
	46
	47	uint64_t rtc_r = cpu_riscv_read_rtc();
	48
	49	cpu->env.timecmp = value;
	50	if (cpu->env.timecmp <= rtc_r) {
	51	/* if we're setting an MTIMECMP value in the "past",
	52	immediately raise the timer interrupt */
85ba724f	53	riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
1c77c410 MC	54	return;
	55	}
	56
	57	/* otherwise, set up the future timer interrupt */
85ba724f	58	riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
1c77c410 MC	59	diff = cpu->env.timecmp - rtc_r;
	60	/* back to ns (note args switched in muldiv64) */
	61	next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2a8756ed	62	muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
1c77c410 MC	63	timer_mod(cpu->env.timer, next);
	64	}
	65
	66	/*
	67	* Callback used when the timer set using timer_mod expires.
	68	* Should raise the timer interrupt line
	69	*/
	70	static void sifive_clint_timer_cb(void *opaque)
	71	{
	72	RISCVCPU *cpu = opaque;
85ba724f	73	riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
1c77c410 MC	74	}
	75
	76	/* CPU wants to read rtc or timecmp register */
	77	static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
	78	{
	79	SiFiveCLINTState *clint = opaque;
	80	if (addr >= clint->sip_base &&
	81	addr < clint->sip_base + (clint->num_harts << 2)) {
	82	size_t hartid = (addr - clint->sip_base) >> 2;
	83	CPUState *cpu = qemu_get_cpu(hartid);
	84	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	85	if (!env) {
	86	error_report("clint: invalid timecmp hartid: %zu", hartid);
	87	} else if ((addr & 0x3) == 0) {
	88	return (env->mip & MIP_MSIP) > 0;
	89	} else {
	90	error_report("clint: invalid read: %08x", (uint32_t)addr);
	91	return 0;
	92	}
	93	} else if (addr >= clint->timecmp_base &&
	94	addr < clint->timecmp_base + (clint->num_harts << 3)) {
	95	size_t hartid = (addr - clint->timecmp_base) >> 3;
	96	CPUState *cpu = qemu_get_cpu(hartid);
	97	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	98	if (!env) {
	99	error_report("clint: invalid timecmp hartid: %zu", hartid);
	100	} else if ((addr & 0x7) == 0) {
	101	/* timecmp_lo */
	102	uint64_t timecmp = env->timecmp;
	103	return timecmp & 0xFFFFFFFF;
	104	} else if ((addr & 0x7) == 4) {
	105	/* timecmp_hi */
	106	uint64_t timecmp = env->timecmp;
	107	return (timecmp >> 32) & 0xFFFFFFFF;
	108	} else {
	109	error_report("clint: invalid read: %08x", (uint32_t)addr);
	110	return 0;
	111	}
	112	} else if (addr == clint->time_base) {
	113	/* time_lo */
	114	return cpu_riscv_read_rtc() & 0xFFFFFFFF;
	115	} else if (addr == clint->time_base + 4) {
	116	/* time_hi */
	117	return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
	118	}
	119
	120	error_report("clint: invalid read: %08x", (uint32_t)addr);
	121	return 0;
	122	}
	123
	124	/* CPU wrote to rtc or timecmp register */
	125	static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
	126	unsigned size)
	127	{
	128	SiFiveCLINTState *clint = opaque;
	129
	130	if (addr >= clint->sip_base &&
	131	addr < clint->sip_base + (clint->num_harts << 2)) {
	132	size_t hartid = (addr - clint->sip_base) >> 2;
	133	CPUState *cpu = qemu_get_cpu(hartid);
	134	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	135	if (!env) {
	136	error_report("clint: invalid timecmp hartid: %zu", hartid);
	137	} else if ((addr & 0x3) == 0) {
85ba724f	138	riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MSIP, BOOL_TO_MASK(value));
1c77c410 MC	139	} else {
	140	error_report("clint: invalid sip write: %08x", (uint32_t)addr);
	141	}
	142	return;
	143	} else if (addr >= clint->timecmp_base &&
	144	addr < clint->timecmp_base + (clint->num_harts << 3)) {
	145	size_t hartid = (addr - clint->timecmp_base) >> 3;
	146	CPUState *cpu = qemu_get_cpu(hartid);
	147	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	148	if (!env) {
	149	error_report("clint: invalid timecmp hartid: %zu", hartid);
	150	} else if ((addr & 0x7) == 0) {
	151	/* timecmp_lo */
ef9e41df	152	uint64_t timecmp_hi = env->timecmp >> 32;
1c77c410	153	sifive_clint_write_timecmp(RISCV_CPU(cpu),
ef9e41df	154	timecmp_hi << 32 \| (value & 0xFFFFFFFF));
1c77c410 MC	155	return;
	156	} else if ((addr & 0x7) == 4) {
	157	/* timecmp_hi */
ef9e41df	158	uint64_t timecmp_lo = env->timecmp;
1c77c410	159	sifive_clint_write_timecmp(RISCV_CPU(cpu),
ef9e41df	160	value << 32 \| (timecmp_lo & 0xFFFFFFFF));
1c77c410 MC	161	} else {
	162	error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
	163	}
	164	return;
	165	} else if (addr == clint->time_base) {
	166	/* time_lo */
	167	error_report("clint: time_lo write not implemented");
	168	return;
	169	} else if (addr == clint->time_base + 4) {
	170	/* time_hi */
	171	error_report("clint: time_hi write not implemented");
	172	return;
	173	}
	174
	175	error_report("clint: invalid write: %08x", (uint32_t)addr);
	176	}
	177
	178	static const MemoryRegionOps sifive_clint_ops = {
	179	.read = sifive_clint_read,
	180	.write = sifive_clint_write,
	181	.endianness = DEVICE_LITTLE_ENDIAN,
	182	.valid = {
	183	.min_access_size = 4,
	184	.max_access_size = 4
	185	}
	186	};
	187
	188	static Property sifive_clint_properties[] = {
	189	DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
	190	DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
	191	DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
	192	DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
	193	DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
	194	DEFINE_PROP_END_OF_LIST(),
	195	};
	196
	197	static void sifive_clint_realize(DeviceState dev, Error *errp)
	198	{
	199	SiFiveCLINTState *s = SIFIVE_CLINT(dev);
	200	memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_clint_ops, s,
	201	TYPE_SIFIVE_CLINT, s->aperture_size);
	202	sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
	203	}
	204
	205	static void sifive_clint_class_init(ObjectClass klass, void data)
	206	{
	207	DeviceClass *dc = DEVICE_CLASS(klass);
	208	dc->realize = sifive_clint_realize;
4f67d30b	209	device_class_set_props(dc, sifive_clint_properties);
1c77c410 MC	210	}
	211
	212	static const TypeInfo sifive_clint_info = {
	213	.name = TYPE_SIFIVE_CLINT,
	214	.parent = TYPE_SYS_BUS_DEVICE,
	215	.instance_size = sizeof(SiFiveCLINTState),
	216	.class_init = sifive_clint_class_init,
	217	};
	218
	219	static void sifive_clint_register_types(void)
	220	{
	221	type_register_static(&sifive_clint_info);
	222	}
	223
	224	type_init(sifive_clint_register_types)
	225
	226
	227	/*
	228	* Create CLINT device.
	229	*/
	230	DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
5f3616cc AP	231	uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
5f3616cc AP	232	bool provide_rdtime)
1c77c410 MC	233	{
	234	int i;
	235	for (i = 0; i < num_harts; i++) {
	236	CPUState *cpu = qemu_get_cpu(i);
	237	CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
	238	if (!env) {
	239	continue;
	240	}
5f3616cc AP	241	if (provide_rdtime) {
	242	riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc);
	243	}
1c77c410 MC	244	env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
	245	&sifive_clint_timer_cb, cpu);
	246	env->timecmp = 0;
	247	}
	248
3e80f690	249	DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT);
1c77c410 MC	250	qdev_prop_set_uint32(dev, "num-harts", num_harts);
	251	qdev_prop_set_uint32(dev, "sip-base", sip_base);
	252	qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
	253	qdev_prop_set_uint32(dev, "time-base", time_base);
	254	qdev_prop_set_uint32(dev, "aperture-size", size);
3c6ef471	255	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1c77c410 MC	256	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
	257	return dev;
	258	}