]>
Commit | Line | Data |
---|---|---|
eb637edb MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom E SDK | |
3 | * | |
4 | * Copyright (c) 2017 SiFive, Inc. | |
5 | * | |
6 | * Provides a board compatible with the SiFive Freedom E SDK: | |
7 | * | |
8 | * 0) UART | |
9 | * 1) CLINT (Core Level Interruptor) | |
10 | * 2) PLIC (Platform Level Interrupt Controller) | |
11 | * 3) PRCI (Power, Reset, Clock, Interrupt) | |
12 | * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM | |
13 | * 5) Flash memory emulated as RAM | |
14 | * | |
15 | * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. | |
16 | * The OTP ROM and Flash boot code will be emulated in a future version. | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or modify it | |
19 | * under the terms and conditions of the GNU General Public License, | |
20 | * version 2 or later, as published by the Free Software Foundation. | |
21 | * | |
22 | * This program is distributed in the hope it will be useful, but WITHOUT | |
23 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
24 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
25 | * more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License along with | |
28 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
29 | */ | |
30 | ||
31 | #include "qemu/osdep.h" | |
32 | #include "qemu/log.h" | |
33 | #include "qemu/error-report.h" | |
34 | #include "qapi/error.h" | |
35 | #include "hw/hw.h" | |
36 | #include "hw/boards.h" | |
37 | #include "hw/loader.h" | |
38 | #include "hw/sysbus.h" | |
39 | #include "hw/char/serial.h" | |
40 | #include "target/riscv/cpu.h" | |
41 | #include "hw/riscv/riscv_hart.h" | |
42 | #include "hw/riscv/sifive_plic.h" | |
43 | #include "hw/riscv/sifive_clint.h" | |
44 | #include "hw/riscv/sifive_prci.h" | |
45 | #include "hw/riscv/sifive_uart.h" | |
46 | #include "hw/riscv/sifive_e.h" | |
47 | #include "chardev/char.h" | |
48 | #include "sysemu/arch_init.h" | |
49 | #include "exec/address-spaces.h" | |
50 | #include "elf.h" | |
51 | ||
52 | static const struct MemmapEntry { | |
53 | hwaddr base; | |
54 | hwaddr size; | |
55 | } sifive_e_memmap[] = { | |
56 | [SIFIVE_E_DEBUG] = { 0x0, 0x100 }, | |
57 | [SIFIVE_E_MROM] = { 0x1000, 0x2000 }, | |
58 | [SIFIVE_E_OTP] = { 0x20000, 0x2000 }, | |
59 | [SIFIVE_E_CLINT] = { 0x2000000, 0x10000 }, | |
60 | [SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 }, | |
61 | [SIFIVE_E_AON] = { 0x10000000, 0x8000 }, | |
62 | [SIFIVE_E_PRCI] = { 0x10008000, 0x8000 }, | |
63 | [SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 }, | |
64 | [SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 }, | |
65 | [SIFIVE_E_UART0] = { 0x10013000, 0x1000 }, | |
66 | [SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 }, | |
67 | [SIFIVE_E_PWM0] = { 0x10015000, 0x1000 }, | |
68 | [SIFIVE_E_UART1] = { 0x10023000, 0x1000 }, | |
69 | [SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 }, | |
70 | [SIFIVE_E_PWM1] = { 0x10025000, 0x1000 }, | |
71 | [SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 }, | |
72 | [SIFIVE_E_PWM2] = { 0x10035000, 0x1000 }, | |
73 | [SIFIVE_E_XIP] = { 0x20000000, 0x20000000 }, | |
74 | [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } | |
75 | }; | |
76 | ||
40e46e51 | 77 | static target_ulong load_kernel(const char *kernel_filename) |
eb637edb MC |
78 | { |
79 | uint64_t kernel_entry, kernel_high; | |
80 | ||
4366e1db | 81 | if (load_elf(kernel_filename, NULL, NULL, NULL, |
eb637edb | 82 | &kernel_entry, NULL, &kernel_high, |
89854803 | 83 | 0, EM_RISCV, 1, 0) < 0) { |
371b74e2 | 84 | error_report("could not load kernel '%s'", kernel_filename); |
eb637edb MC |
85 | exit(1); |
86 | } | |
87 | return kernel_entry; | |
88 | } | |
89 | ||
90 | static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, | |
91 | uintptr_t offset, uintptr_t length) | |
92 | { | |
93 | MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); | |
94 | memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); | |
95 | memory_region_add_subregion(parent, offset, mock_mmio); | |
96 | } | |
97 | ||
98 | static void riscv_sifive_e_init(MachineState *machine) | |
99 | { | |
100 | const struct MemmapEntry *memmap = sifive_e_memmap; | |
101 | ||
102 | SiFiveEState *s = g_new0(SiFiveEState, 1); | |
103 | MemoryRegion *sys_mem = get_system_memory(); | |
104 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); | |
5aec3247 | 105 | int i; |
eb637edb | 106 | |
651cd8b7 | 107 | /* Initialize SoC */ |
54f3141a AF |
108 | object_initialize_child(OBJECT(machine), "soc", &s->soc, |
109 | sizeof(s->soc), TYPE_RISCV_E_SOC, | |
110 | &error_abort, NULL); | |
eb637edb MC |
111 | object_property_set_bool(OBJECT(&s->soc), true, "realized", |
112 | &error_abort); | |
113 | ||
114 | /* Data Tightly Integrated Memory */ | |
115 | memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", | |
116 | memmap[SIFIVE_E_DTIM].size, &error_fatal); | |
117 | memory_region_add_subregion(sys_mem, | |
118 | memmap[SIFIVE_E_DTIM].base, main_mem); | |
119 | ||
651cd8b7 AF |
120 | /* Mask ROM reset vector */ |
121 | uint32_t reset_vec[2] = { | |
122 | 0x204002b7, /* 0x1000: lui t0,0x20400 */ | |
123 | 0x00028067, /* 0x1004: jr t0 */ | |
124 | }; | |
125 | ||
126 | /* copy in the reset vector in little_endian byte order */ | |
127 | for (i = 0; i < sizeof(reset_vec) >> 2; i++) { | |
128 | reset_vec[i] = cpu_to_le32(reset_vec[i]); | |
129 | } | |
130 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
131 | memmap[SIFIVE_E_MROM].base, &address_space_memory); | |
132 | ||
133 | if (machine->kernel_filename) { | |
134 | load_kernel(machine->kernel_filename); | |
135 | } | |
136 | } | |
137 | ||
138 | static void riscv_sifive_e_soc_init(Object *obj) | |
139 | { | |
140 | SiFiveESoCState *s = RISCV_E_SOC(obj); | |
141 | ||
54f3141a AF |
142 | object_initialize_child(obj, "cpus", &s->cpus, |
143 | sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, | |
144 | &error_abort, NULL); | |
651cd8b7 AF |
145 | object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", |
146 | &error_abort); | |
147 | object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", | |
148 | &error_abort); | |
30efbf33 FC |
149 | sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", |
150 | &s->gpio, sizeof(s->gpio), | |
151 | TYPE_SIFIVE_GPIO); | |
651cd8b7 AF |
152 | } |
153 | ||
154 | static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) | |
155 | { | |
156 | const struct MemmapEntry *memmap = sifive_e_memmap; | |
30efbf33 | 157 | Error *err = NULL; |
651cd8b7 AF |
158 | |
159 | SiFiveESoCState *s = RISCV_E_SOC(dev); | |
160 | MemoryRegion *sys_mem = get_system_memory(); | |
161 | MemoryRegion *xip_mem = g_new(MemoryRegion, 1); | |
162 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
163 | ||
164 | object_property_set_bool(OBJECT(&s->cpus), true, "realized", | |
165 | &error_abort); | |
166 | ||
eb637edb | 167 | /* Mask ROM */ |
5aec3247 | 168 | memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom", |
eb637edb MC |
169 | memmap[SIFIVE_E_MROM].size, &error_fatal); |
170 | memory_region_add_subregion(sys_mem, | |
171 | memmap[SIFIVE_E_MROM].base, mask_rom); | |
172 | ||
173 | /* MMIO */ | |
174 | s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, | |
175 | (char *)SIFIVE_E_PLIC_HART_CONFIG, | |
176 | SIFIVE_E_PLIC_NUM_SOURCES, | |
177 | SIFIVE_E_PLIC_NUM_PRIORITIES, | |
178 | SIFIVE_E_PLIC_PRIORITY_BASE, | |
179 | SIFIVE_E_PLIC_PENDING_BASE, | |
180 | SIFIVE_E_PLIC_ENABLE_BASE, | |
181 | SIFIVE_E_PLIC_ENABLE_STRIDE, | |
182 | SIFIVE_E_PLIC_CONTEXT_BASE, | |
183 | SIFIVE_E_PLIC_CONTEXT_STRIDE, | |
184 | memmap[SIFIVE_E_PLIC].size); | |
185 | sifive_clint_create(memmap[SIFIVE_E_CLINT].base, | |
186 | memmap[SIFIVE_E_CLINT].size, smp_cpus, | |
187 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); | |
188 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", | |
189 | memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); | |
190 | sifive_prci_create(memmap[SIFIVE_E_PRCI].base); | |
30efbf33 FC |
191 | |
192 | /* GPIO */ | |
193 | ||
194 | object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); | |
195 | if (err) { | |
196 | error_propagate(errp, err); | |
197 | return; | |
198 | } | |
199 | ||
200 | /* Map GPIO registers */ | |
201 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base); | |
202 | ||
203 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
204 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); | |
205 | ||
206 | /* Connect GPIO interrupts to the PLIC */ | |
207 | for (int i = 0; i < 32; i++) { | |
208 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, | |
209 | qdev_get_gpio_in(DEVICE(s->plic), | |
210 | SIFIVE_E_GPIO0_IRQ0 + i)); | |
211 | } | |
212 | ||
eb637edb | 213 | sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, |
647a70a1 | 214 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); |
eb637edb MC |
215 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", |
216 | memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); | |
217 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", | |
218 | memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); | |
194eef09 MC |
219 | sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, |
220 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); | |
eb637edb MC |
221 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", |
222 | memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); | |
223 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", | |
224 | memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); | |
225 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2", | |
226 | memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); | |
227 | sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2", | |
228 | memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); | |
229 | ||
230 | /* Flash memory */ | |
231 | memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip", | |
232 | memmap[SIFIVE_E_XIP].size, &error_fatal); | |
233 | memory_region_set_readonly(xip_mem, true); | |
234 | memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem); | |
eb637edb MC |
235 | } |
236 | ||
eb637edb MC |
237 | static void riscv_sifive_e_machine_init(MachineClass *mc) |
238 | { | |
239 | mc->desc = "RISC-V Board compatible with SiFive E SDK"; | |
240 | mc->init = riscv_sifive_e_init; | |
241 | mc->max_cpus = 1; | |
242 | } | |
243 | ||
244 | DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) | |
651cd8b7 AF |
245 | |
246 | static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data) | |
247 | { | |
248 | DeviceClass *dc = DEVICE_CLASS(oc); | |
249 | ||
250 | dc->realize = riscv_sifive_e_soc_realize; | |
251 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ | |
252 | dc->user_creatable = false; | |
253 | } | |
254 | ||
255 | static const TypeInfo riscv_sifive_e_soc_type_info = { | |
256 | .name = TYPE_RISCV_E_SOC, | |
257 | .parent = TYPE_DEVICE, | |
258 | .instance_size = sizeof(SiFiveESoCState), | |
259 | .instance_init = riscv_sifive_e_soc_init, | |
260 | .class_init = riscv_sifive_e_soc_class_init, | |
261 | }; | |
262 | ||
263 | static void riscv_sifive_e_soc_register_types(void) | |
264 | { | |
265 | type_register_static(&riscv_sifive_e_soc_type_info); | |
266 | } | |
267 | ||
268 | type_init(riscv_sifive_e_soc_register_types) |