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eb637edb MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom E SDK | |
3 | * | |
4 | * Copyright (c) 2017 SiFive, Inc. | |
5 | * | |
6 | * Provides a board compatible with the SiFive Freedom E SDK: | |
7 | * | |
8 | * 0) UART | |
9 | * 1) CLINT (Core Level Interruptor) | |
10 | * 2) PLIC (Platform Level Interrupt Controller) | |
11 | * 3) PRCI (Power, Reset, Clock, Interrupt) | |
12 | * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM | |
13 | * 5) Flash memory emulated as RAM | |
14 | * | |
15 | * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. | |
16 | * The OTP ROM and Flash boot code will be emulated in a future version. | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or modify it | |
19 | * under the terms and conditions of the GNU General Public License, | |
20 | * version 2 or later, as published by the Free Software Foundation. | |
21 | * | |
22 | * This program is distributed in the hope it will be useful, but WITHOUT | |
23 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
24 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
25 | * more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License along with | |
28 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
29 | */ | |
30 | ||
31 | #include "qemu/osdep.h" | |
e2b3ef75 | 32 | #include "qemu/cutils.h" |
eb637edb MC |
33 | #include "qemu/error-report.h" |
34 | #include "qapi/error.h" | |
eb637edb MC |
35 | #include "hw/boards.h" |
36 | #include "hw/loader.h" | |
37 | #include "hw/sysbus.h" | |
38 | #include "hw/char/serial.h" | |
68c9a9b3 | 39 | #include "hw/misc/unimp.h" |
eb637edb MC |
40 | #include "target/riscv/cpu.h" |
41 | #include "hw/riscv/riscv_hart.h" | |
eb637edb | 42 | #include "hw/riscv/sifive_e.h" |
0ac24d56 | 43 | #include "hw/riscv/boot.h" |
b609b7e3 | 44 | #include "hw/char/sifive_uart.h" |
cc63a182 | 45 | #include "hw/intc/riscv_aclint.h" |
84fcf3c1 | 46 | #include "hw/intc/sifive_plic.h" |
89ece6f7 | 47 | #include "hw/misc/sifive_e_prci.h" |
82193640 | 48 | #include "hw/misc/sifive_e_aon.h" |
eb637edb | 49 | #include "chardev/char.h" |
46517dd4 | 50 | #include "sysemu/sysemu.h" |
eb637edb | 51 | |
3de70cec | 52 | static const MemMapEntry sifive_e_memmap[] = { |
5488f276 EH |
53 | [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 }, |
54 | [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 }, | |
55 | [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 }, | |
56 | [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 }, | |
57 | [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 }, | |
58 | [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 }, | |
59 | [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 }, | |
60 | [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 }, | |
61 | [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 }, | |
62 | [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 }, | |
63 | [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 }, | |
64 | [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 }, | |
65 | [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 }, | |
66 | [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 }, | |
67 | [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 }, | |
68 | [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 }, | |
69 | [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 }, | |
70 | [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 }, | |
71 | [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 } | |
eb637edb MC |
72 | }; |
73 | ||
8f8c6c1a | 74 | static void sifive_e_machine_init(MachineState *machine) |
eb637edb | 75 | { |
e2b3ef75 | 76 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
73261285 | 77 | const MemMapEntry *memmap = sifive_e_memmap; |
eb637edb | 78 | |
0869490b | 79 | SiFiveEState *s = RISCV_E_MACHINE(machine); |
eb637edb | 80 | MemoryRegion *sys_mem = get_system_memory(); |
5aec3247 | 81 | int i; |
eb637edb | 82 | |
e2b3ef75 BM |
83 | if (machine->ram_size != mc->default_ram_size) { |
84 | char *sz = size_to_str(mc->default_ram_size); | |
85 | error_report("Invalid RAM size, should be %s", sz); | |
86 | g_free(sz); | |
87 | exit(EXIT_FAILURE); | |
88 | } | |
89 | ||
651cd8b7 | 90 | /* Initialize SoC */ |
9fc7fc4d | 91 | object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); |
8f972e5b | 92 | qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); |
eb637edb MC |
93 | |
94 | /* Data Tightly Integrated Memory */ | |
eb637edb | 95 | memory_region_add_subregion(sys_mem, |
e2b3ef75 | 96 | memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); |
eb637edb | 97 | |
651cd8b7 | 98 | /* Mask ROM reset vector */ |
495134b7 | 99 | uint32_t reset_vec[4]; |
5a842062 AF |
100 | |
101 | if (s->revb) { | |
495134b7 | 102 | reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ |
5a842062 | 103 | } else { |
495134b7 | 104 | reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ |
5a842062 | 105 | } |
495134b7 BM |
106 | reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ |
107 | ||
108 | reset_vec[0] = reset_vec[3] = 0; | |
651cd8b7 AF |
109 | |
110 | /* copy in the reset vector in little_endian byte order */ | |
111 | for (i = 0; i < sizeof(reset_vec) >> 2; i++) { | |
112 | reset_vec[i] = cpu_to_le32(reset_vec[i]); | |
113 | } | |
114 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
5488f276 | 115 | memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); |
651cd8b7 AF |
116 | |
117 | if (machine->kernel_filename) { | |
62c5bc34 | 118 | riscv_load_kernel(machine, &s->soc.cpus, |
487d73fc DHB |
119 | memmap[SIFIVE_E_DEV_DTIM].base, |
120 | false, NULL); | |
651cd8b7 AF |
121 | } |
122 | } | |
123 | ||
5a842062 AF |
124 | static bool sifive_e_machine_get_revb(Object *obj, Error **errp) |
125 | { | |
126 | SiFiveEState *s = RISCV_E_MACHINE(obj); | |
127 | ||
128 | return s->revb; | |
129 | } | |
130 | ||
131 | static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp) | |
132 | { | |
133 | SiFiveEState *s = RISCV_E_MACHINE(obj); | |
134 | ||
135 | s->revb = value; | |
136 | } | |
137 | ||
0869490b AF |
138 | static void sifive_e_machine_instance_init(Object *obj) |
139 | { | |
5a842062 AF |
140 | SiFiveEState *s = RISCV_E_MACHINE(obj); |
141 | ||
142 | s->revb = false; | |
0869490b AF |
143 | } |
144 | ||
145 | static void sifive_e_machine_class_init(ObjectClass *oc, void *data) | |
146 | { | |
147 | MachineClass *mc = MACHINE_CLASS(oc); | |
148 | ||
149 | mc->desc = "RISC-V Board compatible with SiFive E SDK"; | |
8f8c6c1a | 150 | mc->init = sifive_e_machine_init; |
0869490b AF |
151 | mc->max_cpus = 1; |
152 | mc->default_cpu_type = SIFIVE_E_CPU; | |
e2b3ef75 BM |
153 | mc->default_ram_id = "riscv.sifive.e.ram"; |
154 | mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size; | |
fabbcbd9 EH |
155 | |
156 | object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb, | |
157 | sifive_e_machine_set_revb); | |
158 | object_class_property_set_description(oc, "revb", | |
159 | "Set on to tell QEMU that it should model " | |
160 | "the revB HiFive1 board"); | |
0869490b AF |
161 | } |
162 | ||
163 | static const TypeInfo sifive_e_machine_typeinfo = { | |
164 | .name = MACHINE_TYPE_NAME("sifive_e"), | |
165 | .parent = TYPE_MACHINE, | |
166 | .class_init = sifive_e_machine_class_init, | |
167 | .instance_init = sifive_e_machine_instance_init, | |
168 | .instance_size = sizeof(SiFiveEState), | |
169 | }; | |
170 | ||
171 | static void sifive_e_machine_init_register_types(void) | |
172 | { | |
173 | type_register_static(&sifive_e_machine_typeinfo); | |
174 | } | |
175 | ||
176 | type_init(sifive_e_machine_init_register_types) | |
177 | ||
8f8c6c1a | 178 | static void sifive_e_soc_init(Object *obj) |
651cd8b7 | 179 | { |
c4473127 | 180 | MachineState *ms = MACHINE(qdev_get_machine()); |
651cd8b7 AF |
181 | SiFiveESoCState *s = RISCV_E_SOC(obj); |
182 | ||
db873cc5 | 183 | object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); |
5325cc34 | 184 | object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, |
651cd8b7 | 185 | &error_abort); |
73f6ed97 | 186 | object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); |
db873cc5 MA |
187 | object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, |
188 | TYPE_SIFIVE_GPIO); | |
82193640 TW |
189 | object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon, |
190 | TYPE_SIFIVE_E_AON); | |
651cd8b7 AF |
191 | } |
192 | ||
8f8c6c1a | 193 | static void sifive_e_soc_realize(DeviceState *dev, Error **errp) |
651cd8b7 | 194 | { |
c4473127 | 195 | MachineState *ms = MACHINE(qdev_get_machine()); |
73261285 | 196 | const MemMapEntry *memmap = sifive_e_memmap; |
651cd8b7 AF |
197 | SiFiveESoCState *s = RISCV_E_SOC(dev); |
198 | MemoryRegion *sys_mem = get_system_memory(); | |
651cd8b7 | 199 | |
5325cc34 | 200 | object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, |
74dbba9b | 201 | &error_abort); |
91a3387d | 202 | sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); |
651cd8b7 | 203 | |
eb637edb | 204 | /* Mask ROM */ |
414c47d2 | 205 | memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", |
5488f276 | 206 | memmap[SIFIVE_E_DEV_MROM].size, &error_fatal); |
eb637edb | 207 | memory_region_add_subregion(sys_mem, |
5488f276 | 208 | memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); |
eb637edb MC |
209 | |
210 | /* MMIO */ | |
5488f276 | 211 | s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, |
f436ecc3 | 212 | (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0, |
eb637edb MC |
213 | SIFIVE_E_PLIC_NUM_SOURCES, |
214 | SIFIVE_E_PLIC_NUM_PRIORITIES, | |
215 | SIFIVE_E_PLIC_PRIORITY_BASE, | |
216 | SIFIVE_E_PLIC_PENDING_BASE, | |
217 | SIFIVE_E_PLIC_ENABLE_BASE, | |
218 | SIFIVE_E_PLIC_ENABLE_STRIDE, | |
219 | SIFIVE_E_PLIC_CONTEXT_BASE, | |
220 | SIFIVE_E_PLIC_CONTEXT_STRIDE, | |
5488f276 | 221 | memmap[SIFIVE_E_DEV_PLIC].size); |
b8fb878a AP |
222 | riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base, |
223 | 0, ms->smp.cpus, false); | |
224 | riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base + | |
225 | RISCV_ACLINT_SWI_SIZE, | |
226 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, | |
227 | RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, | |
228 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); | |
5488f276 | 229 | sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); |
30efbf33 | 230 | |
82193640 TW |
231 | /* AON */ |
232 | ||
233 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) { | |
234 | return; | |
235 | } | |
236 | ||
237 | /* Map AON registers */ | |
238 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base); | |
239 | ||
30efbf33 FC |
240 | /* GPIO */ |
241 | ||
668f62ec | 242 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
30efbf33 FC |
243 | return; |
244 | } | |
245 | ||
246 | /* Map GPIO registers */ | |
5488f276 | 247 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base); |
30efbf33 FC |
248 | |
249 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
250 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); | |
251 | ||
252 | /* Connect GPIO interrupts to the PLIC */ | |
253 | for (int i = 0; i < 32; i++) { | |
254 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, | |
255 | qdev_get_gpio_in(DEVICE(s->plic), | |
256 | SIFIVE_E_GPIO0_IRQ0 + i)); | |
257 | } | |
82193640 TW |
258 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0, |
259 | qdev_get_gpio_in(DEVICE(s->plic), | |
260 | SIFIVE_E_AON_WDT_IRQ)); | |
30efbf33 | 261 | |
5488f276 | 262 | sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, |
647a70a1 | 263 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); |
68c9a9b3 | 264 | create_unimplemented_device("riscv.sifive.e.qspi0", |
5488f276 | 265 | memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size); |
68c9a9b3 | 266 | create_unimplemented_device("riscv.sifive.e.pwm0", |
5488f276 EH |
267 | memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size); |
268 | sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base, | |
194eef09 | 269 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); |
68c9a9b3 | 270 | create_unimplemented_device("riscv.sifive.e.qspi1", |
5488f276 | 271 | memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size); |
68c9a9b3 | 272 | create_unimplemented_device("riscv.sifive.e.pwm1", |
5488f276 | 273 | memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size); |
68c9a9b3 | 274 | create_unimplemented_device("riscv.sifive.e.qspi2", |
5488f276 | 275 | memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size); |
68c9a9b3 | 276 | create_unimplemented_device("riscv.sifive.e.pwm2", |
5488f276 | 277 | memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size); |
eb637edb MC |
278 | |
279 | /* Flash memory */ | |
414c47d2 | 280 | memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", |
5488f276 EH |
281 | memmap[SIFIVE_E_DEV_XIP].size, &error_fatal); |
282 | memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base, | |
c988de41 | 283 | &s->xip_mem); |
eb637edb MC |
284 | } |
285 | ||
8f8c6c1a | 286 | static void sifive_e_soc_class_init(ObjectClass *oc, void *data) |
651cd8b7 AF |
287 | { |
288 | DeviceClass *dc = DEVICE_CLASS(oc); | |
289 | ||
8f8c6c1a | 290 | dc->realize = sifive_e_soc_realize; |
651cd8b7 AF |
291 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
292 | dc->user_creatable = false; | |
293 | } | |
294 | ||
8f8c6c1a | 295 | static const TypeInfo sifive_e_soc_type_info = { |
651cd8b7 AF |
296 | .name = TYPE_RISCV_E_SOC, |
297 | .parent = TYPE_DEVICE, | |
298 | .instance_size = sizeof(SiFiveESoCState), | |
8f8c6c1a BM |
299 | .instance_init = sifive_e_soc_init, |
300 | .class_init = sifive_e_soc_class_init, | |
651cd8b7 AF |
301 | }; |
302 | ||
8f8c6c1a | 303 | static void sifive_e_soc_register_types(void) |
651cd8b7 | 304 | { |
8f8c6c1a | 305 | type_register_static(&sifive_e_soc_type_info); |
651cd8b7 AF |
306 | } |
307 | ||
8f8c6c1a | 308 | type_init(sifive_e_soc_register_types) |