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30efbf33 | 1 | /* |
2e30ccb4 | 2 | * SiFive System-on-Chip general purpose input/output register definition |
30efbf33 FC |
3 | * |
4 | * Copyright 2019 AdaCore | |
5 | * | |
6 | * Base on nrf51_gpio.c: | |
7 | * | |
8 | * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> | |
9 | * | |
10 | * This code is licensed under the GPL version 2 or later. See | |
11 | * the COPYING file in the top-level directory. | |
12 | */ | |
13 | ||
14 | #include "qemu/osdep.h" | |
15 | #include "qemu/log.h" | |
64552b6b | 16 | #include "hw/irq.h" |
30efbf33 | 17 | #include "hw/riscv/sifive_gpio.h" |
d6454270 | 18 | #include "migration/vmstate.h" |
30efbf33 FC |
19 | #include "trace.h" |
20 | ||
21 | static void update_output_irq(SIFIVEGPIOState *s) | |
22 | { | |
30efbf33 FC |
23 | uint32_t pending; |
24 | uint32_t pin; | |
25 | ||
26 | pending = s->high_ip & s->high_ie; | |
27 | pending |= s->low_ip & s->low_ie; | |
28 | pending |= s->rise_ip & s->rise_ie; | |
29 | pending |= s->fall_ip & s->fall_ie; | |
30 | ||
31 | for (int i = 0; i < SIFIVE_GPIO_PINS; i++) { | |
32 | pin = 1 << i; | |
33 | qemu_set_irq(s->irq[i], (pending & pin) != 0); | |
34 | trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0); | |
35 | } | |
36 | } | |
37 | ||
38 | static void update_state(SIFIVEGPIOState *s) | |
39 | { | |
40 | size_t i; | |
41 | bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en, | |
42 | rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival; | |
43 | ||
44 | for (i = 0; i < SIFIVE_GPIO_PINS; i++) { | |
45 | ||
46 | prev_ival = extract32(s->value, i, 1); | |
47 | in = extract32(s->in, i, 1); | |
48 | in_mask = extract32(s->in_mask, i, 1); | |
49 | port = extract32(s->port, i, 1); | |
50 | out_xor = extract32(s->out_xor, i, 1); | |
51 | pull = extract32(s->pue, i, 1); | |
52 | output_en = extract32(s->output_en, i, 1); | |
53 | input_en = extract32(s->input_en, i, 1); | |
54 | rise_ip = extract32(s->rise_ip, i, 1); | |
55 | fall_ip = extract32(s->fall_ip, i, 1); | |
56 | low_ip = extract32(s->low_ip, i, 1); | |
57 | high_ip = extract32(s->high_ip, i, 1); | |
58 | ||
59 | /* Output value (IOF not supported) */ | |
60 | oval = output_en && (port ^ out_xor); | |
61 | ||
62 | /* Pin both driven externally and internally */ | |
63 | if (output_en && in_mask) { | |
64 | qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i); | |
65 | } | |
66 | ||
67 | if (in_mask) { | |
68 | /* The pin is driven by external device */ | |
69 | actual_value = in; | |
70 | } else if (output_en) { | |
71 | /* The pin is driven by internal circuit */ | |
72 | actual_value = oval; | |
73 | } else { | |
74 | /* Floating? Apply pull-up resistor */ | |
75 | actual_value = pull; | |
76 | } | |
77 | ||
78 | qemu_set_irq(s->output[i], actual_value); | |
79 | ||
80 | /* Input value */ | |
81 | ival = input_en && actual_value; | |
82 | ||
83 | /* Interrupts */ | |
84 | high_ip = high_ip || ival; | |
85 | s->high_ip = deposit32(s->high_ip, i, 1, high_ip); | |
86 | ||
87 | low_ip = low_ip || !ival; | |
88 | s->low_ip = deposit32(s->low_ip, i, 1, low_ip); | |
89 | ||
90 | rise_ip = rise_ip || (ival && !prev_ival); | |
91 | s->rise_ip = deposit32(s->rise_ip, i, 1, rise_ip); | |
92 | ||
93 | fall_ip = fall_ip || (!ival && prev_ival); | |
94 | s->fall_ip = deposit32(s->fall_ip, i, 1, fall_ip); | |
95 | ||
96 | /* Update value */ | |
97 | s->value = deposit32(s->value, i, 1, ival); | |
98 | } | |
99 | update_output_irq(s); | |
100 | } | |
101 | ||
102 | static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size) | |
103 | { | |
104 | SIFIVEGPIOState *s = SIFIVE_GPIO(opaque); | |
105 | uint64_t r = 0; | |
106 | ||
107 | switch (offset) { | |
108 | case SIFIVE_GPIO_REG_VALUE: | |
109 | r = s->value; | |
110 | break; | |
111 | ||
112 | case SIFIVE_GPIO_REG_INPUT_EN: | |
113 | r = s->input_en; | |
114 | break; | |
115 | ||
116 | case SIFIVE_GPIO_REG_OUTPUT_EN: | |
117 | r = s->output_en; | |
118 | break; | |
119 | ||
120 | case SIFIVE_GPIO_REG_PORT: | |
121 | r = s->port; | |
122 | break; | |
123 | ||
124 | case SIFIVE_GPIO_REG_PUE: | |
125 | r = s->pue; | |
126 | break; | |
127 | ||
128 | case SIFIVE_GPIO_REG_DS: | |
129 | r = s->ds; | |
130 | break; | |
131 | ||
132 | case SIFIVE_GPIO_REG_RISE_IE: | |
133 | r = s->rise_ie; | |
134 | break; | |
135 | ||
136 | case SIFIVE_GPIO_REG_RISE_IP: | |
137 | r = s->rise_ip; | |
138 | break; | |
139 | ||
140 | case SIFIVE_GPIO_REG_FALL_IE: | |
141 | r = s->fall_ie; | |
142 | break; | |
143 | ||
144 | case SIFIVE_GPIO_REG_FALL_IP: | |
145 | r = s->fall_ip; | |
146 | break; | |
147 | ||
148 | case SIFIVE_GPIO_REG_HIGH_IE: | |
149 | r = s->high_ie; | |
150 | break; | |
151 | ||
152 | case SIFIVE_GPIO_REG_HIGH_IP: | |
153 | r = s->high_ip; | |
154 | break; | |
155 | ||
156 | case SIFIVE_GPIO_REG_LOW_IE: | |
157 | r = s->low_ie; | |
158 | break; | |
159 | ||
160 | case SIFIVE_GPIO_REG_LOW_IP: | |
161 | r = s->low_ip; | |
162 | break; | |
163 | ||
164 | case SIFIVE_GPIO_REG_IOF_EN: | |
165 | r = s->iof_en; | |
166 | break; | |
167 | ||
168 | case SIFIVE_GPIO_REG_IOF_SEL: | |
169 | r = s->iof_sel; | |
170 | break; | |
171 | ||
172 | case SIFIVE_GPIO_REG_OUT_XOR: | |
173 | r = s->out_xor; | |
174 | break; | |
175 | ||
176 | default: | |
177 | qemu_log_mask(LOG_GUEST_ERROR, | |
178 | "%s: bad read offset 0x%" HWADDR_PRIx "\n", | |
179 | __func__, offset); | |
180 | } | |
181 | ||
182 | trace_sifive_gpio_read(offset, r); | |
183 | ||
184 | return r; | |
185 | } | |
186 | ||
187 | static void sifive_gpio_write(void *opaque, hwaddr offset, | |
2e30ccb4 | 188 | uint64_t value, unsigned int size) |
30efbf33 FC |
189 | { |
190 | SIFIVEGPIOState *s = SIFIVE_GPIO(opaque); | |
191 | ||
192 | trace_sifive_gpio_write(offset, value); | |
193 | ||
194 | switch (offset) { | |
195 | ||
196 | case SIFIVE_GPIO_REG_INPUT_EN: | |
197 | s->input_en = value; | |
198 | break; | |
199 | ||
200 | case SIFIVE_GPIO_REG_OUTPUT_EN: | |
201 | s->output_en = value; | |
202 | break; | |
203 | ||
204 | case SIFIVE_GPIO_REG_PORT: | |
205 | s->port = value; | |
206 | break; | |
207 | ||
208 | case SIFIVE_GPIO_REG_PUE: | |
209 | s->pue = value; | |
210 | break; | |
211 | ||
212 | case SIFIVE_GPIO_REG_DS: | |
213 | s->ds = value; | |
214 | break; | |
215 | ||
216 | case SIFIVE_GPIO_REG_RISE_IE: | |
217 | s->rise_ie = value; | |
218 | break; | |
219 | ||
220 | case SIFIVE_GPIO_REG_RISE_IP: | |
221 | /* Write 1 to clear */ | |
222 | s->rise_ip &= ~value; | |
223 | break; | |
224 | ||
225 | case SIFIVE_GPIO_REG_FALL_IE: | |
226 | s->fall_ie = value; | |
227 | break; | |
228 | ||
229 | case SIFIVE_GPIO_REG_FALL_IP: | |
230 | /* Write 1 to clear */ | |
231 | s->fall_ip &= ~value; | |
232 | break; | |
233 | ||
234 | case SIFIVE_GPIO_REG_HIGH_IE: | |
235 | s->high_ie = value; | |
236 | break; | |
237 | ||
238 | case SIFIVE_GPIO_REG_HIGH_IP: | |
239 | /* Write 1 to clear */ | |
240 | s->high_ip &= ~value; | |
241 | break; | |
242 | ||
243 | case SIFIVE_GPIO_REG_LOW_IE: | |
244 | s->low_ie = value; | |
245 | break; | |
246 | ||
247 | case SIFIVE_GPIO_REG_LOW_IP: | |
248 | /* Write 1 to clear */ | |
249 | s->low_ip &= ~value; | |
250 | break; | |
251 | ||
252 | case SIFIVE_GPIO_REG_IOF_EN: | |
253 | s->iof_en = value; | |
254 | break; | |
255 | ||
256 | case SIFIVE_GPIO_REG_IOF_SEL: | |
257 | s->iof_sel = value; | |
258 | break; | |
259 | ||
260 | case SIFIVE_GPIO_REG_OUT_XOR: | |
261 | s->out_xor = value; | |
262 | break; | |
263 | ||
264 | default: | |
265 | qemu_log_mask(LOG_GUEST_ERROR, | |
266 | "%s: bad write offset 0x%" HWADDR_PRIx "\n", | |
267 | __func__, offset); | |
268 | } | |
269 | ||
270 | update_state(s); | |
271 | } | |
272 | ||
273 | static const MemoryRegionOps gpio_ops = { | |
274 | .read = sifive_gpio_read, | |
275 | .write = sifive_gpio_write, | |
276 | .endianness = DEVICE_LITTLE_ENDIAN, | |
277 | .impl.min_access_size = 4, | |
278 | .impl.max_access_size = 4, | |
279 | }; | |
280 | ||
281 | static void sifive_gpio_set(void *opaque, int line, int value) | |
282 | { | |
283 | SIFIVEGPIOState *s = SIFIVE_GPIO(opaque); | |
284 | ||
285 | trace_sifive_gpio_set(line, value); | |
286 | ||
287 | assert(line >= 0 && line < SIFIVE_GPIO_PINS); | |
288 | ||
289 | s->in_mask = deposit32(s->in_mask, line, 1, value >= 0); | |
290 | if (value >= 0) { | |
291 | s->in = deposit32(s->in, line, 1, value != 0); | |
292 | } | |
293 | ||
294 | update_state(s); | |
295 | } | |
296 | ||
297 | static void sifive_gpio_reset(DeviceState *dev) | |
298 | { | |
299 | SIFIVEGPIOState *s = SIFIVE_GPIO(dev); | |
300 | ||
301 | s->value = 0; | |
302 | s->input_en = 0; | |
303 | s->output_en = 0; | |
304 | s->port = 0; | |
305 | s->pue = 0; | |
306 | s->ds = 0; | |
307 | s->rise_ie = 0; | |
308 | s->rise_ip = 0; | |
309 | s->fall_ie = 0; | |
310 | s->fall_ip = 0; | |
311 | s->high_ie = 0; | |
312 | s->high_ip = 0; | |
313 | s->low_ie = 0; | |
314 | s->low_ip = 0; | |
315 | s->iof_en = 0; | |
316 | s->iof_sel = 0; | |
317 | s->out_xor = 0; | |
318 | s->in = 0; | |
319 | s->in_mask = 0; | |
30efbf33 FC |
320 | } |
321 | ||
322 | static const VMStateDescription vmstate_sifive_gpio = { | |
323 | .name = TYPE_SIFIVE_GPIO, | |
324 | .version_id = 1, | |
325 | .minimum_version_id = 1, | |
326 | .fields = (VMStateField[]) { | |
327 | VMSTATE_UINT32(value, SIFIVEGPIOState), | |
328 | VMSTATE_UINT32(input_en, SIFIVEGPIOState), | |
329 | VMSTATE_UINT32(output_en, SIFIVEGPIOState), | |
330 | VMSTATE_UINT32(port, SIFIVEGPIOState), | |
331 | VMSTATE_UINT32(pue, SIFIVEGPIOState), | |
332 | VMSTATE_UINT32(rise_ie, SIFIVEGPIOState), | |
333 | VMSTATE_UINT32(rise_ip, SIFIVEGPIOState), | |
334 | VMSTATE_UINT32(fall_ie, SIFIVEGPIOState), | |
335 | VMSTATE_UINT32(fall_ip, SIFIVEGPIOState), | |
336 | VMSTATE_UINT32(high_ie, SIFIVEGPIOState), | |
337 | VMSTATE_UINT32(high_ip, SIFIVEGPIOState), | |
338 | VMSTATE_UINT32(low_ie, SIFIVEGPIOState), | |
339 | VMSTATE_UINT32(low_ip, SIFIVEGPIOState), | |
340 | VMSTATE_UINT32(iof_en, SIFIVEGPIOState), | |
341 | VMSTATE_UINT32(iof_sel, SIFIVEGPIOState), | |
342 | VMSTATE_UINT32(out_xor, SIFIVEGPIOState), | |
2e30ccb4 BM |
343 | VMSTATE_UINT32(in, SIFIVEGPIOState), |
344 | VMSTATE_UINT32(in_mask, SIFIVEGPIOState), | |
30efbf33 FC |
345 | VMSTATE_END_OF_LIST() |
346 | } | |
347 | }; | |
348 | ||
349 | static void sifive_gpio_init(Object *obj) | |
350 | { | |
351 | SIFIVEGPIOState *s = SIFIVE_GPIO(obj); | |
352 | ||
353 | memory_region_init_io(&s->mmio, obj, &gpio_ops, s, | |
354 | TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE); | |
355 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | |
356 | ||
30efbf33 FC |
357 | for (int i = 0; i < SIFIVE_GPIO_PINS; i++) { |
358 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); | |
359 | } | |
360 | ||
361 | qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, SIFIVE_GPIO_PINS); | |
362 | qdev_init_gpio_out(DEVICE(s), s->output, SIFIVE_GPIO_PINS); | |
363 | } | |
364 | ||
365 | static void sifive_gpio_class_init(ObjectClass *klass, void *data) | |
366 | { | |
367 | DeviceClass *dc = DEVICE_CLASS(klass); | |
368 | ||
369 | dc->vmsd = &vmstate_sifive_gpio; | |
370 | dc->reset = sifive_gpio_reset; | |
2e30ccb4 | 371 | dc->desc = "SiFive GPIO"; |
30efbf33 FC |
372 | } |
373 | ||
374 | static const TypeInfo sifive_gpio_info = { | |
375 | .name = TYPE_SIFIVE_GPIO, | |
376 | .parent = TYPE_SYS_BUS_DEVICE, | |
377 | .instance_size = sizeof(SIFIVEGPIOState), | |
378 | .instance_init = sifive_gpio_init, | |
379 | .class_init = sifive_gpio_class_init | |
380 | }; | |
381 | ||
382 | static void sifive_gpio_register_types(void) | |
383 | { | |
384 | type_register_static(&sifive_gpio_info); | |
385 | } | |
386 | ||
387 | type_init(sifive_gpio_register_types) |