[mirror_qemu.git] / hw / riscv / sifive_u.c

/*
 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
 * Copyright (c) 2017 SiFive, Inc.
 *
 * Provides a board compatible with the SiFive Freedom U SDK:
 *
 * 0) UART
 * 1) CLINT (Core Level Interruptor)
 * 2) PLIC (Platform Level Interrupt Controller)
 *
 * This board currently uses a hardcoded devicetree that indicates one hart.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
#include "elf.h"

#include <libfdt.h>

static const struct MemmapEntry {
    hwaddr base;
    hwaddr size;
} sifive_u_memmap[] = {
    [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
    [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
    [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
    [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
    [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },
    [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
    [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
};

static uint64_t load_kernel(const char *kernel_filename)
{
    uint64_t kernel_entry, kernel_high;

    if (load_elf(kernel_filename, NULL, NULL,
                 &kernel_entry, NULL, &kernel_high,
                 0, EM_RISCV, 1, 0) < 0) {
        error_report("qemu: could not load kernel '%s'", kernel_filename);
        exit(1);
    }
    return kernel_entry;
}

static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
    uint64_t mem_size, const char *cmdline)
{
    void *fdt;
    int cpu;
    uint32_t *cells;
    char *nodename;
    uint32_t plic_phandle;

    fdt = s->fdt = create_device_tree(&s->fdt_size);
    if (!fdt) {
        error_report("create_device_tree() failed");
        exit(1);
    }

    qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
    qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);

    qemu_fdt_add_subnode(fdt, "/soc");
    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");
    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);

    nodename = g_strdup_printf("/memory@%lx",
        (long)memmap[SIFIVE_U_DRAM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
        mem_size >> 32, mem_size);
    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
    g_free(nodename);

    qemu_fdt_add_subnode(fdt, "/cpus");
    qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
        SIFIVE_CLINT_TIMEBASE_FREQ);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);

    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
        qemu_fdt_add_subnode(fdt, nodename);
        qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
                              SIFIVE_U_CLOCK_FREQ);
        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
        qemu_fdt_add_subnode(fdt, intc);
        qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
        qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
        g_free(isa);
        g_free(intc);
        g_free(nodename);
    }

    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/clint@%lx",
        (long)memmap[SIFIVE_U_CLINT].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_CLINT].base,
        0x0, memmap[SIFIVE_U_CLINT].size);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
    g_free(cells);
    g_free(nodename);

    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
        (long)memmap[SIFIVE_U_PLIC].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_PLIC].base,
        0x0, memmap[SIFIVE_U_PLIC].size);
    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4);
    qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
    qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
    plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
    g_free(cells);
    g_free(nodename);

    nodename = g_strdup_printf("/uart@%lx",
        (long)memmap[SIFIVE_U_UART0].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_UART0].base,
        0x0, memmap[SIFIVE_U_UART0].size);
    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);

    qemu_fdt_add_subnode(fdt, "/chosen");
    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
    qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
    g_free(nodename);
}

static void riscv_sifive_u_init(MachineState *machine)
{
    const struct MemmapEntry *memmap = sifive_u_memmap;

    SiFiveUState *s = g_new0(SiFiveUState, 1);
    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
    int i;

    /* Initialize SOC */
    object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
    object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
                              &error_abort);
    object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type",
                            &error_abort);
    object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->soc), true, "realized",
                            &error_abort);

    /* register RAM */
    memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
                           machine->ram_size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
        main_mem);

    /* create device tree */
    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);

    /* boot rom */
    memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
                           memmap[SIFIVE_U_MROM].size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
                                mask_rom);

    if (machine->kernel_filename) {
        load_kernel(machine->kernel_filename);
    }

    /* reset vector */
    uint32_t reset_vec[8] = {
        0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
        0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
        0xf1402573,                    /*     csrr   a0, mhartid  */
#if defined(TARGET_RISCV32)
        0x0182a283,                    /*     lw     t0, 24(t0) */
#elif defined(TARGET_RISCV64)
        0x0182b283,                    /*     ld     t0, 24(t0) */
#endif
        0x00028067,                    /*     jr     t0 */
        0x00000000,
        memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
        0x00000000,
                                       /* dtb: */
    };

    /* copy in the reset vector in little_endian byte order */
    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
        reset_vec[i] = cpu_to_le32(reset_vec[i]);
    }
    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                          memmap[SIFIVE_U_MROM].base, &address_space_memory);

    /* copy in the device tree */
    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
            memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
        error_report("not enough space to store device-tree");
        exit(1);
    }
    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
                          memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
                          &address_space_memory);

    /* MMIO */
    s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
        (char *)SIFIVE_U_PLIC_HART_CONFIG,
        SIFIVE_U_PLIC_NUM_SOURCES,
        SIFIVE_U_PLIC_NUM_PRIORITIES,
        SIFIVE_U_PLIC_PRIORITY_BASE,
        SIFIVE_U_PLIC_PENDING_BASE,
        SIFIVE_U_PLIC_ENABLE_BASE,
        SIFIVE_U_PLIC_ENABLE_STRIDE,
        SIFIVE_U_PLIC_CONTEXT_BASE,
        SIFIVE_U_PLIC_CONTEXT_STRIDE,
        memmap[SIFIVE_U_PLIC].size);
    sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
        serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]);
    /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
        serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */
    sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
        memmap[SIFIVE_U_CLINT].size, smp_cpus,
        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
}

static void riscv_sifive_u_machine_init(MachineClass *mc)
{
    mc->desc = "RISC-V Board compatible with SiFive U SDK";
    mc->init = riscv_sifive_u_init;
    mc->max_cpus = 1;
}

DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
Commit	Line	Data
a7240d1e MC	1	/*
	2	* QEMU RISC-V Board Compatible with SiFive Freedom U SDK
	3	*
	4	* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
	5	* Copyright (c) 2017 SiFive, Inc.
	6	*
	7	* Provides a board compatible with the SiFive Freedom U SDK:
	8	*
	9	* 0) UART
	10	* 1) CLINT (Core Level Interruptor)
	11	* 2) PLIC (Platform Level Interrupt Controller)
	12	*
	13	* This board currently uses a hardcoded devicetree that indicates one hart.
	14	*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms and conditions of the GNU General Public License,
	17	* version 2 or later, as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope it will be useful, but WITHOUT
	20	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	21	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	22	* more details.
	23	*
	24	* You should have received a copy of the GNU General Public License along with
	25	* this program. If not, see <http://www.gnu.org/licenses/>.
	26	*/
	27
	28	#include "qemu/osdep.h"
	29	#include "qemu/log.h"
	30	#include "qemu/error-report.h"
	31	#include "qapi/error.h"
	32	#include "hw/hw.h"
	33	#include "hw/boards.h"
	34	#include "hw/loader.h"
	35	#include "hw/sysbus.h"
	36	#include "hw/char/serial.h"
	37	#include "target/riscv/cpu.h"
	38	#include "hw/riscv/riscv_hart.h"
	39	#include "hw/riscv/sifive_plic.h"
	40	#include "hw/riscv/sifive_clint.h"
	41	#include "hw/riscv/sifive_uart.h"
	42	#include "hw/riscv/sifive_prci.h"
	43	#include "hw/riscv/sifive_u.h"
	44	#include "chardev/char.h"
	45	#include "sysemu/arch_init.h"
	46	#include "sysemu/device_tree.h"
	47	#include "exec/address-spaces.h"
	48	#include "elf.h"
	49
5aec3247 MC	50	#include <libfdt.h>
5aec3247 MC	51
a7240d1e MC	52	static const struct MemmapEntry {
	53	hwaddr base;
	54	hwaddr size;
	55	} sifive_u_memmap[] = {
	56	[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
5aec3247	57	[SIFIVE_U_MROM] = { 0x1000, 0x11000 },
a7240d1e MC	58	[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
	59	[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
	60	[SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
	61	[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
	62	[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
	63	};
	64
a7240d1e MC	65	static uint64_t load_kernel(const char *kernel_filename)
	66	{
	67	uint64_t kernel_entry, kernel_high;
	68
b7938980	69	if (load_elf(kernel_filename, NULL, NULL,
a7240d1e	70	&kernel_entry, NULL, &kernel_high,
89854803	71	0, EM_RISCV, 1, 0) < 0) {
a7240d1e MC	72	error_report("qemu: could not load kernel '%s'", kernel_filename);
	73	exit(1);
	74	}
	75	return kernel_entry;
	76	}
	77
	78	static void create_fdt(SiFiveUState s, const struct MemmapEntry memmap,
	79	uint64_t mem_size, const char *cmdline)
	80	{
	81	void *fdt;
	82	int cpu;
	83	uint32_t *cells;
	84	char *nodename;
	85	uint32_t plic_phandle;
	86
	87	fdt = s->fdt = create_device_tree(&s->fdt_size);
	88	if (!fdt) {
	89	error_report("create_device_tree() failed");
	90	exit(1);
	91	}
	92
	93	qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
	94	qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
	95	qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
	96	qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
	97
	98	qemu_fdt_add_subnode(fdt, "/soc");
	99	qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
	100	qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");
	101	qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
	102	qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
	103
	104	nodename = g_strdup_printf("/memory@%lx",
	105	(long)memmap[SIFIVE_U_DRAM].base);
	106	qemu_fdt_add_subnode(fdt, nodename);
	107	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	108	memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
	109	mem_size >> 32, mem_size);
	110	qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
	111	g_free(nodename);
	112
	113	qemu_fdt_add_subnode(fdt, "/cpus");
2a8756ed MC	114	qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
2a8756ed MC	115	SIFIVE_CLINT_TIMEBASE_FREQ);
a7240d1e MC	116	qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
	117	qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
	118
	119	for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
	120	nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
	121	char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	122	char *isa = riscv_isa_string(&s->soc.harts[cpu]);
	123	qemu_fdt_add_subnode(fdt, nodename);
2a8756ed MC	124	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
2a8756ed MC	125	SIFIVE_U_CLOCK_FREQ);
a7240d1e MC	126	qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
	127	qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
	128	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
	129	qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
	130	qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
	131	qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
	132	qemu_fdt_add_subnode(fdt, intc);
	133	qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
	134	qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
	135	qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
	136	qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
	137	qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
	138	g_free(isa);
	139	g_free(intc);
	140	g_free(nodename);
	141	}
	142
	143	cells = g_new0(uint32_t, s->soc.num_harts * 4);
	144	for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
	145	nodename =
	146	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	147	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	148	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	149	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
	150	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	151	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
	152	g_free(nodename);
	153	}
	154	nodename = g_strdup_printf("/soc/clint@%lx",
	155	(long)memmap[SIFIVE_U_CLINT].base);
	156	qemu_fdt_add_subnode(fdt, nodename);
	157	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
	158	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	159	0x0, memmap[SIFIVE_U_CLINT].base,
	160	0x0, memmap[SIFIVE_U_CLINT].size);
	161	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
	162	cells, s->soc.num_harts * sizeof(uint32_t) * 4);
	163	g_free(cells);
	164	g_free(nodename);
	165
	166	cells = g_new0(uint32_t, s->soc.num_harts * 4);
	167	for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
	168	nodename =
	169	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	170	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	171	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	172	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
	173	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	174	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
	175	g_free(nodename);
	176	}
	177	nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
	178	(long)memmap[SIFIVE_U_PLIC].base);
	179	qemu_fdt_add_subnode(fdt, nodename);
	180	qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
	181	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
	182	qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
	183	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
	184	cells, s->soc.num_harts * sizeof(uint32_t) * 4);
	185	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	186	0x0, memmap[SIFIVE_U_PLIC].base,
	187	0x0, memmap[SIFIVE_U_PLIC].size);
	188	qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
	189	qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
190	qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4);
191	qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
192	qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
193	plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
194	g_free(cells);
195	g_free(nodename);
196
197	nodename = g_strdup_printf("/uart@%lx",
198	(long)memmap[SIFIVE_U_UART0].base);
199	qemu_fdt_add_subnode(fdt, nodename);
200	qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
201	qemu_fdt_setprop_cells(fdt, nodename, "reg",
202	0x0, memmap[SIFIVE_U_UART0].base,
203	0x0, memmap[SIFIVE_U_UART0].size);
204	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
205	qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
206
207	qemu_fdt_add_subnode(fdt, "/chosen");
208	qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
209	qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
210	g_free(nodename);
211	}
212
213	static void riscv_sifive_u_init(MachineState *machine)
214	{
215	const struct MemmapEntry *memmap = sifive_u_memmap;
216
217	SiFiveUState *s = g_new0(SiFiveUState, 1);
5aec3247	218	MemoryRegion *system_memory = get_system_memory();
a7240d1e	219	MemoryRegion *main_mem = g_new(MemoryRegion, 1);
5aec3247 MC	220	MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
5aec3247 MC	221	int i;
a7240d1e MC	222
	223	/* Initialize SOC */
	224	object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
	225	object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
	226	&error_abort);
	227	object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type",
	228	&error_abort);
	229	object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
	230	&error_abort);
	231	object_property_set_bool(OBJECT(&s->soc), true, "realized",
	232	&error_abort);
	233
	234	/* register RAM */
	235	memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
	236	machine->ram_size, &error_fatal);
5aec3247	237	memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
a7240d1e MC	238	main_mem);
	239
	240	/* create device tree */
	241	create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
	242
	243	/* boot rom */
5aec3247 MC	244	memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
	245	memmap[SIFIVE_U_MROM].size, &error_fatal);
	246	memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
	247	mask_rom);
a7240d1e MC	248
	249	if (machine->kernel_filename) {
	250	load_kernel(machine->kernel_filename);
	251	}
	252
	253	/* reset vector */
	254	uint32_t reset_vec[8] = {
	255	0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
	256	0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
	257	0xf1402573, /* csrr a0, mhartid */
	258	#if defined(TARGET_RISCV32)
	259	0x0182a283, /* lw t0, 24(t0) */
	260	#elif defined(TARGET_RISCV64)
	261	0x0182b283, /* ld t0, 24(t0) */
	262	#endif
	263	0x00028067, /* jr t0 */
	264	0x00000000,
	265	memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
	266	0x00000000,
	267	/* dtb: */
	268	};
	269
5aec3247 MC	270	/* copy in the reset vector in little_endian byte order */
	271	for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
	272	reset_vec[i] = cpu_to_le32(reset_vec[i]);
	273	}
	274	rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
	275	memmap[SIFIVE_U_MROM].base, &address_space_memory);
a7240d1e MC	276
a7240d1e MC	277	/* copy in the device tree */
5aec3247 MC	278	if (fdt_pack(s->fdt) \|\| fdt_totalsize(s->fdt) >
	279	memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
	280	error_report("not enough space to store device-tree");
	281	exit(1);
	282	}
	283	qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
	284	rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
	285	memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
	286	&address_space_memory);
a7240d1e MC	287
	288	/* MMIO */
	289	s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
	290	(char *)SIFIVE_U_PLIC_HART_CONFIG,
	291	SIFIVE_U_PLIC_NUM_SOURCES,
	292	SIFIVE_U_PLIC_NUM_PRIORITIES,
	293	SIFIVE_U_PLIC_PRIORITY_BASE,
	294	SIFIVE_U_PLIC_PENDING_BASE,
	295	SIFIVE_U_PLIC_ENABLE_BASE,
	296	SIFIVE_U_PLIC_ENABLE_STRIDE,
	297	SIFIVE_U_PLIC_CONTEXT_BASE,
	298	SIFIVE_U_PLIC_CONTEXT_STRIDE,
	299	memmap[SIFIVE_U_PLIC].size);
5aec3247	300	sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
9bca0edb	301	serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]);
5aec3247	302	/* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
9bca0edb	303	serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */
a7240d1e MC	304	sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
	305	memmap[SIFIVE_U_CLINT].size, smp_cpus,
	306	SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
	307	}
	308
a7240d1e MC	309	static void riscv_sifive_u_machine_init(MachineClass *mc)
	310	{
	311	mc->desc = "RISC-V Board compatible with SiFive U SDK";
	312	mc->init = riscv_sifive_u_init;
	313	mc->max_cpus = 1;
	314	}
	315
	316	DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)