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a7240d1e MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017 SiFive, Inc. | |
7b6bb66f | 6 | * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> |
a7240d1e MC |
7 | * |
8 | * Provides a board compatible with the SiFive Freedom U SDK: | |
9 | * | |
10 | * 0) UART | |
11 | * 1) CLINT (Core Level Interruptor) | |
12 | * 2) PLIC (Platform Level Interrupt Controller) | |
af14c840 | 13 | * 3) PRCI (Power, Reset, Clock, Interrupt) |
8a88b9f5 BM |
14 | * 4) GPIO (General Purpose Input/Output Controller) |
15 | * 5) OTP (One-Time Programmable) memory with stored serial number | |
16 | * 6) GEM (Gigabit Ethernet Controller) and management block | |
834e027a | 17 | * 7) DMA (Direct Memory Access Controller) |
145b2991 | 18 | * 8) SPI0 connected to an SPI flash |
722f1352 | 19 | * 9) SPI2 connected to an SD card |
ea6eaa06 | 20 | * 10) PWM0 and PWM1 |
a7240d1e | 21 | * |
f3d47d58 | 22 | * This board currently generates devicetree dynamically that indicates at least |
ecdfe393 | 23 | * two harts and up to five harts. |
a7240d1e MC |
24 | * |
25 | * This program is free software; you can redistribute it and/or modify it | |
26 | * under the terms and conditions of the GNU General Public License, | |
27 | * version 2 or later, as published by the Free Software Foundation. | |
28 | * | |
29 | * This program is distributed in the hope it will be useful, but WITHOUT | |
30 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
31 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
32 | * more details. | |
33 | * | |
34 | * You should have received a copy of the GNU General Public License along with | |
35 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
36 | */ | |
37 | ||
38 | #include "qemu/osdep.h" | |
a7240d1e MC |
39 | #include "qemu/error-report.h" |
40 | #include "qapi/error.h" | |
3ca109c3 | 41 | #include "qapi/visitor.h" |
a7240d1e | 42 | #include "hw/boards.h" |
5133ed17 | 43 | #include "hw/irq.h" |
a7240d1e MC |
44 | #include "hw/loader.h" |
45 | #include "hw/sysbus.h" | |
46 | #include "hw/char/serial.h" | |
ecdfe393 | 47 | #include "hw/cpu/cluster.h" |
7b6bb66f | 48 | #include "hw/misc/unimp.h" |
36aa285f | 49 | #include "hw/sd/sd.h" |
145b2991 | 50 | #include "hw/ssi/ssi.h" |
a7240d1e MC |
51 | #include "target/riscv/cpu.h" |
52 | #include "hw/riscv/riscv_hart.h" | |
a7240d1e | 53 | #include "hw/riscv/sifive_u.h" |
0ac24d56 | 54 | #include "hw/riscv/boot.h" |
b609b7e3 | 55 | #include "hw/char/sifive_uart.h" |
cc63a182 | 56 | #include "hw/intc/riscv_aclint.h" |
84fcf3c1 | 57 | #include "hw/intc/sifive_plic.h" |
a7240d1e | 58 | #include "chardev/char.h" |
7b6bb66f | 59 | #include "net/eth.h" |
a7240d1e | 60 | #include "sysemu/device_tree.h" |
5133ed17 | 61 | #include "sysemu/runstate.h" |
46517dd4 | 62 | #include "sysemu/sysemu.h" |
a7240d1e | 63 | |
5aec3247 MC |
64 | #include <libfdt.h> |
65 | ||
074ca702 BM |
66 | /* CLINT timebase frequency */ |
67 | #define CLINT_TIMEBASE_FREQ 1000000 | |
68 | ||
73261285 | 69 | static const MemMapEntry sifive_u_memmap[] = { |
13b8c354 EH |
70 | [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, |
71 | [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, | |
72 | [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, | |
73 | [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, | |
74 | [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, | |
75 | [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, | |
76 | [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, | |
77 | [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, | |
78 | [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, | |
79 | [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, | |
ea6eaa06 AF |
80 | [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 }, |
81 | [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 }, | |
145b2991 | 82 | [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, |
722f1352 | 83 | [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, |
13b8c354 EH |
84 | [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, |
85 | [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, | |
86 | [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, | |
87 | [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, | |
88 | [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, | |
89 | [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, | |
90 | [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, | |
a7240d1e MC |
91 | }; |
92 | ||
5461c4fe | 93 | #define OTP_SERIAL 1 |
5a7f76a3 AF |
94 | #define GEM_REVISION 0x10070109 |
95 | ||
73261285 | 96 | static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, |
f5be2ccb | 97 | bool is_32_bit) |
a7240d1e | 98 | { |
f5be2ccb DHB |
99 | MachineState *ms = MACHINE(s); |
100 | uint64_t mem_size = ms->ram_size; | |
a7240d1e | 101 | void *fdt; |
fc9ec362 | 102 | int cpu; |
a7240d1e MC |
103 | uint32_t *cells; |
104 | char *nodename; | |
5133ed17 | 105 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; |
7b6bb66f | 106 | uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; |
cb53b283 | 107 | static const char * const ethclk_names[2] = { "pclk", "hclk" }; |
7cfbb17f BM |
108 | static const char * const clint_compat[2] = { |
109 | "sifive,clint0", "riscv,clint0" | |
110 | }; | |
60bb5407 BM |
111 | static const char * const plic_compat[2] = { |
112 | "sifive,plic-1.0.0", "riscv,plic0" | |
113 | }; | |
a7240d1e | 114 | |
fc9ec362 BM |
115 | fdt = ms->fdt = create_device_tree(&s->fdt_size); |
116 | if (!fdt) { | |
117 | error_report("create_device_tree() failed"); | |
118 | exit(1); | |
a7240d1e MC |
119 | } |
120 | ||
d372e748 BM |
121 | qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); |
122 | qemu_fdt_setprop_string(fdt, "/", "compatible", | |
123 | "sifive,hifive-unleashed-a00"); | |
a7240d1e MC |
124 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); |
125 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
126 | ||
127 | qemu_fdt_add_subnode(fdt, "/soc"); | |
128 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
2a1a6f6d | 129 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
a7240d1e MC |
130 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
131 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
132 | ||
e1724d09 BM |
133 | hfclk_phandle = phandle++; |
134 | nodename = g_strdup_printf("/hfclk"); | |
135 | qemu_fdt_add_subnode(fdt, nodename); | |
136 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); | |
137 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); | |
138 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
139 | SIFIVE_U_HFCLK_FREQ); | |
140 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
141 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
142 | g_free(nodename); | |
143 | ||
144 | rtcclk_phandle = phandle++; | |
145 | nodename = g_strdup_printf("/rtcclk"); | |
146 | qemu_fdt_add_subnode(fdt, nodename); | |
147 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); | |
148 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); | |
149 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
150 | SIFIVE_U_RTCCLK_FREQ); | |
151 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
152 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
153 | g_free(nodename); | |
154 | ||
a7240d1e | 155 | nodename = g_strdup_printf("/memory@%lx", |
13b8c354 | 156 | (long)memmap[SIFIVE_U_DEV_DRAM].base); |
a7240d1e MC |
157 | qemu_fdt_add_subnode(fdt, nodename); |
158 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 | 159 | memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, |
a7240d1e MC |
160 | mem_size >> 32, mem_size); |
161 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
162 | g_free(nodename); | |
163 | ||
164 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
2a8756ed | 165 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
074ca702 | 166 | CLINT_TIMEBASE_FREQ); |
a7240d1e MC |
167 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
168 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
169 | ||
ecdfe393 | 170 | for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { |
382cb439 | 171 | int cpu_phandle = phandle++; |
a7240d1e MC |
172 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
173 | char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
ecdfe393 | 174 | char *isa; |
a7240d1e | 175 | qemu_fdt_add_subnode(fdt, nodename); |
ecdfe393 BM |
176 | /* cpu 0 is the management hart that does not have mmu */ |
177 | if (cpu != 0) { | |
2206ffa6 AF |
178 | if (is_32_bit) { |
179 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); | |
180 | } else { | |
181 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); | |
182 | } | |
ecdfe393 BM |
183 | isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); |
184 | } else { | |
185 | isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); | |
186 | } | |
a7240d1e MC |
187 | qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); |
188 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | |
189 | qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | |
190 | qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | |
191 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | |
192 | qemu_fdt_add_subnode(fdt, intc); | |
382cb439 | 193 | qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); |
a7240d1e MC |
194 | qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); |
195 | qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | |
196 | qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | |
197 | g_free(isa); | |
198 | g_free(intc); | |
199 | g_free(nodename); | |
200 | } | |
201 | ||
ecdfe393 BM |
202 | cells = g_new0(uint32_t, ms->smp.cpus * 4); |
203 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
204 | nodename = |
205 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
206 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
207 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
208 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
209 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
210 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
211 | g_free(nodename); | |
212 | } | |
213 | nodename = g_strdup_printf("/soc/clint@%lx", | |
13b8c354 | 214 | (long)memmap[SIFIVE_U_DEV_CLINT].base); |
a7240d1e | 215 | qemu_fdt_add_subnode(fdt, nodename); |
7cfbb17f BM |
216 | qemu_fdt_setprop_string_array(fdt, nodename, "compatible", |
217 | (char **)&clint_compat, ARRAY_SIZE(clint_compat)); | |
a7240d1e | 218 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
219 | 0x0, memmap[SIFIVE_U_DEV_CLINT].base, |
220 | 0x0, memmap[SIFIVE_U_DEV_CLINT].size); | |
a7240d1e | 221 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", |
ecdfe393 | 222 | cells, ms->smp.cpus * sizeof(uint32_t) * 4); |
a7240d1e MC |
223 | g_free(cells); |
224 | g_free(nodename); | |
225 | ||
ea85f27d | 226 | nodename = g_strdup_printf("/soc/otp@%lx", |
13b8c354 | 227 | (long)memmap[SIFIVE_U_DEV_OTP].base); |
ea85f27d BM |
228 | qemu_fdt_add_subnode(fdt, nodename); |
229 | qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); | |
230 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
231 | 0x0, memmap[SIFIVE_U_DEV_OTP].base, |
232 | 0x0, memmap[SIFIVE_U_DEV_OTP].size); | |
ea85f27d BM |
233 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
234 | "sifive,fu540-c000-otp"); | |
235 | g_free(nodename); | |
236 | ||
af14c840 BM |
237 | prci_phandle = phandle++; |
238 | nodename = g_strdup_printf("/soc/clock-controller@%lx", | |
13b8c354 | 239 | (long)memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 BM |
240 | qemu_fdt_add_subnode(fdt, nodename); |
241 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); | |
242 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); | |
243 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
244 | hfclk_phandle, rtcclk_phandle); | |
245 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
246 | 0x0, memmap[SIFIVE_U_DEV_PRCI].base, |
247 | 0x0, memmap[SIFIVE_U_DEV_PRCI].size); | |
af14c840 BM |
248 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
249 | "sifive,fu540-c000-prci"); | |
250 | g_free(nodename); | |
251 | ||
382cb439 | 252 | plic_phandle = phandle++; |
ecdfe393 BM |
253 | cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); |
254 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
255 | nodename = |
256 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
257 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
ecdfe393 BM |
258 | /* cpu 0 is the management hart that does not have S-mode */ |
259 | if (cpu == 0) { | |
260 | cells[0] = cpu_to_be32(intc_phandle); | |
261 | cells[1] = cpu_to_be32(IRQ_M_EXT); | |
262 | } else { | |
263 | cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); | |
264 | cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); | |
265 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
266 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); | |
267 | } | |
a7240d1e MC |
268 | g_free(nodename); |
269 | } | |
270 | nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | |
13b8c354 | 271 | (long)memmap[SIFIVE_U_DEV_PLIC].base); |
a7240d1e MC |
272 | qemu_fdt_add_subnode(fdt, nodename); |
273 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); | |
60bb5407 BM |
274 | qemu_fdt_setprop_string_array(fdt, nodename, "compatible", |
275 | (char **)&plic_compat, ARRAY_SIZE(plic_compat)); | |
a7240d1e MC |
276 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); |
277 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 278 | cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); |
a7240d1e | 279 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
280 | 0x0, memmap[SIFIVE_U_DEV_PLIC].base, |
281 | 0x0, memmap[SIFIVE_U_DEV_PLIC].size); | |
724d80c8 BM |
282 | qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", |
283 | SIFIVE_U_PLIC_NUM_SOURCES - 1); | |
04e7edd1 | 284 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); |
a7240d1e MC |
285 | plic_phandle = qemu_fdt_get_phandle(fdt, nodename); |
286 | g_free(cells); | |
287 | g_free(nodename); | |
288 | ||
5133ed17 | 289 | gpio_phandle = phandle++; |
8a88b9f5 | 290 | nodename = g_strdup_printf("/soc/gpio@%lx", |
13b8c354 | 291 | (long)memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 | 292 | qemu_fdt_add_subnode(fdt, nodename); |
5133ed17 | 293 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); |
8a88b9f5 BM |
294 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
295 | prci_phandle, PRCI_CLK_TLCLK); | |
296 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); | |
297 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
298 | qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); | |
299 | qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); | |
300 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
301 | 0x0, memmap[SIFIVE_U_DEV_GPIO].base, |
302 | 0x0, memmap[SIFIVE_U_DEV_GPIO].size); | |
8a88b9f5 BM |
303 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, |
304 | SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, | |
305 | SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, | |
306 | SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, | |
307 | SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, | |
308 | SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); | |
309 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
310 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); | |
311 | g_free(nodename); | |
312 | ||
5133ed17 BM |
313 | nodename = g_strdup_printf("/gpio-restart"); |
314 | qemu_fdt_add_subnode(fdt, nodename); | |
315 | qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); | |
316 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); | |
317 | g_free(nodename); | |
318 | ||
834e027a | 319 | nodename = g_strdup_printf("/soc/dma@%lx", |
13b8c354 | 320 | (long)memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
321 | qemu_fdt_add_subnode(fdt, nodename); |
322 | qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); | |
323 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
324 | SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, | |
325 | SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, | |
326 | SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); | |
327 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
328 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
329 | 0x0, memmap[SIFIVE_U_DEV_PDMA].base, |
330 | 0x0, memmap[SIFIVE_U_DEV_PDMA].size); | |
834e027a BM |
331 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
332 | "sifive,fu540-c000-pdma"); | |
333 | g_free(nodename); | |
334 | ||
6eaf9cf5 | 335 | nodename = g_strdup_printf("/soc/cache-controller@%lx", |
13b8c354 | 336 | (long)memmap[SIFIVE_U_DEV_L2CC].base); |
6eaf9cf5 BM |
337 | qemu_fdt_add_subnode(fdt, nodename); |
338 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
339 | 0x0, memmap[SIFIVE_U_DEV_L2CC].base, |
340 | 0x0, memmap[SIFIVE_U_DEV_L2CC].size); | |
6eaf9cf5 BM |
341 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", |
342 | SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); | |
343 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
344 | qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); | |
345 | qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); | |
346 | qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); | |
347 | qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); | |
348 | qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); | |
349 | qemu_fdt_setprop_string(fdt, nodename, "compatible", | |
350 | "sifive,fu540-c000-ccache"); | |
351 | g_free(nodename); | |
352 | ||
722f1352 BM |
353 | nodename = g_strdup_printf("/soc/spi@%lx", |
354 | (long)memmap[SIFIVE_U_DEV_QSPI2].base); | |
355 | qemu_fdt_add_subnode(fdt, nodename); | |
356 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
357 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); | |
358 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
359 | prci_phandle, PRCI_CLK_TLCLK); | |
360 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); | |
361 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
362 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
363 | 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, | |
364 | 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); | |
365 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); | |
366 | g_free(nodename); | |
367 | ||
368 | nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", | |
369 | (long)memmap[SIFIVE_U_DEV_QSPI2].base); | |
370 | qemu_fdt_add_subnode(fdt, nodename); | |
371 | qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); | |
372 | qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); | |
373 | qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); | |
374 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); | |
375 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); | |
376 | g_free(nodename); | |
377 | ||
145b2991 BM |
378 | nodename = g_strdup_printf("/soc/spi@%lx", |
379 | (long)memmap[SIFIVE_U_DEV_QSPI0].base); | |
380 | qemu_fdt_add_subnode(fdt, nodename); | |
381 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
382 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); | |
383 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
384 | prci_phandle, PRCI_CLK_TLCLK); | |
385 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); | |
386 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
387 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
388 | 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, | |
389 | 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); | |
390 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); | |
391 | g_free(nodename); | |
392 | ||
393 | nodename = g_strdup_printf("/soc/spi@%lx/flash@0", | |
394 | (long)memmap[SIFIVE_U_DEV_QSPI0].base); | |
395 | qemu_fdt_add_subnode(fdt, nodename); | |
396 | qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); | |
397 | qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); | |
398 | qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); | |
399 | qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); | |
400 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); | |
401 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); | |
402 | g_free(nodename); | |
403 | ||
7b6bb66f | 404 | phy_phandle = phandle++; |
5a7f76a3 | 405 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
13b8c354 | 406 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 407 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f BM |
408 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
409 | "sifive,fu540-c000-gem"); | |
5a7f76a3 | 410 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
411 | 0x0, memmap[SIFIVE_U_DEV_GEM].base, |
412 | 0x0, memmap[SIFIVE_U_DEV_GEM].size, | |
413 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, | |
414 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); | |
5a7f76a3 AF |
415 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); |
416 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); | |
7b6bb66f | 417 | qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); |
04e7edd1 BM |
418 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
419 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); | |
fe93582c | 420 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
806c64b7 | 421 | prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); |
cb53b283 BM |
422 | qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", |
423 | (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); | |
7b6bb66f BM |
424 | qemu_fdt_setprop(fdt, nodename, "local-mac-address", |
425 | s->soc.gem.conf.macaddr.a, ETH_ALEN); | |
04e7edd1 BM |
426 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
427 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
c3a28b5d BM |
428 | |
429 | qemu_fdt_add_subnode(fdt, "/aliases"); | |
430 | qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); | |
431 | ||
5a7f76a3 AF |
432 | g_free(nodename); |
433 | ||
434 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", | |
13b8c354 | 435 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 436 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f | 437 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); |
04e7edd1 | 438 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
5a7f76a3 AF |
439 | g_free(nodename); |
440 | ||
ea6eaa06 AF |
441 | nodename = g_strdup_printf("/soc/pwm@%lx", |
442 | (long)memmap[SIFIVE_U_DEV_PWM0].base); | |
443 | qemu_fdt_add_subnode(fdt, nodename); | |
444 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); | |
445 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
446 | 0x0, memmap[SIFIVE_U_DEV_PWM0].base, | |
447 | 0x0, memmap[SIFIVE_U_DEV_PWM0].size); | |
448 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
449 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
450 | SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1, | |
451 | SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3); | |
452 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
453 | prci_phandle, PRCI_CLK_TLCLK); | |
454 | qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); | |
455 | g_free(nodename); | |
456 | ||
457 | nodename = g_strdup_printf("/soc/pwm@%lx", | |
458 | (long)memmap[SIFIVE_U_DEV_PWM1].base); | |
459 | qemu_fdt_add_subnode(fdt, nodename); | |
460 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); | |
461 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
462 | 0x0, memmap[SIFIVE_U_DEV_PWM1].base, | |
463 | 0x0, memmap[SIFIVE_U_DEV_PWM1].size); | |
464 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
465 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
466 | SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1, | |
467 | SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3); | |
468 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
469 | prci_phandle, PRCI_CLK_TLCLK); | |
470 | qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); | |
471 | g_free(nodename); | |
472 | ||
10b43754 AP |
473 | nodename = g_strdup_printf("/soc/serial@%lx", |
474 | (long)memmap[SIFIVE_U_DEV_UART1].base); | |
475 | qemu_fdt_add_subnode(fdt, nodename); | |
476 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
477 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
478 | 0x0, memmap[SIFIVE_U_DEV_UART1].base, | |
479 | 0x0, memmap[SIFIVE_U_DEV_UART1].size); | |
480 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
481 | prci_phandle, PRCI_CLK_TLCLK); | |
482 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
483 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); | |
484 | ||
485 | qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); | |
486 | g_free(nodename); | |
487 | ||
5f7134d3 | 488 | nodename = g_strdup_printf("/soc/serial@%lx", |
13b8c354 | 489 | (long)memmap[SIFIVE_U_DEV_UART0].base); |
a7240d1e MC |
490 | qemu_fdt_add_subnode(fdt, nodename); |
491 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
492 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
493 | 0x0, memmap[SIFIVE_U_DEV_UART0].base, |
494 | 0x0, memmap[SIFIVE_U_DEV_UART0].size); | |
806c64b7 BM |
495 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
496 | prci_phandle, PRCI_CLK_TLCLK); | |
04e7edd1 BM |
497 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
498 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); | |
a7240d1e MC |
499 | |
500 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
501 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | |
44e6dcd3 GR |
502 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); |
503 | ||
a7240d1e MC |
504 | g_free(nodename); |
505 | } | |
506 | ||
5133ed17 BM |
507 | static void sifive_u_machine_reset(void *opaque, int n, int level) |
508 | { | |
509 | /* gpio pin active low triggers reset */ | |
510 | if (!level) { | |
511 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
512 | } | |
513 | } | |
514 | ||
523e3464 | 515 | static void sifive_u_machine_init(MachineState *machine) |
a7240d1e | 516 | { |
73261285 | 517 | const MemMapEntry *memmap = sifive_u_memmap; |
687caef1 | 518 | SiFiveUState *s = RISCV_U_MACHINE(machine); |
5aec3247 | 519 | MemoryRegion *system_memory = get_system_memory(); |
1b3a2308 | 520 | MemoryRegion *flash0 = g_new(MemoryRegion, 1); |
13b8c354 | 521 | target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
38bc4e34 | 522 | target_ulong firmware_end_addr, kernel_start_addr; |
9d3f7108 | 523 | const char *firmware_name; |
8590f536 | 524 | uint32_t start_addr_hi32 = 0x00000000; |
5aec3247 | 525 | int i; |
66b1205b | 526 | uint32_t fdt_load_addr; |
dc144fe1 | 527 | uint64_t kernel_entry; |
145b2991 | 528 | DriveInfo *dinfo; |
36aa285f MA |
529 | BlockBackend *blk; |
530 | DeviceState *flash_dev, *sd_dev, *card_dev; | |
722f1352 | 531 | qemu_irq flash_cs, sd_cs; |
a7240d1e | 532 | |
2308092b | 533 | /* Initialize SoC */ |
9fc7fc4d | 534 | object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); |
5325cc34 MA |
535 | object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, |
536 | &error_abort); | |
099be035 AF |
537 | object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, |
538 | &error_abort); | |
8f972e5b | 539 | qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); |
a7240d1e MC |
540 | |
541 | /* register RAM */ | |
13b8c354 | 542 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, |
c188a9c4 | 543 | machine->ram); |
a7240d1e | 544 | |
1b3a2308 AF |
545 | /* register QSPI0 Flash */ |
546 | memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", | |
13b8c354 EH |
547 | memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); |
548 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, | |
1b3a2308 AF |
549 | flash0); |
550 | ||
5133ed17 BM |
551 | /* register gpio-restart */ |
552 | qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, | |
553 | qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); | |
554 | ||
fc9ec362 BM |
555 | /* load/create device tree */ |
556 | if (machine->dtb) { | |
557 | machine->fdt = load_device_tree(machine->dtb, &s->fdt_size); | |
558 | if (!machine->fdt) { | |
559 | error_report("load_device_tree() failed"); | |
560 | exit(1); | |
561 | } | |
562 | } else { | |
563 | create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); | |
564 | } | |
a7240d1e | 565 | |
17aad9f2 BM |
566 | if (s->start_in_flash) { |
567 | /* | |
568 | * If start_in_flash property is given, assign s->msel to a value | |
569 | * that representing booting from QSPI0 memory-mapped flash. | |
570 | * | |
571 | * This also means that when both start_in_flash and msel properties | |
572 | * are given, start_in_flash takes the precedence over msel. | |
573 | * | |
574 | * Note this is to keep backward compatibility not to break existing | |
575 | * users that use start_in_flash property. | |
576 | */ | |
577 | s->msel = MSEL_MEMMAP_QSPI0_FLASH; | |
578 | } | |
579 | ||
580 | switch (s->msel) { | |
581 | case MSEL_MEMMAP_QSPI0_FLASH: | |
13b8c354 | 582 | start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; |
17aad9f2 BM |
583 | break; |
584 | case MSEL_L2LIM_QSPI0_FLASH: | |
585 | case MSEL_L2LIM_QSPI2_SD: | |
13b8c354 | 586 | start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; |
17aad9f2 BM |
587 | break; |
588 | default: | |
13b8c354 | 589 | start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
17aad9f2 BM |
590 | break; |
591 | } | |
592 | ||
9d3f7108 DHB |
593 | firmware_name = riscv_default_firmware_name(&s->soc.u_cpus); |
594 | firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, | |
595 | start_addr, NULL); | |
b3042223 | 596 | |
a7240d1e | 597 | if (machine->kernel_filename) { |
a8259b53 | 598 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, |
38bc4e34 AF |
599 | firmware_end_addr); |
600 | ||
62c5bc34 | 601 | kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, |
487d73fc | 602 | kernel_start_addr, true, NULL); |
dc144fe1 AP |
603 | } else { |
604 | /* | |
605 | * If dynamic firmware is used, it doesn't know where is the next mode | |
606 | * if kernel argument is not set. | |
607 | */ | |
608 | kernel_entry = 0; | |
a7240d1e MC |
609 | } |
610 | ||
bc2c0153 | 611 | fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, |
4b402886 DHB |
612 | memmap[SIFIVE_U_DEV_DRAM].size, |
613 | machine); | |
bc2c0153 DHB |
614 | riscv_load_fdt(fdt_load_addr, machine->fdt); |
615 | ||
a8259b53 | 616 | if (!riscv_is_32bit(&s->soc.u_cpus)) { |
2206ffa6 AF |
617 | start_addr_hi32 = (uint64_t)start_addr >> 32; |
618 | } | |
66b1205b | 619 | |
a7240d1e | 620 | /* reset vector */ |
623d53cb | 621 | uint32_t reset_vec[12] = { |
17aad9f2 | 622 | s->msel, /* MSEL pin state */ |
dc144fe1 | 623 | 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ |
623d53cb | 624 | 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ |
a7240d1e | 625 | 0xf1402573, /* csrr a0, mhartid */ |
2206ffa6 AF |
626 | 0, |
627 | 0, | |
a7240d1e | 628 | 0x00028067, /* jr t0 */ |
fc41ae23 | 629 | start_addr, /* start: .dword */ |
8590f536 | 630 | start_addr_hi32, |
66b1205b | 631 | fdt_load_addr, /* fdt_laddr: .dword */ |
623d53cb | 632 | 0x00000000, |
66b1205b | 633 | 0x00000000, |
dc144fe1 | 634 | /* fw_dyn: */ |
a7240d1e | 635 | }; |
a8259b53 | 636 | if (riscv_is_32bit(&s->soc.u_cpus)) { |
2206ffa6 AF |
637 | reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ |
638 | reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ | |
639 | } else { | |
640 | reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ | |
641 | reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ | |
642 | } | |
643 | ||
a7240d1e | 644 | |
5aec3247 | 645 | /* copy in the reset vector in little_endian byte order */ |
66b1205b | 646 | for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { |
5aec3247 MC |
647 | reset_vec[i] = cpu_to_le32(reset_vec[i]); |
648 | } | |
649 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
13b8c354 | 650 | memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); |
dc144fe1 | 651 | |
78936771 | 652 | riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, |
13b8c354 | 653 | memmap[SIFIVE_U_DEV_MROM].size, |
dc144fe1 | 654 | sizeof(reset_vec), kernel_entry); |
145b2991 BM |
655 | |
656 | /* Connect an SPI flash to SPI0 */ | |
657 | flash_dev = qdev_new("is25wp256"); | |
64eaa820 | 658 | dinfo = drive_get(IF_MTD, 0, 0); |
145b2991 BM |
659 | if (dinfo) { |
660 | qdev_prop_set_drive_err(flash_dev, "drive", | |
661 | blk_by_legacy_dinfo(dinfo), | |
662 | &error_fatal); | |
663 | } | |
664 | qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); | |
665 | ||
666 | flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); | |
667 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); | |
722f1352 BM |
668 | |
669 | /* Connect an SD card to SPI2 */ | |
670 | sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); | |
671 | ||
672 | sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); | |
673 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); | |
36aa285f MA |
674 | |
675 | dinfo = drive_get(IF_SD, 0, 0); | |
676 | blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; | |
c3287c0f | 677 | card_dev = qdev_new(TYPE_SD_CARD_SPI); |
36aa285f | 678 | qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal); |
36aa285f MA |
679 | qdev_realize_and_unref(card_dev, |
680 | qdev_get_child_bus(sd_dev, "sd-bus"), | |
681 | &error_fatal); | |
2308092b AF |
682 | } |
683 | ||
523e3464 AF |
684 | static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) |
685 | { | |
686 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
687 | ||
688 | return s->start_in_flash; | |
689 | } | |
690 | ||
691 | static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) | |
692 | { | |
693 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
694 | ||
695 | s->start_in_flash = value; | |
696 | } | |
697 | ||
698 | static void sifive_u_machine_instance_init(Object *obj) | |
699 | { | |
700 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
701 | ||
702 | s->start_in_flash = false; | |
cfa32630 | 703 | s->msel = 0; |
96c7fff7 BB |
704 | object_property_add_uint32_ptr(obj, "msel", &s->msel, |
705 | OBJ_PROP_FLAG_READWRITE); | |
cfa32630 BM |
706 | object_property_set_description(obj, "msel", |
707 | "Mode Select (MSEL[3:0]) pin state"); | |
708 | ||
3ca109c3 | 709 | s->serial = OTP_SERIAL; |
96c7fff7 BB |
710 | object_property_add_uint32_ptr(obj, "serial", &s->serial, |
711 | OBJ_PROP_FLAG_READWRITE); | |
7eecec7d | 712 | object_property_set_description(obj, "serial", "Board serial number"); |
523e3464 AF |
713 | } |
714 | ||
715 | static void sifive_u_machine_class_init(ObjectClass *oc, void *data) | |
716 | { | |
717 | MachineClass *mc = MACHINE_CLASS(oc); | |
718 | ||
719 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; | |
720 | mc->init = sifive_u_machine_init; | |
721 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; | |
722 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; | |
1eaada8a | 723 | mc->default_cpu_type = SIFIVE_U_CPU; |
523e3464 | 724 | mc->default_cpus = mc->min_cpus; |
c188a9c4 | 725 | mc->default_ram_id = "riscv.sifive.u.ram"; |
418b473e EH |
726 | |
727 | object_class_property_add_bool(oc, "start-in-flash", | |
728 | sifive_u_machine_get_start_in_flash, | |
729 | sifive_u_machine_set_start_in_flash); | |
730 | object_class_property_set_description(oc, "start-in-flash", | |
731 | "Set on to tell QEMU's ROM to jump to " | |
732 | "flash. Otherwise QEMU will jump to DRAM " | |
733 | "or L2LIM depending on the msel value"); | |
523e3464 AF |
734 | } |
735 | ||
736 | static const TypeInfo sifive_u_machine_typeinfo = { | |
737 | .name = MACHINE_TYPE_NAME("sifive_u"), | |
738 | .parent = TYPE_MACHINE, | |
739 | .class_init = sifive_u_machine_class_init, | |
740 | .instance_init = sifive_u_machine_instance_init, | |
741 | .instance_size = sizeof(SiFiveUState), | |
742 | }; | |
743 | ||
744 | static void sifive_u_machine_init_register_types(void) | |
745 | { | |
746 | type_register_static(&sifive_u_machine_typeinfo); | |
747 | } | |
748 | ||
749 | type_init(sifive_u_machine_init_register_types) | |
750 | ||
139177b1 | 751 | static void sifive_u_soc_instance_init(Object *obj) |
2308092b AF |
752 | { |
753 | SiFiveUSoCState *s = RISCV_U_SOC(obj); | |
754 | ||
9fc7fc4d | 755 | object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
756 | qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); |
757 | ||
db873cc5 MA |
758 | object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, |
759 | TYPE_RISCV_HART_ARRAY); | |
ecdfe393 BM |
760 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); |
761 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); | |
762 | qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); | |
73f6ed97 | 763 | qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); |
ecdfe393 | 764 | |
9fc7fc4d | 765 | object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
766 | qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); |
767 | ||
db873cc5 MA |
768 | object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, |
769 | TYPE_RISCV_HART_ARRAY); | |
5a7f76a3 | 770 | |
db873cc5 MA |
771 | object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); |
772 | object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); | |
773 | object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); | |
8a88b9f5 | 774 | object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); |
834e027a | 775 | object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); |
145b2991 | 776 | object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); |
722f1352 | 777 | object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); |
ea6eaa06 AF |
778 | object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); |
779 | object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM); | |
2308092b AF |
780 | } |
781 | ||
139177b1 | 782 | static void sifive_u_soc_realize(DeviceState *dev, Error **errp) |
2308092b | 783 | { |
c4473127 | 784 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b | 785 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
73261285 | 786 | const MemMapEntry *memmap = sifive_u_memmap; |
2308092b AF |
787 | MemoryRegion *system_memory = get_system_memory(); |
788 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
a6902ef0 | 789 | MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); |
05446f41 | 790 | char *plic_hart_config; |
ea6eaa06 | 791 | int i, j; |
5a7f76a3 | 792 | NICInfo *nd = &nd_table[0]; |
2308092b | 793 | |
099be035 AF |
794 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); |
795 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); | |
796 | qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); | |
797 | qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); | |
798 | ||
91a3387d TO |
799 | sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal); |
800 | sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal); | |
ecdfe393 BM |
801 | /* |
802 | * The cluster must be realized after the RISC-V hart array container, | |
803 | * as the container's CPU object is only created on realize, and the | |
804 | * CPU must exist and have been parented into the cluster before the | |
805 | * cluster is realized. | |
806 | */ | |
ce189ab2 MA |
807 | qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); |
808 | qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); | |
2308092b AF |
809 | |
810 | /* boot rom */ | |
414c47d2 | 811 | memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", |
13b8c354 EH |
812 | memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); |
813 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, | |
2308092b | 814 | mask_rom); |
a7240d1e | 815 | |
a6902ef0 AF |
816 | /* |
817 | * Add L2-LIM at reset size. | |
818 | * This should be reduced in size as the L2 Cache Controller WayEnable | |
819 | * register is incremented. Unfortunately I don't see a nice (or any) way | |
820 | * to handle reducing or blocking out the L2 LIM while still allowing it | |
821 | * be re returned to all enabled after a reset. For the time being, just | |
822 | * leave it enabled all the time. This won't break anything, but will be | |
823 | * too generous to misbehaving guests. | |
824 | */ | |
825 | memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", | |
13b8c354 EH |
826 | memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); |
827 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, | |
a6902ef0 AF |
828 | l2lim_mem); |
829 | ||
05446f41 | 830 | /* create PLIC hart topology configuration string */ |
4e8fb53c | 831 | plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); |
05446f41 | 832 | |
a7240d1e | 833 | /* MMIO */ |
13b8c354 | 834 | s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, |
f436ecc3 | 835 | plic_hart_config, ms->smp.cpus, 0, |
a7240d1e MC |
836 | SIFIVE_U_PLIC_NUM_SOURCES, |
837 | SIFIVE_U_PLIC_NUM_PRIORITIES, | |
838 | SIFIVE_U_PLIC_PRIORITY_BASE, | |
839 | SIFIVE_U_PLIC_PENDING_BASE, | |
840 | SIFIVE_U_PLIC_ENABLE_BASE, | |
841 | SIFIVE_U_PLIC_ENABLE_STRIDE, | |
842 | SIFIVE_U_PLIC_CONTEXT_BASE, | |
843 | SIFIVE_U_PLIC_CONTEXT_STRIDE, | |
13b8c354 | 844 | memmap[SIFIVE_U_DEV_PLIC].size); |
bb8136df | 845 | g_free(plic_hart_config); |
13b8c354 | 846 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, |
647a70a1 | 847 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
13b8c354 | 848 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, |
194eef09 | 849 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); |
b8fb878a AP |
850 | riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, |
851 | ms->smp.cpus, false); | |
852 | riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + | |
853 | RISCV_ACLINT_SWI_SIZE, | |
854 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, | |
855 | RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, | |
074ca702 | 856 | CLINT_TIMEBASE_FREQ, false); |
5a7f76a3 | 857 | |
cbe3a8c5 MA |
858 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { |
859 | return; | |
860 | } | |
13b8c354 | 861 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 | 862 | |
8a88b9f5 | 863 | qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); |
cbe3a8c5 MA |
864 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
865 | return; | |
866 | } | |
13b8c354 | 867 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 BM |
868 | |
869 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
870 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); | |
871 | ||
872 | /* Connect GPIO interrupts to the PLIC */ | |
873 | for (i = 0; i < 16; i++) { | |
874 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, | |
875 | qdev_get_gpio_in(DEVICE(s->plic), | |
876 | SIFIVE_U_GPIO_IRQ0 + i)); | |
834e027a BM |
877 | } |
878 | ||
879 | /* PDMA */ | |
880 | sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); | |
13b8c354 | 881 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
882 | |
883 | /* Connect PDMA interrupts to the PLIC */ | |
884 | for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { | |
885 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, | |
886 | qdev_get_gpio_in(DEVICE(s->plic), | |
887 | SIFIVE_U_PDMA_IRQ0 + i)); | |
8a88b9f5 BM |
888 | } |
889 | ||
fda5b000 | 890 | qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); |
cbe3a8c5 MA |
891 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { |
892 | return; | |
893 | } | |
13b8c354 | 894 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); |
5461c4fe | 895 | |
7ad36e2e | 896 | /* FIXME use qdev NIC properties instead of nd_table[] */ |
5a7f76a3 AF |
897 | if (nd->used) { |
898 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
899 | qdev_set_nic_properties(DEVICE(&s->gem), nd); | |
900 | } | |
5325cc34 | 901 | object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, |
5a7f76a3 | 902 | &error_abort); |
668f62ec | 903 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { |
5a7f76a3 AF |
904 | return; |
905 | } | |
13b8c354 | 906 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 907 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, |
5874f0a7 | 908 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); |
7b6bb66f | 909 | |
ea6eaa06 AF |
910 | /* PWM */ |
911 | for (i = 0; i < 2; i++) { | |
912 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) { | |
913 | return; | |
914 | } | |
915 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, | |
916 | memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i)); | |
917 | ||
918 | /* Connect PWM interrupts to the PLIC */ | |
919 | for (j = 0; j < SIFIVE_PWM_IRQS; j++) { | |
920 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j, | |
921 | qdev_get_gpio_in(DEVICE(s->plic), | |
922 | SIFIVE_U_PWM0_IRQ0 + (i * 4) + j)); | |
923 | } | |
924 | } | |
925 | ||
7b6bb66f | 926 | create_unimplemented_device("riscv.sifive.u.gem-mgmt", |
13b8c354 | 927 | memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); |
3eaea6eb BM |
928 | |
929 | create_unimplemented_device("riscv.sifive.u.dmc", | |
13b8c354 | 930 | memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); |
6eaf9cf5 BM |
931 | |
932 | create_unimplemented_device("riscv.sifive.u.l2cc", | |
13b8c354 | 933 | memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); |
145b2991 BM |
934 | |
935 | sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); | |
936 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, | |
937 | memmap[SIFIVE_U_DEV_QSPI0].base); | |
938 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, | |
939 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); | |
722f1352 BM |
940 | sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); |
941 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, | |
942 | memmap[SIFIVE_U_DEV_QSPI2].base); | |
943 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, | |
944 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); | |
a7240d1e MC |
945 | } |
946 | ||
139177b1 | 947 | static Property sifive_u_soc_props[] = { |
fda5b000 | 948 | DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), |
099be035 | 949 | DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), |
fda5b000 AF |
950 | DEFINE_PROP_END_OF_LIST() |
951 | }; | |
952 | ||
139177b1 | 953 | static void sifive_u_soc_class_init(ObjectClass *oc, void *data) |
2308092b AF |
954 | { |
955 | DeviceClass *dc = DEVICE_CLASS(oc); | |
956 | ||
139177b1 BM |
957 | device_class_set_props(dc, sifive_u_soc_props); |
958 | dc->realize = sifive_u_soc_realize; | |
2308092b AF |
959 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
960 | dc->user_creatable = false; | |
961 | } | |
962 | ||
139177b1 | 963 | static const TypeInfo sifive_u_soc_type_info = { |
2308092b AF |
964 | .name = TYPE_RISCV_U_SOC, |
965 | .parent = TYPE_DEVICE, | |
966 | .instance_size = sizeof(SiFiveUSoCState), | |
139177b1 BM |
967 | .instance_init = sifive_u_soc_instance_init, |
968 | .class_init = sifive_u_soc_class_init, | |
2308092b AF |
969 | }; |
970 | ||
139177b1 | 971 | static void sifive_u_soc_register_types(void) |
2308092b | 972 | { |
139177b1 | 973 | type_register_static(&sifive_u_soc_type_info); |
2308092b AF |
974 | } |
975 | ||
139177b1 | 976 | type_init(sifive_u_soc_register_types) |