[mirror_qemu.git] / hw / riscv / sifive_u.c

/*
 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
 * Copyright (c) 2017 SiFive, Inc.
 *
 * Provides a board compatible with the SiFive Freedom U SDK:
 *
 * 0) UART
 * 1) CLINT (Core Level Interruptor)
 * 2) PLIC (Platform Level Interrupt Controller)
 *
 * This board currently uses a hardcoded devicetree that indicates one hart.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
#include "elf.h"

#include <libfdt.h>

static const struct MemmapEntry {
    hwaddr base;
    hwaddr size;
} sifive_u_memmap[] = {
    [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
    [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
    [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
    [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
    [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },
    [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
    [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
    [SIFIVE_U_GEM] =      { 0x100900FC,     0x2000 },
};

#define GEM_REVISION        0x10070109

static uint64_t load_kernel(const char *kernel_filename)
{
    uint64_t kernel_entry, kernel_high;

    if (load_elf(kernel_filename, NULL, NULL, NULL,
                 &kernel_entry, NULL, &kernel_high,
                 0, EM_RISCV, 1, 0) < 0) {
        error_report("could not load kernel '%s'", kernel_filename);
        exit(1);
    }
    return kernel_entry;
}

static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
    uint64_t mem_size, const char *cmdline)
{
    void *fdt;
    int cpu;
    uint32_t *cells;
    char *nodename;
    char ethclk_names[] = "pclk\0hclk\0tx_clk";
    uint32_t plic_phandle, ethclk_phandle;

    fdt = s->fdt = create_device_tree(&s->fdt_size);
    if (!fdt) {
        error_report("create_device_tree() failed");
        exit(1);
    }

    qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
    qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);

    qemu_fdt_add_subnode(fdt, "/soc");
    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);

    nodename = g_strdup_printf("/memory@%lx",
        (long)memmap[SIFIVE_U_DRAM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
        mem_size >> 32, mem_size);
    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
    g_free(nodename);

    qemu_fdt_add_subnode(fdt, "/cpus");
    qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
        SIFIVE_CLINT_TIMEBASE_FREQ);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);

    for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
        qemu_fdt_add_subnode(fdt, nodename);
        qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
                              SIFIVE_U_CLOCK_FREQ);
        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
        qemu_fdt_add_subnode(fdt, intc);
        qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
        qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
        g_free(isa);
        g_free(intc);
        g_free(nodename);
    }

    cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
    for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/clint@%lx",
        (long)memmap[SIFIVE_U_CLINT].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_CLINT].base,
        0x0, memmap[SIFIVE_U_CLINT].size);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
    g_free(cells);
    g_free(nodename);

    cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
    for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
        (long)memmap[SIFIVE_U_PLIC].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_PLIC].base,
        0x0, memmap[SIFIVE_U_PLIC].size);
    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
    qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
    qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
    plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
    g_free(cells);
    g_free(nodename);

    nodename = g_strdup_printf("/soc/ethclk");
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
        SIFIVE_U_GEM_CLOCK_FREQ);
    qemu_fdt_setprop_cell(fdt, nodename, "phandle", 3);
    qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", 3);
    ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
    g_free(nodename);

    nodename = g_strdup_printf("/soc/ethernet@%lx",
        (long)memmap[SIFIVE_U_GEM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_GEM].base,
        0x0, memmap[SIFIVE_U_GEM].size);
    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
    qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
        ethclk_phandle, ethclk_phandle, ethclk_phandle);
    qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
        sizeof(ethclk_names));
    qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
    qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
    g_free(nodename);

    nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
        (long)memmap[SIFIVE_U_GEM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
    g_free(nodename);

    nodename = g_strdup_printf("/soc/uart@%lx",
        (long)memmap[SIFIVE_U_UART0].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SIFIVE_U_UART0].base,
        0x0, memmap[SIFIVE_U_UART0].size);
    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
                          SIFIVE_U_CLOCK_FREQ / 2);
    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);

    qemu_fdt_add_subnode(fdt, "/chosen");
    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
    if (cmdline) {
        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
    }
    g_free(nodename);
}

static void riscv_sifive_u_init(MachineState *machine)
{
    const struct MemmapEntry *memmap = sifive_u_memmap;

    SiFiveUState *s = g_new0(SiFiveUState, 1);
    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
    int i;

    /* Initialize SoC */
    object_initialize_child(OBJECT(machine), "soc", &s->soc,
                            sizeof(s->soc), TYPE_RISCV_U_SOC,
                            &error_abort, NULL);
    object_property_set_bool(OBJECT(&s->soc), true, "realized",
                            &error_abort);

    /* register RAM */
    memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
                           machine->ram_size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
                                main_mem);

    /* create device tree */
    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);

    if (machine->kernel_filename) {
        load_kernel(machine->kernel_filename);
    }

    /* reset vector */
    uint32_t reset_vec[8] = {
        0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
        0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
        0xf1402573,                    /*     csrr   a0, mhartid  */
#if defined(TARGET_RISCV32)
        0x0182a283,                    /*     lw     t0, 24(t0) */
#elif defined(TARGET_RISCV64)
        0x0182b283,                    /*     ld     t0, 24(t0) */
#endif
        0x00028067,                    /*     jr     t0 */
        0x00000000,
        memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
        0x00000000,
                                       /* dtb: */
    };

    /* copy in the reset vector in little_endian byte order */
    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
        reset_vec[i] = cpu_to_le32(reset_vec[i]);
    }
    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                          memmap[SIFIVE_U_MROM].base, &address_space_memory);

    /* copy in the device tree */
    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
            memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
        error_report("not enough space to store device-tree");
        exit(1);
    }
    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
                          memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
                          &address_space_memory);
}

static void riscv_sifive_u_soc_init(Object *obj)
{
    SiFiveUSoCState *s = RISCV_U_SOC(obj);

    object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
                            TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
    object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
                            &error_abort);
    object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
                            &error_abort);

    sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
                          TYPE_CADENCE_GEM);
}

static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
    SiFiveUSoCState *s = RISCV_U_SOC(dev);
    const struct MemmapEntry *memmap = sifive_u_memmap;
    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
    qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
    int i;
    Error *err = NULL;
    NICInfo *nd = &nd_table[0];

    object_property_set_bool(OBJECT(&s->cpus), true, "realized",
                             &error_abort);

    /* boot rom */
    memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
                           memmap[SIFIVE_U_MROM].size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
                                mask_rom);

    /* MMIO */
    s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
        (char *)SIFIVE_U_PLIC_HART_CONFIG,
        SIFIVE_U_PLIC_NUM_SOURCES,
        SIFIVE_U_PLIC_NUM_PRIORITIES,
        SIFIVE_U_PLIC_PRIORITY_BASE,
        SIFIVE_U_PLIC_PENDING_BASE,
        SIFIVE_U_PLIC_ENABLE_BASE,
        SIFIVE_U_PLIC_ENABLE_STRIDE,
        SIFIVE_U_PLIC_CONTEXT_BASE,
        SIFIVE_U_PLIC_CONTEXT_STRIDE,
        memmap[SIFIVE_U_PLIC].size);
    sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
        serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
    sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
        serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
    sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
        memmap[SIFIVE_U_CLINT].size, smp_cpus,
        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);

    for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
        plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
    }

    if (nd->used) {
        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
        qdev_set_nic_properties(DEVICE(&s->gem), nd);
    }
    object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
                       plic_gpios[SIFIVE_U_GEM_IRQ]);
}

static void riscv_sifive_u_machine_init(MachineClass *mc)
{
    mc->desc = "RISC-V Board compatible with SiFive U SDK";
    mc->init = riscv_sifive_u_init;
    mc->max_cpus = 1;
}

DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)

static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = riscv_sifive_u_soc_realize;
    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
    dc->user_creatable = false;
}

static const TypeInfo riscv_sifive_u_soc_type_info = {
    .name = TYPE_RISCV_U_SOC,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(SiFiveUSoCState),
    .instance_init = riscv_sifive_u_soc_init,
    .class_init = riscv_sifive_u_soc_class_init,
};

static void riscv_sifive_u_soc_register_types(void)
{
    type_register_static(&riscv_sifive_u_soc_type_info);
}

type_init(riscv_sifive_u_soc_register_types)
Commit	Line	Data
a7240d1e MC	1	/*
	2	* QEMU RISC-V Board Compatible with SiFive Freedom U SDK
	3	*
	4	* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
	5	* Copyright (c) 2017 SiFive, Inc.
	6	*
	7	* Provides a board compatible with the SiFive Freedom U SDK:
	8	*
	9	* 0) UART
	10	* 1) CLINT (Core Level Interruptor)
	11	* 2) PLIC (Platform Level Interrupt Controller)
	12	*
	13	* This board currently uses a hardcoded devicetree that indicates one hart.
	14	*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms and conditions of the GNU General Public License,
	17	* version 2 or later, as published by the Free Software Foundation.
	18	*
	19	* This program is distributed in the hope it will be useful, but WITHOUT
	20	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	21	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	22	* more details.
	23	*
	24	* You should have received a copy of the GNU General Public License along with
	25	* this program. If not, see <http://www.gnu.org/licenses/>.
	26	*/
	27
	28	#include "qemu/osdep.h"
	29	#include "qemu/log.h"
	30	#include "qemu/error-report.h"
	31	#include "qapi/error.h"
	32	#include "hw/hw.h"
	33	#include "hw/boards.h"
	34	#include "hw/loader.h"
	35	#include "hw/sysbus.h"
	36	#include "hw/char/serial.h"
	37	#include "target/riscv/cpu.h"
	38	#include "hw/riscv/riscv_hart.h"
	39	#include "hw/riscv/sifive_plic.h"
	40	#include "hw/riscv/sifive_clint.h"
	41	#include "hw/riscv/sifive_uart.h"
	42	#include "hw/riscv/sifive_prci.h"
	43	#include "hw/riscv/sifive_u.h"
	44	#include "chardev/char.h"
	45	#include "sysemu/arch_init.h"
	46	#include "sysemu/device_tree.h"
	47	#include "exec/address-spaces.h"
	48	#include "elf.h"
	49
5aec3247 MC	50	#include <libfdt.h>
5aec3247 MC	51
a7240d1e MC	52	static const struct MemmapEntry {
	53	hwaddr base;
	54	hwaddr size;
	55	} sifive_u_memmap[] = {
	56	[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
5aec3247	57	[SIFIVE_U_MROM] = { 0x1000, 0x11000 },
a7240d1e MC	58	[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
	59	[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
	60	[SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
	61	[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
	62	[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
5a7f76a3	63	[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
a7240d1e MC	64	};
a7240d1e MC	65
5a7f76a3 AF	66	#define GEM_REVISION 0x10070109
5a7f76a3 AF	67
a7240d1e MC	68	static uint64_t load_kernel(const char *kernel_filename)
	69	{
	70	uint64_t kernel_entry, kernel_high;
	71
4366e1db	72	if (load_elf(kernel_filename, NULL, NULL, NULL,
a7240d1e	73	&kernel_entry, NULL, &kernel_high,
89854803	74	0, EM_RISCV, 1, 0) < 0) {
371b74e2	75	error_report("could not load kernel '%s'", kernel_filename);
a7240d1e MC	76	exit(1);
	77	}
	78	return kernel_entry;
	79	}
	80
	81	static void create_fdt(SiFiveUState s, const struct MemmapEntry memmap,
	82	uint64_t mem_size, const char *cmdline)
	83	{
	84	void *fdt;
	85	int cpu;
	86	uint32_t *cells;
	87	char *nodename;
fe93582c AP	88	char ethclk_names[] = "pclk\0hclk\0tx_clk";
fe93582c AP	89	uint32_t plic_phandle, ethclk_phandle;
a7240d1e MC	90
	91	fdt = s->fdt = create_device_tree(&s->fdt_size);
	92	if (!fdt) {
	93	error_report("create_device_tree() failed");
	94	exit(1);
	95	}
	96
	97	qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
	98	qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
	99	qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
	100	qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
	101
	102	qemu_fdt_add_subnode(fdt, "/soc");
	103	qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
2a1a6f6d	104	qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
a7240d1e MC	105	qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
	106	qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
	107
	108	nodename = g_strdup_printf("/memory@%lx",
	109	(long)memmap[SIFIVE_U_DRAM].base);
	110	qemu_fdt_add_subnode(fdt, nodename);
	111	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	112	memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
	113	mem_size >> 32, mem_size);
	114	qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
	115	g_free(nodename);
	116
	117	qemu_fdt_add_subnode(fdt, "/cpus");
2a8756ed MC	118	qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
2a8756ed MC	119	SIFIVE_CLINT_TIMEBASE_FREQ);
a7240d1e MC	120	qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
	121	qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
	122
2308092b	123	for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
a7240d1e MC	124	nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
a7240d1e MC	125	char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
2308092b	126	char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
a7240d1e	127	qemu_fdt_add_subnode(fdt, nodename);
2a8756ed MC	128	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
2a8756ed MC	129	SIFIVE_U_CLOCK_FREQ);
a7240d1e MC	130	qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
	131	qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
	132	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
	133	qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
	134	qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
	135	qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
	136	qemu_fdt_add_subnode(fdt, intc);
	137	qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
	138	qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
	139	qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
	140	qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
	141	qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
	142	g_free(isa);
	143	g_free(intc);
	144	g_free(nodename);
	145	}
	146
2308092b AF	147	cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
2308092b AF	148	for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
a7240d1e MC	149	nodename =
	150	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	151	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	152	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	153	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
	154	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	155	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
	156	g_free(nodename);
	157	}
	158	nodename = g_strdup_printf("/soc/clint@%lx",
	159	(long)memmap[SIFIVE_U_CLINT].base);
	160	qemu_fdt_add_subnode(fdt, nodename);
	161	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
	162	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	163	0x0, memmap[SIFIVE_U_CLINT].base,
	164	0x0, memmap[SIFIVE_U_CLINT].size);
	165	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
2308092b	166	cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
a7240d1e MC	167	g_free(cells);
	168	g_free(nodename);
	169
2308092b AF	170	cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
2308092b AF	171	for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
a7240d1e MC	172	nodename =
	173	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	174	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	175	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	176	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
	177	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	178	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
	179	g_free(nodename);
	180	}
	181	nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
	182	(long)memmap[SIFIVE_U_PLIC].base);
	183	qemu_fdt_add_subnode(fdt, nodename);
	184	qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
	185	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
	186	qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
	187	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
2308092b	188	cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
a7240d1e MC	189	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	190	0x0, memmap[SIFIVE_U_PLIC].base,
	191	0x0, memmap[SIFIVE_U_PLIC].size);
	192	qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
	193	qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
98ceee7f	194	qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
a7240d1e MC	195	qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
	196	qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
	197	plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
	198	g_free(cells);
	199	g_free(nodename);
	200
fe93582c AP	201	nodename = g_strdup_printf("/soc/ethclk");
	202	qemu_fdt_add_subnode(fdt, nodename);
	203	qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
	204	qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
	205	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
	206	SIFIVE_U_GEM_CLOCK_FREQ);
	207	qemu_fdt_setprop_cell(fdt, nodename, "phandle", 3);
	208	qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", 3);
	209	ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
	210	g_free(nodename);
	211
5a7f76a3 AF	212	nodename = g_strdup_printf("/soc/ethernet@%lx",
	213	(long)memmap[SIFIVE_U_GEM].base);
	214	qemu_fdt_add_subnode(fdt, nodename);
	215	qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
	216	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	217	0x0, memmap[SIFIVE_U_GEM].base,
	218	0x0, memmap[SIFIVE_U_GEM].size);
	219	qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
	220	qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
	221	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
	222	qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
fe93582c AP	223	qemu_fdt_setprop_cells(fdt, nodename, "clocks",
	224	ethclk_phandle, ethclk_phandle, ethclk_phandle);
	225	qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
	226	sizeof(ethclk_names));
5a7f76a3 AF	227	qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
	228	qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
	229	g_free(nodename);
	230
	231	nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
	232	(long)memmap[SIFIVE_U_GEM].base);
	233	qemu_fdt_add_subnode(fdt, nodename);
	234	qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
	235	g_free(nodename);
	236
bde3ab9a	237	nodename = g_strdup_printf("/soc/uart@%lx",
a7240d1e MC	238	(long)memmap[SIFIVE_U_UART0].base);
	239	qemu_fdt_add_subnode(fdt, nodename);
	240	qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
	241	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	242	0x0, memmap[SIFIVE_U_UART0].base,
	243	0x0, memmap[SIFIVE_U_UART0].size);
6c60757e AP	244	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
6c60757e AP	245	SIFIVE_U_CLOCK_FREQ / 2);
a7240d1e MC	246	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
	247	qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
	248
	249	qemu_fdt_add_subnode(fdt, "/chosen");
	250	qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
7c28f4da MC	251	if (cmdline) {
	252	qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
	253	}
a7240d1e MC	254	g_free(nodename);
	255	}
	256
	257	static void riscv_sifive_u_init(MachineState *machine)
	258	{
	259	const struct MemmapEntry *memmap = sifive_u_memmap;
	260
	261	SiFiveUState *s = g_new0(SiFiveUState, 1);
5aec3247	262	MemoryRegion *system_memory = get_system_memory();
a7240d1e	263	MemoryRegion *main_mem = g_new(MemoryRegion, 1);
5aec3247	264	int i;
a7240d1e	265
2308092b	266	/* Initialize SoC */
4eea9d7d AF	267	object_initialize_child(OBJECT(machine), "soc", &s->soc,
	268	sizeof(s->soc), TYPE_RISCV_U_SOC,
	269	&error_abort, NULL);
a7240d1e MC	270	object_property_set_bool(OBJECT(&s->soc), true, "realized",
	271	&error_abort);
	272
	273	/* register RAM */
	274	memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
	275	machine->ram_size, &error_fatal);
5aec3247	276	memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
2308092b	277	main_mem);
a7240d1e MC	278
	279	/* create device tree */
	280	create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
	281
a7240d1e MC	282	if (machine->kernel_filename) {
	283	load_kernel(machine->kernel_filename);
	284	}
	285
	286	/* reset vector */
	287	uint32_t reset_vec[8] = {
	288	0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
	289	0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
	290	0xf1402573, /* csrr a0, mhartid */
	291	#if defined(TARGET_RISCV32)
	292	0x0182a283, /* lw t0, 24(t0) */
	293	#elif defined(TARGET_RISCV64)
	294	0x0182b283, /* ld t0, 24(t0) */
	295	#endif
	296	0x00028067, /* jr t0 */
	297	0x00000000,
	298	memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
	299	0x00000000,
	300	/* dtb: */
	301	};
	302
5aec3247 MC	303	/* copy in the reset vector in little_endian byte order */
	304	for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
	305	reset_vec[i] = cpu_to_le32(reset_vec[i]);
	306	}
	307	rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
	308	memmap[SIFIVE_U_MROM].base, &address_space_memory);
a7240d1e MC	309
a7240d1e MC	310	/* copy in the device tree */
5aec3247 MC	311	if (fdt_pack(s->fdt) \|\| fdt_totalsize(s->fdt) >
	312	memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
	313	error_report("not enough space to store device-tree");
	314	exit(1);
	315	}
	316	qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
	317	rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
	318	memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
	319	&address_space_memory);
2308092b AF	320	}
	321
	322	static void riscv_sifive_u_soc_init(Object *obj)
	323	{
	324	SiFiveUSoCState *s = RISCV_U_SOC(obj);
	325
4eea9d7d AF	326	object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
4eea9d7d AF	327	TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
2308092b AF	328	object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
	329	&error_abort);
	330	object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
	331	&error_abort);
5a7f76a3	332
4eea9d7d AF	333	sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
4eea9d7d AF	334	TYPE_CADENCE_GEM);
2308092b AF	335	}
	336
	337	static void riscv_sifive_u_soc_realize(DeviceState dev, Error *errp)
	338	{
	339	SiFiveUSoCState *s = RISCV_U_SOC(dev);
	340	const struct MemmapEntry *memmap = sifive_u_memmap;
	341	MemoryRegion *system_memory = get_system_memory();
	342	MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
5a7f76a3 AF	343	qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
	344	int i;
	345	Error *err = NULL;
	346	NICInfo *nd = &nd_table[0];
2308092b AF	347
	348	object_property_set_bool(OBJECT(&s->cpus), true, "realized",
	349	&error_abort);
	350
	351	/* boot rom */
	352	memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
	353	memmap[SIFIVE_U_MROM].size, &error_fatal);
	354	memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
	355	mask_rom);
a7240d1e MC	356
	357	/* MMIO */
	358	s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
	359	(char *)SIFIVE_U_PLIC_HART_CONFIG,
	360	SIFIVE_U_PLIC_NUM_SOURCES,
	361	SIFIVE_U_PLIC_NUM_PRIORITIES,
	362	SIFIVE_U_PLIC_PRIORITY_BASE,
	363	SIFIVE_U_PLIC_PENDING_BASE,
	364	SIFIVE_U_PLIC_ENABLE_BASE,
	365	SIFIVE_U_PLIC_ENABLE_STRIDE,
	366	SIFIVE_U_PLIC_CONTEXT_BASE,
	367	SIFIVE_U_PLIC_CONTEXT_STRIDE,
	368	memmap[SIFIVE_U_PLIC].size);
5aec3247	369	sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
647a70a1	370	serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
194eef09 MC	371	sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
194eef09 MC	372	serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
a7240d1e MC	373	sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
	374	memmap[SIFIVE_U_CLINT].size, smp_cpus,
	375	SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
5a7f76a3 AF	376
	377	for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
	378	plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
	379	}
	380
	381	if (nd->used) {
	382	qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
	383	qdev_set_nic_properties(DEVICE(&s->gem), nd);
	384	}
	385	object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
	386	&error_abort);
	387	object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
	388	if (err) {
	389	error_propagate(errp, err);
	390	return;
	391	}
	392	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
	393	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
	394	plic_gpios[SIFIVE_U_GEM_IRQ]);
a7240d1e MC	395	}
a7240d1e MC	396
a7240d1e MC	397	static void riscv_sifive_u_machine_init(MachineClass *mc)
	398	{
	399	mc->desc = "RISC-V Board compatible with SiFive U SDK";
	400	mc->init = riscv_sifive_u_init;
	401	mc->max_cpus = 1;
	402	}
	403
	404	DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
2308092b AF	405
	406	static void riscv_sifive_u_soc_class_init(ObjectClass oc, void data)
	407	{
	408	DeviceClass *dc = DEVICE_CLASS(oc);
	409
	410	dc->realize = riscv_sifive_u_soc_realize;
	411	/* Reason: Uses serial_hds in realize function, thus can't be used twice */
	412	dc->user_creatable = false;
	413	}
	414
	415	static const TypeInfo riscv_sifive_u_soc_type_info = {
	416	.name = TYPE_RISCV_U_SOC,
	417	.parent = TYPE_DEVICE,
	418	.instance_size = sizeof(SiFiveUSoCState),
	419	.instance_init = riscv_sifive_u_soc_init,
	420	.class_init = riscv_sifive_u_soc_class_init,
	421	};
	422
	423	static void riscv_sifive_u_soc_register_types(void)
	424	{
	425	type_register_static(&riscv_sifive_u_soc_type_info);
	426	}
	427
	428	type_init(riscv_sifive_u_soc_register_types)