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a7240d1e MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017 SiFive, Inc. | |
6 | * | |
7 | * Provides a board compatible with the SiFive Freedom U SDK: | |
8 | * | |
9 | * 0) UART | |
10 | * 1) CLINT (Core Level Interruptor) | |
11 | * 2) PLIC (Platform Level Interrupt Controller) | |
af14c840 | 12 | * 3) PRCI (Power, Reset, Clock, Interrupt) |
5461c4fe | 13 | * 4) OTP (One-Time Programmable) memory with stored serial number |
a7240d1e | 14 | * |
f3d47d58 | 15 | * This board currently generates devicetree dynamically that indicates at least |
ecdfe393 | 16 | * two harts and up to five harts. |
a7240d1e MC |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify it | |
19 | * under the terms and conditions of the GNU General Public License, | |
20 | * version 2 or later, as published by the Free Software Foundation. | |
21 | * | |
22 | * This program is distributed in the hope it will be useful, but WITHOUT | |
23 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
24 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
25 | * more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License along with | |
28 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
29 | */ | |
30 | ||
31 | #include "qemu/osdep.h" | |
32 | #include "qemu/log.h" | |
33 | #include "qemu/error-report.h" | |
34 | #include "qapi/error.h" | |
a7240d1e MC |
35 | #include "hw/boards.h" |
36 | #include "hw/loader.h" | |
37 | #include "hw/sysbus.h" | |
38 | #include "hw/char/serial.h" | |
ecdfe393 | 39 | #include "hw/cpu/cluster.h" |
a7240d1e MC |
40 | #include "target/riscv/cpu.h" |
41 | #include "hw/riscv/riscv_hart.h" | |
42 | #include "hw/riscv/sifive_plic.h" | |
43 | #include "hw/riscv/sifive_clint.h" | |
44 | #include "hw/riscv/sifive_uart.h" | |
a7240d1e | 45 | #include "hw/riscv/sifive_u.h" |
0ac24d56 | 46 | #include "hw/riscv/boot.h" |
a7240d1e MC |
47 | #include "chardev/char.h" |
48 | #include "sysemu/arch_init.h" | |
49 | #include "sysemu/device_tree.h" | |
46517dd4 | 50 | #include "sysemu/sysemu.h" |
a7240d1e | 51 | #include "exec/address-spaces.h" |
a7240d1e | 52 | |
5aec3247 MC |
53 | #include <libfdt.h> |
54 | ||
fdd1bda4 AF |
55 | #define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" |
56 | ||
a7240d1e MC |
57 | static const struct MemmapEntry { |
58 | hwaddr base; | |
59 | hwaddr size; | |
60 | } sifive_u_memmap[] = { | |
61 | [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, | |
5aec3247 | 62 | [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, |
a7240d1e MC |
63 | [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, |
64 | [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, | |
af14c840 | 65 | [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, |
4b55bc2b BM |
66 | [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, |
67 | [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, | |
5461c4fe | 68 | [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, |
a7240d1e | 69 | [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, |
5a7f76a3 | 70 | [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, |
a7240d1e MC |
71 | }; |
72 | ||
5461c4fe | 73 | #define OTP_SERIAL 1 |
5a7f76a3 AF |
74 | #define GEM_REVISION 0x10070109 |
75 | ||
9f79638e | 76 | static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, |
a7240d1e MC |
77 | uint64_t mem_size, const char *cmdline) |
78 | { | |
ecdfe393 | 79 | MachineState *ms = MACHINE(qdev_get_machine()); |
a7240d1e MC |
80 | void *fdt; |
81 | int cpu; | |
82 | uint32_t *cells; | |
83 | char *nodename; | |
806c64b7 | 84 | char ethclk_names[] = "pclk\0hclk"; |
af14c840 | 85 | uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; |
44e6dcd3 | 86 | uint32_t uartclk_phandle; |
e1724d09 | 87 | uint32_t hfclk_phandle, rtcclk_phandle; |
a7240d1e MC |
88 | |
89 | fdt = s->fdt = create_device_tree(&s->fdt_size); | |
90 | if (!fdt) { | |
91 | error_report("create_device_tree() failed"); | |
92 | exit(1); | |
93 | } | |
94 | ||
95 | qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); | |
96 | qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); | |
97 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
98 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
99 | ||
100 | qemu_fdt_add_subnode(fdt, "/soc"); | |
101 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
2a1a6f6d | 102 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
a7240d1e MC |
103 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
104 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
105 | ||
e1724d09 BM |
106 | hfclk_phandle = phandle++; |
107 | nodename = g_strdup_printf("/hfclk"); | |
108 | qemu_fdt_add_subnode(fdt, nodename); | |
109 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); | |
110 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); | |
111 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
112 | SIFIVE_U_HFCLK_FREQ); | |
113 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
114 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
115 | g_free(nodename); | |
116 | ||
117 | rtcclk_phandle = phandle++; | |
118 | nodename = g_strdup_printf("/rtcclk"); | |
119 | qemu_fdt_add_subnode(fdt, nodename); | |
120 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); | |
121 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); | |
122 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
123 | SIFIVE_U_RTCCLK_FREQ); | |
124 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
125 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
126 | g_free(nodename); | |
127 | ||
a7240d1e MC |
128 | nodename = g_strdup_printf("/memory@%lx", |
129 | (long)memmap[SIFIVE_U_DRAM].base); | |
130 | qemu_fdt_add_subnode(fdt, nodename); | |
131 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
132 | memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, | |
133 | mem_size >> 32, mem_size); | |
134 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
135 | g_free(nodename); | |
136 | ||
137 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
2a8756ed MC |
138 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
139 | SIFIVE_CLINT_TIMEBASE_FREQ); | |
a7240d1e MC |
140 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
141 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
142 | ||
ecdfe393 | 143 | for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { |
382cb439 | 144 | int cpu_phandle = phandle++; |
a7240d1e MC |
145 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
146 | char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
ecdfe393 | 147 | char *isa; |
a7240d1e | 148 | qemu_fdt_add_subnode(fdt, nodename); |
2a8756ed MC |
149 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", |
150 | SIFIVE_U_CLOCK_FREQ); | |
ecdfe393 BM |
151 | /* cpu 0 is the management hart that does not have mmu */ |
152 | if (cpu != 0) { | |
153 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); | |
154 | isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); | |
155 | } else { | |
156 | isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); | |
157 | } | |
a7240d1e MC |
158 | qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); |
159 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | |
160 | qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | |
161 | qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | |
162 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | |
163 | qemu_fdt_add_subnode(fdt, intc); | |
382cb439 | 164 | qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); |
a7240d1e MC |
165 | qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); |
166 | qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | |
167 | qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | |
168 | g_free(isa); | |
169 | g_free(intc); | |
170 | g_free(nodename); | |
171 | } | |
172 | ||
ecdfe393 BM |
173 | cells = g_new0(uint32_t, ms->smp.cpus * 4); |
174 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
175 | nodename = |
176 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
177 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
178 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
179 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
180 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
181 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
182 | g_free(nodename); | |
183 | } | |
184 | nodename = g_strdup_printf("/soc/clint@%lx", | |
185 | (long)memmap[SIFIVE_U_CLINT].base); | |
186 | qemu_fdt_add_subnode(fdt, nodename); | |
187 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); | |
188 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
189 | 0x0, memmap[SIFIVE_U_CLINT].base, | |
190 | 0x0, memmap[SIFIVE_U_CLINT].size); | |
191 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 192 | cells, ms->smp.cpus * sizeof(uint32_t) * 4); |
a7240d1e MC |
193 | g_free(cells); |
194 | g_free(nodename); | |
195 | ||
af14c840 BM |
196 | prci_phandle = phandle++; |
197 | nodename = g_strdup_printf("/soc/clock-controller@%lx", | |
198 | (long)memmap[SIFIVE_U_PRCI].base); | |
199 | qemu_fdt_add_subnode(fdt, nodename); | |
200 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); | |
201 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); | |
202 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
203 | hfclk_phandle, rtcclk_phandle); | |
204 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
205 | 0x0, memmap[SIFIVE_U_PRCI].base, | |
206 | 0x0, memmap[SIFIVE_U_PRCI].size); | |
207 | qemu_fdt_setprop_string(fdt, nodename, "compatible", | |
208 | "sifive,fu540-c000-prci"); | |
209 | g_free(nodename); | |
210 | ||
382cb439 | 211 | plic_phandle = phandle++; |
ecdfe393 BM |
212 | cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); |
213 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
214 | nodename = |
215 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
216 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
ecdfe393 BM |
217 | /* cpu 0 is the management hart that does not have S-mode */ |
218 | if (cpu == 0) { | |
219 | cells[0] = cpu_to_be32(intc_phandle); | |
220 | cells[1] = cpu_to_be32(IRQ_M_EXT); | |
221 | } else { | |
222 | cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); | |
223 | cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); | |
224 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
225 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); | |
226 | } | |
a7240d1e MC |
227 | g_free(nodename); |
228 | } | |
229 | nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | |
230 | (long)memmap[SIFIVE_U_PLIC].base); | |
231 | qemu_fdt_add_subnode(fdt, nodename); | |
232 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); | |
233 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); | |
234 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
235 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 236 | cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); |
a7240d1e MC |
237 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
238 | 0x0, memmap[SIFIVE_U_PLIC].base, | |
239 | 0x0, memmap[SIFIVE_U_PLIC].size); | |
98ceee7f | 240 | qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); |
04e7edd1 | 241 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); |
a7240d1e MC |
242 | plic_phandle = qemu_fdt_get_phandle(fdt, nodename); |
243 | g_free(cells); | |
244 | g_free(nodename); | |
245 | ||
382cb439 | 246 | ethclk_phandle = phandle++; |
fe93582c AP |
247 | nodename = g_strdup_printf("/soc/ethclk"); |
248 | qemu_fdt_add_subnode(fdt, nodename); | |
249 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
250 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
251 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
252 | SIFIVE_U_GEM_CLOCK_FREQ); | |
382cb439 | 253 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); |
fe93582c AP |
254 | ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); |
255 | g_free(nodename); | |
256 | ||
5a7f76a3 AF |
257 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
258 | (long)memmap[SIFIVE_U_GEM].base); | |
259 | qemu_fdt_add_subnode(fdt, nodename); | |
260 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); | |
261 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
262 | 0x0, memmap[SIFIVE_U_GEM].base, | |
263 | 0x0, memmap[SIFIVE_U_GEM].size); | |
264 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); | |
265 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); | |
04e7edd1 BM |
266 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
267 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); | |
fe93582c | 268 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
806c64b7 | 269 | prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); |
04ece4f8 | 270 | qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, |
fe93582c | 271 | sizeof(ethclk_names)); |
04e7edd1 BM |
272 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
273 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
5a7f76a3 AF |
274 | g_free(nodename); |
275 | ||
276 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", | |
277 | (long)memmap[SIFIVE_U_GEM].base); | |
278 | qemu_fdt_add_subnode(fdt, nodename); | |
04e7edd1 | 279 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
5a7f76a3 AF |
280 | g_free(nodename); |
281 | ||
44e6dcd3 GR |
282 | uartclk_phandle = phandle++; |
283 | nodename = g_strdup_printf("/soc/uartclk"); | |
284 | qemu_fdt_add_subnode(fdt, nodename); | |
285 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
286 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
287 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); | |
288 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle); | |
44e6dcd3 GR |
289 | uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename); |
290 | g_free(nodename); | |
291 | ||
5f7134d3 | 292 | nodename = g_strdup_printf("/soc/serial@%lx", |
a7240d1e MC |
293 | (long)memmap[SIFIVE_U_UART0].base); |
294 | qemu_fdt_add_subnode(fdt, nodename); | |
295 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
296 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
297 | 0x0, memmap[SIFIVE_U_UART0].base, | |
298 | 0x0, memmap[SIFIVE_U_UART0].size); | |
806c64b7 BM |
299 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
300 | prci_phandle, PRCI_CLK_TLCLK); | |
04e7edd1 BM |
301 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
302 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); | |
a7240d1e MC |
303 | |
304 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
305 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | |
7c28f4da MC |
306 | if (cmdline) { |
307 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
308 | } | |
44e6dcd3 GR |
309 | |
310 | qemu_fdt_add_subnode(fdt, "/aliases"); | |
311 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); | |
312 | ||
a7240d1e MC |
313 | g_free(nodename); |
314 | } | |
315 | ||
316 | static void riscv_sifive_u_init(MachineState *machine) | |
317 | { | |
318 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
319 | ||
320 | SiFiveUState *s = g_new0(SiFiveUState, 1); | |
5aec3247 | 321 | MemoryRegion *system_memory = get_system_memory(); |
a7240d1e | 322 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); |
5aec3247 | 323 | int i; |
a7240d1e | 324 | |
2308092b | 325 | /* Initialize SoC */ |
4eea9d7d AF |
326 | object_initialize_child(OBJECT(machine), "soc", &s->soc, |
327 | sizeof(s->soc), TYPE_RISCV_U_SOC, | |
328 | &error_abort, NULL); | |
a7240d1e MC |
329 | object_property_set_bool(OBJECT(&s->soc), true, "realized", |
330 | &error_abort); | |
331 | ||
332 | /* register RAM */ | |
333 | memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", | |
334 | machine->ram_size, &error_fatal); | |
5aec3247 | 335 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, |
2308092b | 336 | main_mem); |
a7240d1e MC |
337 | |
338 | /* create device tree */ | |
9f79638e | 339 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); |
a7240d1e | 340 | |
fdd1bda4 AF |
341 | riscv_find_and_load_firmware(machine, BIOS_FILENAME, |
342 | memmap[SIFIVE_U_DRAM].base); | |
b3042223 | 343 | |
a7240d1e | 344 | if (machine->kernel_filename) { |
0f8d4462 GR |
345 | uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); |
346 | ||
347 | if (machine->initrd_filename) { | |
348 | hwaddr start; | |
349 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | |
350 | machine->ram_size, kernel_entry, | |
351 | &start); | |
9f79638e | 352 | qemu_fdt_setprop_cell(s->fdt, "/chosen", |
0f8d4462 | 353 | "linux,initrd-start", start); |
9f79638e | 354 | qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", |
0f8d4462 GR |
355 | end); |
356 | } | |
a7240d1e MC |
357 | } |
358 | ||
359 | /* reset vector */ | |
360 | uint32_t reset_vec[8] = { | |
361 | 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ | |
362 | 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ | |
363 | 0xf1402573, /* csrr a0, mhartid */ | |
364 | #if defined(TARGET_RISCV32) | |
365 | 0x0182a283, /* lw t0, 24(t0) */ | |
366 | #elif defined(TARGET_RISCV64) | |
367 | 0x0182b283, /* ld t0, 24(t0) */ | |
368 | #endif | |
369 | 0x00028067, /* jr t0 */ | |
370 | 0x00000000, | |
371 | memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ | |
372 | 0x00000000, | |
373 | /* dtb: */ | |
374 | }; | |
375 | ||
5aec3247 MC |
376 | /* copy in the reset vector in little_endian byte order */ |
377 | for (i = 0; i < sizeof(reset_vec) >> 2; i++) { | |
378 | reset_vec[i] = cpu_to_le32(reset_vec[i]); | |
379 | } | |
380 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
381 | memmap[SIFIVE_U_MROM].base, &address_space_memory); | |
a7240d1e MC |
382 | |
383 | /* copy in the device tree */ | |
5aec3247 MC |
384 | if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > |
385 | memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { | |
386 | error_report("not enough space to store device-tree"); | |
387 | exit(1); | |
388 | } | |
389 | qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); | |
390 | rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), | |
391 | memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), | |
392 | &address_space_memory); | |
2308092b AF |
393 | } |
394 | ||
395 | static void riscv_sifive_u_soc_init(Object *obj) | |
396 | { | |
c4473127 | 397 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
398 | SiFiveUSoCState *s = RISCV_U_SOC(obj); |
399 | ||
ecdfe393 BM |
400 | object_initialize_child(obj, "e-cluster", &s->e_cluster, |
401 | sizeof(s->e_cluster), TYPE_CPU_CLUSTER, | |
402 | &error_abort, NULL); | |
403 | qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); | |
404 | ||
405 | object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", | |
406 | &s->e_cpus, sizeof(s->e_cpus), | |
407 | TYPE_RISCV_HART_ARRAY, &error_abort, | |
408 | NULL); | |
409 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); | |
410 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); | |
411 | qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); | |
412 | ||
413 | object_initialize_child(obj, "u-cluster", &s->u_cluster, | |
414 | sizeof(s->u_cluster), TYPE_CPU_CLUSTER, | |
415 | &error_abort, NULL); | |
416 | qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); | |
417 | ||
418 | object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", | |
419 | &s->u_cpus, sizeof(s->u_cpus), | |
420 | TYPE_RISCV_HART_ARRAY, &error_abort, | |
421 | NULL); | |
422 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); | |
423 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); | |
424 | qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); | |
5a7f76a3 | 425 | |
af14c840 BM |
426 | sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci), |
427 | TYPE_SIFIVE_U_PRCI); | |
5461c4fe BM |
428 | sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), |
429 | TYPE_SIFIVE_U_OTP); | |
430 | qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL); | |
4eea9d7d AF |
431 | sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), |
432 | TYPE_CADENCE_GEM); | |
2308092b AF |
433 | } |
434 | ||
435 | static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) | |
436 | { | |
c4473127 | 437 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
438 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
439 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
440 | MemoryRegion *system_memory = get_system_memory(); | |
441 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
5a7f76a3 | 442 | qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; |
05446f41 BM |
443 | char *plic_hart_config; |
444 | size_t plic_hart_config_len; | |
5a7f76a3 AF |
445 | int i; |
446 | Error *err = NULL; | |
447 | NICInfo *nd = &nd_table[0]; | |
2308092b | 448 | |
ecdfe393 BM |
449 | object_property_set_bool(OBJECT(&s->e_cpus), true, "realized", |
450 | &error_abort); | |
451 | object_property_set_bool(OBJECT(&s->u_cpus), true, "realized", | |
452 | &error_abort); | |
453 | /* | |
454 | * The cluster must be realized after the RISC-V hart array container, | |
455 | * as the container's CPU object is only created on realize, and the | |
456 | * CPU must exist and have been parented into the cluster before the | |
457 | * cluster is realized. | |
458 | */ | |
459 | object_property_set_bool(OBJECT(&s->e_cluster), true, "realized", | |
460 | &error_abort); | |
461 | object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", | |
2308092b AF |
462 | &error_abort); |
463 | ||
464 | /* boot rom */ | |
465 | memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", | |
466 | memmap[SIFIVE_U_MROM].size, &error_fatal); | |
467 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, | |
468 | mask_rom); | |
a7240d1e | 469 | |
05446f41 | 470 | /* create PLIC hart topology configuration string */ |
c4473127 LX |
471 | plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * |
472 | ms->smp.cpus; | |
05446f41 | 473 | plic_hart_config = g_malloc0(plic_hart_config_len); |
c4473127 | 474 | for (i = 0; i < ms->smp.cpus; i++) { |
05446f41 | 475 | if (i != 0) { |
ef965ce2 BM |
476 | strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, |
477 | plic_hart_config_len); | |
478 | } else { | |
479 | strncat(plic_hart_config, "M", plic_hart_config_len); | |
05446f41 | 480 | } |
05446f41 BM |
481 | plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); |
482 | } | |
483 | ||
a7240d1e MC |
484 | /* MMIO */ |
485 | s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, | |
05446f41 | 486 | plic_hart_config, |
a7240d1e MC |
487 | SIFIVE_U_PLIC_NUM_SOURCES, |
488 | SIFIVE_U_PLIC_NUM_PRIORITIES, | |
489 | SIFIVE_U_PLIC_PRIORITY_BASE, | |
490 | SIFIVE_U_PLIC_PENDING_BASE, | |
491 | SIFIVE_U_PLIC_ENABLE_BASE, | |
492 | SIFIVE_U_PLIC_ENABLE_STRIDE, | |
493 | SIFIVE_U_PLIC_CONTEXT_BASE, | |
494 | SIFIVE_U_PLIC_CONTEXT_STRIDE, | |
495 | memmap[SIFIVE_U_PLIC].size); | |
5aec3247 | 496 | sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, |
647a70a1 | 497 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
194eef09 MC |
498 | sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, |
499 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); | |
a7240d1e | 500 | sifive_clint_create(memmap[SIFIVE_U_CLINT].base, |
c4473127 | 501 | memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, |
a7240d1e | 502 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); |
5a7f76a3 | 503 | |
af14c840 BM |
504 | object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); |
505 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); | |
506 | ||
5461c4fe BM |
507 | object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); |
508 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); | |
509 | ||
5a7f76a3 AF |
510 | for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { |
511 | plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); | |
512 | } | |
513 | ||
514 | if (nd->used) { | |
515 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
516 | qdev_set_nic_properties(DEVICE(&s->gem), nd); | |
517 | } | |
518 | object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", | |
519 | &error_abort); | |
520 | object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); | |
521 | if (err) { | |
522 | error_propagate(errp, err); | |
523 | return; | |
524 | } | |
525 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); | |
526 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, | |
527 | plic_gpios[SIFIVE_U_GEM_IRQ]); | |
a7240d1e MC |
528 | } |
529 | ||
a7240d1e MC |
530 | static void riscv_sifive_u_machine_init(MachineClass *mc) |
531 | { | |
532 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; | |
533 | mc->init = riscv_sifive_u_init; | |
ecdfe393 | 534 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; |
f3d47d58 BM |
535 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; |
536 | mc->default_cpus = mc->min_cpus; | |
a7240d1e MC |
537 | } |
538 | ||
539 | DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) | |
2308092b AF |
540 | |
541 | static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) | |
542 | { | |
543 | DeviceClass *dc = DEVICE_CLASS(oc); | |
544 | ||
545 | dc->realize = riscv_sifive_u_soc_realize; | |
546 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ | |
547 | dc->user_creatable = false; | |
548 | } | |
549 | ||
550 | static const TypeInfo riscv_sifive_u_soc_type_info = { | |
551 | .name = TYPE_RISCV_U_SOC, | |
552 | .parent = TYPE_DEVICE, | |
553 | .instance_size = sizeof(SiFiveUSoCState), | |
554 | .instance_init = riscv_sifive_u_soc_init, | |
555 | .class_init = riscv_sifive_u_soc_class_init, | |
556 | }; | |
557 | ||
558 | static void riscv_sifive_u_soc_register_types(void) | |
559 | { | |
560 | type_register_static(&riscv_sifive_u_soc_type_info); | |
561 | } | |
562 | ||
563 | type_init(riscv_sifive_u_soc_register_types) |