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a7240d1e MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017 SiFive, Inc. | |
7b6bb66f | 6 | * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> |
a7240d1e MC |
7 | * |
8 | * Provides a board compatible with the SiFive Freedom U SDK: | |
9 | * | |
10 | * 0) UART | |
11 | * 1) CLINT (Core Level Interruptor) | |
12 | * 2) PLIC (Platform Level Interrupt Controller) | |
af14c840 | 13 | * 3) PRCI (Power, Reset, Clock, Interrupt) |
8a88b9f5 BM |
14 | * 4) GPIO (General Purpose Input/Output Controller) |
15 | * 5) OTP (One-Time Programmable) memory with stored serial number | |
16 | * 6) GEM (Gigabit Ethernet Controller) and management block | |
834e027a | 17 | * 7) DMA (Direct Memory Access Controller) |
145b2991 | 18 | * 8) SPI0 connected to an SPI flash |
722f1352 | 19 | * 9) SPI2 connected to an SD card |
ea6eaa06 | 20 | * 10) PWM0 and PWM1 |
a7240d1e | 21 | * |
f3d47d58 | 22 | * This board currently generates devicetree dynamically that indicates at least |
ecdfe393 | 23 | * two harts and up to five harts. |
a7240d1e MC |
24 | * |
25 | * This program is free software; you can redistribute it and/or modify it | |
26 | * under the terms and conditions of the GNU General Public License, | |
27 | * version 2 or later, as published by the Free Software Foundation. | |
28 | * | |
29 | * This program is distributed in the hope it will be useful, but WITHOUT | |
30 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
31 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
32 | * more details. | |
33 | * | |
34 | * You should have received a copy of the GNU General Public License along with | |
35 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
36 | */ | |
37 | ||
38 | #include "qemu/osdep.h" | |
a7240d1e MC |
39 | #include "qemu/error-report.h" |
40 | #include "qapi/error.h" | |
3ca109c3 | 41 | #include "qapi/visitor.h" |
a7240d1e | 42 | #include "hw/boards.h" |
5133ed17 | 43 | #include "hw/irq.h" |
a7240d1e MC |
44 | #include "hw/loader.h" |
45 | #include "hw/sysbus.h" | |
46 | #include "hw/char/serial.h" | |
ecdfe393 | 47 | #include "hw/cpu/cluster.h" |
7b6bb66f | 48 | #include "hw/misc/unimp.h" |
36aa285f | 49 | #include "hw/sd/sd.h" |
145b2991 | 50 | #include "hw/ssi/ssi.h" |
a7240d1e MC |
51 | #include "target/riscv/cpu.h" |
52 | #include "hw/riscv/riscv_hart.h" | |
a7240d1e | 53 | #include "hw/riscv/sifive_u.h" |
0ac24d56 | 54 | #include "hw/riscv/boot.h" |
b609b7e3 | 55 | #include "hw/char/sifive_uart.h" |
cc63a182 | 56 | #include "hw/intc/riscv_aclint.h" |
84fcf3c1 | 57 | #include "hw/intc/sifive_plic.h" |
a7240d1e | 58 | #include "chardev/char.h" |
7b6bb66f | 59 | #include "net/eth.h" |
a7240d1e | 60 | #include "sysemu/device_tree.h" |
5133ed17 | 61 | #include "sysemu/runstate.h" |
46517dd4 | 62 | #include "sysemu/sysemu.h" |
a7240d1e | 63 | |
5aec3247 MC |
64 | #include <libfdt.h> |
65 | ||
074ca702 BM |
66 | /* CLINT timebase frequency */ |
67 | #define CLINT_TIMEBASE_FREQ 1000000 | |
68 | ||
73261285 | 69 | static const MemMapEntry sifive_u_memmap[] = { |
13b8c354 EH |
70 | [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, |
71 | [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, | |
72 | [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, | |
73 | [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, | |
74 | [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, | |
75 | [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, | |
76 | [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, | |
77 | [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, | |
78 | [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, | |
79 | [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, | |
ea6eaa06 AF |
80 | [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 }, |
81 | [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 }, | |
145b2991 | 82 | [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, |
722f1352 | 83 | [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, |
13b8c354 EH |
84 | [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, |
85 | [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, | |
86 | [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, | |
87 | [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, | |
88 | [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, | |
89 | [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, | |
90 | [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, | |
a7240d1e MC |
91 | }; |
92 | ||
5461c4fe | 93 | #define OTP_SERIAL 1 |
5a7f76a3 AF |
94 | #define GEM_REVISION 0x10070109 |
95 | ||
73261285 | 96 | static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, |
f5be2ccb | 97 | bool is_32_bit) |
a7240d1e | 98 | { |
f5be2ccb DHB |
99 | MachineState *ms = MACHINE(s); |
100 | uint64_t mem_size = ms->ram_size; | |
a7240d1e | 101 | void *fdt; |
60c7dfa2 | 102 | int cpu, fdt_size; |
a7240d1e MC |
103 | uint32_t *cells; |
104 | char *nodename; | |
5133ed17 | 105 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; |
7b6bb66f | 106 | uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; |
cb53b283 | 107 | static const char * const ethclk_names[2] = { "pclk", "hclk" }; |
7cfbb17f BM |
108 | static const char * const clint_compat[2] = { |
109 | "sifive,clint0", "riscv,clint0" | |
110 | }; | |
60bb5407 BM |
111 | static const char * const plic_compat[2] = { |
112 | "sifive,plic-1.0.0", "riscv,plic0" | |
113 | }; | |
a7240d1e | 114 | |
f2ce39b4 | 115 | if (ms->dtb) { |
60c7dfa2 | 116 | fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size); |
d5c90cf3 AP |
117 | if (!fdt) { |
118 | error_report("load_device_tree() failed"); | |
119 | exit(1); | |
120 | } | |
d5c90cf3 | 121 | } else { |
60c7dfa2 | 122 | fdt = ms->fdt = create_device_tree(&fdt_size); |
d5c90cf3 AP |
123 | if (!fdt) { |
124 | error_report("create_device_tree() failed"); | |
125 | exit(1); | |
126 | } | |
a7240d1e MC |
127 | } |
128 | ||
d372e748 BM |
129 | qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); |
130 | qemu_fdt_setprop_string(fdt, "/", "compatible", | |
131 | "sifive,hifive-unleashed-a00"); | |
a7240d1e MC |
132 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); |
133 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
134 | ||
135 | qemu_fdt_add_subnode(fdt, "/soc"); | |
136 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
2a1a6f6d | 137 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
a7240d1e MC |
138 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
139 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
140 | ||
e1724d09 BM |
141 | hfclk_phandle = phandle++; |
142 | nodename = g_strdup_printf("/hfclk"); | |
143 | qemu_fdt_add_subnode(fdt, nodename); | |
144 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); | |
145 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); | |
146 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
147 | SIFIVE_U_HFCLK_FREQ); | |
148 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
149 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
150 | g_free(nodename); | |
151 | ||
152 | rtcclk_phandle = phandle++; | |
153 | nodename = g_strdup_printf("/rtcclk"); | |
154 | qemu_fdt_add_subnode(fdt, nodename); | |
155 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); | |
156 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); | |
157 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
158 | SIFIVE_U_RTCCLK_FREQ); | |
159 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
160 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
161 | g_free(nodename); | |
162 | ||
a7240d1e | 163 | nodename = g_strdup_printf("/memory@%lx", |
13b8c354 | 164 | (long)memmap[SIFIVE_U_DEV_DRAM].base); |
a7240d1e MC |
165 | qemu_fdt_add_subnode(fdt, nodename); |
166 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 | 167 | memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, |
a7240d1e MC |
168 | mem_size >> 32, mem_size); |
169 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
170 | g_free(nodename); | |
171 | ||
172 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
2a8756ed | 173 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
074ca702 | 174 | CLINT_TIMEBASE_FREQ); |
a7240d1e MC |
175 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
176 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
177 | ||
ecdfe393 | 178 | for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { |
382cb439 | 179 | int cpu_phandle = phandle++; |
a7240d1e MC |
180 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
181 | char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
ecdfe393 | 182 | char *isa; |
a7240d1e | 183 | qemu_fdt_add_subnode(fdt, nodename); |
ecdfe393 BM |
184 | /* cpu 0 is the management hart that does not have mmu */ |
185 | if (cpu != 0) { | |
2206ffa6 AF |
186 | if (is_32_bit) { |
187 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); | |
188 | } else { | |
189 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); | |
190 | } | |
ecdfe393 BM |
191 | isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); |
192 | } else { | |
193 | isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); | |
194 | } | |
a7240d1e MC |
195 | qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); |
196 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | |
197 | qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | |
198 | qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | |
199 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | |
200 | qemu_fdt_add_subnode(fdt, intc); | |
382cb439 | 201 | qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); |
a7240d1e MC |
202 | qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); |
203 | qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | |
204 | qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | |
205 | g_free(isa); | |
206 | g_free(intc); | |
207 | g_free(nodename); | |
208 | } | |
209 | ||
ecdfe393 BM |
210 | cells = g_new0(uint32_t, ms->smp.cpus * 4); |
211 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
212 | nodename = |
213 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
214 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
215 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
216 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
217 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
218 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
219 | g_free(nodename); | |
220 | } | |
221 | nodename = g_strdup_printf("/soc/clint@%lx", | |
13b8c354 | 222 | (long)memmap[SIFIVE_U_DEV_CLINT].base); |
a7240d1e | 223 | qemu_fdt_add_subnode(fdt, nodename); |
7cfbb17f BM |
224 | qemu_fdt_setprop_string_array(fdt, nodename, "compatible", |
225 | (char **)&clint_compat, ARRAY_SIZE(clint_compat)); | |
a7240d1e | 226 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
227 | 0x0, memmap[SIFIVE_U_DEV_CLINT].base, |
228 | 0x0, memmap[SIFIVE_U_DEV_CLINT].size); | |
a7240d1e | 229 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", |
ecdfe393 | 230 | cells, ms->smp.cpus * sizeof(uint32_t) * 4); |
a7240d1e MC |
231 | g_free(cells); |
232 | g_free(nodename); | |
233 | ||
ea85f27d | 234 | nodename = g_strdup_printf("/soc/otp@%lx", |
13b8c354 | 235 | (long)memmap[SIFIVE_U_DEV_OTP].base); |
ea85f27d BM |
236 | qemu_fdt_add_subnode(fdt, nodename); |
237 | qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); | |
238 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
239 | 0x0, memmap[SIFIVE_U_DEV_OTP].base, |
240 | 0x0, memmap[SIFIVE_U_DEV_OTP].size); | |
ea85f27d BM |
241 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
242 | "sifive,fu540-c000-otp"); | |
243 | g_free(nodename); | |
244 | ||
af14c840 BM |
245 | prci_phandle = phandle++; |
246 | nodename = g_strdup_printf("/soc/clock-controller@%lx", | |
13b8c354 | 247 | (long)memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 BM |
248 | qemu_fdt_add_subnode(fdt, nodename); |
249 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); | |
250 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); | |
251 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
252 | hfclk_phandle, rtcclk_phandle); | |
253 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
254 | 0x0, memmap[SIFIVE_U_DEV_PRCI].base, |
255 | 0x0, memmap[SIFIVE_U_DEV_PRCI].size); | |
af14c840 BM |
256 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
257 | "sifive,fu540-c000-prci"); | |
258 | g_free(nodename); | |
259 | ||
382cb439 | 260 | plic_phandle = phandle++; |
ecdfe393 BM |
261 | cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); |
262 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
263 | nodename = |
264 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
265 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
ecdfe393 BM |
266 | /* cpu 0 is the management hart that does not have S-mode */ |
267 | if (cpu == 0) { | |
268 | cells[0] = cpu_to_be32(intc_phandle); | |
269 | cells[1] = cpu_to_be32(IRQ_M_EXT); | |
270 | } else { | |
271 | cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); | |
272 | cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); | |
273 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
274 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); | |
275 | } | |
a7240d1e MC |
276 | g_free(nodename); |
277 | } | |
278 | nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | |
13b8c354 | 279 | (long)memmap[SIFIVE_U_DEV_PLIC].base); |
a7240d1e MC |
280 | qemu_fdt_add_subnode(fdt, nodename); |
281 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); | |
60bb5407 BM |
282 | qemu_fdt_setprop_string_array(fdt, nodename, "compatible", |
283 | (char **)&plic_compat, ARRAY_SIZE(plic_compat)); | |
a7240d1e MC |
284 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); |
285 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 286 | cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); |
a7240d1e | 287 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
288 | 0x0, memmap[SIFIVE_U_DEV_PLIC].base, |
289 | 0x0, memmap[SIFIVE_U_DEV_PLIC].size); | |
724d80c8 BM |
290 | qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", |
291 | SIFIVE_U_PLIC_NUM_SOURCES - 1); | |
04e7edd1 | 292 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); |
a7240d1e MC |
293 | plic_phandle = qemu_fdt_get_phandle(fdt, nodename); |
294 | g_free(cells); | |
295 | g_free(nodename); | |
296 | ||
5133ed17 | 297 | gpio_phandle = phandle++; |
8a88b9f5 | 298 | nodename = g_strdup_printf("/soc/gpio@%lx", |
13b8c354 | 299 | (long)memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 | 300 | qemu_fdt_add_subnode(fdt, nodename); |
5133ed17 | 301 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); |
8a88b9f5 BM |
302 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
303 | prci_phandle, PRCI_CLK_TLCLK); | |
304 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); | |
305 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
306 | qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); | |
307 | qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); | |
308 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
309 | 0x0, memmap[SIFIVE_U_DEV_GPIO].base, |
310 | 0x0, memmap[SIFIVE_U_DEV_GPIO].size); | |
8a88b9f5 BM |
311 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, |
312 | SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, | |
313 | SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, | |
314 | SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, | |
315 | SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, | |
316 | SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); | |
317 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
318 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); | |
319 | g_free(nodename); | |
320 | ||
5133ed17 BM |
321 | nodename = g_strdup_printf("/gpio-restart"); |
322 | qemu_fdt_add_subnode(fdt, nodename); | |
323 | qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); | |
324 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); | |
325 | g_free(nodename); | |
326 | ||
834e027a | 327 | nodename = g_strdup_printf("/soc/dma@%lx", |
13b8c354 | 328 | (long)memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
329 | qemu_fdt_add_subnode(fdt, nodename); |
330 | qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); | |
331 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
332 | SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, | |
333 | SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, | |
334 | SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); | |
335 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
336 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
337 | 0x0, memmap[SIFIVE_U_DEV_PDMA].base, |
338 | 0x0, memmap[SIFIVE_U_DEV_PDMA].size); | |
834e027a BM |
339 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
340 | "sifive,fu540-c000-pdma"); | |
341 | g_free(nodename); | |
342 | ||
6eaf9cf5 | 343 | nodename = g_strdup_printf("/soc/cache-controller@%lx", |
13b8c354 | 344 | (long)memmap[SIFIVE_U_DEV_L2CC].base); |
6eaf9cf5 BM |
345 | qemu_fdt_add_subnode(fdt, nodename); |
346 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
347 | 0x0, memmap[SIFIVE_U_DEV_L2CC].base, |
348 | 0x0, memmap[SIFIVE_U_DEV_L2CC].size); | |
6eaf9cf5 BM |
349 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", |
350 | SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); | |
351 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
352 | qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); | |
353 | qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); | |
354 | qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); | |
355 | qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); | |
356 | qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); | |
357 | qemu_fdt_setprop_string(fdt, nodename, "compatible", | |
358 | "sifive,fu540-c000-ccache"); | |
359 | g_free(nodename); | |
360 | ||
722f1352 BM |
361 | nodename = g_strdup_printf("/soc/spi@%lx", |
362 | (long)memmap[SIFIVE_U_DEV_QSPI2].base); | |
363 | qemu_fdt_add_subnode(fdt, nodename); | |
364 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
365 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); | |
366 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
367 | prci_phandle, PRCI_CLK_TLCLK); | |
368 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); | |
369 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
370 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
371 | 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, | |
372 | 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); | |
373 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); | |
374 | g_free(nodename); | |
375 | ||
376 | nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", | |
377 | (long)memmap[SIFIVE_U_DEV_QSPI2].base); | |
378 | qemu_fdt_add_subnode(fdt, nodename); | |
379 | qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); | |
380 | qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); | |
381 | qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); | |
382 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); | |
383 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); | |
384 | g_free(nodename); | |
385 | ||
145b2991 BM |
386 | nodename = g_strdup_printf("/soc/spi@%lx", |
387 | (long)memmap[SIFIVE_U_DEV_QSPI0].base); | |
388 | qemu_fdt_add_subnode(fdt, nodename); | |
389 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
390 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); | |
391 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
392 | prci_phandle, PRCI_CLK_TLCLK); | |
393 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); | |
394 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
395 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
396 | 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, | |
397 | 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); | |
398 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); | |
399 | g_free(nodename); | |
400 | ||
401 | nodename = g_strdup_printf("/soc/spi@%lx/flash@0", | |
402 | (long)memmap[SIFIVE_U_DEV_QSPI0].base); | |
403 | qemu_fdt_add_subnode(fdt, nodename); | |
404 | qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); | |
405 | qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); | |
406 | qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); | |
407 | qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); | |
408 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); | |
409 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); | |
410 | g_free(nodename); | |
411 | ||
7b6bb66f | 412 | phy_phandle = phandle++; |
5a7f76a3 | 413 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
13b8c354 | 414 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 415 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f BM |
416 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
417 | "sifive,fu540-c000-gem"); | |
5a7f76a3 | 418 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
419 | 0x0, memmap[SIFIVE_U_DEV_GEM].base, |
420 | 0x0, memmap[SIFIVE_U_DEV_GEM].size, | |
421 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, | |
422 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); | |
5a7f76a3 AF |
423 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); |
424 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); | |
7b6bb66f | 425 | qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); |
04e7edd1 BM |
426 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
427 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); | |
fe93582c | 428 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
806c64b7 | 429 | prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); |
cb53b283 BM |
430 | qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", |
431 | (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); | |
7b6bb66f BM |
432 | qemu_fdt_setprop(fdt, nodename, "local-mac-address", |
433 | s->soc.gem.conf.macaddr.a, ETH_ALEN); | |
04e7edd1 BM |
434 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
435 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
c3a28b5d BM |
436 | |
437 | qemu_fdt_add_subnode(fdt, "/aliases"); | |
438 | qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); | |
439 | ||
5a7f76a3 AF |
440 | g_free(nodename); |
441 | ||
442 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", | |
13b8c354 | 443 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 444 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f | 445 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); |
04e7edd1 | 446 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
5a7f76a3 AF |
447 | g_free(nodename); |
448 | ||
ea6eaa06 AF |
449 | nodename = g_strdup_printf("/soc/pwm@%lx", |
450 | (long)memmap[SIFIVE_U_DEV_PWM0].base); | |
451 | qemu_fdt_add_subnode(fdt, nodename); | |
452 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); | |
453 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
454 | 0x0, memmap[SIFIVE_U_DEV_PWM0].base, | |
455 | 0x0, memmap[SIFIVE_U_DEV_PWM0].size); | |
456 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
457 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
458 | SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1, | |
459 | SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3); | |
460 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
461 | prci_phandle, PRCI_CLK_TLCLK); | |
462 | qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); | |
463 | g_free(nodename); | |
464 | ||
465 | nodename = g_strdup_printf("/soc/pwm@%lx", | |
466 | (long)memmap[SIFIVE_U_DEV_PWM1].base); | |
467 | qemu_fdt_add_subnode(fdt, nodename); | |
468 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); | |
469 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
470 | 0x0, memmap[SIFIVE_U_DEV_PWM1].base, | |
471 | 0x0, memmap[SIFIVE_U_DEV_PWM1].size); | |
472 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
473 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
474 | SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1, | |
475 | SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3); | |
476 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
477 | prci_phandle, PRCI_CLK_TLCLK); | |
478 | qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); | |
479 | g_free(nodename); | |
480 | ||
10b43754 AP |
481 | nodename = g_strdup_printf("/soc/serial@%lx", |
482 | (long)memmap[SIFIVE_U_DEV_UART1].base); | |
483 | qemu_fdt_add_subnode(fdt, nodename); | |
484 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
485 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
486 | 0x0, memmap[SIFIVE_U_DEV_UART1].base, | |
487 | 0x0, memmap[SIFIVE_U_DEV_UART1].size); | |
488 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
489 | prci_phandle, PRCI_CLK_TLCLK); | |
490 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
491 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); | |
492 | ||
493 | qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); | |
494 | g_free(nodename); | |
495 | ||
5f7134d3 | 496 | nodename = g_strdup_printf("/soc/serial@%lx", |
13b8c354 | 497 | (long)memmap[SIFIVE_U_DEV_UART0].base); |
a7240d1e MC |
498 | qemu_fdt_add_subnode(fdt, nodename); |
499 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
500 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
501 | 0x0, memmap[SIFIVE_U_DEV_UART0].base, |
502 | 0x0, memmap[SIFIVE_U_DEV_UART0].size); | |
806c64b7 BM |
503 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
504 | prci_phandle, PRCI_CLK_TLCLK); | |
04e7edd1 BM |
505 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
506 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); | |
a7240d1e MC |
507 | |
508 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
509 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | |
44e6dcd3 GR |
510 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); |
511 | ||
a7240d1e MC |
512 | g_free(nodename); |
513 | } | |
514 | ||
5133ed17 BM |
515 | static void sifive_u_machine_reset(void *opaque, int n, int level) |
516 | { | |
517 | /* gpio pin active low triggers reset */ | |
518 | if (!level) { | |
519 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
520 | } | |
521 | } | |
522 | ||
523e3464 | 523 | static void sifive_u_machine_init(MachineState *machine) |
a7240d1e | 524 | { |
73261285 | 525 | const MemMapEntry *memmap = sifive_u_memmap; |
687caef1 | 526 | SiFiveUState *s = RISCV_U_MACHINE(machine); |
5aec3247 | 527 | MemoryRegion *system_memory = get_system_memory(); |
1b3a2308 | 528 | MemoryRegion *flash0 = g_new(MemoryRegion, 1); |
13b8c354 | 529 | target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
38bc4e34 | 530 | target_ulong firmware_end_addr, kernel_start_addr; |
9d3f7108 | 531 | const char *firmware_name; |
8590f536 | 532 | uint32_t start_addr_hi32 = 0x00000000; |
5aec3247 | 533 | int i; |
66b1205b | 534 | uint32_t fdt_load_addr; |
dc144fe1 | 535 | uint64_t kernel_entry; |
145b2991 | 536 | DriveInfo *dinfo; |
36aa285f MA |
537 | BlockBackend *blk; |
538 | DeviceState *flash_dev, *sd_dev, *card_dev; | |
722f1352 | 539 | qemu_irq flash_cs, sd_cs; |
a7240d1e | 540 | |
2308092b | 541 | /* Initialize SoC */ |
9fc7fc4d | 542 | object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); |
5325cc34 MA |
543 | object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, |
544 | &error_abort); | |
099be035 AF |
545 | object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, |
546 | &error_abort); | |
8f972e5b | 547 | qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); |
a7240d1e MC |
548 | |
549 | /* register RAM */ | |
13b8c354 | 550 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, |
c188a9c4 | 551 | machine->ram); |
a7240d1e | 552 | |
1b3a2308 AF |
553 | /* register QSPI0 Flash */ |
554 | memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", | |
13b8c354 EH |
555 | memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); |
556 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, | |
1b3a2308 AF |
557 | flash0); |
558 | ||
5133ed17 BM |
559 | /* register gpio-restart */ |
560 | qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, | |
561 | qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); | |
562 | ||
a7240d1e | 563 | /* create device tree */ |
f5be2ccb | 564 | create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); |
a7240d1e | 565 | |
17aad9f2 BM |
566 | if (s->start_in_flash) { |
567 | /* | |
568 | * If start_in_flash property is given, assign s->msel to a value | |
569 | * that representing booting from QSPI0 memory-mapped flash. | |
570 | * | |
571 | * This also means that when both start_in_flash and msel properties | |
572 | * are given, start_in_flash takes the precedence over msel. | |
573 | * | |
574 | * Note this is to keep backward compatibility not to break existing | |
575 | * users that use start_in_flash property. | |
576 | */ | |
577 | s->msel = MSEL_MEMMAP_QSPI0_FLASH; | |
578 | } | |
579 | ||
580 | switch (s->msel) { | |
581 | case MSEL_MEMMAP_QSPI0_FLASH: | |
13b8c354 | 582 | start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; |
17aad9f2 BM |
583 | break; |
584 | case MSEL_L2LIM_QSPI0_FLASH: | |
585 | case MSEL_L2LIM_QSPI2_SD: | |
13b8c354 | 586 | start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; |
17aad9f2 BM |
587 | break; |
588 | default: | |
13b8c354 | 589 | start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
17aad9f2 BM |
590 | break; |
591 | } | |
592 | ||
9d3f7108 DHB |
593 | firmware_name = riscv_default_firmware_name(&s->soc.u_cpus); |
594 | firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, | |
595 | start_addr, NULL); | |
b3042223 | 596 | |
a7240d1e | 597 | if (machine->kernel_filename) { |
a8259b53 | 598 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, |
38bc4e34 AF |
599 | firmware_end_addr); |
600 | ||
60c1f05e | 601 | kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); |
0f8d4462 GR |
602 | |
603 | if (machine->initrd_filename) { | |
1f991461 | 604 | riscv_load_initrd(machine, kernel_entry); |
0f8d4462 | 605 | } |
b1f19f23 DHB |
606 | |
607 | if (machine->kernel_cmdline && *machine->kernel_cmdline) { | |
608 | qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", | |
609 | machine->kernel_cmdline); | |
610 | } | |
dc144fe1 AP |
611 | } else { |
612 | /* | |
613 | * If dynamic firmware is used, it doesn't know where is the next mode | |
614 | * if kernel argument is not set. | |
615 | */ | |
616 | kernel_entry = 0; | |
a7240d1e MC |
617 | } |
618 | ||
66b1205b | 619 | /* Compute the fdt load address in dram */ |
13b8c354 | 620 | fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, |
60c7dfa2 | 621 | machine->ram_size, machine->fdt); |
a8259b53 | 622 | if (!riscv_is_32bit(&s->soc.u_cpus)) { |
2206ffa6 AF |
623 | start_addr_hi32 = (uint64_t)start_addr >> 32; |
624 | } | |
66b1205b | 625 | |
a7240d1e | 626 | /* reset vector */ |
623d53cb | 627 | uint32_t reset_vec[12] = { |
17aad9f2 | 628 | s->msel, /* MSEL pin state */ |
dc144fe1 | 629 | 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ |
623d53cb | 630 | 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ |
a7240d1e | 631 | 0xf1402573, /* csrr a0, mhartid */ |
2206ffa6 AF |
632 | 0, |
633 | 0, | |
a7240d1e | 634 | 0x00028067, /* jr t0 */ |
fc41ae23 | 635 | start_addr, /* start: .dword */ |
8590f536 | 636 | start_addr_hi32, |
66b1205b | 637 | fdt_load_addr, /* fdt_laddr: .dword */ |
623d53cb | 638 | 0x00000000, |
66b1205b | 639 | 0x00000000, |
dc144fe1 | 640 | /* fw_dyn: */ |
a7240d1e | 641 | }; |
a8259b53 | 642 | if (riscv_is_32bit(&s->soc.u_cpus)) { |
2206ffa6 AF |
643 | reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ |
644 | reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ | |
645 | } else { | |
646 | reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ | |
647 | reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ | |
648 | } | |
649 | ||
a7240d1e | 650 | |
5aec3247 | 651 | /* copy in the reset vector in little_endian byte order */ |
66b1205b | 652 | for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { |
5aec3247 MC |
653 | reset_vec[i] = cpu_to_le32(reset_vec[i]); |
654 | } | |
655 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
13b8c354 | 656 | memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); |
dc144fe1 | 657 | |
78936771 | 658 | riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, |
13b8c354 | 659 | memmap[SIFIVE_U_DEV_MROM].size, |
dc144fe1 | 660 | sizeof(reset_vec), kernel_entry); |
145b2991 BM |
661 | |
662 | /* Connect an SPI flash to SPI0 */ | |
663 | flash_dev = qdev_new("is25wp256"); | |
64eaa820 | 664 | dinfo = drive_get(IF_MTD, 0, 0); |
145b2991 BM |
665 | if (dinfo) { |
666 | qdev_prop_set_drive_err(flash_dev, "drive", | |
667 | blk_by_legacy_dinfo(dinfo), | |
668 | &error_fatal); | |
669 | } | |
670 | qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); | |
671 | ||
672 | flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); | |
673 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); | |
722f1352 BM |
674 | |
675 | /* Connect an SD card to SPI2 */ | |
676 | sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); | |
677 | ||
678 | sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); | |
679 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); | |
36aa285f MA |
680 | |
681 | dinfo = drive_get(IF_SD, 0, 0); | |
682 | blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; | |
683 | card_dev = qdev_new(TYPE_SD_CARD); | |
684 | qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal); | |
685 | qdev_prop_set_bit(card_dev, "spi", true); | |
686 | qdev_realize_and_unref(card_dev, | |
687 | qdev_get_child_bus(sd_dev, "sd-bus"), | |
688 | &error_fatal); | |
2308092b AF |
689 | } |
690 | ||
523e3464 AF |
691 | static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) |
692 | { | |
693 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
694 | ||
695 | return s->start_in_flash; | |
696 | } | |
697 | ||
698 | static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) | |
699 | { | |
700 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
701 | ||
702 | s->start_in_flash = value; | |
703 | } | |
704 | ||
705 | static void sifive_u_machine_instance_init(Object *obj) | |
706 | { | |
707 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
708 | ||
709 | s->start_in_flash = false; | |
cfa32630 | 710 | s->msel = 0; |
96c7fff7 BB |
711 | object_property_add_uint32_ptr(obj, "msel", &s->msel, |
712 | OBJ_PROP_FLAG_READWRITE); | |
cfa32630 BM |
713 | object_property_set_description(obj, "msel", |
714 | "Mode Select (MSEL[3:0]) pin state"); | |
715 | ||
3ca109c3 | 716 | s->serial = OTP_SERIAL; |
96c7fff7 BB |
717 | object_property_add_uint32_ptr(obj, "serial", &s->serial, |
718 | OBJ_PROP_FLAG_READWRITE); | |
7eecec7d | 719 | object_property_set_description(obj, "serial", "Board serial number"); |
523e3464 AF |
720 | } |
721 | ||
722 | static void sifive_u_machine_class_init(ObjectClass *oc, void *data) | |
723 | { | |
724 | MachineClass *mc = MACHINE_CLASS(oc); | |
725 | ||
726 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; | |
727 | mc->init = sifive_u_machine_init; | |
728 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; | |
729 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; | |
1eaada8a | 730 | mc->default_cpu_type = SIFIVE_U_CPU; |
523e3464 | 731 | mc->default_cpus = mc->min_cpus; |
c188a9c4 | 732 | mc->default_ram_id = "riscv.sifive.u.ram"; |
418b473e EH |
733 | |
734 | object_class_property_add_bool(oc, "start-in-flash", | |
735 | sifive_u_machine_get_start_in_flash, | |
736 | sifive_u_machine_set_start_in_flash); | |
737 | object_class_property_set_description(oc, "start-in-flash", | |
738 | "Set on to tell QEMU's ROM to jump to " | |
739 | "flash. Otherwise QEMU will jump to DRAM " | |
740 | "or L2LIM depending on the msel value"); | |
523e3464 AF |
741 | } |
742 | ||
743 | static const TypeInfo sifive_u_machine_typeinfo = { | |
744 | .name = MACHINE_TYPE_NAME("sifive_u"), | |
745 | .parent = TYPE_MACHINE, | |
746 | .class_init = sifive_u_machine_class_init, | |
747 | .instance_init = sifive_u_machine_instance_init, | |
748 | .instance_size = sizeof(SiFiveUState), | |
749 | }; | |
750 | ||
751 | static void sifive_u_machine_init_register_types(void) | |
752 | { | |
753 | type_register_static(&sifive_u_machine_typeinfo); | |
754 | } | |
755 | ||
756 | type_init(sifive_u_machine_init_register_types) | |
757 | ||
139177b1 | 758 | static void sifive_u_soc_instance_init(Object *obj) |
2308092b AF |
759 | { |
760 | SiFiveUSoCState *s = RISCV_U_SOC(obj); | |
761 | ||
9fc7fc4d | 762 | object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
763 | qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); |
764 | ||
db873cc5 MA |
765 | object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, |
766 | TYPE_RISCV_HART_ARRAY); | |
ecdfe393 BM |
767 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); |
768 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); | |
769 | qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); | |
73f6ed97 | 770 | qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); |
ecdfe393 | 771 | |
9fc7fc4d | 772 | object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
773 | qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); |
774 | ||
db873cc5 MA |
775 | object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, |
776 | TYPE_RISCV_HART_ARRAY); | |
5a7f76a3 | 777 | |
db873cc5 MA |
778 | object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); |
779 | object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); | |
780 | object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); | |
8a88b9f5 | 781 | object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); |
834e027a | 782 | object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); |
145b2991 | 783 | object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); |
722f1352 | 784 | object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); |
ea6eaa06 AF |
785 | object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); |
786 | object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM); | |
2308092b AF |
787 | } |
788 | ||
139177b1 | 789 | static void sifive_u_soc_realize(DeviceState *dev, Error **errp) |
2308092b | 790 | { |
c4473127 | 791 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b | 792 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
73261285 | 793 | const MemMapEntry *memmap = sifive_u_memmap; |
2308092b AF |
794 | MemoryRegion *system_memory = get_system_memory(); |
795 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
a6902ef0 | 796 | MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); |
05446f41 | 797 | char *plic_hart_config; |
ea6eaa06 | 798 | int i, j; |
5a7f76a3 | 799 | NICInfo *nd = &nd_table[0]; |
2308092b | 800 | |
099be035 AF |
801 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); |
802 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); | |
803 | qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); | |
804 | qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); | |
805 | ||
91a3387d TO |
806 | sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal); |
807 | sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal); | |
ecdfe393 BM |
808 | /* |
809 | * The cluster must be realized after the RISC-V hart array container, | |
810 | * as the container's CPU object is only created on realize, and the | |
811 | * CPU must exist and have been parented into the cluster before the | |
812 | * cluster is realized. | |
813 | */ | |
ce189ab2 MA |
814 | qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); |
815 | qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); | |
2308092b AF |
816 | |
817 | /* boot rom */ | |
414c47d2 | 818 | memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", |
13b8c354 EH |
819 | memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); |
820 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, | |
2308092b | 821 | mask_rom); |
a7240d1e | 822 | |
a6902ef0 AF |
823 | /* |
824 | * Add L2-LIM at reset size. | |
825 | * This should be reduced in size as the L2 Cache Controller WayEnable | |
826 | * register is incremented. Unfortunately I don't see a nice (or any) way | |
827 | * to handle reducing or blocking out the L2 LIM while still allowing it | |
828 | * be re returned to all enabled after a reset. For the time being, just | |
829 | * leave it enabled all the time. This won't break anything, but will be | |
830 | * too generous to misbehaving guests. | |
831 | */ | |
832 | memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", | |
13b8c354 EH |
833 | memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); |
834 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, | |
a6902ef0 AF |
835 | l2lim_mem); |
836 | ||
05446f41 | 837 | /* create PLIC hart topology configuration string */ |
4e8fb53c | 838 | plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); |
05446f41 | 839 | |
a7240d1e | 840 | /* MMIO */ |
13b8c354 | 841 | s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, |
f436ecc3 | 842 | plic_hart_config, ms->smp.cpus, 0, |
a7240d1e MC |
843 | SIFIVE_U_PLIC_NUM_SOURCES, |
844 | SIFIVE_U_PLIC_NUM_PRIORITIES, | |
845 | SIFIVE_U_PLIC_PRIORITY_BASE, | |
846 | SIFIVE_U_PLIC_PENDING_BASE, | |
847 | SIFIVE_U_PLIC_ENABLE_BASE, | |
848 | SIFIVE_U_PLIC_ENABLE_STRIDE, | |
849 | SIFIVE_U_PLIC_CONTEXT_BASE, | |
850 | SIFIVE_U_PLIC_CONTEXT_STRIDE, | |
13b8c354 | 851 | memmap[SIFIVE_U_DEV_PLIC].size); |
bb8136df | 852 | g_free(plic_hart_config); |
13b8c354 | 853 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, |
647a70a1 | 854 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
13b8c354 | 855 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, |
194eef09 | 856 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); |
b8fb878a AP |
857 | riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, |
858 | ms->smp.cpus, false); | |
859 | riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + | |
860 | RISCV_ACLINT_SWI_SIZE, | |
861 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, | |
862 | RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, | |
074ca702 | 863 | CLINT_TIMEBASE_FREQ, false); |
5a7f76a3 | 864 | |
cbe3a8c5 MA |
865 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { |
866 | return; | |
867 | } | |
13b8c354 | 868 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 | 869 | |
8a88b9f5 | 870 | qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); |
cbe3a8c5 MA |
871 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
872 | return; | |
873 | } | |
13b8c354 | 874 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 BM |
875 | |
876 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
877 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); | |
878 | ||
879 | /* Connect GPIO interrupts to the PLIC */ | |
880 | for (i = 0; i < 16; i++) { | |
881 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, | |
882 | qdev_get_gpio_in(DEVICE(s->plic), | |
883 | SIFIVE_U_GPIO_IRQ0 + i)); | |
834e027a BM |
884 | } |
885 | ||
886 | /* PDMA */ | |
887 | sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); | |
13b8c354 | 888 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
889 | |
890 | /* Connect PDMA interrupts to the PLIC */ | |
891 | for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { | |
892 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, | |
893 | qdev_get_gpio_in(DEVICE(s->plic), | |
894 | SIFIVE_U_PDMA_IRQ0 + i)); | |
8a88b9f5 BM |
895 | } |
896 | ||
fda5b000 | 897 | qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); |
cbe3a8c5 MA |
898 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { |
899 | return; | |
900 | } | |
13b8c354 | 901 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); |
5461c4fe | 902 | |
7ad36e2e | 903 | /* FIXME use qdev NIC properties instead of nd_table[] */ |
5a7f76a3 AF |
904 | if (nd->used) { |
905 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
906 | qdev_set_nic_properties(DEVICE(&s->gem), nd); | |
907 | } | |
5325cc34 | 908 | object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, |
5a7f76a3 | 909 | &error_abort); |
668f62ec | 910 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { |
5a7f76a3 AF |
911 | return; |
912 | } | |
13b8c354 | 913 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 914 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, |
5874f0a7 | 915 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); |
7b6bb66f | 916 | |
ea6eaa06 AF |
917 | /* PWM */ |
918 | for (i = 0; i < 2; i++) { | |
919 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) { | |
920 | return; | |
921 | } | |
922 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, | |
923 | memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i)); | |
924 | ||
925 | /* Connect PWM interrupts to the PLIC */ | |
926 | for (j = 0; j < SIFIVE_PWM_IRQS; j++) { | |
927 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j, | |
928 | qdev_get_gpio_in(DEVICE(s->plic), | |
929 | SIFIVE_U_PWM0_IRQ0 + (i * 4) + j)); | |
930 | } | |
931 | } | |
932 | ||
7b6bb66f | 933 | create_unimplemented_device("riscv.sifive.u.gem-mgmt", |
13b8c354 | 934 | memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); |
3eaea6eb BM |
935 | |
936 | create_unimplemented_device("riscv.sifive.u.dmc", | |
13b8c354 | 937 | memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); |
6eaf9cf5 BM |
938 | |
939 | create_unimplemented_device("riscv.sifive.u.l2cc", | |
13b8c354 | 940 | memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); |
145b2991 BM |
941 | |
942 | sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); | |
943 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, | |
944 | memmap[SIFIVE_U_DEV_QSPI0].base); | |
945 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, | |
946 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); | |
722f1352 BM |
947 | sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); |
948 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, | |
949 | memmap[SIFIVE_U_DEV_QSPI2].base); | |
950 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, | |
951 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); | |
a7240d1e MC |
952 | } |
953 | ||
139177b1 | 954 | static Property sifive_u_soc_props[] = { |
fda5b000 | 955 | DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), |
099be035 | 956 | DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), |
fda5b000 AF |
957 | DEFINE_PROP_END_OF_LIST() |
958 | }; | |
959 | ||
139177b1 | 960 | static void sifive_u_soc_class_init(ObjectClass *oc, void *data) |
2308092b AF |
961 | { |
962 | DeviceClass *dc = DEVICE_CLASS(oc); | |
963 | ||
139177b1 BM |
964 | device_class_set_props(dc, sifive_u_soc_props); |
965 | dc->realize = sifive_u_soc_realize; | |
2308092b AF |
966 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
967 | dc->user_creatable = false; | |
968 | } | |
969 | ||
139177b1 | 970 | static const TypeInfo sifive_u_soc_type_info = { |
2308092b AF |
971 | .name = TYPE_RISCV_U_SOC, |
972 | .parent = TYPE_DEVICE, | |
973 | .instance_size = sizeof(SiFiveUSoCState), | |
139177b1 BM |
974 | .instance_init = sifive_u_soc_instance_init, |
975 | .class_init = sifive_u_soc_class_init, | |
2308092b AF |
976 | }; |
977 | ||
139177b1 | 978 | static void sifive_u_soc_register_types(void) |
2308092b | 979 | { |
139177b1 | 980 | type_register_static(&sifive_u_soc_type_info); |
2308092b AF |
981 | } |
982 | ||
139177b1 | 983 | type_init(sifive_u_soc_register_types) |