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a7240d1e MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017 SiFive, Inc. | |
7b6bb66f | 6 | * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> |
a7240d1e MC |
7 | * |
8 | * Provides a board compatible with the SiFive Freedom U SDK: | |
9 | * | |
10 | * 0) UART | |
11 | * 1) CLINT (Core Level Interruptor) | |
12 | * 2) PLIC (Platform Level Interrupt Controller) | |
af14c840 | 13 | * 3) PRCI (Power, Reset, Clock, Interrupt) |
8a88b9f5 BM |
14 | * 4) GPIO (General Purpose Input/Output Controller) |
15 | * 5) OTP (One-Time Programmable) memory with stored serial number | |
16 | * 6) GEM (Gigabit Ethernet Controller) and management block | |
a7240d1e | 17 | * |
f3d47d58 | 18 | * This board currently generates devicetree dynamically that indicates at least |
ecdfe393 | 19 | * two harts and up to five harts. |
a7240d1e MC |
20 | * |
21 | * This program is free software; you can redistribute it and/or modify it | |
22 | * under the terms and conditions of the GNU General Public License, | |
23 | * version 2 or later, as published by the Free Software Foundation. | |
24 | * | |
25 | * This program is distributed in the hope it will be useful, but WITHOUT | |
26 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
27 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
28 | * more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License along with | |
31 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
32 | */ | |
33 | ||
34 | #include "qemu/osdep.h" | |
35 | #include "qemu/log.h" | |
36 | #include "qemu/error-report.h" | |
37 | #include "qapi/error.h" | |
3ca109c3 | 38 | #include "qapi/visitor.h" |
a7240d1e | 39 | #include "hw/boards.h" |
5133ed17 | 40 | #include "hw/irq.h" |
a7240d1e MC |
41 | #include "hw/loader.h" |
42 | #include "hw/sysbus.h" | |
43 | #include "hw/char/serial.h" | |
ecdfe393 | 44 | #include "hw/cpu/cluster.h" |
7b6bb66f | 45 | #include "hw/misc/unimp.h" |
a7240d1e MC |
46 | #include "target/riscv/cpu.h" |
47 | #include "hw/riscv/riscv_hart.h" | |
48 | #include "hw/riscv/sifive_plic.h" | |
49 | #include "hw/riscv/sifive_clint.h" | |
50 | #include "hw/riscv/sifive_uart.h" | |
a7240d1e | 51 | #include "hw/riscv/sifive_u.h" |
0ac24d56 | 52 | #include "hw/riscv/boot.h" |
a7240d1e | 53 | #include "chardev/char.h" |
7b6bb66f | 54 | #include "net/eth.h" |
a7240d1e MC |
55 | #include "sysemu/arch_init.h" |
56 | #include "sysemu/device_tree.h" | |
5133ed17 | 57 | #include "sysemu/runstate.h" |
46517dd4 | 58 | #include "sysemu/sysemu.h" |
a7240d1e | 59 | |
5aec3247 MC |
60 | #include <libfdt.h> |
61 | ||
b78c3296 | 62 | #if defined(TARGET_RISCV32) |
2cacd841 | 63 | # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" |
b78c3296 | 64 | #else |
2cacd841 | 65 | # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" |
b78c3296 | 66 | #endif |
fdd1bda4 | 67 | |
a7240d1e MC |
68 | static const struct MemmapEntry { |
69 | hwaddr base; | |
70 | hwaddr size; | |
71 | } sifive_u_memmap[] = { | |
72 | [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, | |
9eb8b14a | 73 | [SIFIVE_U_MROM] = { 0x1000, 0xf000 }, |
a7240d1e | 74 | [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, |
6eaf9cf5 | 75 | [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 }, |
a6902ef0 | 76 | [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 }, |
a7240d1e | 77 | [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, |
af14c840 | 78 | [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, |
4b55bc2b BM |
79 | [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, |
80 | [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, | |
8a88b9f5 | 81 | [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 }, |
5461c4fe | 82 | [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, |
7b6bb66f BM |
83 | [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, |
84 | [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, | |
3eaea6eb | 85 | [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 }, |
49093916 BM |
86 | [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 }, |
87 | [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, | |
a7240d1e MC |
88 | }; |
89 | ||
5461c4fe | 90 | #define OTP_SERIAL 1 |
5a7f76a3 AF |
91 | #define GEM_REVISION 0x10070109 |
92 | ||
9f79638e | 93 | static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, |
a7240d1e MC |
94 | uint64_t mem_size, const char *cmdline) |
95 | { | |
ecdfe393 | 96 | MachineState *ms = MACHINE(qdev_get_machine()); |
a7240d1e MC |
97 | void *fdt; |
98 | int cpu; | |
99 | uint32_t *cells; | |
100 | char *nodename; | |
806c64b7 | 101 | char ethclk_names[] = "pclk\0hclk"; |
5133ed17 | 102 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; |
7b6bb66f | 103 | uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; |
a7240d1e MC |
104 | |
105 | fdt = s->fdt = create_device_tree(&s->fdt_size); | |
106 | if (!fdt) { | |
107 | error_report("create_device_tree() failed"); | |
108 | exit(1); | |
109 | } | |
110 | ||
d372e748 BM |
111 | qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); |
112 | qemu_fdt_setprop_string(fdt, "/", "compatible", | |
113 | "sifive,hifive-unleashed-a00"); | |
a7240d1e MC |
114 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); |
115 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
116 | ||
117 | qemu_fdt_add_subnode(fdt, "/soc"); | |
118 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
2a1a6f6d | 119 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
a7240d1e MC |
120 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
121 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
122 | ||
e1724d09 BM |
123 | hfclk_phandle = phandle++; |
124 | nodename = g_strdup_printf("/hfclk"); | |
125 | qemu_fdt_add_subnode(fdt, nodename); | |
126 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); | |
127 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); | |
128 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
129 | SIFIVE_U_HFCLK_FREQ); | |
130 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
131 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
132 | g_free(nodename); | |
133 | ||
134 | rtcclk_phandle = phandle++; | |
135 | nodename = g_strdup_printf("/rtcclk"); | |
136 | qemu_fdt_add_subnode(fdt, nodename); | |
137 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); | |
138 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); | |
139 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
140 | SIFIVE_U_RTCCLK_FREQ); | |
141 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
142 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
143 | g_free(nodename); | |
144 | ||
a7240d1e MC |
145 | nodename = g_strdup_printf("/memory@%lx", |
146 | (long)memmap[SIFIVE_U_DRAM].base); | |
147 | qemu_fdt_add_subnode(fdt, nodename); | |
148 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
149 | memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, | |
150 | mem_size >> 32, mem_size); | |
151 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
152 | g_free(nodename); | |
153 | ||
154 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
2a8756ed MC |
155 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
156 | SIFIVE_CLINT_TIMEBASE_FREQ); | |
a7240d1e MC |
157 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
158 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
159 | ||
ecdfe393 | 160 | for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { |
382cb439 | 161 | int cpu_phandle = phandle++; |
a7240d1e MC |
162 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
163 | char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
ecdfe393 | 164 | char *isa; |
a7240d1e | 165 | qemu_fdt_add_subnode(fdt, nodename); |
ecdfe393 BM |
166 | /* cpu 0 is the management hart that does not have mmu */ |
167 | if (cpu != 0) { | |
e883e992 BM |
168 | #if defined(TARGET_RISCV32) |
169 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); | |
170 | #else | |
ecdfe393 | 171 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); |
e883e992 | 172 | #endif |
ecdfe393 BM |
173 | isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); |
174 | } else { | |
175 | isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); | |
176 | } | |
a7240d1e MC |
177 | qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); |
178 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | |
179 | qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | |
180 | qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | |
181 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | |
182 | qemu_fdt_add_subnode(fdt, intc); | |
382cb439 | 183 | qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); |
a7240d1e MC |
184 | qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); |
185 | qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | |
186 | qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | |
187 | g_free(isa); | |
188 | g_free(intc); | |
189 | g_free(nodename); | |
190 | } | |
191 | ||
ecdfe393 BM |
192 | cells = g_new0(uint32_t, ms->smp.cpus * 4); |
193 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
194 | nodename = |
195 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
196 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
197 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
198 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
199 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
200 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
201 | g_free(nodename); | |
202 | } | |
203 | nodename = g_strdup_printf("/soc/clint@%lx", | |
204 | (long)memmap[SIFIVE_U_CLINT].base); | |
205 | qemu_fdt_add_subnode(fdt, nodename); | |
206 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); | |
207 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
208 | 0x0, memmap[SIFIVE_U_CLINT].base, | |
209 | 0x0, memmap[SIFIVE_U_CLINT].size); | |
210 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 211 | cells, ms->smp.cpus * sizeof(uint32_t) * 4); |
a7240d1e MC |
212 | g_free(cells); |
213 | g_free(nodename); | |
214 | ||
ea85f27d BM |
215 | nodename = g_strdup_printf("/soc/otp@%lx", |
216 | (long)memmap[SIFIVE_U_OTP].base); | |
217 | qemu_fdt_add_subnode(fdt, nodename); | |
218 | qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); | |
219 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
220 | 0x0, memmap[SIFIVE_U_OTP].base, | |
221 | 0x0, memmap[SIFIVE_U_OTP].size); | |
222 | qemu_fdt_setprop_string(fdt, nodename, "compatible", | |
223 | "sifive,fu540-c000-otp"); | |
224 | g_free(nodename); | |
225 | ||
af14c840 BM |
226 | prci_phandle = phandle++; |
227 | nodename = g_strdup_printf("/soc/clock-controller@%lx", | |
228 | (long)memmap[SIFIVE_U_PRCI].base); | |
229 | qemu_fdt_add_subnode(fdt, nodename); | |
230 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); | |
231 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); | |
232 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
233 | hfclk_phandle, rtcclk_phandle); | |
234 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
235 | 0x0, memmap[SIFIVE_U_PRCI].base, | |
236 | 0x0, memmap[SIFIVE_U_PRCI].size); | |
237 | qemu_fdt_setprop_string(fdt, nodename, "compatible", | |
238 | "sifive,fu540-c000-prci"); | |
239 | g_free(nodename); | |
240 | ||
382cb439 | 241 | plic_phandle = phandle++; |
ecdfe393 BM |
242 | cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); |
243 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
244 | nodename = |
245 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
246 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
ecdfe393 BM |
247 | /* cpu 0 is the management hart that does not have S-mode */ |
248 | if (cpu == 0) { | |
249 | cells[0] = cpu_to_be32(intc_phandle); | |
250 | cells[1] = cpu_to_be32(IRQ_M_EXT); | |
251 | } else { | |
252 | cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); | |
253 | cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); | |
254 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
255 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); | |
256 | } | |
a7240d1e MC |
257 | g_free(nodename); |
258 | } | |
259 | nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | |
260 | (long)memmap[SIFIVE_U_PLIC].base); | |
261 | qemu_fdt_add_subnode(fdt, nodename); | |
262 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); | |
263 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); | |
264 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
265 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 266 | cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); |
a7240d1e MC |
267 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
268 | 0x0, memmap[SIFIVE_U_PLIC].base, | |
269 | 0x0, memmap[SIFIVE_U_PLIC].size); | |
98ceee7f | 270 | qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); |
04e7edd1 | 271 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); |
a7240d1e MC |
272 | plic_phandle = qemu_fdt_get_phandle(fdt, nodename); |
273 | g_free(cells); | |
274 | g_free(nodename); | |
275 | ||
5133ed17 | 276 | gpio_phandle = phandle++; |
8a88b9f5 BM |
277 | nodename = g_strdup_printf("/soc/gpio@%lx", |
278 | (long)memmap[SIFIVE_U_GPIO].base); | |
279 | qemu_fdt_add_subnode(fdt, nodename); | |
5133ed17 | 280 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); |
8a88b9f5 BM |
281 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
282 | prci_phandle, PRCI_CLK_TLCLK); | |
283 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); | |
284 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
285 | qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); | |
286 | qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); | |
287 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
288 | 0x0, memmap[SIFIVE_U_GPIO].base, | |
289 | 0x0, memmap[SIFIVE_U_GPIO].size); | |
290 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, | |
291 | SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, | |
292 | SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, | |
293 | SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, | |
294 | SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, | |
295 | SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); | |
296 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
297 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); | |
298 | g_free(nodename); | |
299 | ||
5133ed17 BM |
300 | nodename = g_strdup_printf("/gpio-restart"); |
301 | qemu_fdt_add_subnode(fdt, nodename); | |
302 | qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); | |
303 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); | |
304 | g_free(nodename); | |
305 | ||
6eaf9cf5 BM |
306 | nodename = g_strdup_printf("/soc/cache-controller@%lx", |
307 | (long)memmap[SIFIVE_U_L2CC].base); | |
308 | qemu_fdt_add_subnode(fdt, nodename); | |
309 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
310 | 0x0, memmap[SIFIVE_U_L2CC].base, | |
311 | 0x0, memmap[SIFIVE_U_L2CC].size); | |
312 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
313 | SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); | |
314 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
315 | qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); | |
316 | qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); | |
317 | qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); | |
318 | qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); | |
319 | qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); | |
320 | qemu_fdt_setprop_string(fdt, nodename, "compatible", | |
321 | "sifive,fu540-c000-ccache"); | |
322 | g_free(nodename); | |
323 | ||
7b6bb66f | 324 | phy_phandle = phandle++; |
5a7f76a3 AF |
325 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
326 | (long)memmap[SIFIVE_U_GEM].base); | |
327 | qemu_fdt_add_subnode(fdt, nodename); | |
7b6bb66f BM |
328 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
329 | "sifive,fu540-c000-gem"); | |
5a7f76a3 AF |
330 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
331 | 0x0, memmap[SIFIVE_U_GEM].base, | |
7b6bb66f BM |
332 | 0x0, memmap[SIFIVE_U_GEM].size, |
333 | 0x0, memmap[SIFIVE_U_GEM_MGMT].base, | |
334 | 0x0, memmap[SIFIVE_U_GEM_MGMT].size); | |
5a7f76a3 AF |
335 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); |
336 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); | |
7b6bb66f | 337 | qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); |
04e7edd1 BM |
338 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
339 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); | |
fe93582c | 340 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
806c64b7 | 341 | prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); |
04ece4f8 | 342 | qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, |
fe93582c | 343 | sizeof(ethclk_names)); |
7b6bb66f BM |
344 | qemu_fdt_setprop(fdt, nodename, "local-mac-address", |
345 | s->soc.gem.conf.macaddr.a, ETH_ALEN); | |
04e7edd1 BM |
346 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
347 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
c3a28b5d BM |
348 | |
349 | qemu_fdt_add_subnode(fdt, "/aliases"); | |
350 | qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); | |
351 | ||
5a7f76a3 AF |
352 | g_free(nodename); |
353 | ||
354 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", | |
355 | (long)memmap[SIFIVE_U_GEM].base); | |
356 | qemu_fdt_add_subnode(fdt, nodename); | |
7b6bb66f | 357 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); |
04e7edd1 | 358 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
5a7f76a3 AF |
359 | g_free(nodename); |
360 | ||
5f7134d3 | 361 | nodename = g_strdup_printf("/soc/serial@%lx", |
a7240d1e MC |
362 | (long)memmap[SIFIVE_U_UART0].base); |
363 | qemu_fdt_add_subnode(fdt, nodename); | |
364 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
365 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
366 | 0x0, memmap[SIFIVE_U_UART0].base, | |
367 | 0x0, memmap[SIFIVE_U_UART0].size); | |
806c64b7 BM |
368 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
369 | prci_phandle, PRCI_CLK_TLCLK); | |
04e7edd1 BM |
370 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
371 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); | |
a7240d1e MC |
372 | |
373 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
374 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | |
7c28f4da MC |
375 | if (cmdline) { |
376 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
377 | } | |
44e6dcd3 | 378 | |
44e6dcd3 GR |
379 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); |
380 | ||
a7240d1e MC |
381 | g_free(nodename); |
382 | } | |
383 | ||
5133ed17 BM |
384 | static void sifive_u_machine_reset(void *opaque, int n, int level) |
385 | { | |
386 | /* gpio pin active low triggers reset */ | |
387 | if (!level) { | |
388 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
389 | } | |
390 | } | |
391 | ||
523e3464 | 392 | static void sifive_u_machine_init(MachineState *machine) |
a7240d1e MC |
393 | { |
394 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
687caef1 | 395 | SiFiveUState *s = RISCV_U_MACHINE(machine); |
5aec3247 | 396 | MemoryRegion *system_memory = get_system_memory(); |
a7240d1e | 397 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); |
1b3a2308 | 398 | MemoryRegion *flash0 = g_new(MemoryRegion, 1); |
fc41ae23 | 399 | target_ulong start_addr = memmap[SIFIVE_U_DRAM].base; |
8590f536 | 400 | uint32_t start_addr_hi32 = 0x00000000; |
5aec3247 | 401 | int i; |
66b1205b | 402 | uint32_t fdt_load_addr; |
dc144fe1 | 403 | uint64_t kernel_entry; |
a7240d1e | 404 | |
2308092b | 405 | /* Initialize SoC */ |
9fc7fc4d | 406 | object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); |
5325cc34 MA |
407 | object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, |
408 | &error_abort); | |
ce189ab2 | 409 | qdev_realize(DEVICE(&s->soc), NULL, &error_abort); |
a7240d1e MC |
410 | |
411 | /* register RAM */ | |
412 | memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", | |
413 | machine->ram_size, &error_fatal); | |
5aec3247 | 414 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, |
2308092b | 415 | main_mem); |
a7240d1e | 416 | |
1b3a2308 AF |
417 | /* register QSPI0 Flash */ |
418 | memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", | |
419 | memmap[SIFIVE_U_FLASH0].size, &error_fatal); | |
420 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base, | |
421 | flash0); | |
422 | ||
5133ed17 BM |
423 | /* register gpio-restart */ |
424 | qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, | |
425 | qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); | |
426 | ||
a7240d1e | 427 | /* create device tree */ |
9f79638e | 428 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); |
a7240d1e | 429 | |
17aad9f2 BM |
430 | if (s->start_in_flash) { |
431 | /* | |
432 | * If start_in_flash property is given, assign s->msel to a value | |
433 | * that representing booting from QSPI0 memory-mapped flash. | |
434 | * | |
435 | * This also means that when both start_in_flash and msel properties | |
436 | * are given, start_in_flash takes the precedence over msel. | |
437 | * | |
438 | * Note this is to keep backward compatibility not to break existing | |
439 | * users that use start_in_flash property. | |
440 | */ | |
441 | s->msel = MSEL_MEMMAP_QSPI0_FLASH; | |
442 | } | |
443 | ||
444 | switch (s->msel) { | |
445 | case MSEL_MEMMAP_QSPI0_FLASH: | |
446 | start_addr = memmap[SIFIVE_U_FLASH0].base; | |
447 | break; | |
448 | case MSEL_L2LIM_QSPI0_FLASH: | |
449 | case MSEL_L2LIM_QSPI2_SD: | |
450 | start_addr = memmap[SIFIVE_U_L2LIM].base; | |
451 | break; | |
452 | default: | |
453 | start_addr = memmap[SIFIVE_U_DRAM].base; | |
454 | break; | |
455 | } | |
456 | ||
457 | riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL); | |
b3042223 | 458 | |
a7240d1e | 459 | if (machine->kernel_filename) { |
dc144fe1 | 460 | kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL); |
0f8d4462 GR |
461 | |
462 | if (machine->initrd_filename) { | |
463 | hwaddr start; | |
464 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | |
465 | machine->ram_size, kernel_entry, | |
466 | &start); | |
9f79638e | 467 | qemu_fdt_setprop_cell(s->fdt, "/chosen", |
0f8d4462 | 468 | "linux,initrd-start", start); |
9f79638e | 469 | qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", |
0f8d4462 GR |
470 | end); |
471 | } | |
dc144fe1 AP |
472 | } else { |
473 | /* | |
474 | * If dynamic firmware is used, it doesn't know where is the next mode | |
475 | * if kernel argument is not set. | |
476 | */ | |
477 | kernel_entry = 0; | |
a7240d1e MC |
478 | } |
479 | ||
66b1205b AP |
480 | /* Compute the fdt load address in dram */ |
481 | fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base, | |
482 | machine->ram_size, s->fdt); | |
8590f536 AP |
483 | #if defined(TARGET_RISCV64) |
484 | start_addr_hi32 = start_addr >> 32; | |
485 | #endif | |
66b1205b | 486 | |
a7240d1e | 487 | /* reset vector */ |
66b1205b | 488 | uint32_t reset_vec[11] = { |
17aad9f2 | 489 | s->msel, /* MSEL pin state */ |
dc144fe1 AP |
490 | 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ |
491 | 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ | |
a7240d1e MC |
492 | 0xf1402573, /* csrr a0, mhartid */ |
493 | #if defined(TARGET_RISCV32) | |
66b1205b | 494 | 0x0202a583, /* lw a1, 32(t0) */ |
a7240d1e MC |
495 | 0x0182a283, /* lw t0, 24(t0) */ |
496 | #elif defined(TARGET_RISCV64) | |
66b1205b AP |
497 | 0x0202b583, /* ld a1, 32(t0) */ |
498 | 0x0182b283, /* ld t0, 24(t0) */ | |
a7240d1e MC |
499 | #endif |
500 | 0x00028067, /* jr t0 */ | |
fc41ae23 | 501 | start_addr, /* start: .dword */ |
8590f536 | 502 | start_addr_hi32, |
66b1205b AP |
503 | fdt_load_addr, /* fdt_laddr: .dword */ |
504 | 0x00000000, | |
dc144fe1 | 505 | /* fw_dyn: */ |
a7240d1e MC |
506 | }; |
507 | ||
5aec3247 | 508 | /* copy in the reset vector in little_endian byte order */ |
66b1205b | 509 | for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { |
5aec3247 MC |
510 | reset_vec[i] = cpu_to_le32(reset_vec[i]); |
511 | } | |
512 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
513 | memmap[SIFIVE_U_MROM].base, &address_space_memory); | |
dc144fe1 AP |
514 | |
515 | riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base, | |
516 | memmap[SIFIVE_U_MROM].size, | |
517 | sizeof(reset_vec), kernel_entry); | |
2308092b AF |
518 | } |
519 | ||
523e3464 AF |
520 | static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) |
521 | { | |
522 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
523 | ||
524 | return s->start_in_flash; | |
525 | } | |
526 | ||
527 | static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) | |
528 | { | |
529 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
530 | ||
531 | s->start_in_flash = value; | |
532 | } | |
533 | ||
3e9667cd BM |
534 | static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, |
535 | const char *name, void *opaque, | |
536 | Error **errp) | |
3ca109c3 BM |
537 | { |
538 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
539 | } | |
540 | ||
3e9667cd BM |
541 | static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, |
542 | const char *name, void *opaque, | |
543 | Error **errp) | |
3ca109c3 BM |
544 | { |
545 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
546 | } | |
547 | ||
523e3464 AF |
548 | static void sifive_u_machine_instance_init(Object *obj) |
549 | { | |
550 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
551 | ||
552 | s->start_in_flash = false; | |
d2623129 MA |
553 | object_property_add_bool(obj, "start-in-flash", |
554 | sifive_u_machine_get_start_in_flash, | |
555 | sifive_u_machine_set_start_in_flash); | |
523e3464 AF |
556 | object_property_set_description(obj, "start-in-flash", |
557 | "Set on to tell QEMU's ROM to jump to " | |
17aad9f2 BM |
558 | "flash. Otherwise QEMU will jump to DRAM " |
559 | "or L2LIM depending on the msel value"); | |
3ca109c3 | 560 | |
cfa32630 BM |
561 | s->msel = 0; |
562 | object_property_add(obj, "msel", "uint32", | |
563 | sifive_u_machine_get_uint32_prop, | |
564 | sifive_u_machine_set_uint32_prop, NULL, &s->msel); | |
565 | object_property_set_description(obj, "msel", | |
566 | "Mode Select (MSEL[3:0]) pin state"); | |
567 | ||
3ca109c3 | 568 | s->serial = OTP_SERIAL; |
d2623129 | 569 | object_property_add(obj, "serial", "uint32", |
3e9667cd BM |
570 | sifive_u_machine_get_uint32_prop, |
571 | sifive_u_machine_set_uint32_prop, NULL, &s->serial); | |
7eecec7d | 572 | object_property_set_description(obj, "serial", "Board serial number"); |
523e3464 AF |
573 | } |
574 | ||
575 | static void sifive_u_machine_class_init(ObjectClass *oc, void *data) | |
576 | { | |
577 | MachineClass *mc = MACHINE_CLASS(oc); | |
578 | ||
579 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; | |
580 | mc->init = sifive_u_machine_init; | |
581 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; | |
582 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; | |
583 | mc->default_cpus = mc->min_cpus; | |
584 | } | |
585 | ||
586 | static const TypeInfo sifive_u_machine_typeinfo = { | |
587 | .name = MACHINE_TYPE_NAME("sifive_u"), | |
588 | .parent = TYPE_MACHINE, | |
589 | .class_init = sifive_u_machine_class_init, | |
590 | .instance_init = sifive_u_machine_instance_init, | |
591 | .instance_size = sizeof(SiFiveUState), | |
592 | }; | |
593 | ||
594 | static void sifive_u_machine_init_register_types(void) | |
595 | { | |
596 | type_register_static(&sifive_u_machine_typeinfo); | |
597 | } | |
598 | ||
599 | type_init(sifive_u_machine_init_register_types) | |
600 | ||
139177b1 | 601 | static void sifive_u_soc_instance_init(Object *obj) |
2308092b | 602 | { |
c4473127 | 603 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
604 | SiFiveUSoCState *s = RISCV_U_SOC(obj); |
605 | ||
9fc7fc4d | 606 | object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
607 | qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); |
608 | ||
db873cc5 MA |
609 | object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, |
610 | TYPE_RISCV_HART_ARRAY); | |
ecdfe393 BM |
611 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); |
612 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); | |
613 | qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); | |
73f6ed97 | 614 | qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); |
ecdfe393 | 615 | |
9fc7fc4d | 616 | object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
617 | qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); |
618 | ||
db873cc5 MA |
619 | object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, |
620 | TYPE_RISCV_HART_ARRAY); | |
ecdfe393 BM |
621 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); |
622 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); | |
623 | qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); | |
73f6ed97 | 624 | qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); |
5a7f76a3 | 625 | |
db873cc5 MA |
626 | object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); |
627 | object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); | |
628 | object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); | |
8a88b9f5 | 629 | object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); |
2308092b AF |
630 | } |
631 | ||
139177b1 | 632 | static void sifive_u_soc_realize(DeviceState *dev, Error **errp) |
2308092b | 633 | { |
c4473127 | 634 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
635 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
636 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
637 | MemoryRegion *system_memory = get_system_memory(); | |
638 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
a6902ef0 | 639 | MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); |
05446f41 BM |
640 | char *plic_hart_config; |
641 | size_t plic_hart_config_len; | |
5a7f76a3 | 642 | int i; |
5a7f76a3 | 643 | NICInfo *nd = &nd_table[0]; |
2308092b | 644 | |
db873cc5 MA |
645 | sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); |
646 | sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); | |
ecdfe393 BM |
647 | /* |
648 | * The cluster must be realized after the RISC-V hart array container, | |
649 | * as the container's CPU object is only created on realize, and the | |
650 | * CPU must exist and have been parented into the cluster before the | |
651 | * cluster is realized. | |
652 | */ | |
ce189ab2 MA |
653 | qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); |
654 | qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); | |
2308092b AF |
655 | |
656 | /* boot rom */ | |
414c47d2 | 657 | memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", |
2308092b AF |
658 | memmap[SIFIVE_U_MROM].size, &error_fatal); |
659 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, | |
660 | mask_rom); | |
a7240d1e | 661 | |
a6902ef0 AF |
662 | /* |
663 | * Add L2-LIM at reset size. | |
664 | * This should be reduced in size as the L2 Cache Controller WayEnable | |
665 | * register is incremented. Unfortunately I don't see a nice (or any) way | |
666 | * to handle reducing or blocking out the L2 LIM while still allowing it | |
667 | * be re returned to all enabled after a reset. For the time being, just | |
668 | * leave it enabled all the time. This won't break anything, but will be | |
669 | * too generous to misbehaving guests. | |
670 | */ | |
671 | memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", | |
672 | memmap[SIFIVE_U_L2LIM].size, &error_fatal); | |
673 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, | |
674 | l2lim_mem); | |
675 | ||
05446f41 | 676 | /* create PLIC hart topology configuration string */ |
c4473127 LX |
677 | plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * |
678 | ms->smp.cpus; | |
05446f41 | 679 | plic_hart_config = g_malloc0(plic_hart_config_len); |
c4473127 | 680 | for (i = 0; i < ms->smp.cpus; i++) { |
05446f41 | 681 | if (i != 0) { |
ef965ce2 BM |
682 | strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, |
683 | plic_hart_config_len); | |
684 | } else { | |
685 | strncat(plic_hart_config, "M", plic_hart_config_len); | |
05446f41 | 686 | } |
05446f41 BM |
687 | plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); |
688 | } | |
689 | ||
a7240d1e MC |
690 | /* MMIO */ |
691 | s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, | |
c9270e10 | 692 | plic_hart_config, 0, |
a7240d1e MC |
693 | SIFIVE_U_PLIC_NUM_SOURCES, |
694 | SIFIVE_U_PLIC_NUM_PRIORITIES, | |
695 | SIFIVE_U_PLIC_PRIORITY_BASE, | |
696 | SIFIVE_U_PLIC_PENDING_BASE, | |
697 | SIFIVE_U_PLIC_ENABLE_BASE, | |
698 | SIFIVE_U_PLIC_ENABLE_STRIDE, | |
699 | SIFIVE_U_PLIC_CONTEXT_BASE, | |
700 | SIFIVE_U_PLIC_CONTEXT_STRIDE, | |
701 | memmap[SIFIVE_U_PLIC].size); | |
bb8136df | 702 | g_free(plic_hart_config); |
5aec3247 | 703 | sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, |
647a70a1 | 704 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
194eef09 MC |
705 | sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, |
706 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); | |
a7240d1e | 707 | sifive_clint_create(memmap[SIFIVE_U_CLINT].base, |
3bf03f08 | 708 | memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus, |
a47ef6e9 BM |
709 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, |
710 | SIFIVE_CLINT_TIMEBASE_FREQ, false); | |
5a7f76a3 | 711 | |
cbe3a8c5 MA |
712 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { |
713 | return; | |
714 | } | |
af14c840 BM |
715 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); |
716 | ||
8a88b9f5 | 717 | qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); |
cbe3a8c5 MA |
718 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
719 | return; | |
720 | } | |
8a88b9f5 BM |
721 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base); |
722 | ||
723 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
724 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); | |
725 | ||
726 | /* Connect GPIO interrupts to the PLIC */ | |
727 | for (i = 0; i < 16; i++) { | |
728 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, | |
729 | qdev_get_gpio_in(DEVICE(s->plic), | |
730 | SIFIVE_U_GPIO_IRQ0 + i)); | |
731 | } | |
732 | ||
fda5b000 | 733 | qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); |
cbe3a8c5 MA |
734 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { |
735 | return; | |
736 | } | |
5461c4fe BM |
737 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); |
738 | ||
7ad36e2e | 739 | /* FIXME use qdev NIC properties instead of nd_table[] */ |
5a7f76a3 AF |
740 | if (nd->used) { |
741 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
742 | qdev_set_nic_properties(DEVICE(&s->gem), nd); | |
743 | } | |
5325cc34 | 744 | object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, |
5a7f76a3 | 745 | &error_abort); |
668f62ec | 746 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { |
5a7f76a3 AF |
747 | return; |
748 | } | |
749 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); | |
750 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, | |
5874f0a7 | 751 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); |
7b6bb66f BM |
752 | |
753 | create_unimplemented_device("riscv.sifive.u.gem-mgmt", | |
754 | memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); | |
3eaea6eb BM |
755 | |
756 | create_unimplemented_device("riscv.sifive.u.dmc", | |
757 | memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size); | |
6eaf9cf5 BM |
758 | |
759 | create_unimplemented_device("riscv.sifive.u.l2cc", | |
760 | memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size); | |
a7240d1e MC |
761 | } |
762 | ||
139177b1 | 763 | static Property sifive_u_soc_props[] = { |
fda5b000 AF |
764 | DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), |
765 | DEFINE_PROP_END_OF_LIST() | |
766 | }; | |
767 | ||
139177b1 | 768 | static void sifive_u_soc_class_init(ObjectClass *oc, void *data) |
2308092b AF |
769 | { |
770 | DeviceClass *dc = DEVICE_CLASS(oc); | |
771 | ||
139177b1 BM |
772 | device_class_set_props(dc, sifive_u_soc_props); |
773 | dc->realize = sifive_u_soc_realize; | |
2308092b AF |
774 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
775 | dc->user_creatable = false; | |
776 | } | |
777 | ||
139177b1 | 778 | static const TypeInfo sifive_u_soc_type_info = { |
2308092b AF |
779 | .name = TYPE_RISCV_U_SOC, |
780 | .parent = TYPE_DEVICE, | |
781 | .instance_size = sizeof(SiFiveUSoCState), | |
139177b1 BM |
782 | .instance_init = sifive_u_soc_instance_init, |
783 | .class_init = sifive_u_soc_class_init, | |
2308092b AF |
784 | }; |
785 | ||
139177b1 | 786 | static void sifive_u_soc_register_types(void) |
2308092b | 787 | { |
139177b1 | 788 | type_register_static(&sifive_u_soc_type_info); |
2308092b AF |
789 | } |
790 | ||
139177b1 | 791 | type_init(sifive_u_soc_register_types) |