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a7240d1e MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017 SiFive, Inc. | |
7b6bb66f | 6 | * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> |
a7240d1e MC |
7 | * |
8 | * Provides a board compatible with the SiFive Freedom U SDK: | |
9 | * | |
10 | * 0) UART | |
11 | * 1) CLINT (Core Level Interruptor) | |
12 | * 2) PLIC (Platform Level Interrupt Controller) | |
af14c840 | 13 | * 3) PRCI (Power, Reset, Clock, Interrupt) |
8a88b9f5 BM |
14 | * 4) GPIO (General Purpose Input/Output Controller) |
15 | * 5) OTP (One-Time Programmable) memory with stored serial number | |
16 | * 6) GEM (Gigabit Ethernet Controller) and management block | |
834e027a | 17 | * 7) DMA (Direct Memory Access Controller) |
a7240d1e | 18 | * |
f3d47d58 | 19 | * This board currently generates devicetree dynamically that indicates at least |
ecdfe393 | 20 | * two harts and up to five harts. |
a7240d1e MC |
21 | * |
22 | * This program is free software; you can redistribute it and/or modify it | |
23 | * under the terms and conditions of the GNU General Public License, | |
24 | * version 2 or later, as published by the Free Software Foundation. | |
25 | * | |
26 | * This program is distributed in the hope it will be useful, but WITHOUT | |
27 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
28 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
29 | * more details. | |
30 | * | |
31 | * You should have received a copy of the GNU General Public License along with | |
32 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
33 | */ | |
34 | ||
35 | #include "qemu/osdep.h" | |
36 | #include "qemu/log.h" | |
37 | #include "qemu/error-report.h" | |
38 | #include "qapi/error.h" | |
3ca109c3 | 39 | #include "qapi/visitor.h" |
a7240d1e | 40 | #include "hw/boards.h" |
5133ed17 | 41 | #include "hw/irq.h" |
a7240d1e MC |
42 | #include "hw/loader.h" |
43 | #include "hw/sysbus.h" | |
44 | #include "hw/char/serial.h" | |
ecdfe393 | 45 | #include "hw/cpu/cluster.h" |
7b6bb66f | 46 | #include "hw/misc/unimp.h" |
a7240d1e MC |
47 | #include "target/riscv/cpu.h" |
48 | #include "hw/riscv/riscv_hart.h" | |
a7240d1e | 49 | #include "hw/riscv/sifive_u.h" |
0ac24d56 | 50 | #include "hw/riscv/boot.h" |
b609b7e3 | 51 | #include "hw/char/sifive_uart.h" |
406fafd5 | 52 | #include "hw/intc/sifive_clint.h" |
84fcf3c1 | 53 | #include "hw/intc/sifive_plic.h" |
a7240d1e | 54 | #include "chardev/char.h" |
7b6bb66f | 55 | #include "net/eth.h" |
a7240d1e MC |
56 | #include "sysemu/arch_init.h" |
57 | #include "sysemu/device_tree.h" | |
5133ed17 | 58 | #include "sysemu/runstate.h" |
46517dd4 | 59 | #include "sysemu/sysemu.h" |
a7240d1e | 60 | |
5aec3247 MC |
61 | #include <libfdt.h> |
62 | ||
b78c3296 | 63 | #if defined(TARGET_RISCV32) |
2cacd841 | 64 | # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" |
b78c3296 | 65 | #else |
2cacd841 | 66 | # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" |
b78c3296 | 67 | #endif |
fdd1bda4 | 68 | |
a7240d1e MC |
69 | static const struct MemmapEntry { |
70 | hwaddr base; | |
71 | hwaddr size; | |
72 | } sifive_u_memmap[] = { | |
13b8c354 EH |
73 | [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, |
74 | [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, | |
75 | [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, | |
76 | [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, | |
77 | [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, | |
78 | [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, | |
79 | [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, | |
80 | [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, | |
81 | [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, | |
82 | [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, | |
83 | [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, | |
84 | [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, | |
85 | [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, | |
86 | [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, | |
87 | [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, | |
88 | [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, | |
89 | [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, | |
a7240d1e MC |
90 | }; |
91 | ||
5461c4fe | 92 | #define OTP_SERIAL 1 |
5a7f76a3 AF |
93 | #define GEM_REVISION 0x10070109 |
94 | ||
9f79638e | 95 | static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, |
a7240d1e MC |
96 | uint64_t mem_size, const char *cmdline) |
97 | { | |
ecdfe393 | 98 | MachineState *ms = MACHINE(qdev_get_machine()); |
a7240d1e MC |
99 | void *fdt; |
100 | int cpu; | |
101 | uint32_t *cells; | |
102 | char *nodename; | |
806c64b7 | 103 | char ethclk_names[] = "pclk\0hclk"; |
5133ed17 | 104 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; |
7b6bb66f | 105 | uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; |
a7240d1e | 106 | |
f2ce39b4 PB |
107 | if (ms->dtb) { |
108 | fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); | |
d5c90cf3 AP |
109 | if (!fdt) { |
110 | error_report("load_device_tree() failed"); | |
111 | exit(1); | |
112 | } | |
113 | goto update_bootargs; | |
114 | } else { | |
115 | fdt = s->fdt = create_device_tree(&s->fdt_size); | |
116 | if (!fdt) { | |
117 | error_report("create_device_tree() failed"); | |
118 | exit(1); | |
119 | } | |
a7240d1e MC |
120 | } |
121 | ||
d372e748 BM |
122 | qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); |
123 | qemu_fdt_setprop_string(fdt, "/", "compatible", | |
124 | "sifive,hifive-unleashed-a00"); | |
a7240d1e MC |
125 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); |
126 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
127 | ||
128 | qemu_fdt_add_subnode(fdt, "/soc"); | |
129 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
2a1a6f6d | 130 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
a7240d1e MC |
131 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
132 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
133 | ||
e1724d09 BM |
134 | hfclk_phandle = phandle++; |
135 | nodename = g_strdup_printf("/hfclk"); | |
136 | qemu_fdt_add_subnode(fdt, nodename); | |
137 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); | |
138 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); | |
139 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
140 | SIFIVE_U_HFCLK_FREQ); | |
141 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
142 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
143 | g_free(nodename); | |
144 | ||
145 | rtcclk_phandle = phandle++; | |
146 | nodename = g_strdup_printf("/rtcclk"); | |
147 | qemu_fdt_add_subnode(fdt, nodename); | |
148 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); | |
149 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); | |
150 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
151 | SIFIVE_U_RTCCLK_FREQ); | |
152 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
153 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
154 | g_free(nodename); | |
155 | ||
a7240d1e | 156 | nodename = g_strdup_printf("/memory@%lx", |
13b8c354 | 157 | (long)memmap[SIFIVE_U_DEV_DRAM].base); |
a7240d1e MC |
158 | qemu_fdt_add_subnode(fdt, nodename); |
159 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 | 160 | memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, |
a7240d1e MC |
161 | mem_size >> 32, mem_size); |
162 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
163 | g_free(nodename); | |
164 | ||
165 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
2a8756ed MC |
166 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
167 | SIFIVE_CLINT_TIMEBASE_FREQ); | |
a7240d1e MC |
168 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
169 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
170 | ||
ecdfe393 | 171 | for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { |
382cb439 | 172 | int cpu_phandle = phandle++; |
a7240d1e MC |
173 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
174 | char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
ecdfe393 | 175 | char *isa; |
a7240d1e | 176 | qemu_fdt_add_subnode(fdt, nodename); |
ecdfe393 BM |
177 | /* cpu 0 is the management hart that does not have mmu */ |
178 | if (cpu != 0) { | |
e883e992 BM |
179 | #if defined(TARGET_RISCV32) |
180 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); | |
181 | #else | |
ecdfe393 | 182 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); |
e883e992 | 183 | #endif |
ecdfe393 BM |
184 | isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); |
185 | } else { | |
186 | isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); | |
187 | } | |
a7240d1e MC |
188 | qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); |
189 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | |
190 | qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | |
191 | qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | |
192 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | |
193 | qemu_fdt_add_subnode(fdt, intc); | |
382cb439 | 194 | qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); |
a7240d1e MC |
195 | qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); |
196 | qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | |
197 | qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | |
198 | g_free(isa); | |
199 | g_free(intc); | |
200 | g_free(nodename); | |
201 | } | |
202 | ||
ecdfe393 BM |
203 | cells = g_new0(uint32_t, ms->smp.cpus * 4); |
204 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
205 | nodename = |
206 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
207 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
208 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
209 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
210 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
211 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
212 | g_free(nodename); | |
213 | } | |
214 | nodename = g_strdup_printf("/soc/clint@%lx", | |
13b8c354 | 215 | (long)memmap[SIFIVE_U_DEV_CLINT].base); |
a7240d1e MC |
216 | qemu_fdt_add_subnode(fdt, nodename); |
217 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); | |
218 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
219 | 0x0, memmap[SIFIVE_U_DEV_CLINT].base, |
220 | 0x0, memmap[SIFIVE_U_DEV_CLINT].size); | |
a7240d1e | 221 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", |
ecdfe393 | 222 | cells, ms->smp.cpus * sizeof(uint32_t) * 4); |
a7240d1e MC |
223 | g_free(cells); |
224 | g_free(nodename); | |
225 | ||
ea85f27d | 226 | nodename = g_strdup_printf("/soc/otp@%lx", |
13b8c354 | 227 | (long)memmap[SIFIVE_U_DEV_OTP].base); |
ea85f27d BM |
228 | qemu_fdt_add_subnode(fdt, nodename); |
229 | qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); | |
230 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
231 | 0x0, memmap[SIFIVE_U_DEV_OTP].base, |
232 | 0x0, memmap[SIFIVE_U_DEV_OTP].size); | |
ea85f27d BM |
233 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
234 | "sifive,fu540-c000-otp"); | |
235 | g_free(nodename); | |
236 | ||
af14c840 BM |
237 | prci_phandle = phandle++; |
238 | nodename = g_strdup_printf("/soc/clock-controller@%lx", | |
13b8c354 | 239 | (long)memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 BM |
240 | qemu_fdt_add_subnode(fdt, nodename); |
241 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); | |
242 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); | |
243 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
244 | hfclk_phandle, rtcclk_phandle); | |
245 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
246 | 0x0, memmap[SIFIVE_U_DEV_PRCI].base, |
247 | 0x0, memmap[SIFIVE_U_DEV_PRCI].size); | |
af14c840 BM |
248 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
249 | "sifive,fu540-c000-prci"); | |
250 | g_free(nodename); | |
251 | ||
382cb439 | 252 | plic_phandle = phandle++; |
ecdfe393 BM |
253 | cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); |
254 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
255 | nodename = |
256 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
257 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
ecdfe393 BM |
258 | /* cpu 0 is the management hart that does not have S-mode */ |
259 | if (cpu == 0) { | |
260 | cells[0] = cpu_to_be32(intc_phandle); | |
261 | cells[1] = cpu_to_be32(IRQ_M_EXT); | |
262 | } else { | |
263 | cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); | |
264 | cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); | |
265 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
266 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); | |
267 | } | |
a7240d1e MC |
268 | g_free(nodename); |
269 | } | |
270 | nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | |
13b8c354 | 271 | (long)memmap[SIFIVE_U_DEV_PLIC].base); |
a7240d1e MC |
272 | qemu_fdt_add_subnode(fdt, nodename); |
273 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); | |
274 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); | |
275 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
276 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 277 | cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); |
a7240d1e | 278 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
279 | 0x0, memmap[SIFIVE_U_DEV_PLIC].base, |
280 | 0x0, memmap[SIFIVE_U_DEV_PLIC].size); | |
98ceee7f | 281 | qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); |
04e7edd1 | 282 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); |
a7240d1e MC |
283 | plic_phandle = qemu_fdt_get_phandle(fdt, nodename); |
284 | g_free(cells); | |
285 | g_free(nodename); | |
286 | ||
5133ed17 | 287 | gpio_phandle = phandle++; |
8a88b9f5 | 288 | nodename = g_strdup_printf("/soc/gpio@%lx", |
13b8c354 | 289 | (long)memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 | 290 | qemu_fdt_add_subnode(fdt, nodename); |
5133ed17 | 291 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); |
8a88b9f5 BM |
292 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
293 | prci_phandle, PRCI_CLK_TLCLK); | |
294 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); | |
295 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
296 | qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); | |
297 | qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); | |
298 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
299 | 0x0, memmap[SIFIVE_U_DEV_GPIO].base, |
300 | 0x0, memmap[SIFIVE_U_DEV_GPIO].size); | |
8a88b9f5 BM |
301 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, |
302 | SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, | |
303 | SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, | |
304 | SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, | |
305 | SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, | |
306 | SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); | |
307 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
308 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); | |
309 | g_free(nodename); | |
310 | ||
5133ed17 BM |
311 | nodename = g_strdup_printf("/gpio-restart"); |
312 | qemu_fdt_add_subnode(fdt, nodename); | |
313 | qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); | |
314 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); | |
315 | g_free(nodename); | |
316 | ||
834e027a | 317 | nodename = g_strdup_printf("/soc/dma@%lx", |
13b8c354 | 318 | (long)memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
319 | qemu_fdt_add_subnode(fdt, nodename); |
320 | qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); | |
321 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
322 | SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, | |
323 | SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, | |
324 | SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); | |
325 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
326 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
327 | 0x0, memmap[SIFIVE_U_DEV_PDMA].base, |
328 | 0x0, memmap[SIFIVE_U_DEV_PDMA].size); | |
834e027a BM |
329 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
330 | "sifive,fu540-c000-pdma"); | |
331 | g_free(nodename); | |
332 | ||
6eaf9cf5 | 333 | nodename = g_strdup_printf("/soc/cache-controller@%lx", |
13b8c354 | 334 | (long)memmap[SIFIVE_U_DEV_L2CC].base); |
6eaf9cf5 BM |
335 | qemu_fdt_add_subnode(fdt, nodename); |
336 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
337 | 0x0, memmap[SIFIVE_U_DEV_L2CC].base, |
338 | 0x0, memmap[SIFIVE_U_DEV_L2CC].size); | |
6eaf9cf5 BM |
339 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", |
340 | SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); | |
341 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
342 | qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); | |
343 | qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); | |
344 | qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); | |
345 | qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); | |
346 | qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); | |
347 | qemu_fdt_setprop_string(fdt, nodename, "compatible", | |
348 | "sifive,fu540-c000-ccache"); | |
349 | g_free(nodename); | |
350 | ||
7b6bb66f | 351 | phy_phandle = phandle++; |
5a7f76a3 | 352 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
13b8c354 | 353 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 354 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f BM |
355 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
356 | "sifive,fu540-c000-gem"); | |
5a7f76a3 | 357 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
358 | 0x0, memmap[SIFIVE_U_DEV_GEM].base, |
359 | 0x0, memmap[SIFIVE_U_DEV_GEM].size, | |
360 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, | |
361 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); | |
5a7f76a3 AF |
362 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); |
363 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); | |
7b6bb66f | 364 | qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); |
04e7edd1 BM |
365 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
366 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); | |
fe93582c | 367 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
806c64b7 | 368 | prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); |
04ece4f8 | 369 | qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, |
fe93582c | 370 | sizeof(ethclk_names)); |
7b6bb66f BM |
371 | qemu_fdt_setprop(fdt, nodename, "local-mac-address", |
372 | s->soc.gem.conf.macaddr.a, ETH_ALEN); | |
04e7edd1 BM |
373 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
374 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
c3a28b5d BM |
375 | |
376 | qemu_fdt_add_subnode(fdt, "/aliases"); | |
377 | qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); | |
378 | ||
5a7f76a3 AF |
379 | g_free(nodename); |
380 | ||
381 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", | |
13b8c354 | 382 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 383 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f | 384 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); |
04e7edd1 | 385 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
5a7f76a3 AF |
386 | g_free(nodename); |
387 | ||
10b43754 AP |
388 | nodename = g_strdup_printf("/soc/serial@%lx", |
389 | (long)memmap[SIFIVE_U_DEV_UART1].base); | |
390 | qemu_fdt_add_subnode(fdt, nodename); | |
391 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
392 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
393 | 0x0, memmap[SIFIVE_U_DEV_UART1].base, | |
394 | 0x0, memmap[SIFIVE_U_DEV_UART1].size); | |
395 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
396 | prci_phandle, PRCI_CLK_TLCLK); | |
397 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
398 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); | |
399 | ||
400 | qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); | |
401 | g_free(nodename); | |
402 | ||
5f7134d3 | 403 | nodename = g_strdup_printf("/soc/serial@%lx", |
13b8c354 | 404 | (long)memmap[SIFIVE_U_DEV_UART0].base); |
a7240d1e MC |
405 | qemu_fdt_add_subnode(fdt, nodename); |
406 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
407 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
408 | 0x0, memmap[SIFIVE_U_DEV_UART0].base, |
409 | 0x0, memmap[SIFIVE_U_DEV_UART0].size); | |
806c64b7 BM |
410 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
411 | prci_phandle, PRCI_CLK_TLCLK); | |
04e7edd1 BM |
412 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
413 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); | |
a7240d1e MC |
414 | |
415 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
416 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | |
44e6dcd3 GR |
417 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); |
418 | ||
a7240d1e | 419 | g_free(nodename); |
d5c90cf3 AP |
420 | |
421 | update_bootargs: | |
422 | if (cmdline) { | |
423 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
424 | } | |
a7240d1e MC |
425 | } |
426 | ||
5133ed17 BM |
427 | static void sifive_u_machine_reset(void *opaque, int n, int level) |
428 | { | |
429 | /* gpio pin active low triggers reset */ | |
430 | if (!level) { | |
431 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
432 | } | |
433 | } | |
434 | ||
523e3464 | 435 | static void sifive_u_machine_init(MachineState *machine) |
a7240d1e MC |
436 | { |
437 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
687caef1 | 438 | SiFiveUState *s = RISCV_U_MACHINE(machine); |
5aec3247 | 439 | MemoryRegion *system_memory = get_system_memory(); |
a7240d1e | 440 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); |
1b3a2308 | 441 | MemoryRegion *flash0 = g_new(MemoryRegion, 1); |
13b8c354 | 442 | target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
38bc4e34 | 443 | target_ulong firmware_end_addr, kernel_start_addr; |
8590f536 | 444 | uint32_t start_addr_hi32 = 0x00000000; |
5aec3247 | 445 | int i; |
66b1205b | 446 | uint32_t fdt_load_addr; |
dc144fe1 | 447 | uint64_t kernel_entry; |
a7240d1e | 448 | |
2308092b | 449 | /* Initialize SoC */ |
9fc7fc4d | 450 | object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); |
5325cc34 MA |
451 | object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, |
452 | &error_abort); | |
099be035 AF |
453 | object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, |
454 | &error_abort); | |
ce189ab2 | 455 | qdev_realize(DEVICE(&s->soc), NULL, &error_abort); |
a7240d1e MC |
456 | |
457 | /* register RAM */ | |
458 | memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", | |
459 | machine->ram_size, &error_fatal); | |
13b8c354 | 460 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, |
2308092b | 461 | main_mem); |
a7240d1e | 462 | |
1b3a2308 AF |
463 | /* register QSPI0 Flash */ |
464 | memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", | |
13b8c354 EH |
465 | memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); |
466 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, | |
1b3a2308 AF |
467 | flash0); |
468 | ||
5133ed17 BM |
469 | /* register gpio-restart */ |
470 | qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, | |
471 | qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); | |
472 | ||
a7240d1e | 473 | /* create device tree */ |
9f79638e | 474 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); |
a7240d1e | 475 | |
17aad9f2 BM |
476 | if (s->start_in_flash) { |
477 | /* | |
478 | * If start_in_flash property is given, assign s->msel to a value | |
479 | * that representing booting from QSPI0 memory-mapped flash. | |
480 | * | |
481 | * This also means that when both start_in_flash and msel properties | |
482 | * are given, start_in_flash takes the precedence over msel. | |
483 | * | |
484 | * Note this is to keep backward compatibility not to break existing | |
485 | * users that use start_in_flash property. | |
486 | */ | |
487 | s->msel = MSEL_MEMMAP_QSPI0_FLASH; | |
488 | } | |
489 | ||
490 | switch (s->msel) { | |
491 | case MSEL_MEMMAP_QSPI0_FLASH: | |
13b8c354 | 492 | start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; |
17aad9f2 BM |
493 | break; |
494 | case MSEL_L2LIM_QSPI0_FLASH: | |
495 | case MSEL_L2LIM_QSPI2_SD: | |
13b8c354 | 496 | start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; |
17aad9f2 BM |
497 | break; |
498 | default: | |
13b8c354 | 499 | start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
17aad9f2 BM |
500 | break; |
501 | } | |
502 | ||
38bc4e34 AF |
503 | firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, |
504 | start_addr, NULL); | |
b3042223 | 505 | |
a7240d1e | 506 | if (machine->kernel_filename) { |
38bc4e34 AF |
507 | kernel_start_addr = riscv_calc_kernel_start_addr(machine, |
508 | firmware_end_addr); | |
509 | ||
510 | kernel_entry = riscv_load_kernel(machine->kernel_filename, | |
511 | kernel_start_addr, NULL); | |
0f8d4462 GR |
512 | |
513 | if (machine->initrd_filename) { | |
514 | hwaddr start; | |
515 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | |
516 | machine->ram_size, kernel_entry, | |
517 | &start); | |
9f79638e | 518 | qemu_fdt_setprop_cell(s->fdt, "/chosen", |
0f8d4462 | 519 | "linux,initrd-start", start); |
9f79638e | 520 | qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", |
0f8d4462 GR |
521 | end); |
522 | } | |
dc144fe1 AP |
523 | } else { |
524 | /* | |
525 | * If dynamic firmware is used, it doesn't know where is the next mode | |
526 | * if kernel argument is not set. | |
527 | */ | |
528 | kernel_entry = 0; | |
a7240d1e MC |
529 | } |
530 | ||
66b1205b | 531 | /* Compute the fdt load address in dram */ |
13b8c354 | 532 | fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, |
66b1205b | 533 | machine->ram_size, s->fdt); |
8590f536 AP |
534 | #if defined(TARGET_RISCV64) |
535 | start_addr_hi32 = start_addr >> 32; | |
536 | #endif | |
66b1205b | 537 | |
a7240d1e | 538 | /* reset vector */ |
66b1205b | 539 | uint32_t reset_vec[11] = { |
17aad9f2 | 540 | s->msel, /* MSEL pin state */ |
dc144fe1 AP |
541 | 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ |
542 | 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ | |
a7240d1e MC |
543 | 0xf1402573, /* csrr a0, mhartid */ |
544 | #if defined(TARGET_RISCV32) | |
66b1205b | 545 | 0x0202a583, /* lw a1, 32(t0) */ |
a7240d1e MC |
546 | 0x0182a283, /* lw t0, 24(t0) */ |
547 | #elif defined(TARGET_RISCV64) | |
66b1205b AP |
548 | 0x0202b583, /* ld a1, 32(t0) */ |
549 | 0x0182b283, /* ld t0, 24(t0) */ | |
a7240d1e MC |
550 | #endif |
551 | 0x00028067, /* jr t0 */ | |
fc41ae23 | 552 | start_addr, /* start: .dword */ |
8590f536 | 553 | start_addr_hi32, |
66b1205b AP |
554 | fdt_load_addr, /* fdt_laddr: .dword */ |
555 | 0x00000000, | |
dc144fe1 | 556 | /* fw_dyn: */ |
a7240d1e MC |
557 | }; |
558 | ||
5aec3247 | 559 | /* copy in the reset vector in little_endian byte order */ |
66b1205b | 560 | for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { |
5aec3247 MC |
561 | reset_vec[i] = cpu_to_le32(reset_vec[i]); |
562 | } | |
563 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
13b8c354 | 564 | memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); |
dc144fe1 | 565 | |
78936771 | 566 | riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, |
13b8c354 | 567 | memmap[SIFIVE_U_DEV_MROM].size, |
dc144fe1 | 568 | sizeof(reset_vec), kernel_entry); |
2308092b AF |
569 | } |
570 | ||
523e3464 AF |
571 | static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) |
572 | { | |
573 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
574 | ||
575 | return s->start_in_flash; | |
576 | } | |
577 | ||
578 | static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) | |
579 | { | |
580 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
581 | ||
582 | s->start_in_flash = value; | |
583 | } | |
584 | ||
3e9667cd BM |
585 | static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, |
586 | const char *name, void *opaque, | |
587 | Error **errp) | |
3ca109c3 BM |
588 | { |
589 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
590 | } | |
591 | ||
3e9667cd BM |
592 | static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, |
593 | const char *name, void *opaque, | |
594 | Error **errp) | |
3ca109c3 BM |
595 | { |
596 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
597 | } | |
598 | ||
523e3464 AF |
599 | static void sifive_u_machine_instance_init(Object *obj) |
600 | { | |
601 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
602 | ||
603 | s->start_in_flash = false; | |
cfa32630 BM |
604 | s->msel = 0; |
605 | object_property_add(obj, "msel", "uint32", | |
606 | sifive_u_machine_get_uint32_prop, | |
607 | sifive_u_machine_set_uint32_prop, NULL, &s->msel); | |
608 | object_property_set_description(obj, "msel", | |
609 | "Mode Select (MSEL[3:0]) pin state"); | |
610 | ||
3ca109c3 | 611 | s->serial = OTP_SERIAL; |
d2623129 | 612 | object_property_add(obj, "serial", "uint32", |
3e9667cd BM |
613 | sifive_u_machine_get_uint32_prop, |
614 | sifive_u_machine_set_uint32_prop, NULL, &s->serial); | |
7eecec7d | 615 | object_property_set_description(obj, "serial", "Board serial number"); |
523e3464 AF |
616 | } |
617 | ||
618 | static void sifive_u_machine_class_init(ObjectClass *oc, void *data) | |
619 | { | |
620 | MachineClass *mc = MACHINE_CLASS(oc); | |
621 | ||
622 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; | |
623 | mc->init = sifive_u_machine_init; | |
624 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; | |
625 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; | |
099be035 AF |
626 | #if defined(TARGET_RISCV32) |
627 | mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; | |
628 | #elif defined(TARGET_RISCV64) | |
629 | mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; | |
630 | #endif | |
523e3464 | 631 | mc->default_cpus = mc->min_cpus; |
418b473e EH |
632 | |
633 | object_class_property_add_bool(oc, "start-in-flash", | |
634 | sifive_u_machine_get_start_in_flash, | |
635 | sifive_u_machine_set_start_in_flash); | |
636 | object_class_property_set_description(oc, "start-in-flash", | |
637 | "Set on to tell QEMU's ROM to jump to " | |
638 | "flash. Otherwise QEMU will jump to DRAM " | |
639 | "or L2LIM depending on the msel value"); | |
523e3464 AF |
640 | } |
641 | ||
642 | static const TypeInfo sifive_u_machine_typeinfo = { | |
643 | .name = MACHINE_TYPE_NAME("sifive_u"), | |
644 | .parent = TYPE_MACHINE, | |
645 | .class_init = sifive_u_machine_class_init, | |
646 | .instance_init = sifive_u_machine_instance_init, | |
647 | .instance_size = sizeof(SiFiveUState), | |
648 | }; | |
649 | ||
650 | static void sifive_u_machine_init_register_types(void) | |
651 | { | |
652 | type_register_static(&sifive_u_machine_typeinfo); | |
653 | } | |
654 | ||
655 | type_init(sifive_u_machine_init_register_types) | |
656 | ||
139177b1 | 657 | static void sifive_u_soc_instance_init(Object *obj) |
2308092b AF |
658 | { |
659 | SiFiveUSoCState *s = RISCV_U_SOC(obj); | |
660 | ||
9fc7fc4d | 661 | object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
662 | qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); |
663 | ||
db873cc5 MA |
664 | object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, |
665 | TYPE_RISCV_HART_ARRAY); | |
ecdfe393 BM |
666 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); |
667 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); | |
668 | qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); | |
73f6ed97 | 669 | qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); |
ecdfe393 | 670 | |
9fc7fc4d | 671 | object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
672 | qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); |
673 | ||
db873cc5 MA |
674 | object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, |
675 | TYPE_RISCV_HART_ARRAY); | |
5a7f76a3 | 676 | |
db873cc5 MA |
677 | object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); |
678 | object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); | |
679 | object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); | |
8a88b9f5 | 680 | object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); |
834e027a | 681 | object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); |
2308092b AF |
682 | } |
683 | ||
139177b1 | 684 | static void sifive_u_soc_realize(DeviceState *dev, Error **errp) |
2308092b | 685 | { |
c4473127 | 686 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
687 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
688 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
689 | MemoryRegion *system_memory = get_system_memory(); | |
690 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
a6902ef0 | 691 | MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); |
05446f41 BM |
692 | char *plic_hart_config; |
693 | size_t plic_hart_config_len; | |
5a7f76a3 | 694 | int i; |
5a7f76a3 | 695 | NICInfo *nd = &nd_table[0]; |
2308092b | 696 | |
099be035 AF |
697 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); |
698 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); | |
699 | qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); | |
700 | qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); | |
701 | ||
db873cc5 MA |
702 | sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); |
703 | sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); | |
ecdfe393 BM |
704 | /* |
705 | * The cluster must be realized after the RISC-V hart array container, | |
706 | * as the container's CPU object is only created on realize, and the | |
707 | * CPU must exist and have been parented into the cluster before the | |
708 | * cluster is realized. | |
709 | */ | |
ce189ab2 MA |
710 | qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); |
711 | qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); | |
2308092b AF |
712 | |
713 | /* boot rom */ | |
414c47d2 | 714 | memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", |
13b8c354 EH |
715 | memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); |
716 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, | |
2308092b | 717 | mask_rom); |
a7240d1e | 718 | |
a6902ef0 AF |
719 | /* |
720 | * Add L2-LIM at reset size. | |
721 | * This should be reduced in size as the L2 Cache Controller WayEnable | |
722 | * register is incremented. Unfortunately I don't see a nice (or any) way | |
723 | * to handle reducing or blocking out the L2 LIM while still allowing it | |
724 | * be re returned to all enabled after a reset. For the time being, just | |
725 | * leave it enabled all the time. This won't break anything, but will be | |
726 | * too generous to misbehaving guests. | |
727 | */ | |
728 | memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", | |
13b8c354 EH |
729 | memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); |
730 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, | |
a6902ef0 AF |
731 | l2lim_mem); |
732 | ||
05446f41 | 733 | /* create PLIC hart topology configuration string */ |
c4473127 LX |
734 | plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * |
735 | ms->smp.cpus; | |
05446f41 | 736 | plic_hart_config = g_malloc0(plic_hart_config_len); |
c4473127 | 737 | for (i = 0; i < ms->smp.cpus; i++) { |
05446f41 | 738 | if (i != 0) { |
ef965ce2 BM |
739 | strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, |
740 | plic_hart_config_len); | |
741 | } else { | |
742 | strncat(plic_hart_config, "M", plic_hart_config_len); | |
05446f41 | 743 | } |
05446f41 BM |
744 | plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); |
745 | } | |
746 | ||
a7240d1e | 747 | /* MMIO */ |
13b8c354 | 748 | s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, |
c9270e10 | 749 | plic_hart_config, 0, |
a7240d1e MC |
750 | SIFIVE_U_PLIC_NUM_SOURCES, |
751 | SIFIVE_U_PLIC_NUM_PRIORITIES, | |
752 | SIFIVE_U_PLIC_PRIORITY_BASE, | |
753 | SIFIVE_U_PLIC_PENDING_BASE, | |
754 | SIFIVE_U_PLIC_ENABLE_BASE, | |
755 | SIFIVE_U_PLIC_ENABLE_STRIDE, | |
756 | SIFIVE_U_PLIC_CONTEXT_BASE, | |
757 | SIFIVE_U_PLIC_CONTEXT_STRIDE, | |
13b8c354 | 758 | memmap[SIFIVE_U_DEV_PLIC].size); |
bb8136df | 759 | g_free(plic_hart_config); |
13b8c354 | 760 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, |
647a70a1 | 761 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
13b8c354 | 762 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, |
194eef09 | 763 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); |
13b8c354 EH |
764 | sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, |
765 | memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, | |
a47ef6e9 BM |
766 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, |
767 | SIFIVE_CLINT_TIMEBASE_FREQ, false); | |
5a7f76a3 | 768 | |
cbe3a8c5 MA |
769 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { |
770 | return; | |
771 | } | |
13b8c354 | 772 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 | 773 | |
8a88b9f5 | 774 | qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); |
cbe3a8c5 MA |
775 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
776 | return; | |
777 | } | |
13b8c354 | 778 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 BM |
779 | |
780 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
781 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); | |
782 | ||
783 | /* Connect GPIO interrupts to the PLIC */ | |
784 | for (i = 0; i < 16; i++) { | |
785 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, | |
786 | qdev_get_gpio_in(DEVICE(s->plic), | |
787 | SIFIVE_U_GPIO_IRQ0 + i)); | |
834e027a BM |
788 | } |
789 | ||
790 | /* PDMA */ | |
791 | sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); | |
13b8c354 | 792 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
793 | |
794 | /* Connect PDMA interrupts to the PLIC */ | |
795 | for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { | |
796 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, | |
797 | qdev_get_gpio_in(DEVICE(s->plic), | |
798 | SIFIVE_U_PDMA_IRQ0 + i)); | |
8a88b9f5 BM |
799 | } |
800 | ||
fda5b000 | 801 | qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); |
cbe3a8c5 MA |
802 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { |
803 | return; | |
804 | } | |
13b8c354 | 805 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); |
5461c4fe | 806 | |
7ad36e2e | 807 | /* FIXME use qdev NIC properties instead of nd_table[] */ |
5a7f76a3 AF |
808 | if (nd->used) { |
809 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
810 | qdev_set_nic_properties(DEVICE(&s->gem), nd); | |
811 | } | |
5325cc34 | 812 | object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, |
5a7f76a3 | 813 | &error_abort); |
668f62ec | 814 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { |
5a7f76a3 AF |
815 | return; |
816 | } | |
13b8c354 | 817 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 818 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, |
5874f0a7 | 819 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); |
7b6bb66f BM |
820 | |
821 | create_unimplemented_device("riscv.sifive.u.gem-mgmt", | |
13b8c354 | 822 | memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); |
3eaea6eb BM |
823 | |
824 | create_unimplemented_device("riscv.sifive.u.dmc", | |
13b8c354 | 825 | memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); |
6eaf9cf5 BM |
826 | |
827 | create_unimplemented_device("riscv.sifive.u.l2cc", | |
13b8c354 | 828 | memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); |
a7240d1e MC |
829 | } |
830 | ||
139177b1 | 831 | static Property sifive_u_soc_props[] = { |
fda5b000 | 832 | DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), |
099be035 | 833 | DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), |
fda5b000 AF |
834 | DEFINE_PROP_END_OF_LIST() |
835 | }; | |
836 | ||
139177b1 | 837 | static void sifive_u_soc_class_init(ObjectClass *oc, void *data) |
2308092b AF |
838 | { |
839 | DeviceClass *dc = DEVICE_CLASS(oc); | |
840 | ||
139177b1 BM |
841 | device_class_set_props(dc, sifive_u_soc_props); |
842 | dc->realize = sifive_u_soc_realize; | |
2308092b AF |
843 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
844 | dc->user_creatable = false; | |
845 | } | |
846 | ||
139177b1 | 847 | static const TypeInfo sifive_u_soc_type_info = { |
2308092b AF |
848 | .name = TYPE_RISCV_U_SOC, |
849 | .parent = TYPE_DEVICE, | |
850 | .instance_size = sizeof(SiFiveUSoCState), | |
139177b1 BM |
851 | .instance_init = sifive_u_soc_instance_init, |
852 | .class_init = sifive_u_soc_class_init, | |
2308092b AF |
853 | }; |
854 | ||
139177b1 | 855 | static void sifive_u_soc_register_types(void) |
2308092b | 856 | { |
139177b1 | 857 | type_register_static(&sifive_u_soc_type_info); |
2308092b AF |
858 | } |
859 | ||
139177b1 | 860 | type_init(sifive_u_soc_register_types) |