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a7240d1e MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017 SiFive, Inc. | |
7b6bb66f | 6 | * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> |
a7240d1e MC |
7 | * |
8 | * Provides a board compatible with the SiFive Freedom U SDK: | |
9 | * | |
10 | * 0) UART | |
11 | * 1) CLINT (Core Level Interruptor) | |
12 | * 2) PLIC (Platform Level Interrupt Controller) | |
af14c840 | 13 | * 3) PRCI (Power, Reset, Clock, Interrupt) |
8a88b9f5 BM |
14 | * 4) GPIO (General Purpose Input/Output Controller) |
15 | * 5) OTP (One-Time Programmable) memory with stored serial number | |
16 | * 6) GEM (Gigabit Ethernet Controller) and management block | |
834e027a | 17 | * 7) DMA (Direct Memory Access Controller) |
a7240d1e | 18 | * |
f3d47d58 | 19 | * This board currently generates devicetree dynamically that indicates at least |
ecdfe393 | 20 | * two harts and up to five harts. |
a7240d1e MC |
21 | * |
22 | * This program is free software; you can redistribute it and/or modify it | |
23 | * under the terms and conditions of the GNU General Public License, | |
24 | * version 2 or later, as published by the Free Software Foundation. | |
25 | * | |
26 | * This program is distributed in the hope it will be useful, but WITHOUT | |
27 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
28 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
29 | * more details. | |
30 | * | |
31 | * You should have received a copy of the GNU General Public License along with | |
32 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
33 | */ | |
34 | ||
35 | #include "qemu/osdep.h" | |
36 | #include "qemu/log.h" | |
37 | #include "qemu/error-report.h" | |
38 | #include "qapi/error.h" | |
3ca109c3 | 39 | #include "qapi/visitor.h" |
a7240d1e | 40 | #include "hw/boards.h" |
5133ed17 | 41 | #include "hw/irq.h" |
a7240d1e MC |
42 | #include "hw/loader.h" |
43 | #include "hw/sysbus.h" | |
44 | #include "hw/char/serial.h" | |
ecdfe393 | 45 | #include "hw/cpu/cluster.h" |
7b6bb66f | 46 | #include "hw/misc/unimp.h" |
a7240d1e MC |
47 | #include "target/riscv/cpu.h" |
48 | #include "hw/riscv/riscv_hart.h" | |
a7240d1e | 49 | #include "hw/riscv/sifive_u.h" |
0ac24d56 | 50 | #include "hw/riscv/boot.h" |
b609b7e3 | 51 | #include "hw/char/sifive_uart.h" |
406fafd5 | 52 | #include "hw/intc/sifive_clint.h" |
84fcf3c1 | 53 | #include "hw/intc/sifive_plic.h" |
a7240d1e | 54 | #include "chardev/char.h" |
7b6bb66f | 55 | #include "net/eth.h" |
a7240d1e MC |
56 | #include "sysemu/arch_init.h" |
57 | #include "sysemu/device_tree.h" | |
5133ed17 | 58 | #include "sysemu/runstate.h" |
46517dd4 | 59 | #include "sysemu/sysemu.h" |
a7240d1e | 60 | |
5aec3247 MC |
61 | #include <libfdt.h> |
62 | ||
b78c3296 | 63 | #if defined(TARGET_RISCV32) |
2cacd841 | 64 | # define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" |
b78c3296 | 65 | #else |
2cacd841 | 66 | # define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" |
b78c3296 | 67 | #endif |
fdd1bda4 | 68 | |
a7240d1e MC |
69 | static const struct MemmapEntry { |
70 | hwaddr base; | |
71 | hwaddr size; | |
72 | } sifive_u_memmap[] = { | |
13b8c354 EH |
73 | [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, |
74 | [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, | |
75 | [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, | |
76 | [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, | |
77 | [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, | |
78 | [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, | |
79 | [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, | |
80 | [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, | |
81 | [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, | |
82 | [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, | |
83 | [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, | |
84 | [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, | |
85 | [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, | |
86 | [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, | |
87 | [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, | |
88 | [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, | |
89 | [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, | |
a7240d1e MC |
90 | }; |
91 | ||
5461c4fe | 92 | #define OTP_SERIAL 1 |
5a7f76a3 AF |
93 | #define GEM_REVISION 0x10070109 |
94 | ||
9f79638e | 95 | static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, |
a7240d1e MC |
96 | uint64_t mem_size, const char *cmdline) |
97 | { | |
ecdfe393 | 98 | MachineState *ms = MACHINE(qdev_get_machine()); |
a7240d1e MC |
99 | void *fdt; |
100 | int cpu; | |
101 | uint32_t *cells; | |
102 | char *nodename; | |
806c64b7 | 103 | char ethclk_names[] = "pclk\0hclk"; |
5133ed17 | 104 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; |
7b6bb66f | 105 | uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; |
a7240d1e MC |
106 | |
107 | fdt = s->fdt = create_device_tree(&s->fdt_size); | |
108 | if (!fdt) { | |
109 | error_report("create_device_tree() failed"); | |
110 | exit(1); | |
111 | } | |
112 | ||
d372e748 BM |
113 | qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); |
114 | qemu_fdt_setprop_string(fdt, "/", "compatible", | |
115 | "sifive,hifive-unleashed-a00"); | |
a7240d1e MC |
116 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); |
117 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
118 | ||
119 | qemu_fdt_add_subnode(fdt, "/soc"); | |
120 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
2a1a6f6d | 121 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
a7240d1e MC |
122 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
123 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
124 | ||
e1724d09 BM |
125 | hfclk_phandle = phandle++; |
126 | nodename = g_strdup_printf("/hfclk"); | |
127 | qemu_fdt_add_subnode(fdt, nodename); | |
128 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); | |
129 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); | |
130 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
131 | SIFIVE_U_HFCLK_FREQ); | |
132 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
133 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
134 | g_free(nodename); | |
135 | ||
136 | rtcclk_phandle = phandle++; | |
137 | nodename = g_strdup_printf("/rtcclk"); | |
138 | qemu_fdt_add_subnode(fdt, nodename); | |
139 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); | |
140 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); | |
141 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
142 | SIFIVE_U_RTCCLK_FREQ); | |
143 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
144 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
145 | g_free(nodename); | |
146 | ||
a7240d1e | 147 | nodename = g_strdup_printf("/memory@%lx", |
13b8c354 | 148 | (long)memmap[SIFIVE_U_DEV_DRAM].base); |
a7240d1e MC |
149 | qemu_fdt_add_subnode(fdt, nodename); |
150 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 | 151 | memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, |
a7240d1e MC |
152 | mem_size >> 32, mem_size); |
153 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
154 | g_free(nodename); | |
155 | ||
156 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
2a8756ed MC |
157 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
158 | SIFIVE_CLINT_TIMEBASE_FREQ); | |
a7240d1e MC |
159 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
160 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
161 | ||
ecdfe393 | 162 | for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { |
382cb439 | 163 | int cpu_phandle = phandle++; |
a7240d1e MC |
164 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
165 | char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
ecdfe393 | 166 | char *isa; |
a7240d1e | 167 | qemu_fdt_add_subnode(fdt, nodename); |
ecdfe393 BM |
168 | /* cpu 0 is the management hart that does not have mmu */ |
169 | if (cpu != 0) { | |
e883e992 BM |
170 | #if defined(TARGET_RISCV32) |
171 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); | |
172 | #else | |
ecdfe393 | 173 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); |
e883e992 | 174 | #endif |
ecdfe393 BM |
175 | isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); |
176 | } else { | |
177 | isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); | |
178 | } | |
a7240d1e MC |
179 | qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); |
180 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | |
181 | qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | |
182 | qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | |
183 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | |
184 | qemu_fdt_add_subnode(fdt, intc); | |
382cb439 | 185 | qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); |
a7240d1e MC |
186 | qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); |
187 | qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | |
188 | qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | |
189 | g_free(isa); | |
190 | g_free(intc); | |
191 | g_free(nodename); | |
192 | } | |
193 | ||
ecdfe393 BM |
194 | cells = g_new0(uint32_t, ms->smp.cpus * 4); |
195 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
196 | nodename = |
197 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
198 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
199 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
200 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
201 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
202 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
203 | g_free(nodename); | |
204 | } | |
205 | nodename = g_strdup_printf("/soc/clint@%lx", | |
13b8c354 | 206 | (long)memmap[SIFIVE_U_DEV_CLINT].base); |
a7240d1e MC |
207 | qemu_fdt_add_subnode(fdt, nodename); |
208 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); | |
209 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
210 | 0x0, memmap[SIFIVE_U_DEV_CLINT].base, |
211 | 0x0, memmap[SIFIVE_U_DEV_CLINT].size); | |
a7240d1e | 212 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", |
ecdfe393 | 213 | cells, ms->smp.cpus * sizeof(uint32_t) * 4); |
a7240d1e MC |
214 | g_free(cells); |
215 | g_free(nodename); | |
216 | ||
ea85f27d | 217 | nodename = g_strdup_printf("/soc/otp@%lx", |
13b8c354 | 218 | (long)memmap[SIFIVE_U_DEV_OTP].base); |
ea85f27d BM |
219 | qemu_fdt_add_subnode(fdt, nodename); |
220 | qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); | |
221 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
222 | 0x0, memmap[SIFIVE_U_DEV_OTP].base, |
223 | 0x0, memmap[SIFIVE_U_DEV_OTP].size); | |
ea85f27d BM |
224 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
225 | "sifive,fu540-c000-otp"); | |
226 | g_free(nodename); | |
227 | ||
af14c840 BM |
228 | prci_phandle = phandle++; |
229 | nodename = g_strdup_printf("/soc/clock-controller@%lx", | |
13b8c354 | 230 | (long)memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 BM |
231 | qemu_fdt_add_subnode(fdt, nodename); |
232 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); | |
233 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); | |
234 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
235 | hfclk_phandle, rtcclk_phandle); | |
236 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
237 | 0x0, memmap[SIFIVE_U_DEV_PRCI].base, |
238 | 0x0, memmap[SIFIVE_U_DEV_PRCI].size); | |
af14c840 BM |
239 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
240 | "sifive,fu540-c000-prci"); | |
241 | g_free(nodename); | |
242 | ||
382cb439 | 243 | plic_phandle = phandle++; |
ecdfe393 BM |
244 | cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); |
245 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
246 | nodename = |
247 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
248 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
ecdfe393 BM |
249 | /* cpu 0 is the management hart that does not have S-mode */ |
250 | if (cpu == 0) { | |
251 | cells[0] = cpu_to_be32(intc_phandle); | |
252 | cells[1] = cpu_to_be32(IRQ_M_EXT); | |
253 | } else { | |
254 | cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); | |
255 | cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); | |
256 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
257 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); | |
258 | } | |
a7240d1e MC |
259 | g_free(nodename); |
260 | } | |
261 | nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | |
13b8c354 | 262 | (long)memmap[SIFIVE_U_DEV_PLIC].base); |
a7240d1e MC |
263 | qemu_fdt_add_subnode(fdt, nodename); |
264 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); | |
265 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); | |
266 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
267 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 268 | cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); |
a7240d1e | 269 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
270 | 0x0, memmap[SIFIVE_U_DEV_PLIC].base, |
271 | 0x0, memmap[SIFIVE_U_DEV_PLIC].size); | |
98ceee7f | 272 | qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); |
04e7edd1 | 273 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); |
a7240d1e MC |
274 | plic_phandle = qemu_fdt_get_phandle(fdt, nodename); |
275 | g_free(cells); | |
276 | g_free(nodename); | |
277 | ||
5133ed17 | 278 | gpio_phandle = phandle++; |
8a88b9f5 | 279 | nodename = g_strdup_printf("/soc/gpio@%lx", |
13b8c354 | 280 | (long)memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 | 281 | qemu_fdt_add_subnode(fdt, nodename); |
5133ed17 | 282 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); |
8a88b9f5 BM |
283 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
284 | prci_phandle, PRCI_CLK_TLCLK); | |
285 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); | |
286 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
287 | qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); | |
288 | qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); | |
289 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
290 | 0x0, memmap[SIFIVE_U_DEV_GPIO].base, |
291 | 0x0, memmap[SIFIVE_U_DEV_GPIO].size); | |
8a88b9f5 BM |
292 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, |
293 | SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, | |
294 | SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, | |
295 | SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, | |
296 | SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, | |
297 | SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); | |
298 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
299 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); | |
300 | g_free(nodename); | |
301 | ||
5133ed17 BM |
302 | nodename = g_strdup_printf("/gpio-restart"); |
303 | qemu_fdt_add_subnode(fdt, nodename); | |
304 | qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); | |
305 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); | |
306 | g_free(nodename); | |
307 | ||
834e027a | 308 | nodename = g_strdup_printf("/soc/dma@%lx", |
13b8c354 | 309 | (long)memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
310 | qemu_fdt_add_subnode(fdt, nodename); |
311 | qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); | |
312 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
313 | SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, | |
314 | SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, | |
315 | SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); | |
316 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
317 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
318 | 0x0, memmap[SIFIVE_U_DEV_PDMA].base, |
319 | 0x0, memmap[SIFIVE_U_DEV_PDMA].size); | |
834e027a BM |
320 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
321 | "sifive,fu540-c000-pdma"); | |
322 | g_free(nodename); | |
323 | ||
6eaf9cf5 | 324 | nodename = g_strdup_printf("/soc/cache-controller@%lx", |
13b8c354 | 325 | (long)memmap[SIFIVE_U_DEV_L2CC].base); |
6eaf9cf5 BM |
326 | qemu_fdt_add_subnode(fdt, nodename); |
327 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
328 | 0x0, memmap[SIFIVE_U_DEV_L2CC].base, |
329 | 0x0, memmap[SIFIVE_U_DEV_L2CC].size); | |
6eaf9cf5 BM |
330 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", |
331 | SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); | |
332 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
333 | qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); | |
334 | qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); | |
335 | qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); | |
336 | qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); | |
337 | qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); | |
338 | qemu_fdt_setprop_string(fdt, nodename, "compatible", | |
339 | "sifive,fu540-c000-ccache"); | |
340 | g_free(nodename); | |
341 | ||
7b6bb66f | 342 | phy_phandle = phandle++; |
5a7f76a3 | 343 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
13b8c354 | 344 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 345 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f BM |
346 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
347 | "sifive,fu540-c000-gem"); | |
5a7f76a3 | 348 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
349 | 0x0, memmap[SIFIVE_U_DEV_GEM].base, |
350 | 0x0, memmap[SIFIVE_U_DEV_GEM].size, | |
351 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, | |
352 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); | |
5a7f76a3 AF |
353 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); |
354 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); | |
7b6bb66f | 355 | qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); |
04e7edd1 BM |
356 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
357 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); | |
fe93582c | 358 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
806c64b7 | 359 | prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); |
04ece4f8 | 360 | qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, |
fe93582c | 361 | sizeof(ethclk_names)); |
7b6bb66f BM |
362 | qemu_fdt_setprop(fdt, nodename, "local-mac-address", |
363 | s->soc.gem.conf.macaddr.a, ETH_ALEN); | |
04e7edd1 BM |
364 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
365 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
c3a28b5d BM |
366 | |
367 | qemu_fdt_add_subnode(fdt, "/aliases"); | |
368 | qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); | |
369 | ||
5a7f76a3 AF |
370 | g_free(nodename); |
371 | ||
372 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", | |
13b8c354 | 373 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 374 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f | 375 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); |
04e7edd1 | 376 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
5a7f76a3 AF |
377 | g_free(nodename); |
378 | ||
5f7134d3 | 379 | nodename = g_strdup_printf("/soc/serial@%lx", |
13b8c354 | 380 | (long)memmap[SIFIVE_U_DEV_UART0].base); |
a7240d1e MC |
381 | qemu_fdt_add_subnode(fdt, nodename); |
382 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
383 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
384 | 0x0, memmap[SIFIVE_U_DEV_UART0].base, |
385 | 0x0, memmap[SIFIVE_U_DEV_UART0].size); | |
806c64b7 BM |
386 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
387 | prci_phandle, PRCI_CLK_TLCLK); | |
04e7edd1 BM |
388 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
389 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); | |
a7240d1e MC |
390 | |
391 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
392 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | |
7c28f4da MC |
393 | if (cmdline) { |
394 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
395 | } | |
44e6dcd3 | 396 | |
44e6dcd3 GR |
397 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); |
398 | ||
a7240d1e MC |
399 | g_free(nodename); |
400 | } | |
401 | ||
5133ed17 BM |
402 | static void sifive_u_machine_reset(void *opaque, int n, int level) |
403 | { | |
404 | /* gpio pin active low triggers reset */ | |
405 | if (!level) { | |
406 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
407 | } | |
408 | } | |
409 | ||
523e3464 | 410 | static void sifive_u_machine_init(MachineState *machine) |
a7240d1e MC |
411 | { |
412 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
687caef1 | 413 | SiFiveUState *s = RISCV_U_MACHINE(machine); |
5aec3247 | 414 | MemoryRegion *system_memory = get_system_memory(); |
a7240d1e | 415 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); |
1b3a2308 | 416 | MemoryRegion *flash0 = g_new(MemoryRegion, 1); |
13b8c354 | 417 | target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
8590f536 | 418 | uint32_t start_addr_hi32 = 0x00000000; |
5aec3247 | 419 | int i; |
66b1205b | 420 | uint32_t fdt_load_addr; |
dc144fe1 | 421 | uint64_t kernel_entry; |
a7240d1e | 422 | |
2308092b | 423 | /* Initialize SoC */ |
9fc7fc4d | 424 | object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); |
5325cc34 MA |
425 | object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, |
426 | &error_abort); | |
099be035 AF |
427 | object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, |
428 | &error_abort); | |
ce189ab2 | 429 | qdev_realize(DEVICE(&s->soc), NULL, &error_abort); |
a7240d1e MC |
430 | |
431 | /* register RAM */ | |
432 | memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", | |
433 | machine->ram_size, &error_fatal); | |
13b8c354 | 434 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, |
2308092b | 435 | main_mem); |
a7240d1e | 436 | |
1b3a2308 AF |
437 | /* register QSPI0 Flash */ |
438 | memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", | |
13b8c354 EH |
439 | memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); |
440 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, | |
1b3a2308 AF |
441 | flash0); |
442 | ||
5133ed17 BM |
443 | /* register gpio-restart */ |
444 | qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, | |
445 | qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); | |
446 | ||
a7240d1e | 447 | /* create device tree */ |
9f79638e | 448 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); |
a7240d1e | 449 | |
17aad9f2 BM |
450 | if (s->start_in_flash) { |
451 | /* | |
452 | * If start_in_flash property is given, assign s->msel to a value | |
453 | * that representing booting from QSPI0 memory-mapped flash. | |
454 | * | |
455 | * This also means that when both start_in_flash and msel properties | |
456 | * are given, start_in_flash takes the precedence over msel. | |
457 | * | |
458 | * Note this is to keep backward compatibility not to break existing | |
459 | * users that use start_in_flash property. | |
460 | */ | |
461 | s->msel = MSEL_MEMMAP_QSPI0_FLASH; | |
462 | } | |
463 | ||
464 | switch (s->msel) { | |
465 | case MSEL_MEMMAP_QSPI0_FLASH: | |
13b8c354 | 466 | start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; |
17aad9f2 BM |
467 | break; |
468 | case MSEL_L2LIM_QSPI0_FLASH: | |
469 | case MSEL_L2LIM_QSPI2_SD: | |
13b8c354 | 470 | start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; |
17aad9f2 BM |
471 | break; |
472 | default: | |
13b8c354 | 473 | start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
17aad9f2 BM |
474 | break; |
475 | } | |
476 | ||
477 | riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL); | |
b3042223 | 478 | |
a7240d1e | 479 | if (machine->kernel_filename) { |
dc144fe1 | 480 | kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL); |
0f8d4462 GR |
481 | |
482 | if (machine->initrd_filename) { | |
483 | hwaddr start; | |
484 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | |
485 | machine->ram_size, kernel_entry, | |
486 | &start); | |
9f79638e | 487 | qemu_fdt_setprop_cell(s->fdt, "/chosen", |
0f8d4462 | 488 | "linux,initrd-start", start); |
9f79638e | 489 | qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", |
0f8d4462 GR |
490 | end); |
491 | } | |
dc144fe1 AP |
492 | } else { |
493 | /* | |
494 | * If dynamic firmware is used, it doesn't know where is the next mode | |
495 | * if kernel argument is not set. | |
496 | */ | |
497 | kernel_entry = 0; | |
a7240d1e MC |
498 | } |
499 | ||
66b1205b | 500 | /* Compute the fdt load address in dram */ |
13b8c354 | 501 | fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, |
66b1205b | 502 | machine->ram_size, s->fdt); |
8590f536 AP |
503 | #if defined(TARGET_RISCV64) |
504 | start_addr_hi32 = start_addr >> 32; | |
505 | #endif | |
66b1205b | 506 | |
a7240d1e | 507 | /* reset vector */ |
66b1205b | 508 | uint32_t reset_vec[11] = { |
17aad9f2 | 509 | s->msel, /* MSEL pin state */ |
dc144fe1 AP |
510 | 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ |
511 | 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ | |
a7240d1e MC |
512 | 0xf1402573, /* csrr a0, mhartid */ |
513 | #if defined(TARGET_RISCV32) | |
66b1205b | 514 | 0x0202a583, /* lw a1, 32(t0) */ |
a7240d1e MC |
515 | 0x0182a283, /* lw t0, 24(t0) */ |
516 | #elif defined(TARGET_RISCV64) | |
66b1205b AP |
517 | 0x0202b583, /* ld a1, 32(t0) */ |
518 | 0x0182b283, /* ld t0, 24(t0) */ | |
a7240d1e MC |
519 | #endif |
520 | 0x00028067, /* jr t0 */ | |
fc41ae23 | 521 | start_addr, /* start: .dword */ |
8590f536 | 522 | start_addr_hi32, |
66b1205b AP |
523 | fdt_load_addr, /* fdt_laddr: .dword */ |
524 | 0x00000000, | |
dc144fe1 | 525 | /* fw_dyn: */ |
a7240d1e MC |
526 | }; |
527 | ||
5aec3247 | 528 | /* copy in the reset vector in little_endian byte order */ |
66b1205b | 529 | for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { |
5aec3247 MC |
530 | reset_vec[i] = cpu_to_le32(reset_vec[i]); |
531 | } | |
532 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
13b8c354 | 533 | memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); |
dc144fe1 | 534 | |
13b8c354 EH |
535 | riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base, |
536 | memmap[SIFIVE_U_DEV_MROM].size, | |
dc144fe1 | 537 | sizeof(reset_vec), kernel_entry); |
2308092b AF |
538 | } |
539 | ||
523e3464 AF |
540 | static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) |
541 | { | |
542 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
543 | ||
544 | return s->start_in_flash; | |
545 | } | |
546 | ||
547 | static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) | |
548 | { | |
549 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
550 | ||
551 | s->start_in_flash = value; | |
552 | } | |
553 | ||
3e9667cd BM |
554 | static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, |
555 | const char *name, void *opaque, | |
556 | Error **errp) | |
3ca109c3 BM |
557 | { |
558 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
559 | } | |
560 | ||
3e9667cd BM |
561 | static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, |
562 | const char *name, void *opaque, | |
563 | Error **errp) | |
3ca109c3 BM |
564 | { |
565 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
566 | } | |
567 | ||
523e3464 AF |
568 | static void sifive_u_machine_instance_init(Object *obj) |
569 | { | |
570 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
571 | ||
572 | s->start_in_flash = false; | |
cfa32630 BM |
573 | s->msel = 0; |
574 | object_property_add(obj, "msel", "uint32", | |
575 | sifive_u_machine_get_uint32_prop, | |
576 | sifive_u_machine_set_uint32_prop, NULL, &s->msel); | |
577 | object_property_set_description(obj, "msel", | |
578 | "Mode Select (MSEL[3:0]) pin state"); | |
579 | ||
3ca109c3 | 580 | s->serial = OTP_SERIAL; |
d2623129 | 581 | object_property_add(obj, "serial", "uint32", |
3e9667cd BM |
582 | sifive_u_machine_get_uint32_prop, |
583 | sifive_u_machine_set_uint32_prop, NULL, &s->serial); | |
7eecec7d | 584 | object_property_set_description(obj, "serial", "Board serial number"); |
523e3464 AF |
585 | } |
586 | ||
587 | static void sifive_u_machine_class_init(ObjectClass *oc, void *data) | |
588 | { | |
589 | MachineClass *mc = MACHINE_CLASS(oc); | |
590 | ||
591 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; | |
592 | mc->init = sifive_u_machine_init; | |
593 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; | |
594 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; | |
099be035 AF |
595 | #if defined(TARGET_RISCV32) |
596 | mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; | |
597 | #elif defined(TARGET_RISCV64) | |
598 | mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; | |
599 | #endif | |
523e3464 | 600 | mc->default_cpus = mc->min_cpus; |
418b473e EH |
601 | |
602 | object_class_property_add_bool(oc, "start-in-flash", | |
603 | sifive_u_machine_get_start_in_flash, | |
604 | sifive_u_machine_set_start_in_flash); | |
605 | object_class_property_set_description(oc, "start-in-flash", | |
606 | "Set on to tell QEMU's ROM to jump to " | |
607 | "flash. Otherwise QEMU will jump to DRAM " | |
608 | "or L2LIM depending on the msel value"); | |
523e3464 AF |
609 | } |
610 | ||
611 | static const TypeInfo sifive_u_machine_typeinfo = { | |
612 | .name = MACHINE_TYPE_NAME("sifive_u"), | |
613 | .parent = TYPE_MACHINE, | |
614 | .class_init = sifive_u_machine_class_init, | |
615 | .instance_init = sifive_u_machine_instance_init, | |
616 | .instance_size = sizeof(SiFiveUState), | |
617 | }; | |
618 | ||
619 | static void sifive_u_machine_init_register_types(void) | |
620 | { | |
621 | type_register_static(&sifive_u_machine_typeinfo); | |
622 | } | |
623 | ||
624 | type_init(sifive_u_machine_init_register_types) | |
625 | ||
139177b1 | 626 | static void sifive_u_soc_instance_init(Object *obj) |
2308092b AF |
627 | { |
628 | SiFiveUSoCState *s = RISCV_U_SOC(obj); | |
629 | ||
9fc7fc4d | 630 | object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
631 | qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); |
632 | ||
db873cc5 MA |
633 | object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, |
634 | TYPE_RISCV_HART_ARRAY); | |
ecdfe393 BM |
635 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); |
636 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); | |
637 | qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); | |
73f6ed97 | 638 | qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); |
ecdfe393 | 639 | |
9fc7fc4d | 640 | object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
641 | qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); |
642 | ||
db873cc5 MA |
643 | object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, |
644 | TYPE_RISCV_HART_ARRAY); | |
5a7f76a3 | 645 | |
db873cc5 MA |
646 | object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); |
647 | object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); | |
648 | object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); | |
8a88b9f5 | 649 | object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); |
834e027a | 650 | object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); |
2308092b AF |
651 | } |
652 | ||
139177b1 | 653 | static void sifive_u_soc_realize(DeviceState *dev, Error **errp) |
2308092b | 654 | { |
c4473127 | 655 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
656 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
657 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
658 | MemoryRegion *system_memory = get_system_memory(); | |
659 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
a6902ef0 | 660 | MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); |
05446f41 BM |
661 | char *plic_hart_config; |
662 | size_t plic_hart_config_len; | |
5a7f76a3 | 663 | int i; |
5a7f76a3 | 664 | NICInfo *nd = &nd_table[0]; |
2308092b | 665 | |
099be035 AF |
666 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); |
667 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); | |
668 | qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); | |
669 | qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); | |
670 | ||
db873cc5 MA |
671 | sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); |
672 | sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); | |
ecdfe393 BM |
673 | /* |
674 | * The cluster must be realized after the RISC-V hart array container, | |
675 | * as the container's CPU object is only created on realize, and the | |
676 | * CPU must exist and have been parented into the cluster before the | |
677 | * cluster is realized. | |
678 | */ | |
ce189ab2 MA |
679 | qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); |
680 | qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); | |
2308092b AF |
681 | |
682 | /* boot rom */ | |
414c47d2 | 683 | memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", |
13b8c354 EH |
684 | memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); |
685 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, | |
2308092b | 686 | mask_rom); |
a7240d1e | 687 | |
a6902ef0 AF |
688 | /* |
689 | * Add L2-LIM at reset size. | |
690 | * This should be reduced in size as the L2 Cache Controller WayEnable | |
691 | * register is incremented. Unfortunately I don't see a nice (or any) way | |
692 | * to handle reducing or blocking out the L2 LIM while still allowing it | |
693 | * be re returned to all enabled after a reset. For the time being, just | |
694 | * leave it enabled all the time. This won't break anything, but will be | |
695 | * too generous to misbehaving guests. | |
696 | */ | |
697 | memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", | |
13b8c354 EH |
698 | memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); |
699 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, | |
a6902ef0 AF |
700 | l2lim_mem); |
701 | ||
05446f41 | 702 | /* create PLIC hart topology configuration string */ |
c4473127 LX |
703 | plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * |
704 | ms->smp.cpus; | |
05446f41 | 705 | plic_hart_config = g_malloc0(plic_hart_config_len); |
c4473127 | 706 | for (i = 0; i < ms->smp.cpus; i++) { |
05446f41 | 707 | if (i != 0) { |
ef965ce2 BM |
708 | strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, |
709 | plic_hart_config_len); | |
710 | } else { | |
711 | strncat(plic_hart_config, "M", plic_hart_config_len); | |
05446f41 | 712 | } |
05446f41 BM |
713 | plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); |
714 | } | |
715 | ||
a7240d1e | 716 | /* MMIO */ |
13b8c354 | 717 | s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, |
c9270e10 | 718 | plic_hart_config, 0, |
a7240d1e MC |
719 | SIFIVE_U_PLIC_NUM_SOURCES, |
720 | SIFIVE_U_PLIC_NUM_PRIORITIES, | |
721 | SIFIVE_U_PLIC_PRIORITY_BASE, | |
722 | SIFIVE_U_PLIC_PENDING_BASE, | |
723 | SIFIVE_U_PLIC_ENABLE_BASE, | |
724 | SIFIVE_U_PLIC_ENABLE_STRIDE, | |
725 | SIFIVE_U_PLIC_CONTEXT_BASE, | |
726 | SIFIVE_U_PLIC_CONTEXT_STRIDE, | |
13b8c354 | 727 | memmap[SIFIVE_U_DEV_PLIC].size); |
bb8136df | 728 | g_free(plic_hart_config); |
13b8c354 | 729 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, |
647a70a1 | 730 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
13b8c354 | 731 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, |
194eef09 | 732 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); |
13b8c354 EH |
733 | sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, |
734 | memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, | |
a47ef6e9 BM |
735 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, |
736 | SIFIVE_CLINT_TIMEBASE_FREQ, false); | |
5a7f76a3 | 737 | |
cbe3a8c5 MA |
738 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { |
739 | return; | |
740 | } | |
13b8c354 | 741 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 | 742 | |
8a88b9f5 | 743 | qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); |
cbe3a8c5 MA |
744 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
745 | return; | |
746 | } | |
13b8c354 | 747 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 BM |
748 | |
749 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
750 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); | |
751 | ||
752 | /* Connect GPIO interrupts to the PLIC */ | |
753 | for (i = 0; i < 16; i++) { | |
754 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, | |
755 | qdev_get_gpio_in(DEVICE(s->plic), | |
756 | SIFIVE_U_GPIO_IRQ0 + i)); | |
834e027a BM |
757 | } |
758 | ||
759 | /* PDMA */ | |
760 | sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); | |
13b8c354 | 761 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
762 | |
763 | /* Connect PDMA interrupts to the PLIC */ | |
764 | for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { | |
765 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, | |
766 | qdev_get_gpio_in(DEVICE(s->plic), | |
767 | SIFIVE_U_PDMA_IRQ0 + i)); | |
8a88b9f5 BM |
768 | } |
769 | ||
fda5b000 | 770 | qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); |
cbe3a8c5 MA |
771 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { |
772 | return; | |
773 | } | |
13b8c354 | 774 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); |
5461c4fe | 775 | |
7ad36e2e | 776 | /* FIXME use qdev NIC properties instead of nd_table[] */ |
5a7f76a3 AF |
777 | if (nd->used) { |
778 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
779 | qdev_set_nic_properties(DEVICE(&s->gem), nd); | |
780 | } | |
5325cc34 | 781 | object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, |
5a7f76a3 | 782 | &error_abort); |
668f62ec | 783 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { |
5a7f76a3 AF |
784 | return; |
785 | } | |
13b8c354 | 786 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 787 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, |
5874f0a7 | 788 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); |
7b6bb66f BM |
789 | |
790 | create_unimplemented_device("riscv.sifive.u.gem-mgmt", | |
13b8c354 | 791 | memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); |
3eaea6eb BM |
792 | |
793 | create_unimplemented_device("riscv.sifive.u.dmc", | |
13b8c354 | 794 | memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); |
6eaf9cf5 BM |
795 | |
796 | create_unimplemented_device("riscv.sifive.u.l2cc", | |
13b8c354 | 797 | memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); |
a7240d1e MC |
798 | } |
799 | ||
139177b1 | 800 | static Property sifive_u_soc_props[] = { |
fda5b000 | 801 | DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), |
099be035 | 802 | DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), |
fda5b000 AF |
803 | DEFINE_PROP_END_OF_LIST() |
804 | }; | |
805 | ||
139177b1 | 806 | static void sifive_u_soc_class_init(ObjectClass *oc, void *data) |
2308092b AF |
807 | { |
808 | DeviceClass *dc = DEVICE_CLASS(oc); | |
809 | ||
139177b1 BM |
810 | device_class_set_props(dc, sifive_u_soc_props); |
811 | dc->realize = sifive_u_soc_realize; | |
2308092b AF |
812 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
813 | dc->user_creatable = false; | |
814 | } | |
815 | ||
139177b1 | 816 | static const TypeInfo sifive_u_soc_type_info = { |
2308092b AF |
817 | .name = TYPE_RISCV_U_SOC, |
818 | .parent = TYPE_DEVICE, | |
819 | .instance_size = sizeof(SiFiveUSoCState), | |
139177b1 BM |
820 | .instance_init = sifive_u_soc_instance_init, |
821 | .class_init = sifive_u_soc_class_init, | |
2308092b AF |
822 | }; |
823 | ||
139177b1 | 824 | static void sifive_u_soc_register_types(void) |
2308092b | 825 | { |
139177b1 | 826 | type_register_static(&sifive_u_soc_type_info); |
2308092b AF |
827 | } |
828 | ||
139177b1 | 829 | type_init(sifive_u_soc_register_types) |