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a7240d1e MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017 SiFive, Inc. | |
7b6bb66f | 6 | * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> |
a7240d1e MC |
7 | * |
8 | * Provides a board compatible with the SiFive Freedom U SDK: | |
9 | * | |
10 | * 0) UART | |
11 | * 1) CLINT (Core Level Interruptor) | |
12 | * 2) PLIC (Platform Level Interrupt Controller) | |
af14c840 | 13 | * 3) PRCI (Power, Reset, Clock, Interrupt) |
8a88b9f5 BM |
14 | * 4) GPIO (General Purpose Input/Output Controller) |
15 | * 5) OTP (One-Time Programmable) memory with stored serial number | |
16 | * 6) GEM (Gigabit Ethernet Controller) and management block | |
834e027a | 17 | * 7) DMA (Direct Memory Access Controller) |
145b2991 | 18 | * 8) SPI0 connected to an SPI flash |
722f1352 | 19 | * 9) SPI2 connected to an SD card |
a7240d1e | 20 | * |
f3d47d58 | 21 | * This board currently generates devicetree dynamically that indicates at least |
ecdfe393 | 22 | * two harts and up to five harts. |
a7240d1e MC |
23 | * |
24 | * This program is free software; you can redistribute it and/or modify it | |
25 | * under the terms and conditions of the GNU General Public License, | |
26 | * version 2 or later, as published by the Free Software Foundation. | |
27 | * | |
28 | * This program is distributed in the hope it will be useful, but WITHOUT | |
29 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
30 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
31 | * more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along with | |
34 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
35 | */ | |
36 | ||
37 | #include "qemu/osdep.h" | |
a7240d1e MC |
38 | #include "qemu/error-report.h" |
39 | #include "qapi/error.h" | |
3ca109c3 | 40 | #include "qapi/visitor.h" |
a7240d1e | 41 | #include "hw/boards.h" |
5133ed17 | 42 | #include "hw/irq.h" |
a7240d1e MC |
43 | #include "hw/loader.h" |
44 | #include "hw/sysbus.h" | |
45 | #include "hw/char/serial.h" | |
ecdfe393 | 46 | #include "hw/cpu/cluster.h" |
7b6bb66f | 47 | #include "hw/misc/unimp.h" |
145b2991 | 48 | #include "hw/ssi/ssi.h" |
a7240d1e MC |
49 | #include "target/riscv/cpu.h" |
50 | #include "hw/riscv/riscv_hart.h" | |
a7240d1e | 51 | #include "hw/riscv/sifive_u.h" |
0ac24d56 | 52 | #include "hw/riscv/boot.h" |
b609b7e3 | 53 | #include "hw/char/sifive_uart.h" |
406fafd5 | 54 | #include "hw/intc/sifive_clint.h" |
84fcf3c1 | 55 | #include "hw/intc/sifive_plic.h" |
a7240d1e | 56 | #include "chardev/char.h" |
7b6bb66f | 57 | #include "net/eth.h" |
a7240d1e | 58 | #include "sysemu/device_tree.h" |
5133ed17 | 59 | #include "sysemu/runstate.h" |
46517dd4 | 60 | #include "sysemu/sysemu.h" |
a7240d1e | 61 | |
5aec3247 MC |
62 | #include <libfdt.h> |
63 | ||
074ca702 BM |
64 | /* CLINT timebase frequency */ |
65 | #define CLINT_TIMEBASE_FREQ 1000000 | |
66 | ||
73261285 | 67 | static const MemMapEntry sifive_u_memmap[] = { |
13b8c354 EH |
68 | [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, |
69 | [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, | |
70 | [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, | |
71 | [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, | |
72 | [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, | |
73 | [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, | |
74 | [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, | |
75 | [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, | |
76 | [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, | |
77 | [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, | |
145b2991 | 78 | [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, |
722f1352 | 79 | [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, |
13b8c354 EH |
80 | [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, |
81 | [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, | |
82 | [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, | |
83 | [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, | |
84 | [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, | |
85 | [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, | |
86 | [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, | |
a7240d1e MC |
87 | }; |
88 | ||
5461c4fe | 89 | #define OTP_SERIAL 1 |
5a7f76a3 AF |
90 | #define GEM_REVISION 0x10070109 |
91 | ||
73261285 | 92 | static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, |
2206ffa6 | 93 | uint64_t mem_size, const char *cmdline, bool is_32_bit) |
a7240d1e | 94 | { |
ecdfe393 | 95 | MachineState *ms = MACHINE(qdev_get_machine()); |
a7240d1e MC |
96 | void *fdt; |
97 | int cpu; | |
98 | uint32_t *cells; | |
99 | char *nodename; | |
5133ed17 | 100 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; |
7b6bb66f | 101 | uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; |
cb53b283 | 102 | static const char * const ethclk_names[2] = { "pclk", "hclk" }; |
7cfbb17f BM |
103 | static const char * const clint_compat[2] = { |
104 | "sifive,clint0", "riscv,clint0" | |
105 | }; | |
60bb5407 BM |
106 | static const char * const plic_compat[2] = { |
107 | "sifive,plic-1.0.0", "riscv,plic0" | |
108 | }; | |
a7240d1e | 109 | |
f2ce39b4 PB |
110 | if (ms->dtb) { |
111 | fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); | |
d5c90cf3 AP |
112 | if (!fdt) { |
113 | error_report("load_device_tree() failed"); | |
114 | exit(1); | |
115 | } | |
116 | goto update_bootargs; | |
117 | } else { | |
118 | fdt = s->fdt = create_device_tree(&s->fdt_size); | |
119 | if (!fdt) { | |
120 | error_report("create_device_tree() failed"); | |
121 | exit(1); | |
122 | } | |
a7240d1e MC |
123 | } |
124 | ||
d372e748 BM |
125 | qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); |
126 | qemu_fdt_setprop_string(fdt, "/", "compatible", | |
127 | "sifive,hifive-unleashed-a00"); | |
a7240d1e MC |
128 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); |
129 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
130 | ||
131 | qemu_fdt_add_subnode(fdt, "/soc"); | |
132 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
2a1a6f6d | 133 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
a7240d1e MC |
134 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
135 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
136 | ||
e1724d09 BM |
137 | hfclk_phandle = phandle++; |
138 | nodename = g_strdup_printf("/hfclk"); | |
139 | qemu_fdt_add_subnode(fdt, nodename); | |
140 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); | |
141 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); | |
142 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
143 | SIFIVE_U_HFCLK_FREQ); | |
144 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
145 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
146 | g_free(nodename); | |
147 | ||
148 | rtcclk_phandle = phandle++; | |
149 | nodename = g_strdup_printf("/rtcclk"); | |
150 | qemu_fdt_add_subnode(fdt, nodename); | |
151 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); | |
152 | qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); | |
153 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
154 | SIFIVE_U_RTCCLK_FREQ); | |
155 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
156 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
157 | g_free(nodename); | |
158 | ||
a7240d1e | 159 | nodename = g_strdup_printf("/memory@%lx", |
13b8c354 | 160 | (long)memmap[SIFIVE_U_DEV_DRAM].base); |
a7240d1e MC |
161 | qemu_fdt_add_subnode(fdt, nodename); |
162 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 | 163 | memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, |
a7240d1e MC |
164 | mem_size >> 32, mem_size); |
165 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
166 | g_free(nodename); | |
167 | ||
168 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
2a8756ed | 169 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
074ca702 | 170 | CLINT_TIMEBASE_FREQ); |
a7240d1e MC |
171 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
172 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
173 | ||
ecdfe393 | 174 | for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { |
382cb439 | 175 | int cpu_phandle = phandle++; |
a7240d1e MC |
176 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
177 | char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
ecdfe393 | 178 | char *isa; |
a7240d1e | 179 | qemu_fdt_add_subnode(fdt, nodename); |
ecdfe393 BM |
180 | /* cpu 0 is the management hart that does not have mmu */ |
181 | if (cpu != 0) { | |
2206ffa6 AF |
182 | if (is_32_bit) { |
183 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); | |
184 | } else { | |
185 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); | |
186 | } | |
ecdfe393 BM |
187 | isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); |
188 | } else { | |
189 | isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); | |
190 | } | |
a7240d1e MC |
191 | qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); |
192 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | |
193 | qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | |
194 | qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | |
195 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | |
196 | qemu_fdt_add_subnode(fdt, intc); | |
382cb439 | 197 | qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); |
a7240d1e MC |
198 | qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); |
199 | qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | |
200 | qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | |
201 | g_free(isa); | |
202 | g_free(intc); | |
203 | g_free(nodename); | |
204 | } | |
205 | ||
ecdfe393 BM |
206 | cells = g_new0(uint32_t, ms->smp.cpus * 4); |
207 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
208 | nodename = |
209 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
210 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
211 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
212 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
213 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
214 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
215 | g_free(nodename); | |
216 | } | |
217 | nodename = g_strdup_printf("/soc/clint@%lx", | |
13b8c354 | 218 | (long)memmap[SIFIVE_U_DEV_CLINT].base); |
a7240d1e | 219 | qemu_fdt_add_subnode(fdt, nodename); |
7cfbb17f BM |
220 | qemu_fdt_setprop_string_array(fdt, nodename, "compatible", |
221 | (char **)&clint_compat, ARRAY_SIZE(clint_compat)); | |
a7240d1e | 222 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
223 | 0x0, memmap[SIFIVE_U_DEV_CLINT].base, |
224 | 0x0, memmap[SIFIVE_U_DEV_CLINT].size); | |
a7240d1e | 225 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", |
ecdfe393 | 226 | cells, ms->smp.cpus * sizeof(uint32_t) * 4); |
a7240d1e MC |
227 | g_free(cells); |
228 | g_free(nodename); | |
229 | ||
ea85f27d | 230 | nodename = g_strdup_printf("/soc/otp@%lx", |
13b8c354 | 231 | (long)memmap[SIFIVE_U_DEV_OTP].base); |
ea85f27d BM |
232 | qemu_fdt_add_subnode(fdt, nodename); |
233 | qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); | |
234 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
235 | 0x0, memmap[SIFIVE_U_DEV_OTP].base, |
236 | 0x0, memmap[SIFIVE_U_DEV_OTP].size); | |
ea85f27d BM |
237 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
238 | "sifive,fu540-c000-otp"); | |
239 | g_free(nodename); | |
240 | ||
af14c840 BM |
241 | prci_phandle = phandle++; |
242 | nodename = g_strdup_printf("/soc/clock-controller@%lx", | |
13b8c354 | 243 | (long)memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 BM |
244 | qemu_fdt_add_subnode(fdt, nodename); |
245 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); | |
246 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); | |
247 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
248 | hfclk_phandle, rtcclk_phandle); | |
249 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
250 | 0x0, memmap[SIFIVE_U_DEV_PRCI].base, |
251 | 0x0, memmap[SIFIVE_U_DEV_PRCI].size); | |
af14c840 BM |
252 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
253 | "sifive,fu540-c000-prci"); | |
254 | g_free(nodename); | |
255 | ||
382cb439 | 256 | plic_phandle = phandle++; |
ecdfe393 BM |
257 | cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); |
258 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
259 | nodename = |
260 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
261 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
ecdfe393 BM |
262 | /* cpu 0 is the management hart that does not have S-mode */ |
263 | if (cpu == 0) { | |
264 | cells[0] = cpu_to_be32(intc_phandle); | |
265 | cells[1] = cpu_to_be32(IRQ_M_EXT); | |
266 | } else { | |
267 | cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); | |
268 | cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); | |
269 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
270 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); | |
271 | } | |
a7240d1e MC |
272 | g_free(nodename); |
273 | } | |
274 | nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | |
13b8c354 | 275 | (long)memmap[SIFIVE_U_DEV_PLIC].base); |
a7240d1e MC |
276 | qemu_fdt_add_subnode(fdt, nodename); |
277 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); | |
60bb5407 BM |
278 | qemu_fdt_setprop_string_array(fdt, nodename, "compatible", |
279 | (char **)&plic_compat, ARRAY_SIZE(plic_compat)); | |
a7240d1e MC |
280 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); |
281 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 282 | cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); |
a7240d1e | 283 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
284 | 0x0, memmap[SIFIVE_U_DEV_PLIC].base, |
285 | 0x0, memmap[SIFIVE_U_DEV_PLIC].size); | |
98ceee7f | 286 | qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); |
04e7edd1 | 287 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); |
a7240d1e MC |
288 | plic_phandle = qemu_fdt_get_phandle(fdt, nodename); |
289 | g_free(cells); | |
290 | g_free(nodename); | |
291 | ||
5133ed17 | 292 | gpio_phandle = phandle++; |
8a88b9f5 | 293 | nodename = g_strdup_printf("/soc/gpio@%lx", |
13b8c354 | 294 | (long)memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 | 295 | qemu_fdt_add_subnode(fdt, nodename); |
5133ed17 | 296 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); |
8a88b9f5 BM |
297 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
298 | prci_phandle, PRCI_CLK_TLCLK); | |
299 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); | |
300 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
301 | qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); | |
302 | qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); | |
303 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
304 | 0x0, memmap[SIFIVE_U_DEV_GPIO].base, |
305 | 0x0, memmap[SIFIVE_U_DEV_GPIO].size); | |
8a88b9f5 BM |
306 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, |
307 | SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, | |
308 | SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, | |
309 | SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, | |
310 | SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, | |
311 | SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); | |
312 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
313 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); | |
314 | g_free(nodename); | |
315 | ||
5133ed17 BM |
316 | nodename = g_strdup_printf("/gpio-restart"); |
317 | qemu_fdt_add_subnode(fdt, nodename); | |
318 | qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); | |
319 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); | |
320 | g_free(nodename); | |
321 | ||
834e027a | 322 | nodename = g_strdup_printf("/soc/dma@%lx", |
13b8c354 | 323 | (long)memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
324 | qemu_fdt_add_subnode(fdt, nodename); |
325 | qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); | |
326 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", | |
327 | SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, | |
328 | SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, | |
329 | SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); | |
330 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
331 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
332 | 0x0, memmap[SIFIVE_U_DEV_PDMA].base, |
333 | 0x0, memmap[SIFIVE_U_DEV_PDMA].size); | |
834e027a BM |
334 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
335 | "sifive,fu540-c000-pdma"); | |
336 | g_free(nodename); | |
337 | ||
6eaf9cf5 | 338 | nodename = g_strdup_printf("/soc/cache-controller@%lx", |
13b8c354 | 339 | (long)memmap[SIFIVE_U_DEV_L2CC].base); |
6eaf9cf5 BM |
340 | qemu_fdt_add_subnode(fdt, nodename); |
341 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
342 | 0x0, memmap[SIFIVE_U_DEV_L2CC].base, |
343 | 0x0, memmap[SIFIVE_U_DEV_L2CC].size); | |
6eaf9cf5 BM |
344 | qemu_fdt_setprop_cells(fdt, nodename, "interrupts", |
345 | SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); | |
346 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
347 | qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); | |
348 | qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); | |
349 | qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); | |
350 | qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); | |
351 | qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); | |
352 | qemu_fdt_setprop_string(fdt, nodename, "compatible", | |
353 | "sifive,fu540-c000-ccache"); | |
354 | g_free(nodename); | |
355 | ||
722f1352 BM |
356 | nodename = g_strdup_printf("/soc/spi@%lx", |
357 | (long)memmap[SIFIVE_U_DEV_QSPI2].base); | |
358 | qemu_fdt_add_subnode(fdt, nodename); | |
359 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
360 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); | |
361 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
362 | prci_phandle, PRCI_CLK_TLCLK); | |
363 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); | |
364 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
365 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
366 | 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, | |
367 | 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); | |
368 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); | |
369 | g_free(nodename); | |
370 | ||
371 | nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", | |
372 | (long)memmap[SIFIVE_U_DEV_QSPI2].base); | |
373 | qemu_fdt_add_subnode(fdt, nodename); | |
374 | qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); | |
375 | qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); | |
376 | qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); | |
377 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); | |
378 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); | |
379 | g_free(nodename); | |
380 | ||
145b2991 BM |
381 | nodename = g_strdup_printf("/soc/spi@%lx", |
382 | (long)memmap[SIFIVE_U_DEV_QSPI0].base); | |
383 | qemu_fdt_add_subnode(fdt, nodename); | |
384 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
385 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); | |
386 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
387 | prci_phandle, PRCI_CLK_TLCLK); | |
388 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); | |
389 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
390 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
391 | 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, | |
392 | 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); | |
393 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); | |
394 | g_free(nodename); | |
395 | ||
396 | nodename = g_strdup_printf("/soc/spi@%lx/flash@0", | |
397 | (long)memmap[SIFIVE_U_DEV_QSPI0].base); | |
398 | qemu_fdt_add_subnode(fdt, nodename); | |
399 | qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); | |
400 | qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); | |
401 | qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); | |
402 | qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); | |
403 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); | |
404 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); | |
405 | g_free(nodename); | |
406 | ||
7b6bb66f | 407 | phy_phandle = phandle++; |
5a7f76a3 | 408 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
13b8c354 | 409 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 410 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f BM |
411 | qemu_fdt_setprop_string(fdt, nodename, "compatible", |
412 | "sifive,fu540-c000-gem"); | |
5a7f76a3 | 413 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
13b8c354 EH |
414 | 0x0, memmap[SIFIVE_U_DEV_GEM].base, |
415 | 0x0, memmap[SIFIVE_U_DEV_GEM].size, | |
416 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, | |
417 | 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); | |
5a7f76a3 AF |
418 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); |
419 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); | |
7b6bb66f | 420 | qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); |
04e7edd1 BM |
421 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
422 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); | |
fe93582c | 423 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
806c64b7 | 424 | prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); |
cb53b283 BM |
425 | qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", |
426 | (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); | |
7b6bb66f BM |
427 | qemu_fdt_setprop(fdt, nodename, "local-mac-address", |
428 | s->soc.gem.conf.macaddr.a, ETH_ALEN); | |
04e7edd1 BM |
429 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
430 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
c3a28b5d BM |
431 | |
432 | qemu_fdt_add_subnode(fdt, "/aliases"); | |
433 | qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); | |
434 | ||
5a7f76a3 AF |
435 | g_free(nodename); |
436 | ||
437 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", | |
13b8c354 | 438 | (long)memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 439 | qemu_fdt_add_subnode(fdt, nodename); |
7b6bb66f | 440 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); |
04e7edd1 | 441 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
5a7f76a3 AF |
442 | g_free(nodename); |
443 | ||
10b43754 AP |
444 | nodename = g_strdup_printf("/soc/serial@%lx", |
445 | (long)memmap[SIFIVE_U_DEV_UART1].base); | |
446 | qemu_fdt_add_subnode(fdt, nodename); | |
447 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
448 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
449 | 0x0, memmap[SIFIVE_U_DEV_UART1].base, | |
450 | 0x0, memmap[SIFIVE_U_DEV_UART1].size); | |
451 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", | |
452 | prci_phandle, PRCI_CLK_TLCLK); | |
453 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
454 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); | |
455 | ||
456 | qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); | |
457 | g_free(nodename); | |
458 | ||
5f7134d3 | 459 | nodename = g_strdup_printf("/soc/serial@%lx", |
13b8c354 | 460 | (long)memmap[SIFIVE_U_DEV_UART0].base); |
a7240d1e MC |
461 | qemu_fdt_add_subnode(fdt, nodename); |
462 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
463 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
13b8c354 EH |
464 | 0x0, memmap[SIFIVE_U_DEV_UART0].base, |
465 | 0x0, memmap[SIFIVE_U_DEV_UART0].size); | |
806c64b7 BM |
466 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
467 | prci_phandle, PRCI_CLK_TLCLK); | |
04e7edd1 BM |
468 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
469 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); | |
a7240d1e MC |
470 | |
471 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
472 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | |
44e6dcd3 GR |
473 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); |
474 | ||
a7240d1e | 475 | g_free(nodename); |
d5c90cf3 AP |
476 | |
477 | update_bootargs: | |
478 | if (cmdline) { | |
479 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
480 | } | |
a7240d1e MC |
481 | } |
482 | ||
5133ed17 BM |
483 | static void sifive_u_machine_reset(void *opaque, int n, int level) |
484 | { | |
485 | /* gpio pin active low triggers reset */ | |
486 | if (!level) { | |
487 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | |
488 | } | |
489 | } | |
490 | ||
523e3464 | 491 | static void sifive_u_machine_init(MachineState *machine) |
a7240d1e | 492 | { |
73261285 | 493 | const MemMapEntry *memmap = sifive_u_memmap; |
687caef1 | 494 | SiFiveUState *s = RISCV_U_MACHINE(machine); |
5aec3247 | 495 | MemoryRegion *system_memory = get_system_memory(); |
a7240d1e | 496 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); |
1b3a2308 | 497 | MemoryRegion *flash0 = g_new(MemoryRegion, 1); |
13b8c354 | 498 | target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
38bc4e34 | 499 | target_ulong firmware_end_addr, kernel_start_addr; |
8590f536 | 500 | uint32_t start_addr_hi32 = 0x00000000; |
5aec3247 | 501 | int i; |
66b1205b | 502 | uint32_t fdt_load_addr; |
dc144fe1 | 503 | uint64_t kernel_entry; |
145b2991 | 504 | DriveInfo *dinfo; |
722f1352 BM |
505 | DeviceState *flash_dev, *sd_dev; |
506 | qemu_irq flash_cs, sd_cs; | |
a7240d1e | 507 | |
2308092b | 508 | /* Initialize SoC */ |
9fc7fc4d | 509 | object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); |
5325cc34 MA |
510 | object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, |
511 | &error_abort); | |
099be035 AF |
512 | object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, |
513 | &error_abort); | |
ce189ab2 | 514 | qdev_realize(DEVICE(&s->soc), NULL, &error_abort); |
a7240d1e MC |
515 | |
516 | /* register RAM */ | |
517 | memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", | |
518 | machine->ram_size, &error_fatal); | |
13b8c354 | 519 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, |
2308092b | 520 | main_mem); |
a7240d1e | 521 | |
1b3a2308 AF |
522 | /* register QSPI0 Flash */ |
523 | memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", | |
13b8c354 EH |
524 | memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); |
525 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, | |
1b3a2308 AF |
526 | flash0); |
527 | ||
5133ed17 BM |
528 | /* register gpio-restart */ |
529 | qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, | |
530 | qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); | |
531 | ||
a7240d1e | 532 | /* create device tree */ |
2206ffa6 | 533 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, |
a8259b53 | 534 | riscv_is_32bit(&s->soc.u_cpus)); |
a7240d1e | 535 | |
17aad9f2 BM |
536 | if (s->start_in_flash) { |
537 | /* | |
538 | * If start_in_flash property is given, assign s->msel to a value | |
539 | * that representing booting from QSPI0 memory-mapped flash. | |
540 | * | |
541 | * This also means that when both start_in_flash and msel properties | |
542 | * are given, start_in_flash takes the precedence over msel. | |
543 | * | |
544 | * Note this is to keep backward compatibility not to break existing | |
545 | * users that use start_in_flash property. | |
546 | */ | |
547 | s->msel = MSEL_MEMMAP_QSPI0_FLASH; | |
548 | } | |
549 | ||
550 | switch (s->msel) { | |
551 | case MSEL_MEMMAP_QSPI0_FLASH: | |
13b8c354 | 552 | start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; |
17aad9f2 BM |
553 | break; |
554 | case MSEL_L2LIM_QSPI0_FLASH: | |
555 | case MSEL_L2LIM_QSPI2_SD: | |
13b8c354 | 556 | start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; |
17aad9f2 BM |
557 | break; |
558 | default: | |
13b8c354 | 559 | start_addr = memmap[SIFIVE_U_DEV_DRAM].base; |
17aad9f2 BM |
560 | break; |
561 | } | |
562 | ||
a8259b53 | 563 | if (riscv_is_32bit(&s->soc.u_cpus)) { |
2206ffa6 | 564 | firmware_end_addr = riscv_find_and_load_firmware(machine, |
a0acd0a1 | 565 | RISCV32_BIOS_BIN, start_addr, NULL); |
2206ffa6 AF |
566 | } else { |
567 | firmware_end_addr = riscv_find_and_load_firmware(machine, | |
a0acd0a1 | 568 | RISCV64_BIOS_BIN, start_addr, NULL); |
2206ffa6 | 569 | } |
b3042223 | 570 | |
a7240d1e | 571 | if (machine->kernel_filename) { |
a8259b53 | 572 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, |
38bc4e34 AF |
573 | firmware_end_addr); |
574 | ||
575 | kernel_entry = riscv_load_kernel(machine->kernel_filename, | |
576 | kernel_start_addr, NULL); | |
0f8d4462 GR |
577 | |
578 | if (machine->initrd_filename) { | |
579 | hwaddr start; | |
580 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | |
581 | machine->ram_size, kernel_entry, | |
582 | &start); | |
9f79638e | 583 | qemu_fdt_setprop_cell(s->fdt, "/chosen", |
0f8d4462 | 584 | "linux,initrd-start", start); |
9f79638e | 585 | qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", |
0f8d4462 GR |
586 | end); |
587 | } | |
dc144fe1 AP |
588 | } else { |
589 | /* | |
590 | * If dynamic firmware is used, it doesn't know where is the next mode | |
591 | * if kernel argument is not set. | |
592 | */ | |
593 | kernel_entry = 0; | |
a7240d1e MC |
594 | } |
595 | ||
66b1205b | 596 | /* Compute the fdt load address in dram */ |
13b8c354 | 597 | fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, |
66b1205b | 598 | machine->ram_size, s->fdt); |
a8259b53 | 599 | if (!riscv_is_32bit(&s->soc.u_cpus)) { |
2206ffa6 AF |
600 | start_addr_hi32 = (uint64_t)start_addr >> 32; |
601 | } | |
66b1205b | 602 | |
a7240d1e | 603 | /* reset vector */ |
623d53cb | 604 | uint32_t reset_vec[12] = { |
17aad9f2 | 605 | s->msel, /* MSEL pin state */ |
dc144fe1 | 606 | 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ |
623d53cb | 607 | 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ |
a7240d1e | 608 | 0xf1402573, /* csrr a0, mhartid */ |
2206ffa6 AF |
609 | 0, |
610 | 0, | |
a7240d1e | 611 | 0x00028067, /* jr t0 */ |
fc41ae23 | 612 | start_addr, /* start: .dword */ |
8590f536 | 613 | start_addr_hi32, |
66b1205b | 614 | fdt_load_addr, /* fdt_laddr: .dword */ |
623d53cb | 615 | 0x00000000, |
66b1205b | 616 | 0x00000000, |
dc144fe1 | 617 | /* fw_dyn: */ |
a7240d1e | 618 | }; |
a8259b53 | 619 | if (riscv_is_32bit(&s->soc.u_cpus)) { |
2206ffa6 AF |
620 | reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ |
621 | reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ | |
622 | } else { | |
623 | reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ | |
624 | reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ | |
625 | } | |
626 | ||
a7240d1e | 627 | |
5aec3247 | 628 | /* copy in the reset vector in little_endian byte order */ |
66b1205b | 629 | for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { |
5aec3247 MC |
630 | reset_vec[i] = cpu_to_le32(reset_vec[i]); |
631 | } | |
632 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
13b8c354 | 633 | memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); |
dc144fe1 | 634 | |
78936771 | 635 | riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, |
13b8c354 | 636 | memmap[SIFIVE_U_DEV_MROM].size, |
dc144fe1 | 637 | sizeof(reset_vec), kernel_entry); |
145b2991 BM |
638 | |
639 | /* Connect an SPI flash to SPI0 */ | |
640 | flash_dev = qdev_new("is25wp256"); | |
641 | dinfo = drive_get_next(IF_MTD); | |
642 | if (dinfo) { | |
643 | qdev_prop_set_drive_err(flash_dev, "drive", | |
644 | blk_by_legacy_dinfo(dinfo), | |
645 | &error_fatal); | |
646 | } | |
647 | qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); | |
648 | ||
649 | flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); | |
650 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); | |
722f1352 BM |
651 | |
652 | /* Connect an SD card to SPI2 */ | |
653 | sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); | |
654 | ||
655 | sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); | |
656 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); | |
2308092b AF |
657 | } |
658 | ||
523e3464 AF |
659 | static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) |
660 | { | |
661 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
662 | ||
663 | return s->start_in_flash; | |
664 | } | |
665 | ||
666 | static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) | |
667 | { | |
668 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
669 | ||
670 | s->start_in_flash = value; | |
671 | } | |
672 | ||
3e9667cd BM |
673 | static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v, |
674 | const char *name, void *opaque, | |
675 | Error **errp) | |
3ca109c3 BM |
676 | { |
677 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
678 | } | |
679 | ||
3e9667cd BM |
680 | static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v, |
681 | const char *name, void *opaque, | |
682 | Error **errp) | |
3ca109c3 BM |
683 | { |
684 | visit_type_uint32(v, name, (uint32_t *)opaque, errp); | |
685 | } | |
686 | ||
523e3464 AF |
687 | static void sifive_u_machine_instance_init(Object *obj) |
688 | { | |
689 | SiFiveUState *s = RISCV_U_MACHINE(obj); | |
690 | ||
691 | s->start_in_flash = false; | |
cfa32630 BM |
692 | s->msel = 0; |
693 | object_property_add(obj, "msel", "uint32", | |
694 | sifive_u_machine_get_uint32_prop, | |
695 | sifive_u_machine_set_uint32_prop, NULL, &s->msel); | |
696 | object_property_set_description(obj, "msel", | |
697 | "Mode Select (MSEL[3:0]) pin state"); | |
698 | ||
3ca109c3 | 699 | s->serial = OTP_SERIAL; |
d2623129 | 700 | object_property_add(obj, "serial", "uint32", |
3e9667cd BM |
701 | sifive_u_machine_get_uint32_prop, |
702 | sifive_u_machine_set_uint32_prop, NULL, &s->serial); | |
7eecec7d | 703 | object_property_set_description(obj, "serial", "Board serial number"); |
523e3464 AF |
704 | } |
705 | ||
706 | static void sifive_u_machine_class_init(ObjectClass *oc, void *data) | |
707 | { | |
708 | MachineClass *mc = MACHINE_CLASS(oc); | |
709 | ||
710 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; | |
711 | mc->init = sifive_u_machine_init; | |
712 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; | |
713 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; | |
1eaada8a | 714 | mc->default_cpu_type = SIFIVE_U_CPU; |
523e3464 | 715 | mc->default_cpus = mc->min_cpus; |
418b473e EH |
716 | |
717 | object_class_property_add_bool(oc, "start-in-flash", | |
718 | sifive_u_machine_get_start_in_flash, | |
719 | sifive_u_machine_set_start_in_flash); | |
720 | object_class_property_set_description(oc, "start-in-flash", | |
721 | "Set on to tell QEMU's ROM to jump to " | |
722 | "flash. Otherwise QEMU will jump to DRAM " | |
723 | "or L2LIM depending on the msel value"); | |
523e3464 AF |
724 | } |
725 | ||
726 | static const TypeInfo sifive_u_machine_typeinfo = { | |
727 | .name = MACHINE_TYPE_NAME("sifive_u"), | |
728 | .parent = TYPE_MACHINE, | |
729 | .class_init = sifive_u_machine_class_init, | |
730 | .instance_init = sifive_u_machine_instance_init, | |
731 | .instance_size = sizeof(SiFiveUState), | |
732 | }; | |
733 | ||
734 | static void sifive_u_machine_init_register_types(void) | |
735 | { | |
736 | type_register_static(&sifive_u_machine_typeinfo); | |
737 | } | |
738 | ||
739 | type_init(sifive_u_machine_init_register_types) | |
740 | ||
139177b1 | 741 | static void sifive_u_soc_instance_init(Object *obj) |
2308092b AF |
742 | { |
743 | SiFiveUSoCState *s = RISCV_U_SOC(obj); | |
744 | ||
9fc7fc4d | 745 | object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
746 | qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); |
747 | ||
db873cc5 MA |
748 | object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, |
749 | TYPE_RISCV_HART_ARRAY); | |
ecdfe393 BM |
750 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); |
751 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); | |
752 | qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); | |
73f6ed97 | 753 | qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); |
ecdfe393 | 754 | |
9fc7fc4d | 755 | object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); |
ecdfe393 BM |
756 | qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); |
757 | ||
db873cc5 MA |
758 | object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, |
759 | TYPE_RISCV_HART_ARRAY); | |
5a7f76a3 | 760 | |
db873cc5 MA |
761 | object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); |
762 | object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); | |
763 | object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); | |
8a88b9f5 | 764 | object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); |
834e027a | 765 | object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); |
145b2991 | 766 | object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); |
722f1352 | 767 | object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); |
2308092b AF |
768 | } |
769 | ||
139177b1 | 770 | static void sifive_u_soc_realize(DeviceState *dev, Error **errp) |
2308092b | 771 | { |
c4473127 | 772 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b | 773 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
73261285 | 774 | const MemMapEntry *memmap = sifive_u_memmap; |
2308092b AF |
775 | MemoryRegion *system_memory = get_system_memory(); |
776 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
a6902ef0 | 777 | MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); |
05446f41 BM |
778 | char *plic_hart_config; |
779 | size_t plic_hart_config_len; | |
5a7f76a3 | 780 | int i; |
5a7f76a3 | 781 | NICInfo *nd = &nd_table[0]; |
2308092b | 782 | |
099be035 AF |
783 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); |
784 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); | |
785 | qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); | |
786 | qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); | |
787 | ||
db873cc5 MA |
788 | sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); |
789 | sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); | |
ecdfe393 BM |
790 | /* |
791 | * The cluster must be realized after the RISC-V hart array container, | |
792 | * as the container's CPU object is only created on realize, and the | |
793 | * CPU must exist and have been parented into the cluster before the | |
794 | * cluster is realized. | |
795 | */ | |
ce189ab2 MA |
796 | qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); |
797 | qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); | |
2308092b AF |
798 | |
799 | /* boot rom */ | |
414c47d2 | 800 | memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", |
13b8c354 EH |
801 | memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); |
802 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, | |
2308092b | 803 | mask_rom); |
a7240d1e | 804 | |
a6902ef0 AF |
805 | /* |
806 | * Add L2-LIM at reset size. | |
807 | * This should be reduced in size as the L2 Cache Controller WayEnable | |
808 | * register is incremented. Unfortunately I don't see a nice (or any) way | |
809 | * to handle reducing or blocking out the L2 LIM while still allowing it | |
810 | * be re returned to all enabled after a reset. For the time being, just | |
811 | * leave it enabled all the time. This won't break anything, but will be | |
812 | * too generous to misbehaving guests. | |
813 | */ | |
814 | memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", | |
13b8c354 EH |
815 | memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); |
816 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, | |
a6902ef0 AF |
817 | l2lim_mem); |
818 | ||
05446f41 | 819 | /* create PLIC hart topology configuration string */ |
c4473127 LX |
820 | plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * |
821 | ms->smp.cpus; | |
05446f41 | 822 | plic_hart_config = g_malloc0(plic_hart_config_len); |
c4473127 | 823 | for (i = 0; i < ms->smp.cpus; i++) { |
05446f41 | 824 | if (i != 0) { |
ef965ce2 BM |
825 | strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, |
826 | plic_hart_config_len); | |
827 | } else { | |
828 | strncat(plic_hart_config, "M", plic_hart_config_len); | |
05446f41 | 829 | } |
05446f41 BM |
830 | plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); |
831 | } | |
832 | ||
a7240d1e | 833 | /* MMIO */ |
13b8c354 | 834 | s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, |
c9270e10 | 835 | plic_hart_config, 0, |
a7240d1e MC |
836 | SIFIVE_U_PLIC_NUM_SOURCES, |
837 | SIFIVE_U_PLIC_NUM_PRIORITIES, | |
838 | SIFIVE_U_PLIC_PRIORITY_BASE, | |
839 | SIFIVE_U_PLIC_PENDING_BASE, | |
840 | SIFIVE_U_PLIC_ENABLE_BASE, | |
841 | SIFIVE_U_PLIC_ENABLE_STRIDE, | |
842 | SIFIVE_U_PLIC_CONTEXT_BASE, | |
843 | SIFIVE_U_PLIC_CONTEXT_STRIDE, | |
13b8c354 | 844 | memmap[SIFIVE_U_DEV_PLIC].size); |
bb8136df | 845 | g_free(plic_hart_config); |
13b8c354 | 846 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, |
647a70a1 | 847 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
13b8c354 | 848 | sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, |
194eef09 | 849 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); |
13b8c354 EH |
850 | sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, |
851 | memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, | |
a47ef6e9 | 852 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, |
074ca702 | 853 | CLINT_TIMEBASE_FREQ, false); |
5a7f76a3 | 854 | |
cbe3a8c5 MA |
855 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { |
856 | return; | |
857 | } | |
13b8c354 | 858 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); |
af14c840 | 859 | |
8a88b9f5 | 860 | qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); |
cbe3a8c5 MA |
861 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
862 | return; | |
863 | } | |
13b8c354 | 864 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); |
8a88b9f5 BM |
865 | |
866 | /* Pass all GPIOs to the SOC layer so they are available to the board */ | |
867 | qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); | |
868 | ||
869 | /* Connect GPIO interrupts to the PLIC */ | |
870 | for (i = 0; i < 16; i++) { | |
871 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, | |
872 | qdev_get_gpio_in(DEVICE(s->plic), | |
873 | SIFIVE_U_GPIO_IRQ0 + i)); | |
834e027a BM |
874 | } |
875 | ||
876 | /* PDMA */ | |
877 | sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); | |
13b8c354 | 878 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); |
834e027a BM |
879 | |
880 | /* Connect PDMA interrupts to the PLIC */ | |
881 | for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { | |
882 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, | |
883 | qdev_get_gpio_in(DEVICE(s->plic), | |
884 | SIFIVE_U_PDMA_IRQ0 + i)); | |
8a88b9f5 BM |
885 | } |
886 | ||
fda5b000 | 887 | qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); |
cbe3a8c5 MA |
888 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { |
889 | return; | |
890 | } | |
13b8c354 | 891 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); |
5461c4fe | 892 | |
7ad36e2e | 893 | /* FIXME use qdev NIC properties instead of nd_table[] */ |
5a7f76a3 AF |
894 | if (nd->used) { |
895 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
896 | qdev_set_nic_properties(DEVICE(&s->gem), nd); | |
897 | } | |
5325cc34 | 898 | object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, |
5a7f76a3 | 899 | &error_abort); |
668f62ec | 900 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { |
5a7f76a3 AF |
901 | return; |
902 | } | |
13b8c354 | 903 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); |
5a7f76a3 | 904 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, |
5874f0a7 | 905 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); |
7b6bb66f BM |
906 | |
907 | create_unimplemented_device("riscv.sifive.u.gem-mgmt", | |
13b8c354 | 908 | memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); |
3eaea6eb BM |
909 | |
910 | create_unimplemented_device("riscv.sifive.u.dmc", | |
13b8c354 | 911 | memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); |
6eaf9cf5 BM |
912 | |
913 | create_unimplemented_device("riscv.sifive.u.l2cc", | |
13b8c354 | 914 | memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); |
145b2991 BM |
915 | |
916 | sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); | |
917 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, | |
918 | memmap[SIFIVE_U_DEV_QSPI0].base); | |
919 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, | |
920 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); | |
722f1352 BM |
921 | sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); |
922 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, | |
923 | memmap[SIFIVE_U_DEV_QSPI2].base); | |
924 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, | |
925 | qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); | |
a7240d1e MC |
926 | } |
927 | ||
139177b1 | 928 | static Property sifive_u_soc_props[] = { |
fda5b000 | 929 | DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), |
099be035 | 930 | DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), |
fda5b000 AF |
931 | DEFINE_PROP_END_OF_LIST() |
932 | }; | |
933 | ||
139177b1 | 934 | static void sifive_u_soc_class_init(ObjectClass *oc, void *data) |
2308092b AF |
935 | { |
936 | DeviceClass *dc = DEVICE_CLASS(oc); | |
937 | ||
139177b1 BM |
938 | device_class_set_props(dc, sifive_u_soc_props); |
939 | dc->realize = sifive_u_soc_realize; | |
2308092b AF |
940 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ |
941 | dc->user_creatable = false; | |
942 | } | |
943 | ||
139177b1 | 944 | static const TypeInfo sifive_u_soc_type_info = { |
2308092b AF |
945 | .name = TYPE_RISCV_U_SOC, |
946 | .parent = TYPE_DEVICE, | |
947 | .instance_size = sizeof(SiFiveUSoCState), | |
139177b1 BM |
948 | .instance_init = sifive_u_soc_instance_init, |
949 | .class_init = sifive_u_soc_class_init, | |
2308092b AF |
950 | }; |
951 | ||
139177b1 | 952 | static void sifive_u_soc_register_types(void) |
2308092b | 953 | { |
139177b1 | 954 | type_register_static(&sifive_u_soc_type_info); |
2308092b AF |
955 | } |
956 | ||
139177b1 | 957 | type_init(sifive_u_soc_register_types) |