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a7240d1e MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017 SiFive, Inc. | |
6 | * | |
7 | * Provides a board compatible with the SiFive Freedom U SDK: | |
8 | * | |
9 | * 0) UART | |
10 | * 1) CLINT (Core Level Interruptor) | |
11 | * 2) PLIC (Platform Level Interrupt Controller) | |
12 | * | |
13 | * This board currently uses a hardcoded devicetree that indicates one hart. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms and conditions of the GNU General Public License, | |
17 | * version 2 or later, as published by the Free Software Foundation. | |
18 | * | |
19 | * This program is distributed in the hope it will be useful, but WITHOUT | |
20 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
21 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
22 | * more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along with | |
25 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
26 | */ | |
27 | ||
28 | #include "qemu/osdep.h" | |
29 | #include "qemu/log.h" | |
30 | #include "qemu/error-report.h" | |
31 | #include "qapi/error.h" | |
a7240d1e MC |
32 | #include "hw/boards.h" |
33 | #include "hw/loader.h" | |
34 | #include "hw/sysbus.h" | |
35 | #include "hw/char/serial.h" | |
36 | #include "target/riscv/cpu.h" | |
37 | #include "hw/riscv/riscv_hart.h" | |
38 | #include "hw/riscv/sifive_plic.h" | |
39 | #include "hw/riscv/sifive_clint.h" | |
40 | #include "hw/riscv/sifive_uart.h" | |
a7240d1e | 41 | #include "hw/riscv/sifive_u.h" |
0ac24d56 | 42 | #include "hw/riscv/boot.h" |
a7240d1e MC |
43 | #include "chardev/char.h" |
44 | #include "sysemu/arch_init.h" | |
45 | #include "sysemu/device_tree.h" | |
46517dd4 | 46 | #include "sysemu/sysemu.h" |
a7240d1e | 47 | #include "exec/address-spaces.h" |
a7240d1e | 48 | |
5aec3247 MC |
49 | #include <libfdt.h> |
50 | ||
fdd1bda4 AF |
51 | #define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" |
52 | ||
a7240d1e MC |
53 | static const struct MemmapEntry { |
54 | hwaddr base; | |
55 | hwaddr size; | |
56 | } sifive_u_memmap[] = { | |
57 | [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, | |
5aec3247 | 58 | [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, |
a7240d1e MC |
59 | [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, |
60 | [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, | |
61 | [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, | |
62 | [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, | |
63 | [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, | |
5a7f76a3 | 64 | [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, |
a7240d1e MC |
65 | }; |
66 | ||
5a7f76a3 AF |
67 | #define GEM_REVISION 0x10070109 |
68 | ||
9f79638e | 69 | static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, |
a7240d1e MC |
70 | uint64_t mem_size, const char *cmdline) |
71 | { | |
72 | void *fdt; | |
73 | int cpu; | |
74 | uint32_t *cells; | |
75 | char *nodename; | |
fe93582c | 76 | char ethclk_names[] = "pclk\0hclk\0tx_clk"; |
382cb439 | 77 | uint32_t plic_phandle, ethclk_phandle, phandle = 1; |
44e6dcd3 | 78 | uint32_t uartclk_phandle; |
a7240d1e MC |
79 | |
80 | fdt = s->fdt = create_device_tree(&s->fdt_size); | |
81 | if (!fdt) { | |
82 | error_report("create_device_tree() failed"); | |
83 | exit(1); | |
84 | } | |
85 | ||
86 | qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); | |
87 | qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); | |
88 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
89 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
90 | ||
91 | qemu_fdt_add_subnode(fdt, "/soc"); | |
92 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
2a1a6f6d | 93 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
a7240d1e MC |
94 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
95 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
96 | ||
97 | nodename = g_strdup_printf("/memory@%lx", | |
98 | (long)memmap[SIFIVE_U_DRAM].base); | |
99 | qemu_fdt_add_subnode(fdt, nodename); | |
100 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
101 | memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, | |
102 | mem_size >> 32, mem_size); | |
103 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
104 | g_free(nodename); | |
105 | ||
106 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
2a8756ed MC |
107 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
108 | SIFIVE_CLINT_TIMEBASE_FREQ); | |
a7240d1e MC |
109 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
110 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
111 | ||
2308092b | 112 | for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { |
382cb439 | 113 | int cpu_phandle = phandle++; |
a7240d1e MC |
114 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
115 | char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
2308092b | 116 | char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); |
a7240d1e | 117 | qemu_fdt_add_subnode(fdt, nodename); |
2a8756ed MC |
118 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", |
119 | SIFIVE_U_CLOCK_FREQ); | |
a7240d1e MC |
120 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); |
121 | qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); | |
122 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | |
123 | qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | |
124 | qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | |
125 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | |
126 | qemu_fdt_add_subnode(fdt, intc); | |
382cb439 | 127 | qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); |
a7240d1e MC |
128 | qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); |
129 | qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | |
130 | qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | |
131 | g_free(isa); | |
132 | g_free(intc); | |
133 | g_free(nodename); | |
134 | } | |
135 | ||
2308092b AF |
136 | cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); |
137 | for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { | |
a7240d1e MC |
138 | nodename = |
139 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
140 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
141 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
142 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
143 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
144 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
145 | g_free(nodename); | |
146 | } | |
147 | nodename = g_strdup_printf("/soc/clint@%lx", | |
148 | (long)memmap[SIFIVE_U_CLINT].base); | |
149 | qemu_fdt_add_subnode(fdt, nodename); | |
150 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); | |
151 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
152 | 0x0, memmap[SIFIVE_U_CLINT].base, | |
153 | 0x0, memmap[SIFIVE_U_CLINT].size); | |
154 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
2308092b | 155 | cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); |
a7240d1e MC |
156 | g_free(cells); |
157 | g_free(nodename); | |
158 | ||
382cb439 | 159 | plic_phandle = phandle++; |
2308092b AF |
160 | cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); |
161 | for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { | |
a7240d1e MC |
162 | nodename = |
163 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
164 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
165 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
166 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); | |
167 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
168 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); | |
169 | g_free(nodename); | |
170 | } | |
171 | nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | |
172 | (long)memmap[SIFIVE_U_PLIC].base); | |
173 | qemu_fdt_add_subnode(fdt, nodename); | |
174 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); | |
175 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); | |
176 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
177 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
2308092b | 178 | cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); |
a7240d1e MC |
179 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
180 | 0x0, memmap[SIFIVE_U_PLIC].base, | |
181 | 0x0, memmap[SIFIVE_U_PLIC].size); | |
98ceee7f | 182 | qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); |
04e7edd1 | 183 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); |
a7240d1e MC |
184 | plic_phandle = qemu_fdt_get_phandle(fdt, nodename); |
185 | g_free(cells); | |
186 | g_free(nodename); | |
187 | ||
382cb439 | 188 | ethclk_phandle = phandle++; |
fe93582c AP |
189 | nodename = g_strdup_printf("/soc/ethclk"); |
190 | qemu_fdt_add_subnode(fdt, nodename); | |
191 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
192 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
193 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
194 | SIFIVE_U_GEM_CLOCK_FREQ); | |
382cb439 | 195 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); |
fe93582c AP |
196 | ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); |
197 | g_free(nodename); | |
198 | ||
5a7f76a3 AF |
199 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
200 | (long)memmap[SIFIVE_U_GEM].base); | |
201 | qemu_fdt_add_subnode(fdt, nodename); | |
202 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); | |
203 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
204 | 0x0, memmap[SIFIVE_U_GEM].base, | |
205 | 0x0, memmap[SIFIVE_U_GEM].size); | |
206 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); | |
207 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); | |
04e7edd1 BM |
208 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
209 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); | |
fe93582c AP |
210 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
211 | ethclk_phandle, ethclk_phandle, ethclk_phandle); | |
04ece4f8 | 212 | qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, |
fe93582c | 213 | sizeof(ethclk_names)); |
04e7edd1 BM |
214 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
215 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
5a7f76a3 AF |
216 | g_free(nodename); |
217 | ||
218 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", | |
219 | (long)memmap[SIFIVE_U_GEM].base); | |
220 | qemu_fdt_add_subnode(fdt, nodename); | |
04e7edd1 | 221 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
5a7f76a3 AF |
222 | g_free(nodename); |
223 | ||
44e6dcd3 GR |
224 | uartclk_phandle = phandle++; |
225 | nodename = g_strdup_printf("/soc/uartclk"); | |
226 | qemu_fdt_add_subnode(fdt, nodename); | |
227 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
228 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
229 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); | |
230 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle); | |
44e6dcd3 GR |
231 | uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename); |
232 | g_free(nodename); | |
233 | ||
bde3ab9a | 234 | nodename = g_strdup_printf("/soc/uart@%lx", |
a7240d1e MC |
235 | (long)memmap[SIFIVE_U_UART0].base); |
236 | qemu_fdt_add_subnode(fdt, nodename); | |
237 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
238 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
239 | 0x0, memmap[SIFIVE_U_UART0].base, | |
240 | 0x0, memmap[SIFIVE_U_UART0].size); | |
04e7edd1 BM |
241 | qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle); |
242 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
243 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); | |
a7240d1e MC |
244 | |
245 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
246 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | |
7c28f4da MC |
247 | if (cmdline) { |
248 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
249 | } | |
44e6dcd3 GR |
250 | |
251 | qemu_fdt_add_subnode(fdt, "/aliases"); | |
252 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); | |
253 | ||
a7240d1e MC |
254 | g_free(nodename); |
255 | } | |
256 | ||
257 | static void riscv_sifive_u_init(MachineState *machine) | |
258 | { | |
259 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
260 | ||
261 | SiFiveUState *s = g_new0(SiFiveUState, 1); | |
5aec3247 | 262 | MemoryRegion *system_memory = get_system_memory(); |
a7240d1e | 263 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); |
5aec3247 | 264 | int i; |
a7240d1e | 265 | |
2308092b | 266 | /* Initialize SoC */ |
4eea9d7d AF |
267 | object_initialize_child(OBJECT(machine), "soc", &s->soc, |
268 | sizeof(s->soc), TYPE_RISCV_U_SOC, | |
269 | &error_abort, NULL); | |
a7240d1e MC |
270 | object_property_set_bool(OBJECT(&s->soc), true, "realized", |
271 | &error_abort); | |
272 | ||
273 | /* register RAM */ | |
274 | memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", | |
275 | machine->ram_size, &error_fatal); | |
5aec3247 | 276 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, |
2308092b | 277 | main_mem); |
a7240d1e MC |
278 | |
279 | /* create device tree */ | |
9f79638e | 280 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); |
a7240d1e | 281 | |
fdd1bda4 AF |
282 | riscv_find_and_load_firmware(machine, BIOS_FILENAME, |
283 | memmap[SIFIVE_U_DRAM].base); | |
b3042223 | 284 | |
a7240d1e | 285 | if (machine->kernel_filename) { |
0f8d4462 GR |
286 | uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); |
287 | ||
288 | if (machine->initrd_filename) { | |
289 | hwaddr start; | |
290 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | |
291 | machine->ram_size, kernel_entry, | |
292 | &start); | |
9f79638e | 293 | qemu_fdt_setprop_cell(s->fdt, "/chosen", |
0f8d4462 | 294 | "linux,initrd-start", start); |
9f79638e | 295 | qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", |
0f8d4462 GR |
296 | end); |
297 | } | |
a7240d1e MC |
298 | } |
299 | ||
300 | /* reset vector */ | |
301 | uint32_t reset_vec[8] = { | |
302 | 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ | |
303 | 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ | |
304 | 0xf1402573, /* csrr a0, mhartid */ | |
305 | #if defined(TARGET_RISCV32) | |
306 | 0x0182a283, /* lw t0, 24(t0) */ | |
307 | #elif defined(TARGET_RISCV64) | |
308 | 0x0182b283, /* ld t0, 24(t0) */ | |
309 | #endif | |
310 | 0x00028067, /* jr t0 */ | |
311 | 0x00000000, | |
312 | memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ | |
313 | 0x00000000, | |
314 | /* dtb: */ | |
315 | }; | |
316 | ||
5aec3247 MC |
317 | /* copy in the reset vector in little_endian byte order */ |
318 | for (i = 0; i < sizeof(reset_vec) >> 2; i++) { | |
319 | reset_vec[i] = cpu_to_le32(reset_vec[i]); | |
320 | } | |
321 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
322 | memmap[SIFIVE_U_MROM].base, &address_space_memory); | |
a7240d1e MC |
323 | |
324 | /* copy in the device tree */ | |
5aec3247 MC |
325 | if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > |
326 | memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { | |
327 | error_report("not enough space to store device-tree"); | |
328 | exit(1); | |
329 | } | |
330 | qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); | |
331 | rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), | |
332 | memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), | |
333 | &address_space_memory); | |
2308092b AF |
334 | } |
335 | ||
336 | static void riscv_sifive_u_soc_init(Object *obj) | |
337 | { | |
c4473127 | 338 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
339 | SiFiveUSoCState *s = RISCV_U_SOC(obj); |
340 | ||
4eea9d7d AF |
341 | object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), |
342 | TYPE_RISCV_HART_ARRAY, &error_abort, NULL); | |
2308092b AF |
343 | object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", |
344 | &error_abort); | |
c4473127 | 345 | object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", |
2308092b | 346 | &error_abort); |
5a7f76a3 | 347 | |
4eea9d7d AF |
348 | sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), |
349 | TYPE_CADENCE_GEM); | |
2308092b AF |
350 | } |
351 | ||
352 | static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) | |
353 | { | |
c4473127 | 354 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
355 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
356 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
357 | MemoryRegion *system_memory = get_system_memory(); | |
358 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
5a7f76a3 | 359 | qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; |
05446f41 BM |
360 | char *plic_hart_config; |
361 | size_t plic_hart_config_len; | |
5a7f76a3 AF |
362 | int i; |
363 | Error *err = NULL; | |
364 | NICInfo *nd = &nd_table[0]; | |
2308092b AF |
365 | |
366 | object_property_set_bool(OBJECT(&s->cpus), true, "realized", | |
367 | &error_abort); | |
368 | ||
369 | /* boot rom */ | |
370 | memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", | |
371 | memmap[SIFIVE_U_MROM].size, &error_fatal); | |
372 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, | |
373 | mask_rom); | |
a7240d1e | 374 | |
05446f41 | 375 | /* create PLIC hart topology configuration string */ |
c4473127 LX |
376 | plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * |
377 | ms->smp.cpus; | |
05446f41 | 378 | plic_hart_config = g_malloc0(plic_hart_config_len); |
c4473127 | 379 | for (i = 0; i < ms->smp.cpus; i++) { |
05446f41 BM |
380 | if (i != 0) { |
381 | strncat(plic_hart_config, ",", plic_hart_config_len); | |
382 | } | |
383 | strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG, | |
384 | plic_hart_config_len); | |
385 | plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); | |
386 | } | |
387 | ||
a7240d1e MC |
388 | /* MMIO */ |
389 | s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, | |
05446f41 | 390 | plic_hart_config, |
a7240d1e MC |
391 | SIFIVE_U_PLIC_NUM_SOURCES, |
392 | SIFIVE_U_PLIC_NUM_PRIORITIES, | |
393 | SIFIVE_U_PLIC_PRIORITY_BASE, | |
394 | SIFIVE_U_PLIC_PENDING_BASE, | |
395 | SIFIVE_U_PLIC_ENABLE_BASE, | |
396 | SIFIVE_U_PLIC_ENABLE_STRIDE, | |
397 | SIFIVE_U_PLIC_CONTEXT_BASE, | |
398 | SIFIVE_U_PLIC_CONTEXT_STRIDE, | |
399 | memmap[SIFIVE_U_PLIC].size); | |
5aec3247 | 400 | sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, |
647a70a1 | 401 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
194eef09 MC |
402 | sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, |
403 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); | |
a7240d1e | 404 | sifive_clint_create(memmap[SIFIVE_U_CLINT].base, |
c4473127 | 405 | memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, |
a7240d1e | 406 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); |
5a7f76a3 AF |
407 | |
408 | for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { | |
409 | plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); | |
410 | } | |
411 | ||
412 | if (nd->used) { | |
413 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
414 | qdev_set_nic_properties(DEVICE(&s->gem), nd); | |
415 | } | |
416 | object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", | |
417 | &error_abort); | |
418 | object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); | |
419 | if (err) { | |
420 | error_propagate(errp, err); | |
421 | return; | |
422 | } | |
423 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); | |
424 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, | |
425 | plic_gpios[SIFIVE_U_GEM_IRQ]); | |
a7240d1e MC |
426 | } |
427 | ||
a7240d1e MC |
428 | static void riscv_sifive_u_machine_init(MachineClass *mc) |
429 | { | |
430 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; | |
431 | mc->init = riscv_sifive_u_init; | |
8b1d0714 AF |
432 | /* The real hardware has 5 CPUs, but one of them is a small embedded power |
433 | * management CPU. | |
434 | */ | |
435 | mc->max_cpus = 4; | |
a7240d1e MC |
436 | } |
437 | ||
438 | DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) | |
2308092b AF |
439 | |
440 | static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) | |
441 | { | |
442 | DeviceClass *dc = DEVICE_CLASS(oc); | |
443 | ||
444 | dc->realize = riscv_sifive_u_soc_realize; | |
445 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ | |
446 | dc->user_creatable = false; | |
447 | } | |
448 | ||
449 | static const TypeInfo riscv_sifive_u_soc_type_info = { | |
450 | .name = TYPE_RISCV_U_SOC, | |
451 | .parent = TYPE_DEVICE, | |
452 | .instance_size = sizeof(SiFiveUSoCState), | |
453 | .instance_init = riscv_sifive_u_soc_init, | |
454 | .class_init = riscv_sifive_u_soc_class_init, | |
455 | }; | |
456 | ||
457 | static void riscv_sifive_u_soc_register_types(void) | |
458 | { | |
459 | type_register_static(&riscv_sifive_u_soc_type_info); | |
460 | } | |
461 | ||
462 | type_init(riscv_sifive_u_soc_register_types) |