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a7240d1e MC |
1 | /* |
2 | * QEMU RISC-V Board Compatible with SiFive Freedom U SDK | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017 SiFive, Inc. | |
6 | * | |
7 | * Provides a board compatible with the SiFive Freedom U SDK: | |
8 | * | |
9 | * 0) UART | |
10 | * 1) CLINT (Core Level Interruptor) | |
11 | * 2) PLIC (Platform Level Interrupt Controller) | |
12 | * | |
f3d47d58 | 13 | * This board currently generates devicetree dynamically that indicates at least |
ecdfe393 | 14 | * two harts and up to five harts. |
a7240d1e MC |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify it | |
17 | * under the terms and conditions of the GNU General Public License, | |
18 | * version 2 or later, as published by the Free Software Foundation. | |
19 | * | |
20 | * This program is distributed in the hope it will be useful, but WITHOUT | |
21 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
22 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
23 | * more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License along with | |
26 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
27 | */ | |
28 | ||
29 | #include "qemu/osdep.h" | |
30 | #include "qemu/log.h" | |
31 | #include "qemu/error-report.h" | |
32 | #include "qapi/error.h" | |
a7240d1e MC |
33 | #include "hw/boards.h" |
34 | #include "hw/loader.h" | |
35 | #include "hw/sysbus.h" | |
36 | #include "hw/char/serial.h" | |
ecdfe393 | 37 | #include "hw/cpu/cluster.h" |
a7240d1e MC |
38 | #include "target/riscv/cpu.h" |
39 | #include "hw/riscv/riscv_hart.h" | |
40 | #include "hw/riscv/sifive_plic.h" | |
41 | #include "hw/riscv/sifive_clint.h" | |
42 | #include "hw/riscv/sifive_uart.h" | |
a7240d1e | 43 | #include "hw/riscv/sifive_u.h" |
0ac24d56 | 44 | #include "hw/riscv/boot.h" |
a7240d1e MC |
45 | #include "chardev/char.h" |
46 | #include "sysemu/arch_init.h" | |
47 | #include "sysemu/device_tree.h" | |
46517dd4 | 48 | #include "sysemu/sysemu.h" |
a7240d1e | 49 | #include "exec/address-spaces.h" |
a7240d1e | 50 | |
5aec3247 MC |
51 | #include <libfdt.h> |
52 | ||
fdd1bda4 AF |
53 | #define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" |
54 | ||
a7240d1e MC |
55 | static const struct MemmapEntry { |
56 | hwaddr base; | |
57 | hwaddr size; | |
58 | } sifive_u_memmap[] = { | |
59 | [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, | |
5aec3247 | 60 | [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, |
a7240d1e MC |
61 | [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, |
62 | [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, | |
63 | [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, | |
64 | [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, | |
65 | [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, | |
5a7f76a3 | 66 | [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, |
a7240d1e MC |
67 | }; |
68 | ||
5a7f76a3 AF |
69 | #define GEM_REVISION 0x10070109 |
70 | ||
9f79638e | 71 | static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, |
a7240d1e MC |
72 | uint64_t mem_size, const char *cmdline) |
73 | { | |
ecdfe393 | 74 | MachineState *ms = MACHINE(qdev_get_machine()); |
a7240d1e MC |
75 | void *fdt; |
76 | int cpu; | |
77 | uint32_t *cells; | |
78 | char *nodename; | |
fe93582c | 79 | char ethclk_names[] = "pclk\0hclk\0tx_clk"; |
382cb439 | 80 | uint32_t plic_phandle, ethclk_phandle, phandle = 1; |
44e6dcd3 | 81 | uint32_t uartclk_phandle; |
a7240d1e MC |
82 | |
83 | fdt = s->fdt = create_device_tree(&s->fdt_size); | |
84 | if (!fdt) { | |
85 | error_report("create_device_tree() failed"); | |
86 | exit(1); | |
87 | } | |
88 | ||
89 | qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); | |
90 | qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); | |
91 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
92 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
93 | ||
94 | qemu_fdt_add_subnode(fdt, "/soc"); | |
95 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
2a1a6f6d | 96 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
a7240d1e MC |
97 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
98 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
99 | ||
100 | nodename = g_strdup_printf("/memory@%lx", | |
101 | (long)memmap[SIFIVE_U_DRAM].base); | |
102 | qemu_fdt_add_subnode(fdt, nodename); | |
103 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
104 | memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, | |
105 | mem_size >> 32, mem_size); | |
106 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | |
107 | g_free(nodename); | |
108 | ||
109 | qemu_fdt_add_subnode(fdt, "/cpus"); | |
2a8756ed MC |
110 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
111 | SIFIVE_CLINT_TIMEBASE_FREQ); | |
a7240d1e MC |
112 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
113 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
114 | ||
ecdfe393 | 115 | for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { |
382cb439 | 116 | int cpu_phandle = phandle++; |
a7240d1e MC |
117 | nodename = g_strdup_printf("/cpus/cpu@%d", cpu); |
118 | char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
ecdfe393 | 119 | char *isa; |
a7240d1e | 120 | qemu_fdt_add_subnode(fdt, nodename); |
2a8756ed MC |
121 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", |
122 | SIFIVE_U_CLOCK_FREQ); | |
ecdfe393 BM |
123 | /* cpu 0 is the management hart that does not have mmu */ |
124 | if (cpu != 0) { | |
125 | qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); | |
126 | isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); | |
127 | } else { | |
128 | isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); | |
129 | } | |
a7240d1e MC |
130 | qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); |
131 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); | |
132 | qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); | |
133 | qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); | |
134 | qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); | |
135 | qemu_fdt_add_subnode(fdt, intc); | |
382cb439 | 136 | qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); |
a7240d1e MC |
137 | qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); |
138 | qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); | |
139 | qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); | |
140 | g_free(isa); | |
141 | g_free(intc); | |
142 | g_free(nodename); | |
143 | } | |
144 | ||
ecdfe393 BM |
145 | cells = g_new0(uint32_t, ms->smp.cpus * 4); |
146 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
147 | nodename = |
148 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
149 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
150 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
151 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
152 | cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
153 | cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
154 | g_free(nodename); | |
155 | } | |
156 | nodename = g_strdup_printf("/soc/clint@%lx", | |
157 | (long)memmap[SIFIVE_U_CLINT].base); | |
158 | qemu_fdt_add_subnode(fdt, nodename); | |
159 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); | |
160 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
161 | 0x0, memmap[SIFIVE_U_CLINT].base, | |
162 | 0x0, memmap[SIFIVE_U_CLINT].size); | |
163 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 164 | cells, ms->smp.cpus * sizeof(uint32_t) * 4); |
a7240d1e MC |
165 | g_free(cells); |
166 | g_free(nodename); | |
167 | ||
382cb439 | 168 | plic_phandle = phandle++; |
ecdfe393 BM |
169 | cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); |
170 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | |
a7240d1e MC |
171 | nodename = |
172 | g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); | |
173 | uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); | |
ecdfe393 BM |
174 | /* cpu 0 is the management hart that does not have S-mode */ |
175 | if (cpu == 0) { | |
176 | cells[0] = cpu_to_be32(intc_phandle); | |
177 | cells[1] = cpu_to_be32(IRQ_M_EXT); | |
178 | } else { | |
179 | cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); | |
180 | cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); | |
181 | cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
182 | cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); | |
183 | } | |
a7240d1e MC |
184 | g_free(nodename); |
185 | } | |
186 | nodename = g_strdup_printf("/soc/interrupt-controller@%lx", | |
187 | (long)memmap[SIFIVE_U_PLIC].base); | |
188 | qemu_fdt_add_subnode(fdt, nodename); | |
189 | qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); | |
190 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); | |
191 | qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); | |
192 | qemu_fdt_setprop(fdt, nodename, "interrupts-extended", | |
ecdfe393 | 193 | cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); |
a7240d1e MC |
194 | qemu_fdt_setprop_cells(fdt, nodename, "reg", |
195 | 0x0, memmap[SIFIVE_U_PLIC].base, | |
196 | 0x0, memmap[SIFIVE_U_PLIC].size); | |
98ceee7f | 197 | qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); |
04e7edd1 | 198 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); |
a7240d1e MC |
199 | plic_phandle = qemu_fdt_get_phandle(fdt, nodename); |
200 | g_free(cells); | |
201 | g_free(nodename); | |
202 | ||
382cb439 | 203 | ethclk_phandle = phandle++; |
fe93582c AP |
204 | nodename = g_strdup_printf("/soc/ethclk"); |
205 | qemu_fdt_add_subnode(fdt, nodename); | |
206 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
207 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
208 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", | |
209 | SIFIVE_U_GEM_CLOCK_FREQ); | |
382cb439 | 210 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); |
fe93582c AP |
211 | ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); |
212 | g_free(nodename); | |
213 | ||
5a7f76a3 AF |
214 | nodename = g_strdup_printf("/soc/ethernet@%lx", |
215 | (long)memmap[SIFIVE_U_GEM].base); | |
216 | qemu_fdt_add_subnode(fdt, nodename); | |
217 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); | |
218 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
219 | 0x0, memmap[SIFIVE_U_GEM].base, | |
220 | 0x0, memmap[SIFIVE_U_GEM].size); | |
221 | qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); | |
222 | qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); | |
04e7edd1 BM |
223 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); |
224 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); | |
fe93582c AP |
225 | qemu_fdt_setprop_cells(fdt, nodename, "clocks", |
226 | ethclk_phandle, ethclk_phandle, ethclk_phandle); | |
04ece4f8 | 227 | qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, |
fe93582c | 228 | sizeof(ethclk_names)); |
04e7edd1 BM |
229 | qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); |
230 | qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); | |
5a7f76a3 AF |
231 | g_free(nodename); |
232 | ||
233 | nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", | |
234 | (long)memmap[SIFIVE_U_GEM].base); | |
235 | qemu_fdt_add_subnode(fdt, nodename); | |
04e7edd1 | 236 | qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); |
5a7f76a3 AF |
237 | g_free(nodename); |
238 | ||
44e6dcd3 GR |
239 | uartclk_phandle = phandle++; |
240 | nodename = g_strdup_printf("/soc/uartclk"); | |
241 | qemu_fdt_add_subnode(fdt, nodename); | |
242 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); | |
243 | qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); | |
244 | qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); | |
245 | qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle); | |
44e6dcd3 GR |
246 | uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename); |
247 | g_free(nodename); | |
248 | ||
bde3ab9a | 249 | nodename = g_strdup_printf("/soc/uart@%lx", |
a7240d1e MC |
250 | (long)memmap[SIFIVE_U_UART0].base); |
251 | qemu_fdt_add_subnode(fdt, nodename); | |
252 | qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); | |
253 | qemu_fdt_setprop_cells(fdt, nodename, "reg", | |
254 | 0x0, memmap[SIFIVE_U_UART0].base, | |
255 | 0x0, memmap[SIFIVE_U_UART0].size); | |
04e7edd1 BM |
256 | qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle); |
257 | qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); | |
258 | qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); | |
a7240d1e MC |
259 | |
260 | qemu_fdt_add_subnode(fdt, "/chosen"); | |
261 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | |
7c28f4da MC |
262 | if (cmdline) { |
263 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | |
264 | } | |
44e6dcd3 GR |
265 | |
266 | qemu_fdt_add_subnode(fdt, "/aliases"); | |
267 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); | |
268 | ||
a7240d1e MC |
269 | g_free(nodename); |
270 | } | |
271 | ||
272 | static void riscv_sifive_u_init(MachineState *machine) | |
273 | { | |
274 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
275 | ||
276 | SiFiveUState *s = g_new0(SiFiveUState, 1); | |
5aec3247 | 277 | MemoryRegion *system_memory = get_system_memory(); |
a7240d1e | 278 | MemoryRegion *main_mem = g_new(MemoryRegion, 1); |
5aec3247 | 279 | int i; |
a7240d1e | 280 | |
2308092b | 281 | /* Initialize SoC */ |
4eea9d7d AF |
282 | object_initialize_child(OBJECT(machine), "soc", &s->soc, |
283 | sizeof(s->soc), TYPE_RISCV_U_SOC, | |
284 | &error_abort, NULL); | |
a7240d1e MC |
285 | object_property_set_bool(OBJECT(&s->soc), true, "realized", |
286 | &error_abort); | |
287 | ||
288 | /* register RAM */ | |
289 | memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", | |
290 | machine->ram_size, &error_fatal); | |
5aec3247 | 291 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, |
2308092b | 292 | main_mem); |
a7240d1e MC |
293 | |
294 | /* create device tree */ | |
9f79638e | 295 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); |
a7240d1e | 296 | |
fdd1bda4 AF |
297 | riscv_find_and_load_firmware(machine, BIOS_FILENAME, |
298 | memmap[SIFIVE_U_DRAM].base); | |
b3042223 | 299 | |
a7240d1e | 300 | if (machine->kernel_filename) { |
0f8d4462 GR |
301 | uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); |
302 | ||
303 | if (machine->initrd_filename) { | |
304 | hwaddr start; | |
305 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | |
306 | machine->ram_size, kernel_entry, | |
307 | &start); | |
9f79638e | 308 | qemu_fdt_setprop_cell(s->fdt, "/chosen", |
0f8d4462 | 309 | "linux,initrd-start", start); |
9f79638e | 310 | qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", |
0f8d4462 GR |
311 | end); |
312 | } | |
a7240d1e MC |
313 | } |
314 | ||
315 | /* reset vector */ | |
316 | uint32_t reset_vec[8] = { | |
317 | 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ | |
318 | 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ | |
319 | 0xf1402573, /* csrr a0, mhartid */ | |
320 | #if defined(TARGET_RISCV32) | |
321 | 0x0182a283, /* lw t0, 24(t0) */ | |
322 | #elif defined(TARGET_RISCV64) | |
323 | 0x0182b283, /* ld t0, 24(t0) */ | |
324 | #endif | |
325 | 0x00028067, /* jr t0 */ | |
326 | 0x00000000, | |
327 | memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ | |
328 | 0x00000000, | |
329 | /* dtb: */ | |
330 | }; | |
331 | ||
5aec3247 MC |
332 | /* copy in the reset vector in little_endian byte order */ |
333 | for (i = 0; i < sizeof(reset_vec) >> 2; i++) { | |
334 | reset_vec[i] = cpu_to_le32(reset_vec[i]); | |
335 | } | |
336 | rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), | |
337 | memmap[SIFIVE_U_MROM].base, &address_space_memory); | |
a7240d1e MC |
338 | |
339 | /* copy in the device tree */ | |
5aec3247 MC |
340 | if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > |
341 | memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { | |
342 | error_report("not enough space to store device-tree"); | |
343 | exit(1); | |
344 | } | |
345 | qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); | |
346 | rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), | |
347 | memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), | |
348 | &address_space_memory); | |
2308092b AF |
349 | } |
350 | ||
351 | static void riscv_sifive_u_soc_init(Object *obj) | |
352 | { | |
c4473127 | 353 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
354 | SiFiveUSoCState *s = RISCV_U_SOC(obj); |
355 | ||
ecdfe393 BM |
356 | object_initialize_child(obj, "e-cluster", &s->e_cluster, |
357 | sizeof(s->e_cluster), TYPE_CPU_CLUSTER, | |
358 | &error_abort, NULL); | |
359 | qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); | |
360 | ||
361 | object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", | |
362 | &s->e_cpus, sizeof(s->e_cpus), | |
363 | TYPE_RISCV_HART_ARRAY, &error_abort, | |
364 | NULL); | |
365 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); | |
366 | qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); | |
367 | qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); | |
368 | ||
369 | object_initialize_child(obj, "u-cluster", &s->u_cluster, | |
370 | sizeof(s->u_cluster), TYPE_CPU_CLUSTER, | |
371 | &error_abort, NULL); | |
372 | qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); | |
373 | ||
374 | object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", | |
375 | &s->u_cpus, sizeof(s->u_cpus), | |
376 | TYPE_RISCV_HART_ARRAY, &error_abort, | |
377 | NULL); | |
378 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); | |
379 | qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); | |
380 | qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); | |
5a7f76a3 | 381 | |
4eea9d7d AF |
382 | sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), |
383 | TYPE_CADENCE_GEM); | |
2308092b AF |
384 | } |
385 | ||
386 | static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) | |
387 | { | |
c4473127 | 388 | MachineState *ms = MACHINE(qdev_get_machine()); |
2308092b AF |
389 | SiFiveUSoCState *s = RISCV_U_SOC(dev); |
390 | const struct MemmapEntry *memmap = sifive_u_memmap; | |
391 | MemoryRegion *system_memory = get_system_memory(); | |
392 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); | |
5a7f76a3 | 393 | qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; |
05446f41 BM |
394 | char *plic_hart_config; |
395 | size_t plic_hart_config_len; | |
5a7f76a3 AF |
396 | int i; |
397 | Error *err = NULL; | |
398 | NICInfo *nd = &nd_table[0]; | |
2308092b | 399 | |
ecdfe393 BM |
400 | object_property_set_bool(OBJECT(&s->e_cpus), true, "realized", |
401 | &error_abort); | |
402 | object_property_set_bool(OBJECT(&s->u_cpus), true, "realized", | |
403 | &error_abort); | |
404 | /* | |
405 | * The cluster must be realized after the RISC-V hart array container, | |
406 | * as the container's CPU object is only created on realize, and the | |
407 | * CPU must exist and have been parented into the cluster before the | |
408 | * cluster is realized. | |
409 | */ | |
410 | object_property_set_bool(OBJECT(&s->e_cluster), true, "realized", | |
411 | &error_abort); | |
412 | object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", | |
2308092b AF |
413 | &error_abort); |
414 | ||
415 | /* boot rom */ | |
416 | memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", | |
417 | memmap[SIFIVE_U_MROM].size, &error_fatal); | |
418 | memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, | |
419 | mask_rom); | |
a7240d1e | 420 | |
05446f41 | 421 | /* create PLIC hart topology configuration string */ |
c4473127 LX |
422 | plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * |
423 | ms->smp.cpus; | |
05446f41 | 424 | plic_hart_config = g_malloc0(plic_hart_config_len); |
c4473127 | 425 | for (i = 0; i < ms->smp.cpus; i++) { |
05446f41 BM |
426 | if (i != 0) { |
427 | strncat(plic_hart_config, ",", plic_hart_config_len); | |
428 | } | |
429 | strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG, | |
430 | plic_hart_config_len); | |
431 | plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); | |
432 | } | |
433 | ||
a7240d1e MC |
434 | /* MMIO */ |
435 | s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, | |
05446f41 | 436 | plic_hart_config, |
a7240d1e MC |
437 | SIFIVE_U_PLIC_NUM_SOURCES, |
438 | SIFIVE_U_PLIC_NUM_PRIORITIES, | |
439 | SIFIVE_U_PLIC_PRIORITY_BASE, | |
440 | SIFIVE_U_PLIC_PENDING_BASE, | |
441 | SIFIVE_U_PLIC_ENABLE_BASE, | |
442 | SIFIVE_U_PLIC_ENABLE_STRIDE, | |
443 | SIFIVE_U_PLIC_CONTEXT_BASE, | |
444 | SIFIVE_U_PLIC_CONTEXT_STRIDE, | |
445 | memmap[SIFIVE_U_PLIC].size); | |
5aec3247 | 446 | sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, |
647a70a1 | 447 | serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); |
194eef09 MC |
448 | sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, |
449 | serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); | |
a7240d1e | 450 | sifive_clint_create(memmap[SIFIVE_U_CLINT].base, |
c4473127 | 451 | memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, |
a7240d1e | 452 | SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); |
5a7f76a3 AF |
453 | |
454 | for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { | |
455 | plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); | |
456 | } | |
457 | ||
458 | if (nd->used) { | |
459 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); | |
460 | qdev_set_nic_properties(DEVICE(&s->gem), nd); | |
461 | } | |
462 | object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", | |
463 | &error_abort); | |
464 | object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); | |
465 | if (err) { | |
466 | error_propagate(errp, err); | |
467 | return; | |
468 | } | |
469 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); | |
470 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, | |
471 | plic_gpios[SIFIVE_U_GEM_IRQ]); | |
a7240d1e MC |
472 | } |
473 | ||
a7240d1e MC |
474 | static void riscv_sifive_u_machine_init(MachineClass *mc) |
475 | { | |
476 | mc->desc = "RISC-V Board compatible with SiFive U SDK"; | |
477 | mc->init = riscv_sifive_u_init; | |
ecdfe393 | 478 | mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; |
f3d47d58 BM |
479 | mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; |
480 | mc->default_cpus = mc->min_cpus; | |
a7240d1e MC |
481 | } |
482 | ||
483 | DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) | |
2308092b AF |
484 | |
485 | static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) | |
486 | { | |
487 | DeviceClass *dc = DEVICE_CLASS(oc); | |
488 | ||
489 | dc->realize = riscv_sifive_u_soc_realize; | |
490 | /* Reason: Uses serial_hds in realize function, thus can't be used twice */ | |
491 | dc->user_creatable = false; | |
492 | } | |
493 | ||
494 | static const TypeInfo riscv_sifive_u_soc_type_info = { | |
495 | .name = TYPE_RISCV_U_SOC, | |
496 | .parent = TYPE_DEVICE, | |
497 | .instance_size = sizeof(SiFiveUSoCState), | |
498 | .instance_init = riscv_sifive_u_soc_init, | |
499 | .class_init = riscv_sifive_u_soc_class_init, | |
500 | }; | |
501 | ||
502 | static void riscv_sifive_u_soc_register_types(void) | |
503 | { | |
504 | type_register_static(&riscv_sifive_u_soc_type_info); | |
505 | } | |
506 | ||
507 | type_init(riscv_sifive_u_soc_register_types) |