[mirror_qemu.git] / hw / riscv / spike.c

/*
 * QEMU RISC-V Spike Board
 *
 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
 * Copyright (c) 2017-2018 SiFive, Inc.
 *
 * This provides a RISC-V Board with the following devices:
 *
 * 0) HTIF Console and Poweroff
 * 1) CLINT (Timer and IPI)
 * 2) PLIC (Platform Level Interrupt Controller)
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_htif.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/spike.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "sysemu/qtest.h"
#include "sysemu/sysemu.h"

#if defined(TARGET_RISCV32)
# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
#else
# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
#endif

static const struct MemmapEntry {
    hwaddr base;
    hwaddr size;
} spike_memmap[] = {
    [SPIKE_MROM] =     {     0x1000,     0xf000 },
    [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
    [SPIKE_DRAM] =     { 0x80000000,        0x0 },
};

static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
    uint64_t mem_size, const char *cmdline)
{
    void *fdt;
    int cpu;
    uint32_t *cells;
    char *nodename;

    fdt = s->fdt = create_device_tree(&s->fdt_size);
    if (!fdt) {
        error_report("create_device_tree() failed");
        exit(1);
    }

    qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
    qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);

    qemu_fdt_add_subnode(fdt, "/htif");
    qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");

    qemu_fdt_add_subnode(fdt, "/soc");
    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);

    nodename = g_strdup_printf("/memory@%lx",
        (long)memmap[SPIKE_DRAM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
        mem_size >> 32, mem_size);
    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
    g_free(nodename);

    qemu_fdt_add_subnode(fdt, "/cpus");
    qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
        SIFIVE_CLINT_TIMEBASE_FREQ);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);

    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
        qemu_fdt_add_subnode(fdt, nodename);
#if defined(TARGET_RISCV32)
        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
#else
        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
#endif
        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
        qemu_fdt_add_subnode(fdt, intc);
        qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
        g_free(isa);
        g_free(intc);
        g_free(nodename);
    }

    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/clint@%lx",
        (long)memmap[SPIKE_CLINT].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[SPIKE_CLINT].base,
        0x0, memmap[SPIKE_CLINT].size);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
    g_free(cells);
    g_free(nodename);

    if (cmdline) {
        qemu_fdt_add_subnode(fdt, "/chosen");
        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
    }
}

static void spike_board_init(MachineState *machine)
{
    const struct MemmapEntry *memmap = spike_memmap;

    SpikeState *s = g_new0(SpikeState, 1);
    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
    unsigned int smp_cpus = machine->smp.cpus;
    uint32_t fdt_load_addr;
    uint64_t kernel_entry;

    /* Initialize SOC */
    object_initialize_child(OBJECT(machine), "soc", &s->soc,
                            TYPE_RISCV_HART_ARRAY);
    object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
                            &error_abort);
    object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
                            &error_abort);
    sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);

    /* register system main memory (actual RAM) */
    memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
                           machine->ram_size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
        main_mem);

    /* create device tree */
    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);

    /* boot rom */
    memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
                           memmap[SPIKE_MROM].size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
                                mask_rom);

    riscv_find_and_load_firmware(machine, BIOS_FILENAME,
                                 memmap[SPIKE_DRAM].base,
                                 htif_symbol_callback);

    if (machine->kernel_filename) {
        kernel_entry = riscv_load_kernel(machine->kernel_filename,
                                         htif_symbol_callback);

        if (machine->initrd_filename) {
            hwaddr start;
            hwaddr end = riscv_load_initrd(machine->initrd_filename,
                                           machine->ram_size, kernel_entry,
                                           &start);
            qemu_fdt_setprop_cell(s->fdt, "/chosen",
                                  "linux,initrd-start", start);
            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
                                  end);
        }
    } else {
       /*
        * If dynamic firmware is used, it doesn't know where is the next mode
        * if kernel argument is not set.
        */
        kernel_entry = 0;
    }

    /* Compute the fdt load address in dram */
    fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
                                   machine->ram_size, s->fdt);
    /* load the reset vector */
    riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
                              memmap[SPIKE_MROM].size, kernel_entry,
                              fdt_load_addr, s->fdt);

    /* initialize HTIF using symbols found in load_kernel */
    htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));

    /* Core Local Interruptor (timer and IPI) */
    sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
        smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
        false);
}

static void spike_machine_init(MachineClass *mc)
{
    mc->desc = "RISC-V Spike Board";
    mc->init = spike_board_init;
    mc->max_cpus = 8;
    mc->is_default = true;
    mc->default_cpu_type = SPIKE_V1_10_0_CPU;
}

DEFINE_MACHINE("spike", spike_machine_init)
Commit	Line	Data
5b4beba1 MC	1	/*
	2	* QEMU RISC-V Spike Board
	3	*
	4	* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
	5	* Copyright (c) 2017-2018 SiFive, Inc.
	6	*
	7	* This provides a RISC-V Board with the following devices:
	8	*
	9	* 0) HTIF Console and Poweroff
	10	* 1) CLINT (Timer and IPI)
	11	* 2) PLIC (Platform Level Interrupt Controller)
	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms and conditions of the GNU General Public License,
	15	* version 2 or later, as published by the Free Software Foundation.
	16	*
	17	* This program is distributed in the hope it will be useful, but WITHOUT
	18	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	19	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	20	* more details.
	21	*
	22	* You should have received a copy of the GNU General Public License along with
	23	* this program. If not, see <http://www.gnu.org/licenses/>.
	24	*/
	25
	26	#include "qemu/osdep.h"
	27	#include "qemu/log.h"
	28	#include "qemu/error-report.h"
	29	#include "qapi/error.h"
5b4beba1 MC	30	#include "hw/boards.h"
	31	#include "hw/loader.h"
	32	#include "hw/sysbus.h"
	33	#include "target/riscv/cpu.h"
	34	#include "hw/riscv/riscv_htif.h"
	35	#include "hw/riscv/riscv_hart.h"
	36	#include "hw/riscv/sifive_clint.h"
	37	#include "hw/riscv/spike.h"
0ac24d56	38	#include "hw/riscv/boot.h"
5b4beba1 MC	39	#include "chardev/char.h"
	40	#include "sysemu/arch_init.h"
	41	#include "sysemu/device_tree.h"
cd69e3a6	42	#include "sysemu/qtest.h"
46517dd4	43	#include "sysemu/sysemu.h"
5aec3247	44
5b8a9863 AP	45	#if defined(TARGET_RISCV32)
	46	# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
	47	#else
	48	# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
	49	#endif
	50
5b4beba1 MC	51	static const struct MemmapEntry {
	52	hwaddr base;
	53	hwaddr size;
	54	} spike_memmap[] = {
9eb8b14a	55	[SPIKE_MROM] = { 0x1000, 0xf000 },
5b4beba1 MC	56	[SPIKE_CLINT] = { 0x2000000, 0x10000 },
	57	[SPIKE_DRAM] = { 0x80000000, 0x0 },
	58	};
	59
5b4beba1 MC	60	static void create_fdt(SpikeState s, const struct MemmapEntry memmap,
	61	uint64_t mem_size, const char *cmdline)
	62	{
	63	void *fdt;
	64	int cpu;
	65	uint32_t *cells;
	66	char *nodename;
	67
	68	fdt = s->fdt = create_device_tree(&s->fdt_size);
	69	if (!fdt) {
	70	error_report("create_device_tree() failed");
	71	exit(1);
	72	}
	73
	74	qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
	75	qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
	76	qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
	77	qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
	78
	79	qemu_fdt_add_subnode(fdt, "/htif");
	80	qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
	81
	82	qemu_fdt_add_subnode(fdt, "/soc");
	83	qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
117caacf	84	qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
5b4beba1 MC	85	qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
	86	qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
	87
	88	nodename = g_strdup_printf("/memory@%lx",
	89	(long)memmap[SPIKE_DRAM].base);
	90	qemu_fdt_add_subnode(fdt, nodename);
	91	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	92	memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
	93	mem_size >> 32, mem_size);
	94	qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
	95	g_free(nodename);
	96
	97	qemu_fdt_add_subnode(fdt, "/cpus");
2a8756ed MC	98	qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
2a8756ed MC	99	SIFIVE_CLINT_TIMEBASE_FREQ);
5b4beba1 MC	100	qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
	101	qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
	102
	103	for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
	104	nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
	105	char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	106	char *isa = riscv_isa_string(&s->soc.harts[cpu]);
	107	qemu_fdt_add_subnode(fdt, nodename);
e883e992 BM	108	#if defined(TARGET_RISCV32)
	109	qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
	110	#else
5b4beba1	111	qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
e883e992	112	#endif
5b4beba1 MC	113	qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
	114	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
	115	qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
	116	qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
	117	qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
	118	qemu_fdt_add_subnode(fdt, intc);
	119	qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
5b4beba1 MC	120	qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
	121	qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
	122	qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
	123	g_free(isa);
	124	g_free(intc);
	125	g_free(nodename);
	126	}
	127
	128	cells = g_new0(uint32_t, s->soc.num_harts * 4);
	129	for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
	130	nodename =
	131	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	132	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	133	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	134	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
	135	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	136	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
	137	g_free(nodename);
	138	}
	139	nodename = g_strdup_printf("/soc/clint@%lx",
	140	(long)memmap[SPIKE_CLINT].base);
	141	qemu_fdt_add_subnode(fdt, nodename);
	142	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
	143	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	144	0x0, memmap[SPIKE_CLINT].base,
	145	0x0, memmap[SPIKE_CLINT].size);
	146	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
	147	cells, s->soc.num_harts * sizeof(uint32_t) * 4);
	148	g_free(cells);
	149	g_free(nodename);
	150
7c28f4da MC	151	if (cmdline) {
	152	qemu_fdt_add_subnode(fdt, "/chosen");
	153	qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
	154	}
cd69e3a6 AF	155	}
	156
	157	static void spike_board_init(MachineState *machine)
	158	{
	159	const struct MemmapEntry *memmap = spike_memmap;
	160
	161	SpikeState *s = g_new0(SpikeState, 1);
	162	MemoryRegion *system_memory = get_system_memory();
	163	MemoryRegion *main_mem = g_new(MemoryRegion, 1);
	164	MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
c4473127	165	unsigned int smp_cpus = machine->smp.cpus;
66b1205b	166	uint32_t fdt_load_addr;
dc144fe1	167	uint64_t kernel_entry;
cd69e3a6 AF	168
cd69e3a6 AF	169	/* Initialize SOC */
0074fce6 MA	170	object_initialize_child(OBJECT(machine), "soc", &s->soc,
0074fce6 MA	171	TYPE_RISCV_HART_ARRAY);
5325cc34	172	object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
cd69e3a6	173	&error_abort);
5325cc34	174	object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
cd69e3a6	175	&error_abort);
0074fce6	176	sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
cd69e3a6 AF	177
	178	/* register system main memory (actual RAM) */
	179	memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
	180	machine->ram_size, &error_fatal);
	181	memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
	182	main_mem);
	183
	184	/* create device tree */
	185	create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
	186
	187	/* boot rom */
	188	memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
	189	memmap[SPIKE_MROM].size, &error_fatal);
	190	memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
	191	mask_rom);
	192
5b8a9863 AP	193	riscv_find_and_load_firmware(machine, BIOS_FILENAME,
	194	memmap[SPIKE_DRAM].base,
	195	htif_symbol_callback);
	196
cd69e3a6	197	if (machine->kernel_filename) {
dc144fe1 AP	198	kernel_entry = riscv_load_kernel(machine->kernel_filename,
dc144fe1 AP	199	htif_symbol_callback);
5b8a9863 AP	200
	201	if (machine->initrd_filename) {
	202	hwaddr start;
	203	hwaddr end = riscv_load_initrd(machine->initrd_filename,
	204	machine->ram_size, kernel_entry,
	205	&start);
	206	qemu_fdt_setprop_cell(s->fdt, "/chosen",
	207	"linux,initrd-start", start);
	208	qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
	209	end);
	210	}
dc144fe1 AP	211	} else {
	212	/*
	213	* If dynamic firmware is used, it doesn't know where is the next mode
	214	* if kernel argument is not set.
	215	*/
	216	kernel_entry = 0;
cd69e3a6 AF	217	}
cd69e3a6 AF	218
66b1205b AP	219	/* Compute the fdt load address in dram */
	220	fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
	221	machine->ram_size, s->fdt);
43cf723a AP	222	/* load the reset vector */
43cf723a AP	223	riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
dc144fe1	224	memmap[SPIKE_MROM].size, kernel_entry,
66b1205b	225	fdt_load_addr, s->fdt);
cd69e3a6 AF	226
	227	/* initialize HTIF using symbols found in load_kernel */
	228	htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
	229
	230	/* Core Local Interruptor (timer and IPI) */
	231	sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
5f3616cc AP	232	smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
5f3616cc AP	233	false);
cd69e3a6	234	}
5b4beba1	235
cd69e3a6 AF	236	static void spike_machine_init(MachineClass *mc)
	237	{
	238	mc->desc = "RISC-V Spike Board";
	239	mc->init = spike_board_init;
31e6d704	240	mc->max_cpus = 8;
ea0ac7f6	241	mc->is_default = true;
cd69e3a6	242	mc->default_cpu_type = SPIKE_V1_10_0_CPU;
5b4beba1 MC	243	}
5b4beba1 MC	244
cd69e3a6	245	DEFINE_MACHINE("spike", spike_machine_init)