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5b4beba1 MC |
1 | /* |
2 | * QEMU RISC-V Spike Board | |
3 | * | |
4 | * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu | |
5 | * Copyright (c) 2017-2018 SiFive, Inc. | |
6 | * | |
7 | * This provides a RISC-V Board with the following devices: | |
8 | * | |
9 | * 0) HTIF Console and Poweroff | |
10 | * 1) CLINT (Timer and IPI) | |
5b4beba1 MC |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms and conditions of the GNU General Public License, | |
14 | * version 2 or later, as published by the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along with | |
22 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | */ | |
24 | ||
25 | #include "qemu/osdep.h" | |
5b4beba1 MC |
26 | #include "qemu/error-report.h" |
27 | #include "qapi/error.h" | |
5b4beba1 MC |
28 | #include "hw/boards.h" |
29 | #include "hw/loader.h" | |
30 | #include "hw/sysbus.h" | |
31 | #include "target/riscv/cpu.h" | |
5b4beba1 | 32 | #include "hw/riscv/riscv_hart.h" |
5b4beba1 | 33 | #include "hw/riscv/spike.h" |
0ac24d56 | 34 | #include "hw/riscv/boot.h" |
a7172791 | 35 | #include "hw/riscv/numa.h" |
70eb9f9c | 36 | #include "hw/char/riscv_htif.h" |
cc63a182 | 37 | #include "hw/intc/riscv_aclint.h" |
5b4beba1 | 38 | #include "chardev/char.h" |
5b4beba1 | 39 | #include "sysemu/device_tree.h" |
46517dd4 | 40 | #include "sysemu/sysemu.h" |
5aec3247 | 41 | |
719b718c DHB |
42 | #include <libfdt.h> |
43 | ||
73261285 | 44 | static const MemMapEntry spike_memmap[] = { |
9eb8b14a | 45 | [SPIKE_MROM] = { 0x1000, 0xf000 }, |
8d8897ac | 46 | [SPIKE_HTIF] = { 0x1000000, 0x1000 }, |
5b4beba1 MC |
47 | [SPIKE_CLINT] = { 0x2000000, 0x10000 }, |
48 | [SPIKE_DRAM] = { 0x80000000, 0x0 }, | |
49 | }; | |
50 | ||
73261285 | 51 | static void create_fdt(SpikeState *s, const MemMapEntry *memmap, |
bd62c13e | 52 | uint64_t mem_size, const char *cmdline, bool is_32_bit) |
5b4beba1 MC |
53 | { |
54 | void *fdt; | |
a7172791 AP |
55 | uint64_t addr, size; |
56 | unsigned long clint_addr; | |
57 | int cpu, socket; | |
58 | MachineState *mc = MACHINE(s); | |
59 | uint32_t *clint_cells; | |
60 | uint32_t cpu_phandle, intc_phandle, phandle = 1; | |
61 | char *name, *mem_name, *clint_name, *clust_name; | |
62 | char *core_name, *cpu_name, *intc_name; | |
7cfbb17f BM |
63 | static const char * const clint_compat[2] = { |
64 | "sifive,clint0", "riscv,clint0" | |
65 | }; | |
5b4beba1 MC |
66 | |
67 | fdt = s->fdt = create_device_tree(&s->fdt_size); | |
68 | if (!fdt) { | |
69 | error_report("create_device_tree() failed"); | |
70 | exit(1); | |
71 | } | |
72 | ||
73 | qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); | |
74 | qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); | |
75 | qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); | |
76 | qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); | |
77 | ||
78 | qemu_fdt_add_subnode(fdt, "/htif"); | |
79 | qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); | |
8d8897ac AP |
80 | if (!htif_uses_elf_symbols()) { |
81 | qemu_fdt_setprop_cells(fdt, "/htif", "reg", | |
82 | 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); | |
83 | } | |
5b4beba1 MC |
84 | |
85 | qemu_fdt_add_subnode(fdt, "/soc"); | |
86 | qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); | |
117caacf | 87 | qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); |
5b4beba1 MC |
88 | qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); |
89 | qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); | |
90 | ||
5b4beba1 | 91 | qemu_fdt_add_subnode(fdt, "/cpus"); |
2a8756ed | 92 | qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", |
b8fb878a | 93 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); |
5b4beba1 MC |
94 | qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); |
95 | qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); | |
a7172791 AP |
96 | qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); |
97 | ||
98 | for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { | |
99 | clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); | |
100 | qemu_fdt_add_subnode(fdt, clust_name); | |
101 | ||
102 | clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); | |
5b4beba1 | 103 | |
a7172791 AP |
104 | for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { |
105 | cpu_phandle = phandle++; | |
106 | ||
107 | cpu_name = g_strdup_printf("/cpus/cpu@%d", | |
108 | s->soc[socket].hartid_base + cpu); | |
109 | qemu_fdt_add_subnode(fdt, cpu_name); | |
bd62c13e AF |
110 | if (is_32_bit) { |
111 | qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); | |
112 | } else { | |
113 | qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); | |
114 | } | |
a7172791 AP |
115 | name = riscv_isa_string(&s->soc[socket].harts[cpu]); |
116 | qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); | |
117 | g_free(name); | |
118 | qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); | |
119 | qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); | |
120 | qemu_fdt_setprop_cell(fdt, cpu_name, "reg", | |
121 | s->soc[socket].hartid_base + cpu); | |
122 | qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); | |
123 | riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); | |
124 | qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); | |
5b4beba1 | 125 | |
a7172791 AP |
126 | intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); |
127 | qemu_fdt_add_subnode(fdt, intc_name); | |
128 | intc_phandle = phandle++; | |
129 | qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); | |
130 | qemu_fdt_setprop_string(fdt, intc_name, "compatible", | |
131 | "riscv,cpu-intc"); | |
132 | qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); | |
133 | qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); | |
134 | ||
135 | clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); | |
136 | clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); | |
137 | clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); | |
138 | clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); | |
139 | ||
140 | core_name = g_strdup_printf("%s/core%d", clust_name, cpu); | |
141 | qemu_fdt_add_subnode(fdt, core_name); | |
142 | qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); | |
143 | ||
144 | g_free(core_name); | |
145 | g_free(intc_name); | |
146 | g_free(cpu_name); | |
147 | } | |
148 | ||
149 | addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); | |
150 | size = riscv_socket_mem_size(mc, socket); | |
151 | mem_name = g_strdup_printf("/memory@%lx", (long)addr); | |
152 | qemu_fdt_add_subnode(fdt, mem_name); | |
153 | qemu_fdt_setprop_cells(fdt, mem_name, "reg", | |
154 | addr >> 32, addr, size >> 32, size); | |
155 | qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); | |
156 | riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); | |
157 | g_free(mem_name); | |
158 | ||
159 | clint_addr = memmap[SPIKE_CLINT].base + | |
160 | (memmap[SPIKE_CLINT].size * socket); | |
161 | clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); | |
162 | qemu_fdt_add_subnode(fdt, clint_name); | |
7cfbb17f BM |
163 | qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", |
164 | (char **)&clint_compat, ARRAY_SIZE(clint_compat)); | |
a7172791 AP |
165 | qemu_fdt_setprop_cells(fdt, clint_name, "reg", |
166 | 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); | |
167 | qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", | |
168 | clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); | |
169 | riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); | |
170 | ||
171 | g_free(clint_name); | |
172 | g_free(clint_cells); | |
173 | g_free(clust_name); | |
5b4beba1 | 174 | } |
a7172791 AP |
175 | |
176 | riscv_socket_fdt_write_distance_matrix(mc, fdt); | |
5b4beba1 | 177 | |
6d3b9c02 BM |
178 | qemu_fdt_add_subnode(fdt, "/chosen"); |
179 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); | |
180 | ||
58303fc0 | 181 | if (cmdline && *cmdline) { |
7c28f4da MC |
182 | qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); |
183 | } | |
cd69e3a6 AF |
184 | } |
185 | ||
186 | static void spike_board_init(MachineState *machine) | |
187 | { | |
73261285 | 188 | const MemMapEntry *memmap = spike_memmap; |
a7172791 | 189 | SpikeState *s = SPIKE_MACHINE(machine); |
cd69e3a6 | 190 | MemoryRegion *system_memory = get_system_memory(); |
cd69e3a6 | 191 | MemoryRegion *mask_rom = g_new(MemoryRegion, 1); |
38bc4e34 | 192 | target_ulong firmware_end_addr, kernel_start_addr; |
66b1205b | 193 | uint32_t fdt_load_addr; |
dc144fe1 | 194 | uint64_t kernel_entry; |
a7172791 AP |
195 | char *soc_name; |
196 | int i, base_hartid, hart_count; | |
cd69e3a6 | 197 | |
a7172791 AP |
198 | /* Check socket count limit */ |
199 | if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { | |
200 | error_report("number of sockets/nodes should be less than %d", | |
201 | SPIKE_SOCKETS_MAX); | |
202 | exit(1); | |
203 | } | |
204 | ||
205 | /* Initialize sockets */ | |
206 | for (i = 0; i < riscv_socket_count(machine); i++) { | |
207 | if (!riscv_socket_check_hartids(machine, i)) { | |
208 | error_report("discontinuous hartids in socket%d", i); | |
209 | exit(1); | |
210 | } | |
211 | ||
212 | base_hartid = riscv_socket_first_hartid(machine, i); | |
213 | if (base_hartid < 0) { | |
214 | error_report("can't find hartid base for socket%d", i); | |
215 | exit(1); | |
216 | } | |
217 | ||
218 | hart_count = riscv_socket_hart_count(machine, i); | |
219 | if (hart_count < 0) { | |
220 | error_report("can't find hart count for socket%d", i); | |
221 | exit(1); | |
222 | } | |
223 | ||
224 | soc_name = g_strdup_printf("soc%d", i); | |
225 | object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], | |
226 | TYPE_RISCV_HART_ARRAY); | |
227 | g_free(soc_name); | |
228 | object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", | |
229 | machine->cpu_type, &error_abort); | |
230 | object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", | |
231 | base_hartid, &error_abort); | |
232 | object_property_set_int(OBJECT(&s->soc[i]), "num-harts", | |
233 | hart_count, &error_abort); | |
4bcfc391 | 234 | sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); |
a7172791 AP |
235 | |
236 | /* Core Local Interruptor (timer and IPI) for each socket */ | |
b8fb878a | 237 | riscv_aclint_swi_create( |
a7172791 | 238 | memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, |
b8fb878a AP |
239 | base_hartid, hart_count, false); |
240 | riscv_aclint_mtimer_create( | |
241 | memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size + | |
242 | RISCV_ACLINT_SWI_SIZE, | |
243 | RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, | |
244 | RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, | |
245 | RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); | |
a7172791 | 246 | } |
cd69e3a6 AF |
247 | |
248 | /* register system main memory (actual RAM) */ | |
cd69e3a6 | 249 | memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, |
11ec06f9 | 250 | machine->ram); |
cd69e3a6 | 251 | |
cd69e3a6 AF |
252 | /* boot rom */ |
253 | memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", | |
254 | memmap[SPIKE_MROM].size, &error_fatal); | |
255 | memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, | |
256 | mask_rom); | |
257 | ||
bd62c13e AF |
258 | /* |
259 | * Not like other RISC-V machines that use plain binary bios images, | |
260 | * keeping ELF files here was intentional because BIN files don't work | |
261 | * for the Spike machine as HTIF emulation depends on ELF parsing. | |
262 | */ | |
a8259b53 | 263 | if (riscv_is_32bit(&s->soc[0])) { |
bd62c13e | 264 | firmware_end_addr = riscv_find_and_load_firmware(machine, |
092dc6df | 265 | RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base, |
bd62c13e AF |
266 | htif_symbol_callback); |
267 | } else { | |
268 | firmware_end_addr = riscv_find_and_load_firmware(machine, | |
092dc6df | 269 | RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base, |
bd62c13e AF |
270 | htif_symbol_callback); |
271 | } | |
5b8a9863 | 272 | |
8d8897ac | 273 | /* Load kernel */ |
cd69e3a6 | 274 | if (machine->kernel_filename) { |
a8259b53 | 275 | kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], |
38bc4e34 AF |
276 | firmware_end_addr); |
277 | ||
dc144fe1 | 278 | kernel_entry = riscv_load_kernel(machine->kernel_filename, |
38bc4e34 | 279 | kernel_start_addr, |
dc144fe1 | 280 | htif_symbol_callback); |
dc144fe1 AP |
281 | } else { |
282 | /* | |
283 | * If dynamic firmware is used, it doesn't know where is the next mode | |
284 | * if kernel argument is not set. | |
285 | */ | |
286 | kernel_entry = 0; | |
cd69e3a6 AF |
287 | } |
288 | ||
8d8897ac AP |
289 | /* Create device tree */ |
290 | create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, | |
291 | riscv_is_32bit(&s->soc[0])); | |
292 | ||
293 | /* Load initrd */ | |
294 | if (machine->kernel_filename && machine->initrd_filename) { | |
295 | hwaddr start; | |
296 | hwaddr end = riscv_load_initrd(machine->initrd_filename, | |
297 | machine->ram_size, kernel_entry, | |
298 | &start); | |
299 | qemu_fdt_setprop_cell(s->fdt, "/chosen", | |
300 | "linux,initrd-start", start); | |
301 | qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", | |
302 | end); | |
303 | } | |
304 | ||
66b1205b AP |
305 | /* Compute the fdt load address in dram */ |
306 | fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, | |
307 | machine->ram_size, s->fdt); | |
719b718c DHB |
308 | |
309 | /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ | |
310 | machine->fdt = s->fdt; | |
311 | ||
43cf723a | 312 | /* load the reset vector */ |
a8259b53 | 313 | riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, |
78936771 | 314 | memmap[SPIKE_MROM].base, |
dc144fe1 | 315 | memmap[SPIKE_MROM].size, kernel_entry, |
6934f15b | 316 | fdt_load_addr); |
cd69e3a6 AF |
317 | |
318 | /* initialize HTIF using symbols found in load_kernel */ | |
a7172791 | 319 | htif_mm_init(system_memory, mask_rom, |
8d8897ac AP |
320 | &s->soc[0].harts[0].env, serial_hd(0), |
321 | memmap[SPIKE_HTIF].base); | |
a7172791 | 322 | } |
cd69e3a6 | 323 | |
a7172791 AP |
324 | static void spike_machine_instance_init(Object *obj) |
325 | { | |
cd69e3a6 | 326 | } |
5b4beba1 | 327 | |
a7172791 | 328 | static void spike_machine_class_init(ObjectClass *oc, void *data) |
cd69e3a6 | 329 | { |
a7172791 AP |
330 | MachineClass *mc = MACHINE_CLASS(oc); |
331 | ||
332 | mc->desc = "RISC-V Spike board"; | |
cd69e3a6 | 333 | mc->init = spike_board_init; |
a7172791 | 334 | mc->max_cpus = SPIKE_CPUS_MAX; |
ea0ac7f6 | 335 | mc->is_default = true; |
dc4d4aae | 336 | mc->default_cpu_type = TYPE_RISCV_CPU_BASE; |
a7172791 AP |
337 | mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; |
338 | mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; | |
339 | mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; | |
340 | mc->numa_mem_supported = true; | |
11ec06f9 | 341 | mc->default_ram_id = "riscv.spike.ram"; |
a7172791 AP |
342 | } |
343 | ||
344 | static const TypeInfo spike_machine_typeinfo = { | |
345 | .name = MACHINE_TYPE_NAME("spike"), | |
346 | .parent = TYPE_MACHINE, | |
347 | .class_init = spike_machine_class_init, | |
348 | .instance_init = spike_machine_instance_init, | |
349 | .instance_size = sizeof(SpikeState), | |
350 | }; | |
351 | ||
352 | static void spike_machine_init_register_types(void) | |
353 | { | |
354 | type_register_static(&spike_machine_typeinfo); | |
5b4beba1 MC |
355 | } |
356 | ||
a7172791 | 357 | type_init(spike_machine_init_register_types) |