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1/*
2 * QEMU RISC-V Spike Board
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This provides a RISC-V Board with the following devices:
8 *
9 * 0) HTIF Console and Poweroff
10 * 1) CLINT (Timer and IPI)
11 * 2) PLIC (Platform Level Interrupt Controller)
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2 or later, as published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along with
23 * this program. If not, see <http://www.gnu.org/licenses/>.
24 */
25
26#include "qemu/osdep.h"
27#include "qemu/log.h"
28#include "qemu/error-report.h"
29#include "qapi/error.h"
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30#include "hw/boards.h"
31#include "hw/loader.h"
32#include "hw/sysbus.h"
33#include "target/riscv/cpu.h"
34#include "hw/riscv/riscv_htif.h"
35#include "hw/riscv/riscv_hart.h"
5b4beba1 36#include "hw/riscv/spike.h"
0ac24d56 37#include "hw/riscv/boot.h"
a7172791 38#include "hw/riscv/numa.h"
406fafd5 39#include "hw/intc/sifive_clint.h"
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40#include "chardev/char.h"
41#include "sysemu/arch_init.h"
42#include "sysemu/device_tree.h"
cd69e3a6 43#include "sysemu/qtest.h"
46517dd4 44#include "sysemu/sysemu.h"
5aec3247 45
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46/*
47 * Not like other RISC-V machines that use plain binary bios images,
48 * keeping ELF files here was intentional because BIN files don't work
49 * for the Spike machine as HTIF emulation depends on ELF parsing.
50 */
5b8a9863 51#if defined(TARGET_RISCV32)
fad14439 52# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.elf"
5b8a9863 53#else
fad14439 54# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.elf"
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55#endif
56
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57static const struct MemmapEntry {
58 hwaddr base;
59 hwaddr size;
60} spike_memmap[] = {
9eb8b14a 61 [SPIKE_MROM] = { 0x1000, 0xf000 },
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62 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
63 [SPIKE_DRAM] = { 0x80000000, 0x0 },
64};
65
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66static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
67 uint64_t mem_size, const char *cmdline)
68{
69 void *fdt;
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70 uint64_t addr, size;
71 unsigned long clint_addr;
72 int cpu, socket;
73 MachineState *mc = MACHINE(s);
74 uint32_t *clint_cells;
75 uint32_t cpu_phandle, intc_phandle, phandle = 1;
76 char *name, *mem_name, *clint_name, *clust_name;
77 char *core_name, *cpu_name, *intc_name;
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78
79 fdt = s->fdt = create_device_tree(&s->fdt_size);
80 if (!fdt) {
81 error_report("create_device_tree() failed");
82 exit(1);
83 }
84
85 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
86 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
87 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
88 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
89
90 qemu_fdt_add_subnode(fdt, "/htif");
91 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
92
93 qemu_fdt_add_subnode(fdt, "/soc");
94 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
117caacf 95 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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96 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
97 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
98
5b4beba1 99 qemu_fdt_add_subnode(fdt, "/cpus");
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100 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
101 SIFIVE_CLINT_TIMEBASE_FREQ);
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102 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
103 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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104 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
105
106 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
107 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
108 qemu_fdt_add_subnode(fdt, clust_name);
109
110 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
5b4beba1 111
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112 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
113 cpu_phandle = phandle++;
114
115 cpu_name = g_strdup_printf("/cpus/cpu@%d",
116 s->soc[socket].hartid_base + cpu);
117 qemu_fdt_add_subnode(fdt, cpu_name);
e883e992 118#if defined(TARGET_RISCV32)
a7172791 119 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
e883e992 120#else
a7172791 121 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
e883e992 122#endif
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123 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
124 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
125 g_free(name);
126 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
127 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
128 qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
129 s->soc[socket].hartid_base + cpu);
130 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
131 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
132 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
5b4beba1 133
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134 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
135 qemu_fdt_add_subnode(fdt, intc_name);
136 intc_phandle = phandle++;
137 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
138 qemu_fdt_setprop_string(fdt, intc_name, "compatible",
139 "riscv,cpu-intc");
140 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
141 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
142
143 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
144 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
145 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
146 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
147
148 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
149 qemu_fdt_add_subnode(fdt, core_name);
150 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
151
152 g_free(core_name);
153 g_free(intc_name);
154 g_free(cpu_name);
155 }
156
157 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
158 size = riscv_socket_mem_size(mc, socket);
159 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
160 qemu_fdt_add_subnode(fdt, mem_name);
161 qemu_fdt_setprop_cells(fdt, mem_name, "reg",
162 addr >> 32, addr, size >> 32, size);
163 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
164 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
165 g_free(mem_name);
166
167 clint_addr = memmap[SPIKE_CLINT].base +
168 (memmap[SPIKE_CLINT].size * socket);
169 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
170 qemu_fdt_add_subnode(fdt, clint_name);
171 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
172 qemu_fdt_setprop_cells(fdt, clint_name, "reg",
173 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
174 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
175 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
176 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
177
178 g_free(clint_name);
179 g_free(clint_cells);
180 g_free(clust_name);
5b4beba1 181 }
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182
183 riscv_socket_fdt_write_distance_matrix(mc, fdt);
5b4beba1 184
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185 if (cmdline) {
186 qemu_fdt_add_subnode(fdt, "/chosen");
187 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
188 }
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189}
190
191static void spike_board_init(MachineState *machine)
192{
193 const struct MemmapEntry *memmap = spike_memmap;
a7172791 194 SpikeState *s = SPIKE_MACHINE(machine);
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195 MemoryRegion *system_memory = get_system_memory();
196 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
197 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
66b1205b 198 uint32_t fdt_load_addr;
dc144fe1 199 uint64_t kernel_entry;
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200 char *soc_name;
201 int i, base_hartid, hart_count;
cd69e3a6 202
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203 /* Check socket count limit */
204 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
205 error_report("number of sockets/nodes should be less than %d",
206 SPIKE_SOCKETS_MAX);
207 exit(1);
208 }
209
210 /* Initialize sockets */
211 for (i = 0; i < riscv_socket_count(machine); i++) {
212 if (!riscv_socket_check_hartids(machine, i)) {
213 error_report("discontinuous hartids in socket%d", i);
214 exit(1);
215 }
216
217 base_hartid = riscv_socket_first_hartid(machine, i);
218 if (base_hartid < 0) {
219 error_report("can't find hartid base for socket%d", i);
220 exit(1);
221 }
222
223 hart_count = riscv_socket_hart_count(machine, i);
224 if (hart_count < 0) {
225 error_report("can't find hart count for socket%d", i);
226 exit(1);
227 }
228
229 soc_name = g_strdup_printf("soc%d", i);
230 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
231 TYPE_RISCV_HART_ARRAY);
232 g_free(soc_name);
233 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
234 machine->cpu_type, &error_abort);
235 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
236 base_hartid, &error_abort);
237 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
238 hart_count, &error_abort);
239 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
240
241 /* Core Local Interruptor (timer and IPI) for each socket */
242 sifive_clint_create(
243 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
244 memmap[SPIKE_CLINT].size, base_hartid, hart_count,
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245 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
246 SIFIVE_CLINT_TIMEBASE_FREQ, false);
a7172791 247 }
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248
249 /* register system main memory (actual RAM) */
250 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
251 machine->ram_size, &error_fatal);
252 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
253 main_mem);
254
255 /* create device tree */
256 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
257
258 /* boot rom */
259 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
260 memmap[SPIKE_MROM].size, &error_fatal);
261 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
262 mask_rom);
263
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264 riscv_find_and_load_firmware(machine, BIOS_FILENAME,
265 memmap[SPIKE_DRAM].base,
266 htif_symbol_callback);
267
cd69e3a6 268 if (machine->kernel_filename) {
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269 kernel_entry = riscv_load_kernel(machine->kernel_filename,
270 htif_symbol_callback);
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271
272 if (machine->initrd_filename) {
273 hwaddr start;
274 hwaddr end = riscv_load_initrd(machine->initrd_filename,
275 machine->ram_size, kernel_entry,
276 &start);
277 qemu_fdt_setprop_cell(s->fdt, "/chosen",
278 "linux,initrd-start", start);
279 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
280 end);
281 }
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282 } else {
283 /*
284 * If dynamic firmware is used, it doesn't know where is the next mode
285 * if kernel argument is not set.
286 */
287 kernel_entry = 0;
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288 }
289
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290 /* Compute the fdt load address in dram */
291 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
292 machine->ram_size, s->fdt);
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293 /* load the reset vector */
294 riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
dc144fe1 295 memmap[SPIKE_MROM].size, kernel_entry,
66b1205b 296 fdt_load_addr, s->fdt);
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297
298 /* initialize HTIF using symbols found in load_kernel */
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299 htif_mm_init(system_memory, mask_rom,
300 &s->soc[0].harts[0].env, serial_hd(0));
301}
cd69e3a6 302
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303static void spike_machine_instance_init(Object *obj)
304{
cd69e3a6 305}
5b4beba1 306
a7172791 307static void spike_machine_class_init(ObjectClass *oc, void *data)
cd69e3a6 308{
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309 MachineClass *mc = MACHINE_CLASS(oc);
310
311 mc->desc = "RISC-V Spike board";
cd69e3a6 312 mc->init = spike_board_init;
a7172791 313 mc->max_cpus = SPIKE_CPUS_MAX;
ea0ac7f6 314 mc->is_default = true;
cd69e3a6 315 mc->default_cpu_type = SPIKE_V1_10_0_CPU;
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316 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
317 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
318 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
319 mc->numa_mem_supported = true;
320}
321
322static const TypeInfo spike_machine_typeinfo = {
323 .name = MACHINE_TYPE_NAME("spike"),
324 .parent = TYPE_MACHINE,
325 .class_init = spike_machine_class_init,
326 .instance_init = spike_machine_instance_init,
327 .instance_size = sizeof(SpikeState),
328};
329
330static void spike_machine_init_register_types(void)
331{
332 type_register_static(&spike_machine_typeinfo);
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333}
334
a7172791 335type_init(spike_machine_init_register_types)