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Merge tag 'pull-include-2023-02-06-v2' of https://repo.or.cz/qemu/armbru into staging
[mirror_qemu.git] / hw / rtc / ds1338.c
CommitLineData
1dfe3943
PB
1/*
2 * MAXIM DS1338 I2C RTC+NVRAM
3 *
4 * Copyright (c) 2009 CodeSourcery.
5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the GNU GPL v2.
6b620ca3
PB
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
1dfe3943
PB
11 */
12
282bc81e 13#include "qemu/osdep.h"
0d09e41a 14#include "hw/i2c/i2c.h"
d6454270 15#include "migration/vmstate.h"
f348b6d1 16#include "qemu/bcd.h"
0b8fa32f 17#include "qemu/module.h"
db1015e9 18#include "qom/object.h"
2f93d8b0 19#include "sysemu/rtc.h"
1dfe3943 20
ba4906a9
PM
21/* Size of NVRAM including both the user-accessible area and the
22 * secondary register area.
23 */
24#define NVRAM_SIZE 64
25
95c93615
AM
26/* Flags definitions */
27#define SECONDS_CH 0x80
28#define HOURS_12 0x40
29#define HOURS_PM 0x20
30#define CTRL_OSF 0x20
31
59ab56b9 32#define TYPE_DS1338 "ds1338"
8063396b 33OBJECT_DECLARE_SIMPLE_TYPE(DS1338State, DS1338)
59ab56b9 34
db1015e9 35struct DS1338State {
59ab56b9
AF
36 I2CSlave parent_obj;
37
f4741402 38 int64_t offset;
871edc5f 39 uint8_t wday_offset;
ba4906a9 40 uint8_t nvram[NVRAM_SIZE];
f4741402
PM
41 int32_t ptr;
42 bool addr_byte;
db1015e9 43};
1dfe3943 44
f4741402
PM
45static const VMStateDescription vmstate_ds1338 = {
46 .name = "ds1338",
871edc5f 47 .version_id = 2,
f4741402 48 .minimum_version_id = 1,
f4741402 49 .fields = (VMStateField[]) {
59ab56b9 50 VMSTATE_I2C_SLAVE(parent_obj, DS1338State),
f4741402 51 VMSTATE_INT64(offset, DS1338State),
871edc5f 52 VMSTATE_UINT8_V(wday_offset, DS1338State, 2),
f4741402
PM
53 VMSTATE_UINT8_ARRAY(nvram, DS1338State, NVRAM_SIZE),
54 VMSTATE_INT32(ptr, DS1338State),
55 VMSTATE_BOOL(addr_byte, DS1338State),
56 VMSTATE_END_OF_LIST()
57 }
58};
59
35b87a86
PM
60static void capture_current_time(DS1338State *s)
61{
62 /* Capture the current time into the secondary registers
63 * which will be actually read by the data transfer operation.
64 */
7f7fd0f2
PM
65 struct tm now;
66 qemu_get_timedate(&now, s->offset);
67 s->nvram[0] = to_bcd(now.tm_sec);
68 s->nvram[1] = to_bcd(now.tm_min);
59dda8e0
AM
69 if (s->nvram[2] & HOURS_12) {
70 int tmp = now.tm_hour;
5c78d6a8
AM
71 if (tmp % 12 == 0) {
72 tmp += 12;
59dda8e0
AM
73 }
74 if (tmp <= 12) {
75 s->nvram[2] = HOURS_12 | to_bcd(tmp);
76 } else {
77 s->nvram[2] = HOURS_12 | HOURS_PM | to_bcd(tmp - 12);
35b87a86
PM
78 }
79 } else {
7f7fd0f2 80 s->nvram[2] = to_bcd(now.tm_hour);
35b87a86 81 }
871edc5f 82 s->nvram[3] = (now.tm_wday + s->wday_offset) % 7 + 1;
7f7fd0f2 83 s->nvram[4] = to_bcd(now.tm_mday);
580f5c00 84 s->nvram[5] = to_bcd(now.tm_mon + 1);
7f7fd0f2 85 s->nvram[6] = to_bcd(now.tm_year - 100);
35b87a86
PM
86}
87
88static void inc_regptr(DS1338State *s)
89{
90 /* The register pointer wraps around after 0x3F; wraparound
91 * causes the current time/date to be retransferred into
92 * the secondary registers.
93 */
94 s->ptr = (s->ptr + 1) & (NVRAM_SIZE - 1);
95 if (!s->ptr) {
96 capture_current_time(s);
97 }
98}
99
d307c28c 100static int ds1338_event(I2CSlave *i2c, enum i2c_event event)
1dfe3943 101{
59ab56b9 102 DS1338State *s = DS1338(i2c);
1dfe3943
PB
103
104 switch (event) {
105 case I2C_START_RECV:
35b87a86
PM
106 /* In h/w, capture happens on any START condition, not just a
107 * START_RECV, but there is no need to actually capture on
108 * START_SEND, because the guest can't get at that data
109 * without going through a START_RECV which would overwrite it.
110 */
111 capture_current_time(s);
1dfe3943
PB
112 break;
113 case I2C_START_SEND:
f4741402 114 s->addr_byte = true;
1dfe3943
PB
115 break;
116 default:
117 break;
118 }
d307c28c
CM
119
120 return 0;
1dfe3943
PB
121}
122
2ac4c5f4 123static uint8_t ds1338_recv(I2CSlave *i2c)
1dfe3943 124{
59ab56b9 125 DS1338State *s = DS1338(i2c);
1dfe3943
PB
126 uint8_t res;
127
128 res = s->nvram[s->ptr];
35b87a86 129 inc_regptr(s);
1dfe3943
PB
130 return res;
131}
132
9e07bdf8 133static int ds1338_send(I2CSlave *i2c, uint8_t data)
1dfe3943 134{
59ab56b9
AF
135 DS1338State *s = DS1338(i2c);
136
1dfe3943 137 if (s->addr_byte) {
ba4906a9 138 s->ptr = data & (NVRAM_SIZE - 1);
f4741402 139 s->addr_byte = false;
1dfe3943
PB
140 return 0;
141 }
996e91f0
AM
142 if (s->ptr < 7) {
143 /* Time register. */
7f7fd0f2
PM
144 struct tm now;
145 qemu_get_timedate(&now, s->offset);
ba4906a9 146 switch(s->ptr) {
1dfe3943
PB
147 case 0:
148 /* TODO: Implement CH (stop) bit. */
7f7fd0f2 149 now.tm_sec = from_bcd(data & 0x7f);
1dfe3943
PB
150 break;
151 case 1:
7f7fd0f2 152 now.tm_min = from_bcd(data & 0x7f);
1dfe3943
PB
153 break;
154 case 2:
59dda8e0
AM
155 if (data & HOURS_12) {
156 int tmp = from_bcd(data & (HOURS_PM - 1));
157 if (data & HOURS_PM) {
158 tmp += 12;
159 }
5c78d6a8
AM
160 if (tmp % 12 == 0) {
161 tmp -= 12;
1dfe3943 162 }
59dda8e0 163 now.tm_hour = tmp;
1dfe3943 164 } else {
59dda8e0 165 now.tm_hour = from_bcd(data & (HOURS_12 - 1));
1dfe3943 166 }
1dfe3943
PB
167 break;
168 case 3:
871edc5f
AM
169 {
170 /* The day field is supposed to contain a value in
171 the range 1-7. Otherwise behavior is undefined.
172 */
173 int user_wday = (data & 7) - 1;
174 s->wday_offset = (user_wday - now.tm_wday + 7) % 7;
175 }
1dfe3943
PB
176 break;
177 case 4:
7f7fd0f2 178 now.tm_mday = from_bcd(data & 0x3f);
1dfe3943
PB
179 break;
180 case 5:
7f7fd0f2 181 now.tm_mon = from_bcd(data & 0x1f) - 1;
fbac6a7d 182 break;
1dfe3943 183 case 6:
7f7fd0f2 184 now.tm_year = from_bcd(data) + 100;
1dfe3943 185 break;
1dfe3943 186 }
7f7fd0f2 187 s->offset = qemu_timedate_diff(&now);
996e91f0
AM
188 } else if (s->ptr == 7) {
189 /* Control register. */
190
191 /* Ensure bits 2, 3 and 6 will read back as zero. */
192 data &= 0xB3;
193
194 /* Attempting to write the OSF flag to logic 1 leaves the
195 value unchanged. */
196 data = (data & ~CTRL_OSF) | (data & s->nvram[s->ptr] & CTRL_OSF);
197
198 s->nvram[s->ptr] = data;
ba4906a9
PM
199 } else {
200 s->nvram[s->ptr] = data;
1dfe3943 201 }
35b87a86 202 inc_regptr(s);
1dfe3943
PB
203 return 0;
204}
205
ed3d37d2
AM
206static void ds1338_reset(DeviceState *dev)
207{
59ab56b9 208 DS1338State *s = DS1338(dev);
ed3d37d2
AM
209
210 /* The clock is running and synchronized with the host */
211 s->offset = 0;
871edc5f 212 s->wday_offset = 0;
ed3d37d2
AM
213 memset(s->nvram, 0, NVRAM_SIZE);
214 s->ptr = 0;
215 s->addr_byte = false;
216}
217
b5ea9327
AL
218static void ds1338_class_init(ObjectClass *klass, void *data)
219{
f4741402 220 DeviceClass *dc = DEVICE_CLASS(klass);
b5ea9327
AL
221 I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
222
b5ea9327
AL
223 k->event = ds1338_event;
224 k->recv = ds1338_recv;
225 k->send = ds1338_send;
ed3d37d2 226 dc->reset = ds1338_reset;
f4741402 227 dc->vmsd = &vmstate_ds1338;
b5ea9327
AL
228}
229
8c43a6f0 230static const TypeInfo ds1338_info = {
59ab56b9 231 .name = TYPE_DS1338,
39bffca2
AL
232 .parent = TYPE_I2C_SLAVE,
233 .instance_size = sizeof(DS1338State),
234 .class_init = ds1338_class_init,
1dfe3943
PB
235};
236
83f7d43a 237static void ds1338_register_types(void)
1dfe3943 238{
39bffca2 239 type_register_static(&ds1338_info);
1dfe3943
PB
240}
241
83f7d43a 242type_init(ds1338_register_types)