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Commit | Line | Data |
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a541f297 | 1 | /* |
819385c5 | 2 | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms |
5fafdf24 | 3 | * |
cf83f140 | 4 | * Copyright (c) 2003-2005, 2007, 2017 Jocelyn Mayer |
051ddccd | 5 | * Copyright (c) 2013 Hervé Poussineau |
5fafdf24 | 6 | * |
a541f297 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
0b8fa32f | 25 | |
282bc81e | 26 | #include "qemu/osdep.h" |
a8d25326 | 27 | #include "qemu-common.h" |
64552b6b | 28 | #include "hw/irq.h" |
a27bd6c7 | 29 | #include "hw/qdev-properties.h" |
819ce6b2 | 30 | #include "hw/rtc/m48t59.h" |
1de7afc9 | 31 | #include "qemu/timer.h" |
54d31236 | 32 | #include "sysemu/runstate.h" |
9c17d615 | 33 | #include "sysemu/sysemu.h" |
83c9f4ca | 34 | #include "hw/sysbus.h" |
022c62cb | 35 | #include "exec/address-spaces.h" |
3e80f690 | 36 | #include "qapi/error.h" |
f348b6d1 | 37 | #include "qemu/bcd.h" |
0b8fa32f | 38 | #include "qemu/module.h" |
e21d73ec | 39 | #include "trace.h" |
a541f297 | 40 | |
c124c4d1 | 41 | #include "m48t59-internal.h" |
d6454270 | 42 | #include "migration/vmstate.h" |
a541f297 | 43 | |
051ddccd HP |
44 | #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx" |
45 | #define M48TXX_SYS_BUS_GET_CLASS(obj) \ | |
46 | OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS) | |
47 | #define M48TXX_SYS_BUS_CLASS(klass) \ | |
48 | OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS) | |
49 | #define M48TXX_SYS_BUS(obj) \ | |
50 | OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS) | |
51 | ||
930f3fe1 BS |
52 | /* |
53 | * Chipset docs: | |
54 | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf | |
55 | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf | |
56 | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf | |
57 | */ | |
58 | ||
051ddccd | 59 | typedef struct M48txxSysBusState { |
29d1ffc3 | 60 | SysBusDevice parent_obj; |
43a34704 | 61 | M48t59State state; |
087bd055 | 62 | MemoryRegion io; |
051ddccd HP |
63 | } M48txxSysBusState; |
64 | ||
65 | typedef struct M48txxSysBusDeviceClass { | |
66 | SysBusDeviceClass parent_class; | |
67 | M48txxInfo info; | |
68 | } M48txxSysBusDeviceClass; | |
69 | ||
c124c4d1 | 70 | static M48txxInfo m48txx_sysbus_info[] = { |
051ddccd | 71 | { |
c124c4d1 | 72 | .bus_name = "sysbus-m48t02", |
051ddccd HP |
73 | .model = 2, |
74 | .size = 0x800, | |
75 | },{ | |
c124c4d1 | 76 | .bus_name = "sysbus-m48t08", |
051ddccd HP |
77 | .model = 8, |
78 | .size = 0x2000, | |
0278377d | 79 | },{ |
c124c4d1 | 80 | .bus_name = "sysbus-m48t59", |
051ddccd HP |
81 | .model = 59, |
82 | .size = 0x2000, | |
83 | } | |
84 | }; | |
85 | ||
f80237d4 | 86 | |
a541f297 | 87 | /* Fake timer functions */ |
a541f297 | 88 | |
a541f297 FB |
89 | /* Alarm management */ |
90 | static void alarm_cb (void *opaque) | |
91 | { | |
f6503059 | 92 | struct tm tm; |
a541f297 | 93 | uint64_t next_time; |
43a34704 | 94 | M48t59State *NVRAM = opaque; |
a541f297 | 95 | |
d537cf6c | 96 | qemu_set_irq(NVRAM->IRQ, 1); |
5fafdf24 | 97 | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
a541f297 FB |
98 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
99 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
100 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
101 | /* Repeat once a month */ |
102 | qemu_get_timedate(&tm, NVRAM->time_offset); | |
103 | tm.tm_mon++; | |
104 | if (tm.tm_mon == 13) { | |
105 | tm.tm_mon = 1; | |
106 | tm.tm_year++; | |
107 | } | |
108 | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; | |
a541f297 FB |
109 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
110 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && | |
111 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
112 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
113 | /* Repeat once a day */ |
114 | next_time = 24 * 60 * 60; | |
a541f297 FB |
115 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
116 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
117 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
118 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
119 | /* Repeat once an hour */ |
120 | next_time = 60 * 60; | |
a541f297 FB |
121 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
122 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
123 | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && | |
124 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
125 | /* Repeat once a minute */ |
126 | next_time = 60; | |
a541f297 | 127 | } else { |
f6503059 AZ |
128 | /* Repeat once a second */ |
129 | next_time = 1; | |
a541f297 | 130 | } |
bc72ad67 | 131 | timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) + |
f6503059 | 132 | next_time * 1000); |
d537cf6c | 133 | qemu_set_irq(NVRAM->IRQ, 0); |
a541f297 FB |
134 | } |
135 | ||
43a34704 | 136 | static void set_alarm(M48t59State *NVRAM) |
f6503059 AZ |
137 | { |
138 | int diff; | |
139 | if (NVRAM->alrm_timer != NULL) { | |
bc72ad67 | 140 | timer_del(NVRAM->alrm_timer); |
f6503059 AZ |
141 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
142 | if (diff > 0) | |
bc72ad67 | 143 | timer_mod(NVRAM->alrm_timer, diff * 1000); |
f6503059 AZ |
144 | } |
145 | } | |
a541f297 | 146 | |
f6503059 | 147 | /* RTC management helpers */ |
43a34704 | 148 | static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 149 | { |
f6503059 | 150 | qemu_get_timedate(tm, NVRAM->time_offset); |
a541f297 FB |
151 | } |
152 | ||
43a34704 | 153 | static void set_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 154 | { |
f6503059 AZ |
155 | NVRAM->time_offset = qemu_timedate_diff(tm); |
156 | set_alarm(NVRAM); | |
a541f297 FB |
157 | } |
158 | ||
159 | /* Watchdog management */ | |
160 | static void watchdog_cb (void *opaque) | |
161 | { | |
43a34704 | 162 | M48t59State *NVRAM = opaque; |
a541f297 FB |
163 | |
164 | NVRAM->buffer[0x1FF0] |= 0x80; | |
165 | if (NVRAM->buffer[0x1FF7] & 0x80) { | |
166 | NVRAM->buffer[0x1FF7] = 0x00; | |
167 | NVRAM->buffer[0x1FFC] &= ~0x40; | |
13ab5daa | 168 | /* May it be a hw CPU Reset instead ? */ |
cf83f140 | 169 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
a541f297 | 170 | } else { |
d537cf6c PB |
171 | qemu_set_irq(NVRAM->IRQ, 1); |
172 | qemu_set_irq(NVRAM->IRQ, 0); | |
a541f297 FB |
173 | } |
174 | } | |
175 | ||
43a34704 | 176 | static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
a541f297 FB |
177 | { |
178 | uint64_t interval; /* in 1/16 seconds */ | |
179 | ||
868d585a | 180 | NVRAM->buffer[0x1FF0] &= ~0x80; |
a541f297 | 181 | if (NVRAM->wd_timer != NULL) { |
bc72ad67 | 182 | timer_del(NVRAM->wd_timer); |
868d585a JM |
183 | if (value != 0) { |
184 | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); | |
bc72ad67 | 185 | timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
868d585a JM |
186 | ((interval * 1000) >> 4)); |
187 | } | |
a541f297 FB |
188 | } |
189 | } | |
190 | ||
191 | /* Direct access to NVRAM */ | |
c124c4d1 | 192 | void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val) |
a541f297 | 193 | { |
a541f297 FB |
194 | struct tm tm; |
195 | int tmp; | |
196 | ||
e21d73ec | 197 | trace_m48txx_nvram_mem_write(addr, val); |
4aed2c33 BS |
198 | |
199 | /* check for NVRAM access */ | |
7bc3018b PB |
200 | if ((NVRAM->model == 2 && addr < 0x7f8) || |
201 | (NVRAM->model == 8 && addr < 0x1ff8) || | |
202 | (NVRAM->model == 59 && addr < 0x1ff0)) { | |
819385c5 | 203 | goto do_write; |
7bc3018b | 204 | } |
4aed2c33 BS |
205 | |
206 | /* TOD access */ | |
819385c5 | 207 | switch (addr) { |
a541f297 FB |
208 | case 0x1FF0: |
209 | /* flags register : read-only */ | |
210 | break; | |
211 | case 0x1FF1: | |
212 | /* unused */ | |
213 | break; | |
214 | case 0x1FF2: | |
215 | /* alarm seconds */ | |
abd0c6bd | 216 | tmp = from_bcd(val & 0x7F); |
819385c5 | 217 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 218 | NVRAM->alarm.tm_sec = tmp; |
819385c5 | 219 | NVRAM->buffer[0x1FF2] = val; |
f6503059 | 220 | set_alarm(NVRAM); |
819385c5 | 221 | } |
a541f297 FB |
222 | break; |
223 | case 0x1FF3: | |
224 | /* alarm minutes */ | |
abd0c6bd | 225 | tmp = from_bcd(val & 0x7F); |
819385c5 | 226 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 227 | NVRAM->alarm.tm_min = tmp; |
819385c5 | 228 | NVRAM->buffer[0x1FF3] = val; |
f6503059 | 229 | set_alarm(NVRAM); |
819385c5 | 230 | } |
a541f297 FB |
231 | break; |
232 | case 0x1FF4: | |
233 | /* alarm hours */ | |
abd0c6bd | 234 | tmp = from_bcd(val & 0x3F); |
819385c5 | 235 | if (tmp >= 0 && tmp <= 23) { |
f6503059 | 236 | NVRAM->alarm.tm_hour = tmp; |
819385c5 | 237 | NVRAM->buffer[0x1FF4] = val; |
f6503059 | 238 | set_alarm(NVRAM); |
819385c5 | 239 | } |
a541f297 FB |
240 | break; |
241 | case 0x1FF5: | |
242 | /* alarm date */ | |
02f5da11 | 243 | tmp = from_bcd(val & 0x3F); |
819385c5 | 244 | if (tmp != 0) { |
f6503059 | 245 | NVRAM->alarm.tm_mday = tmp; |
819385c5 | 246 | NVRAM->buffer[0x1FF5] = val; |
f6503059 | 247 | set_alarm(NVRAM); |
819385c5 | 248 | } |
a541f297 FB |
249 | break; |
250 | case 0x1FF6: | |
251 | /* interrupts */ | |
819385c5 | 252 | NVRAM->buffer[0x1FF6] = val; |
a541f297 FB |
253 | break; |
254 | case 0x1FF7: | |
255 | /* watchdog */ | |
819385c5 FB |
256 | NVRAM->buffer[0x1FF7] = val; |
257 | set_up_watchdog(NVRAM, val); | |
a541f297 FB |
258 | break; |
259 | case 0x1FF8: | |
4aed2c33 | 260 | case 0x07F8: |
a541f297 | 261 | /* control */ |
4aed2c33 | 262 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
a541f297 FB |
263 | break; |
264 | case 0x1FF9: | |
4aed2c33 | 265 | case 0x07F9: |
a541f297 | 266 | /* seconds (BCD) */ |
abd0c6bd | 267 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
268 | if (tmp >= 0 && tmp <= 59) { |
269 | get_time(NVRAM, &tm); | |
270 | tm.tm_sec = tmp; | |
271 | set_time(NVRAM, &tm); | |
272 | } | |
f6503059 | 273 | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
a541f297 FB |
274 | if (val & 0x80) { |
275 | NVRAM->stop_time = time(NULL); | |
276 | } else { | |
277 | NVRAM->time_offset += NVRAM->stop_time - time(NULL); | |
278 | NVRAM->stop_time = 0; | |
279 | } | |
280 | } | |
f6503059 | 281 | NVRAM->buffer[addr] = val & 0x80; |
a541f297 FB |
282 | break; |
283 | case 0x1FFA: | |
4aed2c33 | 284 | case 0x07FA: |
a541f297 | 285 | /* minutes (BCD) */ |
abd0c6bd | 286 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
287 | if (tmp >= 0 && tmp <= 59) { |
288 | get_time(NVRAM, &tm); | |
289 | tm.tm_min = tmp; | |
290 | set_time(NVRAM, &tm); | |
291 | } | |
292 | break; | |
293 | case 0x1FFB: | |
4aed2c33 | 294 | case 0x07FB: |
a541f297 | 295 | /* hours (BCD) */ |
abd0c6bd | 296 | tmp = from_bcd(val & 0x3F); |
a541f297 FB |
297 | if (tmp >= 0 && tmp <= 23) { |
298 | get_time(NVRAM, &tm); | |
299 | tm.tm_hour = tmp; | |
300 | set_time(NVRAM, &tm); | |
301 | } | |
302 | break; | |
303 | case 0x1FFC: | |
4aed2c33 | 304 | case 0x07FC: |
a541f297 | 305 | /* day of the week / century */ |
abd0c6bd | 306 | tmp = from_bcd(val & 0x07); |
a541f297 FB |
307 | get_time(NVRAM, &tm); |
308 | tm.tm_wday = tmp; | |
309 | set_time(NVRAM, &tm); | |
4aed2c33 | 310 | NVRAM->buffer[addr] = val & 0x40; |
a541f297 FB |
311 | break; |
312 | case 0x1FFD: | |
4aed2c33 | 313 | case 0x07FD: |
02f5da11 AT |
314 | /* date (BCD) */ |
315 | tmp = from_bcd(val & 0x3F); | |
a541f297 FB |
316 | if (tmp != 0) { |
317 | get_time(NVRAM, &tm); | |
318 | tm.tm_mday = tmp; | |
319 | set_time(NVRAM, &tm); | |
320 | } | |
321 | break; | |
322 | case 0x1FFE: | |
4aed2c33 | 323 | case 0x07FE: |
a541f297 | 324 | /* month */ |
abd0c6bd | 325 | tmp = from_bcd(val & 0x1F); |
a541f297 FB |
326 | if (tmp >= 1 && tmp <= 12) { |
327 | get_time(NVRAM, &tm); | |
328 | tm.tm_mon = tmp - 1; | |
329 | set_time(NVRAM, &tm); | |
330 | } | |
331 | break; | |
332 | case 0x1FFF: | |
4aed2c33 | 333 | case 0x07FF: |
a541f297 | 334 | /* year */ |
abd0c6bd | 335 | tmp = from_bcd(val); |
a541f297 FB |
336 | if (tmp >= 0 && tmp <= 99) { |
337 | get_time(NVRAM, &tm); | |
6de04973 | 338 | tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900; |
a541f297 FB |
339 | set_time(NVRAM, &tm); |
340 | } | |
341 | break; | |
342 | default: | |
13ab5daa | 343 | /* Check lock registers state */ |
819385c5 | 344 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 345 | break; |
819385c5 | 346 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 347 | break; |
819385c5 FB |
348 | do_write: |
349 | if (addr < NVRAM->size) { | |
350 | NVRAM->buffer[addr] = val & 0xFF; | |
a541f297 FB |
351 | } |
352 | break; | |
353 | } | |
354 | } | |
355 | ||
c124c4d1 | 356 | uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr) |
a541f297 | 357 | { |
a541f297 FB |
358 | struct tm tm; |
359 | uint32_t retval = 0xFF; | |
360 | ||
4aed2c33 | 361 | /* check for NVRAM access */ |
7bc3018b PB |
362 | if ((NVRAM->model == 2 && addr < 0x078f) || |
363 | (NVRAM->model == 8 && addr < 0x1ff8) || | |
364 | (NVRAM->model == 59 && addr < 0x1ff0)) { | |
819385c5 | 365 | goto do_read; |
7bc3018b | 366 | } |
4aed2c33 BS |
367 | |
368 | /* TOD access */ | |
819385c5 | 369 | switch (addr) { |
a541f297 FB |
370 | case 0x1FF0: |
371 | /* flags register */ | |
372 | goto do_read; | |
373 | case 0x1FF1: | |
374 | /* unused */ | |
375 | retval = 0; | |
376 | break; | |
377 | case 0x1FF2: | |
378 | /* alarm seconds */ | |
379 | goto do_read; | |
380 | case 0x1FF3: | |
381 | /* alarm minutes */ | |
382 | goto do_read; | |
383 | case 0x1FF4: | |
384 | /* alarm hours */ | |
385 | goto do_read; | |
386 | case 0x1FF5: | |
387 | /* alarm date */ | |
388 | goto do_read; | |
389 | case 0x1FF6: | |
390 | /* interrupts */ | |
391 | goto do_read; | |
392 | case 0x1FF7: | |
393 | /* A read resets the watchdog */ | |
394 | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]); | |
395 | goto do_read; | |
396 | case 0x1FF8: | |
4aed2c33 | 397 | case 0x07F8: |
a541f297 FB |
398 | /* control */ |
399 | goto do_read; | |
400 | case 0x1FF9: | |
4aed2c33 | 401 | case 0x07F9: |
a541f297 FB |
402 | /* seconds (BCD) */ |
403 | get_time(NVRAM, &tm); | |
abd0c6bd | 404 | retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec); |
a541f297 FB |
405 | break; |
406 | case 0x1FFA: | |
4aed2c33 | 407 | case 0x07FA: |
a541f297 FB |
408 | /* minutes (BCD) */ |
409 | get_time(NVRAM, &tm); | |
abd0c6bd | 410 | retval = to_bcd(tm.tm_min); |
a541f297 FB |
411 | break; |
412 | case 0x1FFB: | |
4aed2c33 | 413 | case 0x07FB: |
a541f297 FB |
414 | /* hours (BCD) */ |
415 | get_time(NVRAM, &tm); | |
abd0c6bd | 416 | retval = to_bcd(tm.tm_hour); |
a541f297 FB |
417 | break; |
418 | case 0x1FFC: | |
4aed2c33 | 419 | case 0x07FC: |
a541f297 FB |
420 | /* day of the week / century */ |
421 | get_time(NVRAM, &tm); | |
4aed2c33 | 422 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
a541f297 FB |
423 | break; |
424 | case 0x1FFD: | |
4aed2c33 | 425 | case 0x07FD: |
a541f297 FB |
426 | /* date */ |
427 | get_time(NVRAM, &tm); | |
abd0c6bd | 428 | retval = to_bcd(tm.tm_mday); |
a541f297 FB |
429 | break; |
430 | case 0x1FFE: | |
4aed2c33 | 431 | case 0x07FE: |
a541f297 FB |
432 | /* month */ |
433 | get_time(NVRAM, &tm); | |
abd0c6bd | 434 | retval = to_bcd(tm.tm_mon + 1); |
a541f297 FB |
435 | break; |
436 | case 0x1FFF: | |
4aed2c33 | 437 | case 0x07FF: |
a541f297 FB |
438 | /* year */ |
439 | get_time(NVRAM, &tm); | |
6de04973 | 440 | retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100); |
a541f297 FB |
441 | break; |
442 | default: | |
13ab5daa | 443 | /* Check lock registers state */ |
819385c5 | 444 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 445 | break; |
819385c5 | 446 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 447 | break; |
819385c5 FB |
448 | do_read: |
449 | if (addr < NVRAM->size) { | |
450 | retval = NVRAM->buffer[addr]; | |
a541f297 FB |
451 | } |
452 | break; | |
453 | } | |
e21d73ec | 454 | trace_m48txx_nvram_mem_read(addr, retval); |
a541f297 FB |
455 | |
456 | return retval; | |
457 | } | |
458 | ||
a541f297 | 459 | /* IO access to NVRAM */ |
087bd055 AG |
460 | static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val, |
461 | unsigned size) | |
a541f297 | 462 | { |
43a34704 | 463 | M48t59State *NVRAM = opaque; |
a541f297 | 464 | |
e21d73ec | 465 | trace_m48txx_nvram_io_write(addr, val); |
a541f297 FB |
466 | switch (addr) { |
467 | case 0: | |
468 | NVRAM->addr &= ~0x00FF; | |
469 | NVRAM->addr |= val; | |
470 | break; | |
471 | case 1: | |
472 | NVRAM->addr &= ~0xFF00; | |
473 | NVRAM->addr |= val << 8; | |
474 | break; | |
475 | case 3: | |
b1f88301 | 476 | m48t59_write(NVRAM, NVRAM->addr, val); |
a541f297 FB |
477 | NVRAM->addr = 0x0000; |
478 | break; | |
479 | default: | |
480 | break; | |
481 | } | |
482 | } | |
483 | ||
087bd055 | 484 | static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size) |
a541f297 | 485 | { |
43a34704 | 486 | M48t59State *NVRAM = opaque; |
13ab5daa | 487 | uint32_t retval; |
a541f297 | 488 | |
13ab5daa FB |
489 | switch (addr) { |
490 | case 3: | |
819385c5 | 491 | retval = m48t59_read(NVRAM, NVRAM->addr); |
13ab5daa FB |
492 | break; |
493 | default: | |
494 | retval = -1; | |
495 | break; | |
496 | } | |
e21d73ec | 497 | trace_m48txx_nvram_io_read(addr, retval); |
a541f297 | 498 | |
13ab5daa | 499 | return retval; |
a541f297 FB |
500 | } |
501 | ||
62b9cf0a | 502 | static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size) |
e1bb04f7 | 503 | { |
43a34704 | 504 | M48t59State *NVRAM = opaque; |
3b46e624 | 505 | |
bf5f78ef | 506 | return m48t59_read(NVRAM, addr); |
e1bb04f7 FB |
507 | } |
508 | ||
62b9cf0a PM |
509 | static void nvram_write(void *opaque, hwaddr addr, uint64_t value, |
510 | unsigned size) | |
e1bb04f7 | 511 | { |
43a34704 | 512 | M48t59State *NVRAM = opaque; |
e1bb04f7 | 513 | |
62b9cf0a | 514 | return m48t59_write(NVRAM, addr, value); |
e1bb04f7 FB |
515 | } |
516 | ||
5a31cd68 | 517 | static const MemoryRegionOps nvram_ops = { |
62b9cf0a PM |
518 | .read = nvram_read, |
519 | .write = nvram_write, | |
520 | .impl.min_access_size = 1, | |
521 | .impl.max_access_size = 1, | |
522 | .valid.min_access_size = 1, | |
523 | .valid.max_access_size = 4, | |
524 | .endianness = DEVICE_BIG_ENDIAN, | |
e1bb04f7 | 525 | }; |
819385c5 | 526 | |
fd484ae4 JQ |
527 | static const VMStateDescription vmstate_m48t59 = { |
528 | .name = "m48t59", | |
529 | .version_id = 1, | |
530 | .minimum_version_id = 1, | |
3aff6c2f | 531 | .fields = (VMStateField[]) { |
fd484ae4 JQ |
532 | VMSTATE_UINT8(lock, M48t59State), |
533 | VMSTATE_UINT16(addr, M48t59State), | |
59046ec2 | 534 | VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, size), |
fd484ae4 JQ |
535 | VMSTATE_END_OF_LIST() |
536 | } | |
537 | }; | |
3ccacc4a | 538 | |
c124c4d1 | 539 | void m48t59_reset_common(M48t59State *NVRAM) |
3ccacc4a | 540 | { |
6e6b7363 BS |
541 | NVRAM->addr = 0; |
542 | NVRAM->lock = 0; | |
3ccacc4a | 543 | if (NVRAM->alrm_timer != NULL) |
bc72ad67 | 544 | timer_del(NVRAM->alrm_timer); |
3ccacc4a BS |
545 | |
546 | if (NVRAM->wd_timer != NULL) | |
bc72ad67 | 547 | timer_del(NVRAM->wd_timer); |
3ccacc4a BS |
548 | } |
549 | ||
285e468d BS |
550 | static void m48t59_reset_sysbus(DeviceState *d) |
551 | { | |
051ddccd | 552 | M48txxSysBusState *sys = M48TXX_SYS_BUS(d); |
43a34704 | 553 | M48t59State *NVRAM = &sys->state; |
285e468d BS |
554 | |
555 | m48t59_reset_common(NVRAM); | |
556 | } | |
557 | ||
c124c4d1 | 558 | const MemoryRegionOps m48t59_io_ops = { |
087bd055 AG |
559 | .read = NVRAM_readb, |
560 | .write = NVRAM_writeb, | |
561 | .impl = { | |
562 | .min_access_size = 1, | |
563 | .max_access_size = 1, | |
564 | }, | |
565 | .endianness = DEVICE_LITTLE_ENDIAN, | |
9936d6e4 RH |
566 | }; |
567 | ||
a541f297 | 568 | /* Initialisation routine */ |
31688246 | 569 | Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base, |
6de04973 MCA |
570 | uint32_t io_base, uint16_t size, int base_year, |
571 | int model) | |
a541f297 | 572 | { |
d27cf0ae BS |
573 | DeviceState *dev; |
574 | SysBusDevice *s; | |
051ddccd | 575 | int i; |
d27cf0ae | 576 | |
c124c4d1 DG |
577 | for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) { |
578 | if (m48txx_sysbus_info[i].size != size || | |
579 | m48txx_sysbus_info[i].model != model) { | |
051ddccd HP |
580 | continue; |
581 | } | |
582 | ||
3e80f690 | 583 | dev = qdev_new(m48txx_sysbus_info[i].bus_name); |
6de04973 | 584 | qdev_prop_set_int32(dev, "base-year", base_year); |
051ddccd | 585 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 586 | sysbus_realize_and_unref(s, &error_fatal); |
051ddccd HP |
587 | sysbus_connect_irq(s, 0, IRQ); |
588 | if (io_base != 0) { | |
589 | memory_region_add_subregion(get_system_io(), io_base, | |
590 | sysbus_mmio_get_region(s, 1)); | |
591 | } | |
592 | if (mem_base != 0) { | |
593 | sysbus_mmio_map(s, 0, mem_base); | |
594 | } | |
595 | ||
31688246 | 596 | return NVRAM(s); |
e1bb04f7 | 597 | } |
d27cf0ae | 598 | |
051ddccd HP |
599 | assert(false); |
600 | return NULL; | |
d27cf0ae BS |
601 | } |
602 | ||
c124c4d1 | 603 | void m48t59_realize_common(M48t59State *s, Error **errp) |
f80237d4 | 604 | { |
7267c094 | 605 | s->buffer = g_malloc0(s->size); |
7bc3018b | 606 | if (s->model == 59) { |
884f17c2 | 607 | s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s); |
bc72ad67 | 608 | s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s); |
819385c5 | 609 | } |
f6503059 | 610 | qemu_get_timedate(&s->alarm, 0); |
f80237d4 BS |
611 | } |
612 | ||
c04e34a9 | 613 | static void m48t59_init1(Object *obj) |
f80237d4 | 614 | { |
c04e34a9 XZ |
615 | M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(obj); |
616 | M48txxSysBusState *d = M48TXX_SYS_BUS(obj); | |
617 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
43a34704 | 618 | M48t59State *s = &d->state; |
f80237d4 | 619 | |
051ddccd HP |
620 | s->model = u->info.model; |
621 | s->size = u->info.size; | |
f80237d4 BS |
622 | sysbus_init_irq(dev, &s->IRQ); |
623 | ||
c04e34a9 | 624 | memory_region_init_io(&s->iomem, obj, &nvram_ops, s, "m48t59.nvram", |
72cd63f8 | 625 | s->size); |
c04e34a9 XZ |
626 | memory_region_init_io(&d->io, obj, &m48t59_io_ops, s, "m48t59", 4); |
627 | } | |
628 | ||
629 | static void m48t59_realize(DeviceState *dev, Error **errp) | |
630 | { | |
631 | M48txxSysBusState *d = M48TXX_SYS_BUS(dev); | |
632 | M48t59State *s = &d->state; | |
633 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
f80237d4 | 634 | |
c04e34a9 XZ |
635 | sysbus_init_mmio(sbd, &s->iomem); |
636 | sysbus_init_mmio(sbd, &d->io); | |
637 | m48t59_realize_common(s, errp); | |
f80237d4 BS |
638 | } |
639 | ||
43745328 HP |
640 | static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr) |
641 | { | |
642 | M48txxSysBusState *d = M48TXX_SYS_BUS(obj); | |
643 | return m48t59_read(&d->state, addr); | |
644 | } | |
645 | ||
646 | static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val) | |
647 | { | |
648 | M48txxSysBusState *d = M48TXX_SYS_BUS(obj); | |
649 | m48t59_write(&d->state, addr, val); | |
650 | } | |
651 | ||
652 | static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock) | |
653 | { | |
654 | M48txxSysBusState *d = M48TXX_SYS_BUS(obj); | |
655 | m48t59_toggle_lock(&d->state, lock); | |
656 | } | |
657 | ||
6de04973 MCA |
658 | static Property m48t59_sysbus_properties[] = { |
659 | DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0), | |
660 | DEFINE_PROP_END_OF_LIST(), | |
661 | }; | |
662 | ||
051ddccd | 663 | static void m48txx_sysbus_class_init(ObjectClass *klass, void *data) |
999e12bb | 664 | { |
39bffca2 | 665 | DeviceClass *dc = DEVICE_CLASS(klass); |
43745328 | 666 | NvramClass *nc = NVRAM_CLASS(klass); |
999e12bb | 667 | |
c04e34a9 | 668 | dc->realize = m48t59_realize; |
39bffca2 | 669 | dc->reset = m48t59_reset_sysbus; |
4f67d30b | 670 | device_class_set_props(dc, m48t59_sysbus_properties); |
c04e34a9 | 671 | dc->vmsd = &vmstate_m48t59; |
43745328 HP |
672 | nc->read = m48txx_sysbus_read; |
673 | nc->write = m48txx_sysbus_write; | |
674 | nc->toggle_lock = m48txx_sysbus_toggle_lock; | |
999e12bb AL |
675 | } |
676 | ||
051ddccd HP |
677 | static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data) |
678 | { | |
679 | M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass); | |
680 | M48txxInfo *info = data; | |
681 | ||
682 | u->info = *info; | |
683 | } | |
684 | ||
43745328 HP |
685 | static const TypeInfo nvram_info = { |
686 | .name = TYPE_NVRAM, | |
687 | .parent = TYPE_INTERFACE, | |
688 | .class_size = sizeof(NvramClass), | |
689 | }; | |
690 | ||
051ddccd HP |
691 | static const TypeInfo m48txx_sysbus_type_info = { |
692 | .name = TYPE_M48TXX_SYS_BUS, | |
693 | .parent = TYPE_SYS_BUS_DEVICE, | |
694 | .instance_size = sizeof(M48txxSysBusState), | |
c04e34a9 | 695 | .instance_init = m48t59_init1, |
051ddccd HP |
696 | .abstract = true, |
697 | .class_init = m48txx_sysbus_class_init, | |
43745328 HP |
698 | .interfaces = (InterfaceInfo[]) { |
699 | { TYPE_NVRAM }, | |
700 | { } | |
701 | } | |
051ddccd HP |
702 | }; |
703 | ||
83f7d43a | 704 | static void m48t59_register_types(void) |
d27cf0ae | 705 | { |
051ddccd HP |
706 | TypeInfo sysbus_type_info = { |
707 | .parent = TYPE_M48TXX_SYS_BUS, | |
708 | .class_size = sizeof(M48txxSysBusDeviceClass), | |
709 | .class_init = m48txx_sysbus_concrete_class_init, | |
710 | }; | |
051ddccd HP |
711 | int i; |
712 | ||
43745328 | 713 | type_register_static(&nvram_info); |
051ddccd | 714 | type_register_static(&m48txx_sysbus_type_info); |
051ddccd | 715 | |
c124c4d1 DG |
716 | for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) { |
717 | sysbus_type_info.name = m48txx_sysbus_info[i].bus_name; | |
718 | sysbus_type_info.class_data = &m48txx_sysbus_info[i]; | |
719 | type_register(&sysbus_type_info); | |
051ddccd | 720 | } |
a541f297 | 721 | } |
d27cf0ae | 722 | |
83f7d43a | 723 | type_init(m48t59_register_types) |