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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU MC146818 RTC emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
f348b6d1 | 26 | #include "qemu/cutils.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
f348b6d1 | 28 | #include "qemu/bcd.h" |
d9cf178c | 29 | #include "hw/acpi/acpi_aml_interface.h" |
2b85e0cd | 30 | #include "hw/intc/kvm_irqcount.h" |
64552b6b | 31 | #include "hw/irq.h" |
a27bd6c7 | 32 | #include "hw/qdev-properties.h" |
ce35e229 | 33 | #include "hw/qdev-properties-system.h" |
1de7afc9 | 34 | #include "qemu/timer.h" |
9c17d615 | 35 | #include "sysemu/sysemu.h" |
1dfb1b2d | 36 | #include "sysemu/replay.h" |
71e8a915 | 37 | #include "sysemu/reset.h" |
54d31236 | 38 | #include "sysemu/runstate.h" |
2f93d8b0 | 39 | #include "sysemu/rtc.h" |
bcdb9064 | 40 | #include "hw/rtc/mc146818rtc.h" |
7ffcb73d | 41 | #include "hw/rtc/mc146818rtc_regs.h" |
d6454270 | 42 | #include "migration/vmstate.h" |
e688df6b | 43 | #include "qapi/error.h" |
1f216b8c | 44 | #include "qapi/qapi-events-misc.h" |
7b1b5d19 | 45 | #include "qapi/visitor.h" |
80cabfad FB |
46 | |
47 | //#define DEBUG_CMOS | |
aa6f63ff | 48 | //#define DEBUG_COALESCED |
80cabfad | 49 | |
ec51e364 IY |
50 | #ifdef DEBUG_CMOS |
51 | # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
52 | #else | |
53 | # define CMOS_DPRINTF(format, ...) do { } while (0) | |
54 | #endif | |
55 | ||
aa6f63ff BS |
56 | #ifdef DEBUG_COALESCED |
57 | # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) | |
58 | #else | |
59 | # define DPRINTF_C(format, ...) do { } while (0) | |
60 | #endif | |
61 | ||
00cf5774 PB |
62 | #define SEC_PER_MIN 60 |
63 | #define MIN_PER_HOUR 60 | |
64 | #define SEC_PER_HOUR 3600 | |
65 | #define HOUR_PER_DAY 24 | |
66 | #define SEC_PER_DAY 86400 | |
56038ef6 | 67 | |
dd17765b | 68 | #define RTC_REINJECT_ON_ACK_COUNT 20 |
e46deaba | 69 | #define RTC_CLOCK_RATE 32768 |
13566fe3 | 70 | #define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768) |
ba32edab | 71 | |
5b21b331 BB |
72 | #define RTC_ISA_BASE 0x70 |
73 | ||
dff38e7b | 74 | static void rtc_set_time(RTCState *s); |
56038ef6 | 75 | static void rtc_update_time(RTCState *s); |
e2826cf4 | 76 | static void rtc_set_cmos(RTCState *s, const struct tm *tm); |
56038ef6 | 77 | static inline int rtc_from_bcd(RTCState *s, int a); |
00cf5774 | 78 | static uint64_t get_next_alarm(RTCState *s); |
56038ef6 | 79 | |
41a9b8b2 YZ |
80 | static inline bool rtc_running(RTCState *s) |
81 | { | |
82 | return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && | |
83 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); | |
84 | } | |
85 | ||
56038ef6 YZ |
86 | static uint64_t get_guest_rtc_ns(RTCState *s) |
87 | { | |
884f17c2 | 88 | uint64_t guest_clock = qemu_clock_get_ns(rtc_clock); |
56038ef6 | 89 | |
9be38598 | 90 | return s->base_rtc * NANOSECONDS_PER_SECOND + |
73bcb24d | 91 | guest_clock - s->last_update + s->offset; |
56038ef6 | 92 | } |
dff38e7b | 93 | |
93b66569 AL |
94 | static void rtc_coalesced_timer_update(RTCState *s) |
95 | { | |
96 | if (s->irq_coalesced == 0) { | |
bc72ad67 | 97 | timer_del(s->coalesced_timer); |
93b66569 AL |
98 | } else { |
99 | /* divide each RTC interval to 2 - 8 smaller intervals */ | |
7cd9681b | 100 | int c = MIN(s->irq_coalesced, 7) + 1; |
884f17c2 | 101 | int64_t next_clock = qemu_clock_get_ns(rtc_clock) + |
bd618eab | 102 | periodic_clock_to_ns(s->period / c); |
bc72ad67 | 103 | timer_mod(s->coalesced_timer, next_clock); |
93b66569 AL |
104 | } |
105 | } | |
106 | ||
e0c8b950 XG |
107 | static QLIST_HEAD(, RTCState) rtc_devices = |
108 | QLIST_HEAD_INITIALIZER(rtc_devices); | |
109 | ||
e0c8b950 XG |
110 | void qmp_rtc_reset_reinjection(Error **errp) |
111 | { | |
112 | RTCState *s; | |
113 | ||
114 | QLIST_FOREACH(s, &rtc_devices, link) { | |
115 | s->irq_coalesced = 0; | |
116 | } | |
117 | } | |
118 | ||
119 | static bool rtc_policy_slew_deliver_irq(RTCState *s) | |
120 | { | |
2b85e0cd | 121 | kvm_reset_irq_delivered(); |
e0c8b950 | 122 | qemu_irq_raise(s->irq); |
2b85e0cd | 123 | return kvm_get_irq_delivered(); |
e0c8b950 XG |
124 | } |
125 | ||
93b66569 AL |
126 | static void rtc_coalesced_timer(void *opaque) |
127 | { | |
128 | RTCState *s = opaque; | |
129 | ||
130 | if (s->irq_coalesced != 0) { | |
93b66569 | 131 | s->cmos_data[RTC_REG_C] |= 0xc0; |
aa6f63ff | 132 | DPRINTF_C("cmos: injecting from timer\n"); |
e0c8b950 | 133 | if (rtc_policy_slew_deliver_irq(s)) { |
93b66569 | 134 | s->irq_coalesced--; |
aa6f63ff BS |
135 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
136 | s->irq_coalesced); | |
93b66569 AL |
137 | } |
138 | } | |
139 | ||
140 | rtc_coalesced_timer_update(s); | |
141 | } | |
93b66569 | 142 | |
369b4135 | 143 | static uint32_t rtc_periodic_clock_ticks(RTCState *s) |
dff38e7b | 144 | { |
369b4135 TY |
145 | int period_code; |
146 | ||
147 | if (!(s->cmos_data[RTC_REG_B] & REG_B_PIE)) { | |
148 | return 0; | |
149 | } | |
dff38e7b FB |
150 | |
151 | period_code = s->cmos_data[RTC_REG_A] & 0x0f; | |
369b4135 | 152 | |
bd618eab | 153 | return periodic_period_to_clock(period_code); |
369b4135 TY |
154 | } |
155 | ||
156 | /* | |
157 | * handle periodic timer. @old_period indicates the periodic timer update | |
158 | * is just due to period adjustment. | |
159 | */ | |
160 | static void | |
7a3e29b1 | 161 | periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_period, bool period_change) |
369b4135 TY |
162 | { |
163 | uint32_t period; | |
164 | int64_t cur_clock, next_irq_clock, lost_clock = 0; | |
165 | ||
166 | period = rtc_periodic_clock_ticks(s); | |
7a3e29b1 PB |
167 | s->period = period; |
168 | ||
b429de73 MT |
169 | if (!period) { |
170 | s->irq_coalesced = 0; | |
171 | timer_del(s->periodic_timer); | |
172 | return; | |
173 | } | |
73bcb24d | 174 | |
b429de73 MT |
175 | /* compute 32 khz clock */ |
176 | cur_clock = | |
177 | muldiv64(current_time, RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND); | |
178 | ||
179 | /* | |
180 | * if the periodic timer's update is due to period re-configuration, | |
181 | * we should count the clock since last interrupt. | |
182 | */ | |
7a3e29b1 | 183 | if (old_period && period_change) { |
b429de73 MT |
184 | int64_t last_periodic_clock, next_periodic_clock; |
185 | ||
186 | next_periodic_clock = muldiv64(s->next_periodic_time, | |
187 | RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND); | |
188 | last_periodic_clock = next_periodic_clock - old_period; | |
189 | lost_clock = cur_clock - last_periodic_clock; | |
190 | assert(lost_clock >= 0); | |
3ae32adf | 191 | } |
369b4135 | 192 | |
3ae32adf PB |
193 | /* |
194 | * s->irq_coalesced can change for two reasons: | |
195 | * | |
196 | * a) if one or more periodic timer interrupts have been lost, | |
197 | * lost_clock will be more that a period. | |
198 | * | |
199 | * b) when the period may be reconfigured, we expect the OS to | |
200 | * treat delayed tick as the new period. So, when switching | |
201 | * from a shorter to a longer period, scale down the missing, | |
202 | * because the OS will treat past delayed ticks as longer | |
203 | * (leftovers are put back into lost_clock). When switching | |
204 | * to a shorter period, scale up the missing ticks since the | |
205 | * OS handler will treat past delayed ticks as shorter. | |
206 | */ | |
207 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { | |
208 | uint32_t old_irq_coalesced = s->irq_coalesced; | |
209 | ||
3ae32adf PB |
210 | lost_clock += old_irq_coalesced * old_period; |
211 | s->irq_coalesced = lost_clock / s->period; | |
212 | lost_clock %= s->period; | |
213 | if (old_irq_coalesced != s->irq_coalesced || | |
214 | old_period != s->period) { | |
215 | DPRINTF_C("cmos: coalesced irqs scaled from %d to %d, " | |
216 | "period scaled from %d to %d\n", old_irq_coalesced, | |
217 | s->irq_coalesced, old_period, s->period); | |
218 | rtc_coalesced_timer_update(s); | |
219 | } | |
220 | } else { | |
369b4135 | 221 | /* |
3ae32adf PB |
222 | * no way to compensate the interrupt if LOST_TICK_POLICY_SLEW |
223 | * is not used, we should make the time progress anyway. | |
369b4135 | 224 | */ |
3ae32adf | 225 | lost_clock = MIN(lost_clock, period); |
b429de73 | 226 | } |
369b4135 | 227 | |
b429de73 | 228 | assert(lost_clock >= 0 && lost_clock <= period); |
369b4135 | 229 | |
b429de73 MT |
230 | next_irq_clock = cur_clock + period - lost_clock; |
231 | s->next_periodic_time = periodic_clock_to_ns(next_irq_clock) + 1; | |
232 | timer_mod(s->periodic_timer, s->next_periodic_time); | |
dff38e7b FB |
233 | } |
234 | ||
235 | static void rtc_periodic_timer(void *opaque) | |
236 | { | |
237 | RTCState *s = opaque; | |
238 | ||
7a3e29b1 | 239 | periodic_timer_update(s, s->next_periodic_time, s->period, false); |
663447d4 | 240 | s->cmos_data[RTC_REG_C] |= REG_C_PF; |
100d9891 | 241 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { |
663447d4 | 242 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
104059da | 243 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
ba32edab | 244 | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT) |
e0c8b950 XG |
245 | s->irq_reinject_on_ack_count = 0; |
246 | if (!rtc_policy_slew_deliver_irq(s)) { | |
93b66569 AL |
247 | s->irq_coalesced++; |
248 | rtc_coalesced_timer_update(s); | |
aa6f63ff BS |
249 | DPRINTF_C("cmos: coalesced irqs increased to %d\n", |
250 | s->irq_coalesced); | |
93b66569 AL |
251 | } |
252 | } else | |
e0c8b950 | 253 | qemu_irq_raise(s->irq); |
100d9891 | 254 | } |
dff38e7b | 255 | } |
80cabfad | 256 | |
56038ef6 YZ |
257 | /* handle update-ended timer */ |
258 | static void check_update_timer(RTCState *s) | |
259 | { | |
260 | uint64_t next_update_time; | |
261 | uint64_t guest_nsec; | |
00cf5774 | 262 | int next_alarm_sec; |
56038ef6 | 263 | |
41a9b8b2 YZ |
264 | /* From the data sheet: "Holding the dividers in reset prevents |
265 | * interrupts from operating, while setting the SET bit allows" | |
6a51d83a | 266 | * them to occur. |
56038ef6 | 267 | */ |
41a9b8b2 | 268 | if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { |
33f21e4f | 269 | assert((s->cmos_data[RTC_REG_A] & REG_A_UIP) == 0); |
bc72ad67 | 270 | timer_del(s->update_timer); |
41a9b8b2 YZ |
271 | return; |
272 | } | |
56038ef6 | 273 | |
13566fe3 | 274 | guest_nsec = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND; |
884f17c2 | 275 | next_update_time = qemu_clock_get_ns(rtc_clock) |
13566fe3 | 276 | + NANOSECONDS_PER_SECOND - guest_nsec; |
00cf5774 PB |
277 | |
278 | /* Compute time of next alarm. One second is already accounted | |
279 | * for in next_update_time. | |
280 | */ | |
281 | next_alarm_sec = get_next_alarm(s); | |
13566fe3 SH |
282 | s->next_alarm_time = next_update_time + |
283 | (next_alarm_sec - 1) * NANOSECONDS_PER_SECOND; | |
00cf5774 | 284 | |
33f21e4f PB |
285 | /* If update_in_progress latched the UIP bit, we must keep the timer |
286 | * programmed to the next second, so that UIP is cleared. Otherwise, | |
287 | * if UF is already set, we might be able to optimize. | |
288 | */ | |
289 | if (!(s->cmos_data[RTC_REG_A] & REG_A_UIP) && | |
290 | (s->cmos_data[RTC_REG_C] & REG_C_UF)) { | |
6a51d83a PB |
291 | /* If AF cannot change (i.e. either it is set already, or |
292 | * SET=1 and then the time is not updated), nothing to do. | |
293 | */ | |
294 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) || | |
295 | (s->cmos_data[RTC_REG_C] & REG_C_AF)) { | |
296 | timer_del(s->update_timer); | |
297 | return; | |
298 | } | |
299 | ||
00cf5774 PB |
300 | /* UF is set, but AF is clear. Program the timer to target |
301 | * the alarm time. */ | |
302 | next_update_time = s->next_alarm_time; | |
303 | } | |
e93379b0 | 304 | if (next_update_time != timer_expire_time_ns(s->update_timer)) { |
bc72ad67 | 305 | timer_mod(s->update_timer, next_update_time); |
56038ef6 YZ |
306 | } |
307 | } | |
308 | ||
309 | static inline uint8_t convert_hour(RTCState *s, uint8_t hour) | |
310 | { | |
311 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { | |
312 | hour %= 12; | |
313 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
314 | hour += 12; | |
315 | } | |
316 | } | |
317 | return hour; | |
318 | } | |
319 | ||
00cf5774 | 320 | static uint64_t get_next_alarm(RTCState *s) |
56038ef6 | 321 | { |
00cf5774 PB |
322 | int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec; |
323 | int32_t hour, min, sec; | |
324 | ||
325 | rtc_update_time(s); | |
56038ef6 YZ |
326 | |
327 | alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]); | |
328 | alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]); | |
329 | alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]); | |
00cf5774 | 330 | alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour); |
56038ef6 YZ |
331 | |
332 | cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); | |
333 | cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
334 | cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]); | |
335 | cur_hour = convert_hour(s, cur_hour); | |
336 | ||
00cf5774 PB |
337 | if (alarm_hour == -1) { |
338 | alarm_hour = cur_hour; | |
339 | if (alarm_min == -1) { | |
340 | alarm_min = cur_min; | |
341 | if (alarm_sec == -1) { | |
342 | alarm_sec = cur_sec + 1; | |
343 | } else if (cur_sec > alarm_sec) { | |
344 | alarm_min++; | |
345 | } | |
346 | } else if (cur_min == alarm_min) { | |
347 | if (alarm_sec == -1) { | |
348 | alarm_sec = cur_sec + 1; | |
349 | } else { | |
350 | if (cur_sec > alarm_sec) { | |
351 | alarm_hour++; | |
352 | } | |
353 | } | |
354 | if (alarm_sec == SEC_PER_MIN) { | |
355 | /* wrap to next hour, minutes is not in don't care mode */ | |
356 | alarm_sec = 0; | |
357 | alarm_hour++; | |
358 | } | |
359 | } else if (cur_min > alarm_min) { | |
360 | alarm_hour++; | |
361 | } | |
362 | } else if (cur_hour == alarm_hour) { | |
363 | if (alarm_min == -1) { | |
364 | alarm_min = cur_min; | |
365 | if (alarm_sec == -1) { | |
366 | alarm_sec = cur_sec + 1; | |
367 | } else if (cur_sec > alarm_sec) { | |
368 | alarm_min++; | |
369 | } | |
370 | ||
371 | if (alarm_sec == SEC_PER_MIN) { | |
372 | alarm_sec = 0; | |
373 | alarm_min++; | |
374 | } | |
375 | /* wrap to next day, hour is not in don't care mode */ | |
376 | alarm_min %= MIN_PER_HOUR; | |
377 | } else if (cur_min == alarm_min) { | |
378 | if (alarm_sec == -1) { | |
379 | alarm_sec = cur_sec + 1; | |
380 | } | |
381 | /* wrap to next day, hours+minutes not in don't care mode */ | |
382 | alarm_sec %= SEC_PER_MIN; | |
383 | } | |
56038ef6 | 384 | } |
56038ef6 | 385 | |
00cf5774 PB |
386 | /* values that are still don't care fire at the next min/sec */ |
387 | if (alarm_min == -1) { | |
388 | alarm_min = 0; | |
389 | } | |
390 | if (alarm_sec == -1) { | |
391 | alarm_sec = 0; | |
392 | } | |
393 | ||
394 | /* keep values in range */ | |
395 | if (alarm_sec == SEC_PER_MIN) { | |
396 | alarm_sec = 0; | |
397 | alarm_min++; | |
398 | } | |
399 | if (alarm_min == MIN_PER_HOUR) { | |
400 | alarm_min = 0; | |
401 | alarm_hour++; | |
402 | } | |
403 | alarm_hour %= HOUR_PER_DAY; | |
404 | ||
405 | hour = alarm_hour - cur_hour; | |
406 | min = hour * MIN_PER_HOUR + alarm_min - cur_min; | |
407 | sec = min * SEC_PER_MIN + alarm_sec - cur_sec; | |
408 | return sec <= 0 ? sec + SEC_PER_DAY : sec; | |
56038ef6 YZ |
409 | } |
410 | ||
411 | static void rtc_update_timer(void *opaque) | |
412 | { | |
413 | RTCState *s = opaque; | |
414 | int32_t irqs = REG_C_UF; | |
415 | int32_t new_irqs; | |
416 | ||
41a9b8b2 YZ |
417 | assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60); |
418 | ||
56038ef6 YZ |
419 | /* UIP might have been latched, update time and clear it. */ |
420 | rtc_update_time(s); | |
421 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
422 | ||
884f17c2 | 423 | if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) { |
56038ef6 YZ |
424 | irqs |= REG_C_AF; |
425 | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { | |
fb064112 | 426 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC, NULL); |
56038ef6 YZ |
427 | } |
428 | } | |
00cf5774 | 429 | |
56038ef6 YZ |
430 | new_irqs = irqs & ~s->cmos_data[RTC_REG_C]; |
431 | s->cmos_data[RTC_REG_C] |= irqs; | |
432 | if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) { | |
433 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
434 | qemu_irq_raise(s->irq); | |
435 | } | |
436 | check_update_timer(s); | |
437 | } | |
438 | ||
0da8c842 AG |
439 | static void cmos_ioport_write(void *opaque, hwaddr addr, |
440 | uint64_t data, unsigned size) | |
80cabfad | 441 | { |
b41a2cd1 | 442 | RTCState *s = opaque; |
369b4135 | 443 | uint32_t old_period; |
9a6e2dcf | 444 | bool update_periodic_timer; |
80cabfad FB |
445 | |
446 | if ((addr & 1) == 0) { | |
447 | s->cmos_index = data & 0x7f; | |
448 | } else { | |
c5539cb4 | 449 | CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n", |
ec51e364 | 450 | s->cmos_index, data); |
dff38e7b | 451 | switch(s->cmos_index) { |
80cabfad FB |
452 | case RTC_SECONDS_ALARM: |
453 | case RTC_MINUTES_ALARM: | |
454 | case RTC_HOURS_ALARM: | |
80cabfad | 455 | s->cmos_data[s->cmos_index] = data; |
56038ef6 | 456 | check_update_timer(s); |
80cabfad | 457 | break; |
7cd9681b | 458 | case RTC_IBM_PS2_CENTURY_BYTE: |
e67edb94 PB |
459 | s->cmos_index = RTC_CENTURY; |
460 | /* fall through */ | |
461 | case RTC_CENTURY: | |
80cabfad FB |
462 | case RTC_SECONDS: |
463 | case RTC_MINUTES: | |
464 | case RTC_HOURS: | |
465 | case RTC_DAY_OF_WEEK: | |
466 | case RTC_DAY_OF_MONTH: | |
467 | case RTC_MONTH: | |
468 | case RTC_YEAR: | |
469 | s->cmos_data[s->cmos_index] = data; | |
dff38e7b | 470 | /* if in set mode, do not update the time */ |
41a9b8b2 | 471 | if (rtc_running(s)) { |
dff38e7b | 472 | rtc_set_time(s); |
56038ef6 | 473 | check_update_timer(s); |
dff38e7b | 474 | } |
80cabfad FB |
475 | break; |
476 | case RTC_REG_A: | |
9a6e2dcf | 477 | update_periodic_timer = (s->cmos_data[RTC_REG_A] ^ data) & 0x0f; |
369b4135 | 478 | old_period = rtc_periodic_clock_ticks(s); |
9a6e2dcf | 479 | |
41a9b8b2 YZ |
480 | if ((data & 0x60) == 0x60) { |
481 | if (rtc_running(s)) { | |
482 | rtc_update_time(s); | |
483 | } | |
484 | /* What happens to UIP when divider reset is enabled is | |
485 | * unclear from the datasheet. Shouldn't matter much | |
486 | * though. | |
487 | */ | |
488 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
489 | } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && | |
490 | (data & 0x70) <= 0x20) { | |
491 | /* when the divider reset is removed, the first update cycle | |
492 | * begins one-half second later*/ | |
493 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
494 | s->offset = 500000000; | |
495 | rtc_set_time(s); | |
496 | } | |
497 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
498 | } | |
dff38e7b FB |
499 | /* UIP bit is read only */ |
500 | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | | |
501 | (s->cmos_data[RTC_REG_A] & REG_A_UIP); | |
9a6e2dcf XG |
502 | |
503 | if (update_periodic_timer) { | |
369b4135 | 504 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), |
7a3e29b1 | 505 | old_period, true); |
9a6e2dcf XG |
506 | } |
507 | ||
56038ef6 | 508 | check_update_timer(s); |
dff38e7b | 509 | break; |
80cabfad | 510 | case RTC_REG_B: |
9a6e2dcf XG |
511 | update_periodic_timer = (s->cmos_data[RTC_REG_B] ^ data) |
512 | & REG_B_PIE; | |
369b4135 | 513 | old_period = rtc_periodic_clock_ticks(s); |
9a6e2dcf | 514 | |
dff38e7b | 515 | if (data & REG_B_SET) { |
56038ef6 | 516 | /* update cmos to when the rtc was stopping */ |
41a9b8b2 | 517 | if (rtc_running(s)) { |
56038ef6 YZ |
518 | rtc_update_time(s); |
519 | } | |
dff38e7b FB |
520 | /* set mode: reset UIP mode */ |
521 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
522 | data &= ~REG_B_UIE; | |
523 | } else { | |
524 | /* if disabling set mode, update the time */ | |
41a9b8b2 YZ |
525 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) && |
526 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { | |
13566fe3 | 527 | s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND; |
dff38e7b FB |
528 | rtc_set_time(s); |
529 | } | |
530 | } | |
9324cc50 YZ |
531 | /* if an interrupt flag is already set when the interrupt |
532 | * becomes enabled, raise an interrupt immediately. */ | |
533 | if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) { | |
534 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
535 | qemu_irq_raise(s->irq); | |
536 | } else { | |
537 | s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF; | |
538 | qemu_irq_lower(s->irq); | |
539 | } | |
bedc572e | 540 | s->cmos_data[RTC_REG_B] = data; |
9a6e2dcf XG |
541 | |
542 | if (update_periodic_timer) { | |
369b4135 | 543 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), |
7a3e29b1 | 544 | old_period, true); |
9a6e2dcf XG |
545 | } |
546 | ||
56038ef6 | 547 | check_update_timer(s); |
80cabfad FB |
548 | break; |
549 | case RTC_REG_C: | |
550 | case RTC_REG_D: | |
551 | /* cannot write to them */ | |
552 | break; | |
553 | default: | |
554 | s->cmos_data[s->cmos_index] = data; | |
555 | break; | |
556 | } | |
557 | } | |
558 | } | |
559 | ||
abd0c6bd | 560 | static inline int rtc_to_bcd(RTCState *s, int a) |
80cabfad | 561 | { |
6f1bf24d | 562 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
563 | return a; |
564 | } else { | |
565 | return ((a / 10) << 4) | (a % 10); | |
566 | } | |
80cabfad FB |
567 | } |
568 | ||
abd0c6bd | 569 | static inline int rtc_from_bcd(RTCState *s, int a) |
80cabfad | 570 | { |
00cf5774 PB |
571 | if ((a & 0xc0) == 0xc0) { |
572 | return -1; | |
573 | } | |
6f1bf24d | 574 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
575 | return a; |
576 | } else { | |
577 | return ((a >> 4) * 10) + (a & 0x0f); | |
578 | } | |
579 | } | |
580 | ||
e2826cf4 | 581 | static void rtc_get_time(RTCState *s, struct tm *tm) |
dff38e7b | 582 | { |
abd0c6bd PB |
583 | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
584 | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
585 | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); | |
3b89eb43 PB |
586 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { |
587 | tm->tm_hour %= 12; | |
588 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
589 | tm->tm_hour += 12; | |
590 | } | |
43f493af | 591 | } |
abd0c6bd PB |
592 | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1; |
593 | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); | |
594 | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; | |
b8994faf PB |
595 | tm->tm_year = |
596 | rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year + | |
597 | rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900; | |
e2826cf4 PB |
598 | } |
599 | ||
600 | static void rtc_set_time(RTCState *s) | |
601 | { | |
602 | struct tm tm; | |
2beb1e5f | 603 | g_autofree const char *qom_path = object_get_canonical_path(OBJECT(s)); |
80cd3478 | 604 | |
e2826cf4 | 605 | rtc_get_time(s, &tm); |
e2826cf4 | 606 | s->base_rtc = mktimegm(&tm); |
884f17c2 | 607 | s->last_update = qemu_clock_get_ns(rtc_clock); |
56038ef6 | 608 | |
2beb1e5f | 609 | qapi_event_send_rtc_change(qemu_timedate_diff(&tm), qom_path); |
43f493af FB |
610 | } |
611 | ||
e2826cf4 | 612 | static void rtc_set_cmos(RTCState *s, const struct tm *tm) |
43f493af | 613 | { |
42fc73a1 | 614 | int year; |
dff38e7b | 615 | |
abd0c6bd PB |
616 | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
617 | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); | |
c29cd656 | 618 | if (s->cmos_data[RTC_REG_B] & REG_B_24H) { |
43f493af | 619 | /* 24 hour format */ |
abd0c6bd | 620 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
43f493af FB |
621 | } else { |
622 | /* 12 hour format */ | |
3b89eb43 PB |
623 | int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12; |
624 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h); | |
43f493af FB |
625 | if (tm->tm_hour >= 12) |
626 | s->cmos_data[RTC_HOURS] |= 0x80; | |
627 | } | |
abd0c6bd PB |
628 | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1); |
629 | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); | |
630 | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1); | |
b8994faf PB |
631 | year = tm->tm_year + 1900 - s->base_year; |
632 | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100); | |
633 | s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100); | |
43f493af FB |
634 | } |
635 | ||
56038ef6 | 636 | static void rtc_update_time(RTCState *s) |
43f493af | 637 | { |
56038ef6 YZ |
638 | struct tm ret; |
639 | time_t guest_sec; | |
640 | int64_t guest_nsec; | |
641 | ||
642 | guest_nsec = get_guest_rtc_ns(s); | |
13566fe3 | 643 | guest_sec = guest_nsec / NANOSECONDS_PER_SECOND; |
56038ef6 | 644 | gmtime_r(&guest_sec, &ret); |
02c6ccc6 AH |
645 | |
646 | /* Is SET flag of Register B disabled? */ | |
647 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) { | |
648 | rtc_set_cmos(s, &ret); | |
649 | } | |
43f493af FB |
650 | } |
651 | ||
56038ef6 | 652 | static int update_in_progress(RTCState *s) |
43f493af | 653 | { |
56038ef6 | 654 | int64_t guest_nsec; |
3b46e624 | 655 | |
41a9b8b2 | 656 | if (!rtc_running(s)) { |
56038ef6 | 657 | return 0; |
dff38e7b | 658 | } |
e93379b0 AB |
659 | if (timer_pending(s->update_timer)) { |
660 | int64_t next_update_time = timer_expire_time_ns(s->update_timer); | |
56038ef6 | 661 | /* Latch UIP until the timer expires. */ |
884f17c2 AB |
662 | if (qemu_clock_get_ns(rtc_clock) >= |
663 | (next_update_time - UIP_HOLD_LENGTH)) { | |
56038ef6 YZ |
664 | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
665 | return 1; | |
dff38e7b FB |
666 | } |
667 | } | |
668 | ||
56038ef6 YZ |
669 | guest_nsec = get_guest_rtc_ns(s); |
670 | /* UIP bit will be set at last 244us of every second. */ | |
13566fe3 SH |
671 | if ((guest_nsec % NANOSECONDS_PER_SECOND) >= |
672 | (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)) { | |
56038ef6 | 673 | return 1; |
dff38e7b | 674 | } |
56038ef6 | 675 | return 0; |
80cabfad FB |
676 | } |
677 | ||
0da8c842 AG |
678 | static uint64_t cmos_ioport_read(void *opaque, hwaddr addr, |
679 | unsigned size) | |
80cabfad | 680 | { |
b41a2cd1 | 681 | RTCState *s = opaque; |
80cabfad FB |
682 | int ret; |
683 | if ((addr & 1) == 0) { | |
684 | return 0xff; | |
685 | } else { | |
686 | switch(s->cmos_index) { | |
7cd9681b | 687 | case RTC_IBM_PS2_CENTURY_BYTE: |
e67edb94 PB |
688 | s->cmos_index = RTC_CENTURY; |
689 | /* fall through */ | |
690 | case RTC_CENTURY: | |
80cabfad FB |
691 | case RTC_SECONDS: |
692 | case RTC_MINUTES: | |
693 | case RTC_HOURS: | |
694 | case RTC_DAY_OF_WEEK: | |
695 | case RTC_DAY_OF_MONTH: | |
696 | case RTC_MONTH: | |
697 | case RTC_YEAR: | |
56038ef6 YZ |
698 | /* if not in set mode, calibrate cmos before |
699 | * reading*/ | |
41a9b8b2 | 700 | if (rtc_running(s)) { |
56038ef6 YZ |
701 | rtc_update_time(s); |
702 | } | |
80cabfad FB |
703 | ret = s->cmos_data[s->cmos_index]; |
704 | break; | |
705 | case RTC_REG_A: | |
33f21e4f | 706 | ret = s->cmos_data[s->cmos_index]; |
56038ef6 | 707 | if (update_in_progress(s)) { |
33f21e4f | 708 | ret |= REG_A_UIP; |
56038ef6 | 709 | } |
80cabfad FB |
710 | break; |
711 | case RTC_REG_C: | |
712 | ret = s->cmos_data[s->cmos_index]; | |
d537cf6c | 713 | qemu_irq_lower(s->irq); |
fbc15e27 | 714 | s->cmos_data[RTC_REG_C] = 0x00; |
56038ef6 YZ |
715 | if (ret & (REG_C_UF | REG_C_AF)) { |
716 | check_update_timer(s); | |
717 | } | |
e0c8b950 | 718 | |
ba32edab | 719 | if(s->irq_coalesced && |
fbc15e27 | 720 | (s->cmos_data[RTC_REG_B] & REG_B_PIE) && |
ba32edab GN |
721 | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
722 | s->irq_reinject_on_ack_count++; | |
fbc15e27 | 723 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF; |
aa6f63ff | 724 | DPRINTF_C("cmos: injecting on ack\n"); |
e0c8b950 | 725 | if (rtc_policy_slew_deliver_irq(s)) { |
ba32edab | 726 | s->irq_coalesced--; |
aa6f63ff BS |
727 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
728 | s->irq_coalesced); | |
729 | } | |
ba32edab | 730 | } |
80cabfad FB |
731 | break; |
732 | default: | |
733 | ret = s->cmos_data[s->cmos_index]; | |
734 | break; | |
735 | } | |
ec51e364 IY |
736 | CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n", |
737 | s->cmos_index, ret); | |
80cabfad FB |
738 | return ret; |
739 | } | |
740 | } | |
741 | ||
1d914fa0 | 742 | void rtc_set_memory(ISADevice *dev, int addr, int val) |
dff38e7b | 743 | { |
0e41271e | 744 | RTCState *s = MC146818_RTC(dev); |
dff38e7b FB |
745 | if (addr >= 0 && addr <= 127) |
746 | s->cmos_data[addr] = val; | |
747 | } | |
748 | ||
b8b7456d IM |
749 | int rtc_get_memory(ISADevice *dev, int addr) |
750 | { | |
751 | RTCState *s = MC146818_RTC(dev); | |
752 | assert(addr >= 0 && addr <= 127); | |
753 | return s->cmos_data[addr]; | |
754 | } | |
755 | ||
1d914fa0 | 756 | static void rtc_set_date_from_host(ISADevice *dev) |
ea55ffb3 | 757 | { |
0e41271e | 758 | RTCState *s = MC146818_RTC(dev); |
f6503059 | 759 | struct tm tm; |
ea55ffb3 | 760 | |
f6503059 | 761 | qemu_get_timedate(&tm, 0); |
56038ef6 YZ |
762 | |
763 | s->base_rtc = mktimegm(&tm); | |
884f17c2 | 764 | s->last_update = qemu_clock_get_ns(rtc_clock); |
56038ef6 YZ |
765 | s->offset = 0; |
766 | ||
767 | /* set the CMOS date */ | |
e2826cf4 | 768 | rtc_set_cmos(s, &tm); |
ea55ffb3 TS |
769 | } |
770 | ||
44b1ff31 | 771 | static int rtc_pre_save(void *opaque) |
3cf294ee JB |
772 | { |
773 | RTCState *s = opaque; | |
774 | ||
775 | rtc_update_time(s); | |
44b1ff31 DDAG |
776 | |
777 | return 0; | |
3cf294ee JB |
778 | } |
779 | ||
6b075b8a | 780 | static int rtc_post_load(void *opaque, int version_id) |
80cabfad | 781 | { |
dff38e7b FB |
782 | RTCState *s = opaque; |
783 | ||
3cf294ee | 784 | if (version_id <= 2 || rtc_clock == QEMU_CLOCK_REALTIME) { |
56038ef6 YZ |
785 | rtc_set_time(s); |
786 | s->offset = 0; | |
787 | check_update_timer(s); | |
788 | } | |
7a3e29b1 | 789 | s->period = rtc_periodic_clock_ticks(s); |
56038ef6 | 790 | |
1dfb1b2d PD |
791 | /* The periodic timer is deterministic in record/replay mode, |
792 | * so there is no need to update it after loading the vmstate. | |
793 | * Reading RTC here would misalign record and replay. | |
794 | */ | |
795 | if (replay_mode == REPLAY_MODE_NONE) { | |
796 | uint64_t now = qemu_clock_get_ns(rtc_clock); | |
797 | if (now < s->next_periodic_time || | |
798 | now > (s->next_periodic_time + get_max_clock_jump())) { | |
7a3e29b1 | 799 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), s->period, false); |
1dfb1b2d | 800 | } |
ae46e239 PD |
801 | } |
802 | ||
048c74c4 | 803 | if (version_id >= 2) { |
104059da | 804 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
048c74c4 JQ |
805 | rtc_coalesced_timer_update(s); |
806 | } | |
048c74c4 | 807 | } |
73822ec8 AL |
808 | return 0; |
809 | } | |
73822ec8 | 810 | |
5cd8cada JQ |
811 | static bool rtc_irq_reinject_on_ack_count_needed(void *opaque) |
812 | { | |
813 | RTCState *s = (RTCState *)opaque; | |
814 | return s->irq_reinject_on_ack_count != 0; | |
815 | } | |
816 | ||
0b102153 | 817 | static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = { |
bb426311 | 818 | .name = "mc146818rtc/irq_reinject_on_ack_count", |
0b102153 PD |
819 | .version_id = 1, |
820 | .minimum_version_id = 1, | |
5cd8cada | 821 | .needed = rtc_irq_reinject_on_ack_count_needed, |
0b102153 PD |
822 | .fields = (VMStateField[]) { |
823 | VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState), | |
824 | VMSTATE_END_OF_LIST() | |
825 | } | |
826 | }; | |
827 | ||
6b075b8a JQ |
828 | static const VMStateDescription vmstate_rtc = { |
829 | .name = "mc146818rtc", | |
56038ef6 | 830 | .version_id = 3, |
6b075b8a | 831 | .minimum_version_id = 1, |
3cf294ee | 832 | .pre_save = rtc_pre_save, |
6b075b8a | 833 | .post_load = rtc_post_load, |
d49805ae | 834 | .fields = (VMStateField[]) { |
6b075b8a JQ |
835 | VMSTATE_BUFFER(cmos_data, RTCState), |
836 | VMSTATE_UINT8(cmos_index, RTCState), | |
89166459 | 837 | VMSTATE_UNUSED(7*4), |
e720677e | 838 | VMSTATE_TIMER_PTR(periodic_timer, RTCState), |
6b075b8a | 839 | VMSTATE_INT64(next_periodic_time, RTCState), |
56038ef6 | 840 | VMSTATE_UNUSED(3*8), |
6b075b8a JQ |
841 | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), |
842 | VMSTATE_UINT32_V(period, RTCState, 2), | |
56038ef6 YZ |
843 | VMSTATE_UINT64_V(base_rtc, RTCState, 3), |
844 | VMSTATE_UINT64_V(last_update, RTCState, 3), | |
845 | VMSTATE_INT64_V(offset, RTCState, 3), | |
e720677e | 846 | VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3), |
00cf5774 | 847 | VMSTATE_UINT64_V(next_alarm_time, RTCState, 3), |
6b075b8a | 848 | VMSTATE_END_OF_LIST() |
0b102153 | 849 | }, |
5cd8cada JQ |
850 | .subsections = (const VMStateDescription*[]) { |
851 | &vmstate_rtc_irq_reinject_on_ack_count, | |
852 | NULL | |
6b075b8a JQ |
853 | } |
854 | }; | |
855 | ||
da98c8eb GH |
856 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
857 | BIOS will read it and start S3 resume at POST Entry */ | |
858 | static void rtc_notify_suspend(Notifier *notifier, void *data) | |
859 | { | |
860 | RTCState *s = container_of(notifier, RTCState, suspend_notifier); | |
0e41271e | 861 | rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE); |
da98c8eb GH |
862 | } |
863 | ||
b2c5009b | 864 | static const MemoryRegionOps cmos_ops = { |
0da8c842 AG |
865 | .read = cmos_ioport_read, |
866 | .write = cmos_ioport_write, | |
867 | .impl = { | |
868 | .min_access_size = 1, | |
869 | .max_access_size = 1, | |
870 | }, | |
871 | .endianness = DEVICE_LITTLE_ENDIAN, | |
b2c5009b RH |
872 | }; |
873 | ||
8e099d14 | 874 | static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp) |
18297050 | 875 | { |
0e41271e | 876 | RTCState *s = MC146818_RTC(obj); |
18297050 | 877 | |
56038ef6 | 878 | rtc_update_time(s); |
8e099d14 | 879 | rtc_get_time(s, current_tm); |
18297050 AL |
880 | } |
881 | ||
db895a1e | 882 | static void rtc_realizefn(DeviceState *dev, Error **errp) |
dff38e7b | 883 | { |
db895a1e | 884 | ISADevice *isadev = ISA_DEVICE(dev); |
0e41271e | 885 | RTCState *s = MC146818_RTC(dev); |
80cabfad | 886 | |
80cabfad FB |
887 | s->cmos_data[RTC_REG_A] = 0x26; |
888 | s->cmos_data[RTC_REG_B] = 0x02; | |
889 | s->cmos_data[RTC_REG_C] = 0x00; | |
890 | s->cmos_data[RTC_REG_D] = 0x80; | |
891 | ||
b8994faf PB |
892 | /* This is for historical reasons. The default base year qdev property |
893 | * was set to 2000 for most machine types before the century byte was | |
894 | * implemented. | |
895 | * | |
896 | * This if statement means that the century byte will be always 0 | |
897 | * (at least until 2079...) for base_year = 1980, but will be set | |
898 | * correctly for base_year = 2000. | |
899 | */ | |
900 | if (s->base_year == 2000) { | |
901 | s->base_year = 0; | |
902 | } | |
903 | ||
3b004a16 BB |
904 | if (s->isairq >= ISA_NUM_IRQS) { |
905 | error_setg(errp, "Maximum value for \"irq\" is: %u", ISA_NUM_IRQS - 1); | |
906 | return; | |
907 | } | |
908 | ||
db895a1e | 909 | rtc_set_date_from_host(isadev); |
ea55ffb3 | 910 | |
433acf0d | 911 | switch (s->lost_tick_policy) { |
104059da | 912 | case LOST_TICK_POLICY_SLEW: |
6875204c | 913 | s->coalesced_timer = |
884f17c2 | 914 | timer_new_ns(rtc_clock, rtc_coalesced_timer, s); |
433acf0d | 915 | break; |
104059da | 916 | case LOST_TICK_POLICY_DISCARD: |
433acf0d JK |
917 | break; |
918 | default: | |
db895a1e AF |
919 | error_setg(errp, "Invalid lost tick policy."); |
920 | return; | |
433acf0d | 921 | } |
433acf0d | 922 | |
884f17c2 AB |
923 | s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s); |
924 | s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s); | |
56038ef6 | 925 | check_update_timer(s); |
dff38e7b | 926 | |
da98c8eb GH |
927 | s->suspend_notifier.notify = rtc_notify_suspend; |
928 | qemu_register_suspend_notifier(&s->suspend_notifier); | |
929 | ||
853dca12 | 930 | memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2); |
5b21b331 | 931 | isa_register_ioport(isadev, &s->io, s->io_base); |
dff38e7b | 932 | |
f98167ea PH |
933 | /* register rtc 0x70 port for coalesced_pio */ |
934 | memory_region_set_flush_coalesced(&s->io); | |
935 | memory_region_init_io(&s->coalesced_io, OBJECT(s), &cmos_ops, | |
936 | s, "rtc-index", 1); | |
937 | memory_region_add_subregion(&s->io, 0, &s->coalesced_io); | |
938 | memory_region_add_coalescing(&s->coalesced_io, 0, 1); | |
939 | ||
5b21b331 | 940 | qdev_set_legacy_instance_id(dev, s->io_base, 3); |
18297050 | 941 | |
d2623129 | 942 | object_property_add_tm(OBJECT(s), "date", rtc_get_date); |
654a36d8 | 943 | |
3638439d | 944 | qdev_init_gpio_out(dev, &s->irq, 1); |
df84f17d | 945 | QLIST_INSERT_HEAD(&rtc_devices, s, link); |
32e0c826 GH |
946 | } |
947 | ||
6c646a11 | 948 | ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq) |
32e0c826 | 949 | { |
0e41271e AF |
950 | DeviceState *dev; |
951 | ISADevice *isadev; | |
3b004a16 | 952 | RTCState *s; |
eeb7c03c | 953 | |
96927c74 | 954 | isadev = isa_new(TYPE_MC146818_RTC); |
0e41271e | 955 | dev = DEVICE(isadev); |
3b004a16 | 956 | s = MC146818_RTC(isadev); |
0e41271e | 957 | qdev_prop_set_int32(dev, "base_year", base_year); |
96927c74 | 958 | isa_realize_and_unref(isadev, bus, &error_fatal); |
7d932dfd | 959 | if (intercept_irq) { |
3638439d | 960 | qdev_connect_gpio_out(dev, 0, intercept_irq); |
7d932dfd | 961 | } else { |
3b004a16 | 962 | isa_connect_gpio_out(isadev, 0, s->isairq); |
7d932dfd | 963 | } |
f2ae8abf | 964 | |
df84f17d | 965 | object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isadev), |
d2623129 | 966 | "date"); |
29551fdc | 967 | |
0e41271e | 968 | return isadev; |
80cabfad FB |
969 | } |
970 | ||
39bffca2 AL |
971 | static Property mc146818rtc_properties[] = { |
972 | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), | |
5b21b331 | 973 | DEFINE_PROP_UINT16("iobase", RTCState, io_base, RTC_ISA_BASE), |
3b004a16 | 974 | DEFINE_PROP_UINT8("irq", RTCState, isairq, RTC_ISA_IRQ), |
39bffca2 | 975 | DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState, |
104059da | 976 | lost_tick_policy, LOST_TICK_POLICY_DISCARD), |
39bffca2 AL |
977 | DEFINE_PROP_END_OF_LIST(), |
978 | }; | |
979 | ||
fae5a042 | 980 | static void rtc_reset_enter(Object *obj, ResetType type) |
bf7bb91e | 981 | { |
fae5a042 | 982 | RTCState *s = MC146818_RTC(obj); |
bf7bb91e | 983 | |
984 | /* Reason: VM do suspend self will set 0xfe | |
985 | * Reset any values other than 0xfe(Guest suspend case) */ | |
986 | if (s->cmos_data[0x0f] != 0xfe) { | |
987 | s->cmos_data[0x0f] = 0x00; | |
988 | } | |
fae5a042 PMD |
989 | |
990 | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); | |
991 | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); | |
992 | check_update_timer(s); | |
993 | ||
994 | ||
995 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { | |
996 | s->irq_coalesced = 0; | |
997 | s->irq_reinject_on_ack_count = 0; | |
998 | } | |
999 | } | |
1000 | ||
1001 | static void rtc_reset_hold(Object *obj) | |
1002 | { | |
1003 | RTCState *s = MC146818_RTC(obj); | |
1004 | ||
1005 | qemu_irq_lower(s->irq); | |
bf7bb91e | 1006 | } |
1007 | ||
d9cf178c | 1008 | static void rtc_build_aml(AcpiDevAmlIf *adev, Aml *scope) |
df9b9b42 | 1009 | { |
d9cf178c | 1010 | RTCState *s = MC146818_RTC(adev); |
df9b9b42 GH |
1011 | Aml *dev; |
1012 | Aml *crs; | |
1013 | ||
f592b94f GH |
1014 | /* |
1015 | * Reserving 8 io ports here, following what physical hardware | |
1016 | * does, even though qemu only responds to the first two ports. | |
1017 | */ | |
df9b9b42 | 1018 | crs = aml_resource_template(); |
5b21b331 | 1019 | aml_append(crs, aml_io(AML_DECODE16, s->io_base, s->io_base, |
f592b94f | 1020 | 0x01, 0x08)); |
3b004a16 | 1021 | aml_append(crs, aml_irq_no_flags(s->isairq)); |
df9b9b42 GH |
1022 | |
1023 | dev = aml_device("RTC"); | |
1024 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00"))); | |
1025 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
1026 | ||
1027 | aml_append(scope, dev); | |
1028 | } | |
1029 | ||
8f04ee08 AL |
1030 | static void rtc_class_initfn(ObjectClass *klass, void *data) |
1031 | { | |
39bffca2 | 1032 | DeviceClass *dc = DEVICE_CLASS(klass); |
fae5a042 | 1033 | ResettableClass *rc = RESETTABLE_CLASS(klass); |
d9cf178c | 1034 | AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass); |
db895a1e AF |
1035 | |
1036 | dc->realize = rtc_realizefn; | |
39bffca2 | 1037 | dc->vmsd = &vmstate_rtc; |
fae5a042 PMD |
1038 | rc->phases.enter = rtc_reset_enter; |
1039 | rc->phases.hold = rtc_reset_hold; | |
d9cf178c | 1040 | adevc->build_dev_aml = rtc_build_aml; |
4f67d30b | 1041 | device_class_set_props(dc, mc146818rtc_properties); |
76d79cf3 | 1042 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
8f04ee08 AL |
1043 | } |
1044 | ||
8c43a6f0 | 1045 | static const TypeInfo mc146818rtc_info = { |
0e41271e | 1046 | .name = TYPE_MC146818_RTC, |
39bffca2 AL |
1047 | .parent = TYPE_ISA_DEVICE, |
1048 | .instance_size = sizeof(RTCState), | |
1049 | .class_init = rtc_class_initfn, | |
d9cf178c IM |
1050 | .interfaces = (InterfaceInfo[]) { |
1051 | { TYPE_ACPI_DEV_AML_IF }, | |
1052 | { }, | |
1053 | }, | |
32e0c826 GH |
1054 | }; |
1055 | ||
83f7d43a | 1056 | static void mc146818rtc_register_types(void) |
100d9891 | 1057 | { |
39bffca2 | 1058 | type_register_static(&mc146818rtc_info); |
100d9891 | 1059 | } |
83f7d43a AF |
1060 | |
1061 | type_init(mc146818rtc_register_types) |