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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
a41b2ff2
PB		 44 */
45
87ecb68b
PB		 46#include "hw.h"
47#include "pci.h"
48#include "qemu-timer.h"
49#include "net.h"
a41b2ff2 50
a41b2ff2
PB		 51/* debug RTL8139 card */
52//#define DEBUG_RTL8139 1
53
6cadb320
FB		 54#define PCI_FREQUENCY 33000000L
55
a41b2ff2
PB		 56/* debug RTL8139 card C+ mode only */
57//#define DEBUG_RTL8139CP 1
58
ccf1d14a
TS		 59/* Calculate CRCs properly on Rx packets */
60#define RTL8139_CALCULATE_RXCRC 1
a41b2ff2 61
6cadb320
FB		 62/* Uncomment to enable on-board timer interrupts */
63//#define RTL8139_ONBOARD_TIMER 1
a41b2ff2
PB		 64
65#if defined(RTL8139_CALCULATE_RXCRC)
66/* For crc32 */
67#include <zlib.h>
68#endif
69
70#define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73/* arg % size for size which is a power of 2 */
74#define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
6cadb320
FB		 77#if defined (DEBUG_RTL8139)
78# define DEBUG_PRINT(x) do { printf x ; } while (0)
79#else
80# define DEBUG_PRINT(x)
81#endif
82
a41b2ff2
PB		 83/* Symbolic offsets to registers. */
84enum RTL8139_registers {
85 MAC0 = 0, /* Ethernet hardware address. */
86 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 87 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
88 /* Dump Tally Conter control register(64bit). C+ mode only */
89 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 90 RxBuf = 0x30,
91 ChipCmd = 0x37,
92 RxBufPtr = 0x38,
93 RxBufAddr = 0x3A,
94 IntrMask = 0x3C,
95 IntrStatus = 0x3E,
96 TxConfig = 0x40,
97 RxConfig = 0x44,
98 Timer = 0x48, /* A general-purpose counter. */
99 RxMissed = 0x4C, /* 24 bits valid, write clears. */
100 Cfg9346 = 0x50,
101 Config0 = 0x51,
102 Config1 = 0x52,
103 FlashReg = 0x54,
104 MediaStatus = 0x58,
105 Config3 = 0x59,
106 Config4 = 0x5A, /* absent on RTL-8139A */
107 HltClk = 0x5B,
108 MultiIntr = 0x5C,
109 PCIRevisionID = 0x5E,
110 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
111 BasicModeCtrl = 0x62,
112 BasicModeStatus = 0x64,
113 NWayAdvert = 0x66,
114 NWayLPAR = 0x68,
115 NWayExpansion = 0x6A,
116 /* Undocumented registers, but required for proper operation. */
117 FIFOTMS = 0x70, /* FIFO Control and test. */
118 CSCR = 0x74, /* Chip Status and Configuration Register. */
119 PARA78 = 0x78,
120 PARA7c = 0x7c, /* Magic transceiver parameter register. */
121 Config5 = 0xD8, /* absent on RTL-8139A */
122 /* C+ mode */
123 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
124 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
125 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
126 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
127 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
128 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
129 TxThresh = 0xEC, /* Early Tx threshold */
130};
131
132enum ClearBitMasks {
133 MultiIntrClear = 0xF000,
134 ChipCmdClear = 0xE2,
135 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
136};
137
138enum ChipCmdBits {
139 CmdReset = 0x10,
140 CmdRxEnb = 0x08,
141 CmdTxEnb = 0x04,
142 RxBufEmpty = 0x01,
143};
144
145/* C+ mode */
146enum CplusCmdBits {
6cadb320
FB		 147 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
148 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
149 CPlusRxEnb = 0x0002,
150 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 151};
152
153/* Interrupt register bits, using my own meaningful names. */
154enum IntrStatusBits {
155 PCIErr = 0x8000,
156 PCSTimeout = 0x4000,
157 RxFIFOOver = 0x40,
158 RxUnderrun = 0x20,
159 RxOverflow = 0x10,
160 TxErr = 0x08,
161 TxOK = 0x04,
162 RxErr = 0x02,
163 RxOK = 0x01,
164
165 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
166};
167
168enum TxStatusBits {
169 TxHostOwns = 0x2000,
170 TxUnderrun = 0x4000,
171 TxStatOK = 0x8000,
172 TxOutOfWindow = 0x20000000,
173 TxAborted = 0x40000000,
174 TxCarrierLost = 0x80000000,
175};
176enum RxStatusBits {
177 RxMulticast = 0x8000,
178 RxPhysical = 0x4000,
179 RxBroadcast = 0x2000,
180 RxBadSymbol = 0x0020,
181 RxRunt = 0x0010,
182 RxTooLong = 0x0008,
183 RxCRCErr = 0x0004,
184 RxBadAlign = 0x0002,
185 RxStatusOK = 0x0001,
186};
187
188/* Bits in RxConfig. */
189enum rx_mode_bits {
190 AcceptErr = 0x20,
191 AcceptRunt = 0x10,
192 AcceptBroadcast = 0x08,
193 AcceptMulticast = 0x04,
194 AcceptMyPhys = 0x02,
195 AcceptAllPhys = 0x01,
196};
197
198/* Bits in TxConfig. */
199enum tx_config_bits {
200
201 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
202 TxIFGShift = 24,
203 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
204 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
205 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
206 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
207
208 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
209 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
210 TxClearAbt = (1 << 0), /* Clear abort (WO) */
211 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
212 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
213
214 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
215};
216
217
218/* Transmit Status of All Descriptors (TSAD) Register */
219enum TSAD_bits {
220 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
221 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
222 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
223 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
224 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
225 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
226 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
227 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
228 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
229 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
230 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
231 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
232 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
233 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
234 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
235 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
236};
237
238
239/* Bits in Config1 */
240enum Config1Bits {
241 Cfg1_PM_Enable = 0x01,
242 Cfg1_VPD_Enable = 0x02,
243 Cfg1_PIO = 0x04,
244 Cfg1_MMIO = 0x08,
245 LWAKE = 0x10, /* not on 8139, 8139A */
246 Cfg1_Driver_Load = 0x20,
247 Cfg1_LED0 = 0x40,
248 Cfg1_LED1 = 0x80,
249 SLEEP = (1 << 1), /* only on 8139, 8139A */
250 PWRDN = (1 << 0), /* only on 8139, 8139A */
251};
252
253/* Bits in Config3 */
254enum Config3Bits {
255 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
256 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
257 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
258 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
259 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
260 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
261 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
262 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
263};
264
265/* Bits in Config4 */
266enum Config4Bits {
267 LWPTN = (1 << 2), /* not on 8139, 8139A */
268};
269
270/* Bits in Config5 */
271enum Config5Bits {
272 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
273 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
274 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
275 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
276 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
277 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
278 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
279};
280
281enum RxConfigBits {
282 /* rx fifo threshold */
283 RxCfgFIFOShift = 13,
284 RxCfgFIFONone = (7 << RxCfgFIFOShift),
285
286 /* Max DMA burst */
287 RxCfgDMAShift = 8,
288 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
289
290 /* rx ring buffer length */
291 RxCfgRcv8K = 0,
292 RxCfgRcv16K = (1 << 11),
293 RxCfgRcv32K = (1 << 12),
294 RxCfgRcv64K = (1 << 11) | (1 << 12),
295
296 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
297 RxNoWrap = (1 << 7),
298};
299
300/* Twister tuning parameters from RealTek.
301 Completely undocumented, but required to tune bad links on some boards. */
302/*
303enum CSCRBits {
304 CSCR_LinkOKBit = 0x0400,
305 CSCR_LinkChangeBit = 0x0800,
306 CSCR_LinkStatusBits = 0x0f000,
307 CSCR_LinkDownOffCmd = 0x003c0,
308 CSCR_LinkDownCmd = 0x0f3c0,
309*/
310enum CSCRBits {
5fafdf24 311 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 312 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
313 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
314 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 315 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 316 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
317 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
318 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
319 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
320};
321
322enum Cfg9346Bits {
323 Cfg9346_Lock = 0x00,
324 Cfg9346_Unlock = 0xC0,
325};
326
327typedef enum {
328 CH_8139 = 0,
329 CH_8139_K,
330 CH_8139A,
331 CH_8139A_G,
332 CH_8139B,
333 CH_8130,
334 CH_8139C,
335 CH_8100,
336 CH_8100B_8139D,
337 CH_8101,
338} chip_t;
339
340enum chip_flags {
341 HasHltClk = (1 << 0),
342 HasLWake = (1 << 1),
343};
344
345#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
346 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
347#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
348
6cadb320
FB		 349#define RTL8139_PCI_REVID_8139 0x10
350#define RTL8139_PCI_REVID_8139CPLUS 0x20
351
352#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
353
a41b2ff2
PB		 354/* Size is 64 * 16bit words */
355#define EEPROM_9346_ADDR_BITS 6
356#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
357#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
358
359enum Chip9346Operation
360{
361 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
362 Chip9346_op_read = 0x80, /* 10 AAAAAA */
363 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
364 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
365 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
366 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
367 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
368};
369
370enum Chip9346Mode
371{
372 Chip9346_none = 0,
373 Chip9346_enter_command_mode,
374 Chip9346_read_command,
375 Chip9346_data_read, /* from output register */
376 Chip9346_data_write, /* to input register, then to contents at specified address */
377 Chip9346_data_write_all, /* to input register, then filling contents */
378};
379
380typedef struct EEprom9346
381{
382 uint16_t contents[EEPROM_9346_SIZE];
383 int mode;
384 uint32_t tick;
385 uint8_t address;
386 uint16_t input;
387 uint16_t output;
388
389 uint8_t eecs;
390 uint8_t eesk;
391 uint8_t eedi;
392 uint8_t eedo;
393} EEprom9346;
394
6cadb320
FB		 395typedef struct RTL8139TallyCounters
396{
397 /* Tally counters */
398 uint64_t TxOk;
399 uint64_t RxOk;
400 uint64_t TxERR;
401 uint32_t RxERR;
402 uint16_t MissPkt;
403 uint16_t FAE;
404 uint32_t Tx1Col;
405 uint32_t TxMCol;
406 uint64_t RxOkPhy;
407 uint64_t RxOkBrd;
408 uint32_t RxOkMul;
409 uint16_t TxAbt;
410 uint16_t TxUndrn;
411} RTL8139TallyCounters;
412
413/* Clears all tally counters */
414static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
415
416/* Writes tally counters to specified physical memory address */
417static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
418
419/* Loads values of tally counters from VM state file */
420static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
421
422/* Saves values of tally counters to VM state file */
423static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
424
a41b2ff2
PB		 425typedef struct RTL8139State {
426 uint8_t phys[8]; /* mac address */
427 uint8_t mult[8]; /* multicast mask array */
428
6cadb320 429 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 430 uint32_t TxAddr[4]; /* TxAddr0 */
431 uint32_t RxBuf; /* Receive buffer */
432 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
433 uint32_t RxBufPtr;
434 uint32_t RxBufAddr;
435
436 uint16_t IntrStatus;
437 uint16_t IntrMask;
438
439 uint32_t TxConfig;
440 uint32_t RxConfig;
441 uint32_t RxMissed;
442
443 uint16_t CSCR;
444
445 uint8_t Cfg9346;
446 uint8_t Config0;
447 uint8_t Config1;
448 uint8_t Config3;
449 uint8_t Config4;
450 uint8_t Config5;
451
452 uint8_t clock_enabled;
453 uint8_t bChipCmdState;
454
455 uint16_t MultiIntr;
456
457 uint16_t BasicModeCtrl;
458 uint16_t BasicModeStatus;
459 uint16_t NWayAdvert;
460 uint16_t NWayLPAR;
461 uint16_t NWayExpansion;
462
463 uint16_t CpCmd;
464 uint8_t TxThresh;
465
a41b2ff2
PB		 466 PCIDevice *pci_dev;
467 VLANClientState *vc;
468 uint8_t macaddr[6];
469 int rtl8139_mmio_io_addr;
470
471 /* C ring mode */
472 uint32_t currTxDesc;
473
474 /* C+ mode */
475 uint32_t currCPlusRxDesc;
476 uint32_t currCPlusTxDesc;
477
478 uint32_t RxRingAddrLO;
479 uint32_t RxRingAddrHI;
480
481 EEprom9346 eeprom;
6cadb320
FB		 482
483 uint32_t TCTR;
484 uint32_t TimerInt;
485 int64_t TCTR_base;
486
487 /* Tally counters */
488 RTL8139TallyCounters tally_counters;
489
490 /* Non-persistent data */
491 uint8_t *cplus_txbuffer;
492 int cplus_txbuffer_len;
493 int cplus_txbuffer_offset;
494
495 /* PCI interrupt timer */
496 QEMUTimer *timer;
497
a41b2ff2
PB		 498} RTL8139State;
499
500void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
501{
6cadb320 502 DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
a41b2ff2
PB		 503
504 switch (command & Chip9346_op_mask)
505 {
506 case Chip9346_op_read:
507 {
508 eeprom->address = command & EEPROM_9346_ADDR_MASK;
509 eeprom->output = eeprom->contents[eeprom->address];
510 eeprom->eedo = 0;
511 eeprom->tick = 0;
512 eeprom->mode = Chip9346_data_read;
6cadb320
FB		 513 DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
514 eeprom->address, eeprom->output));
a41b2ff2
PB		 515 }
516 break;
517
518 case Chip9346_op_write:
519 {
520 eeprom->address = command & EEPROM_9346_ADDR_MASK;
521 eeprom->input = 0;
522 eeprom->tick = 0;
523 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
6cadb320
FB		 524 DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
525 eeprom->address));
a41b2ff2
PB		 526 }
527 break;
528 default:
529 eeprom->mode = Chip9346_none;
530 switch (command & Chip9346_op_ext_mask)
531 {
532 case Chip9346_op_write_enable:
6cadb320 533 DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
a41b2ff2
PB		 534 break;
535 case Chip9346_op_write_all:
6cadb320 536 DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
a41b2ff2
PB		 537 break;
538 case Chip9346_op_write_disable:
6cadb320 539 DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
a41b2ff2
PB		 540 break;
541 }
542 break;
543 }
544}
545
546void prom9346_shift_clock(EEprom9346 *eeprom)
547{
548 int bit = eeprom->eedi?1:0;
549
550 ++ eeprom->tick;
551
6cadb320 552 DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 553
554 switch (eeprom->mode)
555 {
556 case Chip9346_enter_command_mode:
557 if (bit)
558 {
559 eeprom->mode = Chip9346_read_command;
560 eeprom->tick = 0;
561 eeprom->input = 0;
6cadb320 562 DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
a41b2ff2
PB		 563 }
564 break;
565
566 case Chip9346_read_command:
567 eeprom->input = (eeprom->input << 1) | (bit & 1);
568 if (eeprom->tick == 8)
569 {
570 prom9346_decode_command(eeprom, eeprom->input & 0xff);
571 }
572 break;
573
574 case Chip9346_data_read:
575 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
576 eeprom->output <<= 1;
577 if (eeprom->tick == 16)
578 {
6cadb320
FB		 579#if 1
580 // the FreeBSD drivers (rl and re) don't explicitly toggle
581 // CS between reads (or does setting Cfg9346 to 0 count too?),
582 // so we need to enter wait-for-command state here
583 eeprom->mode = Chip9346_enter_command_mode;
584 eeprom->input = 0;
585 eeprom->tick = 0;
586
587 DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
588#else
589 // original behaviour
a41b2ff2
PB		 590 ++eeprom->address;
591 eeprom->address &= EEPROM_9346_ADDR_MASK;
592 eeprom->output = eeprom->contents[eeprom->address];
593 eeprom->tick = 0;
594
6cadb320
FB		 595 DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
596 eeprom->address, eeprom->output));
a41b2ff2
PB		 597#endif
598 }
599 break;
600
601 case Chip9346_data_write:
602 eeprom->input = (eeprom->input << 1) | (bit & 1);
603 if (eeprom->tick == 16)
604 {
6cadb320
FB		 605 DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
606 eeprom->address, eeprom->input));
607
a41b2ff2
PB		 608 eeprom->contents[eeprom->address] = eeprom->input;
609 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
610 eeprom->tick = 0;
611 eeprom->input = 0;
612 }
613 break;
614
615 case Chip9346_data_write_all:
616 eeprom->input = (eeprom->input << 1) | (bit & 1);
617 if (eeprom->tick == 16)
618 {
619 int i;
620 for (i = 0; i < EEPROM_9346_SIZE; i++)
621 {
622 eeprom->contents[i] = eeprom->input;
623 }
6cadb320
FB		 624 DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
625 eeprom->input));
626
a41b2ff2
PB		 627 eeprom->mode = Chip9346_enter_command_mode;
628 eeprom->tick = 0;
629 eeprom->input = 0;
630 }
631 break;
632
633 default:
634 break;
635 }
636}
637
638int prom9346_get_wire(RTL8139State *s)
639{
640 EEprom9346 *eeprom = &s->eeprom;
641 if (!eeprom->eecs)
642 return 0;
643
644 return eeprom->eedo;
645}
646
647void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
648{
649 EEprom9346 *eeprom = &s->eeprom;
650 uint8_t old_eecs = eeprom->eecs;
651 uint8_t old_eesk = eeprom->eesk;
652
653 eeprom->eecs = eecs;
654 eeprom->eesk = eesk;
655 eeprom->eedi = eedi;
656
6cadb320
FB		 657 DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
658 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
a41b2ff2
PB		 659
660 if (!old_eecs && eecs)
661 {
662 /* Synchronize start */
663 eeprom->tick = 0;
664 eeprom->input = 0;
665 eeprom->output = 0;
666 eeprom->mode = Chip9346_enter_command_mode;
667
6cadb320 668 DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
a41b2ff2
PB		 669 }
670
671 if (!eecs)
672 {
6cadb320 673 DEBUG_PRINT(("=== eeprom: end access\n"));
a41b2ff2
PB		 674 return;
675 }
676
677 if (!old_eesk && eesk)
678 {
679 /* SK front rules */
680 prom9346_shift_clock(eeprom);
681 }
682}
683
684static void rtl8139_update_irq(RTL8139State *s)
685{
686 int isr;
687 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 688
80a34d67
PB		 689 DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
690 isr ? 1 : 0, s->IntrStatus, s->IntrMask));
6cadb320 691
d537cf6c 692 qemu_set_irq(s->pci_dev->irq[0], (isr != 0));
a41b2ff2
PB		 693}
694
695#define POLYNOMIAL 0x04c11db6
696
697/* From FreeBSD */
698/* XXX: optimize */
699static int compute_mcast_idx(const uint8_t *ep)
700{
701 uint32_t crc;
702 int carry, i, j;
703 uint8_t b;
704
705 crc = 0xffffffff;
706 for (i = 0; i < 6; i++) {
707 b = *ep++;
708 for (j = 0; j < 8; j++) {
709 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
710 crc <<= 1;
711 b >>= 1;
712 if (carry)
713 crc = ((crc ^ POLYNOMIAL) | carry);
714 }
715 }
716 return (crc >> 26);
717}
718
719static int rtl8139_RxWrap(RTL8139State *s)
720{
721 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
722 return (s->RxConfig & (1 << 7));
723}
724
725static int rtl8139_receiver_enabled(RTL8139State *s)
726{
727 return s->bChipCmdState & CmdRxEnb;
728}
729
730static int rtl8139_transmitter_enabled(RTL8139State *s)
731{
732 return s->bChipCmdState & CmdTxEnb;
733}
734
735static int rtl8139_cp_receiver_enabled(RTL8139State *s)
736{
737 return s->CpCmd & CPlusRxEnb;
738}
739
740static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
741{
742 return s->CpCmd & CPlusTxEnb;
743}
744
745static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
746{
747 if (s->RxBufAddr + size > s->RxBufferSize)
748 {
749 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
750
751 /* write packet data */
ccf1d14a 752 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 753 {
6cadb320 754 DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
a41b2ff2
PB		 755
756 if (size > wrapped)
757 {
758 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
759 buf, size-wrapped );
760 }
761
762 /* reset buffer pointer */
763 s->RxBufAddr = 0;
764
765 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
766 buf + (size-wrapped), wrapped );
767
768 s->RxBufAddr = wrapped;
769
770 return;
771 }
772 }
773
774 /* non-wrapping path or overwrapping enabled */
775 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
776
777 s->RxBufAddr += size;
778}
779
780#define MIN_BUF_SIZE 60
781static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
782{
783#if TARGET_PHYS_ADDR_BITS > 32
784 return low | ((target_phys_addr_t)high << 32);
785#else
786 return low;
787#endif
788}
789
790static int rtl8139_can_receive(void *opaque)
791{
792 RTL8139State *s = opaque;
793 int avail;
794
aa1f17c1 795 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 796 if (!s->clock_enabled)
797 return 1;
798 if (!rtl8139_receiver_enabled(s))
799 return 1;
800
801 if (rtl8139_cp_receiver_enabled(s)) {
802 /* ??? Flow control not implemented in c+ mode.
803 This is a hack to work around slirp deficiencies anyway. */
804 return 1;
805 } else {
806 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
807 s->RxBufferSize);
808 return (avail == 0 || avail >= 1514);
809 }
810}
811
6cadb320 812static void rtl8139_do_receive(void *opaque, const uint8_t *buf, int size, int do_interrupt)
a41b2ff2
PB		 813{
814 RTL8139State *s = opaque;
815
816 uint32_t packet_header = 0;
817
818 uint8_t buf1[60];
5fafdf24 819 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 820 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
821
6cadb320 822 DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
a41b2ff2
PB		 823
824 /* test if board clock is stopped */
825 if (!s->clock_enabled)
826 {
6cadb320 827 DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
a41b2ff2
PB		 828 return;
829 }
830
831 /* first check if receiver is enabled */
832
833 if (!rtl8139_receiver_enabled(s))
834 {
6cadb320 835 DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
a41b2ff2
PB		 836 return;
837 }
838
839 /* XXX: check this */
840 if (s->RxConfig & AcceptAllPhys) {
841 /* promiscuous: receive all */
6cadb320 842 DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
a41b2ff2
PB		 843
844 } else {
845 if (!memcmp(buf, broadcast_macaddr, 6)) {
846 /* broadcast address */
847 if (!(s->RxConfig & AcceptBroadcast))
848 {
6cadb320
FB		 849 DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
850
851 /* update tally counter */
852 ++s->tally_counters.RxERR;
853
a41b2ff2
PB		 854 return;
855 }
856
857 packet_header |= RxBroadcast;
858
6cadb320
FB		 859 DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
860
861 /* update tally counter */
862 ++s->tally_counters.RxOkBrd;
863
a41b2ff2
PB		 864 } else if (buf[0] & 0x01) {
865 /* multicast */
866 if (!(s->RxConfig & AcceptMulticast))
867 {
6cadb320
FB		 868 DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
869
870 /* update tally counter */
871 ++s->tally_counters.RxERR;
872
a41b2ff2
PB		 873 return;
874 }
875
876 int mcast_idx = compute_mcast_idx(buf);
877
878 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
879 {
6cadb320
FB		 880 DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
881
882 /* update tally counter */
883 ++s->tally_counters.RxERR;
884
a41b2ff2
PB		 885 return;
886 }
887
888 packet_header |= RxMulticast;
889
6cadb320
FB		 890 DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
891
892 /* update tally counter */
893 ++s->tally_counters.RxOkMul;
894
a41b2ff2 895 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 896 s->phys[1] == buf[1] &&
897 s->phys[2] == buf[2] &&
898 s->phys[3] == buf[3] &&
899 s->phys[4] == buf[4] &&
a41b2ff2
PB		 900 s->phys[5] == buf[5]) {
901 /* match */
902 if (!(s->RxConfig & AcceptMyPhys))
903 {
6cadb320
FB		 904 DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
905
906 /* update tally counter */
907 ++s->tally_counters.RxERR;
908
a41b2ff2
PB		 909 return;
910 }
911
912 packet_header |= RxPhysical;
913
6cadb320
FB		 914 DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
915
916 /* update tally counter */
917 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 918
919 } else {
920
6cadb320
FB		 921 DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
922
923 /* update tally counter */
924 ++s->tally_counters.RxERR;
925
a41b2ff2
PB		 926 return;
927 }
928 }
929
930 /* if too small buffer, then expand it */
931 if (size < MIN_BUF_SIZE) {
932 memcpy(buf1, buf, size);
933 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
934 buf = buf1;
935 size = MIN_BUF_SIZE;
936 }
937
938 if (rtl8139_cp_receiver_enabled(s))
939 {
6cadb320 940 DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
a41b2ff2
PB		 941
942 /* begin C+ receiver mode */
943
944/* w0 ownership flag */
945#define CP_RX_OWN (1<<31)
946/* w0 end of ring flag */
947#define CP_RX_EOR (1<<30)
948/* w0 bits 0...12 : buffer size */
949#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
950/* w1 tag available flag */
951#define CP_RX_TAVA (1<<16)
952/* w1 bits 0...15 : VLAN tag */
953#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
954/* w2 low 32bit of Rx buffer ptr */
955/* w3 high 32bit of Rx buffer ptr */
956
957 int descriptor = s->currCPlusRxDesc;
958 target_phys_addr_t cplus_rx_ring_desc;
959
960 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
961 cplus_rx_ring_desc += 16 * descriptor;
962
6cadb320
FB		 963 DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
964 descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
a41b2ff2
PB		 965
966 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
967
968 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
969 rxdw0 = le32_to_cpu(val);
970 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
971 rxdw1 = le32_to_cpu(val);
972 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
973 rxbufLO = le32_to_cpu(val);
974 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
975 rxbufHI = le32_to_cpu(val);
976
6cadb320 977 DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 978 descriptor,
6cadb320 979 rxdw0, rxdw1, rxbufLO, rxbufHI));
a41b2ff2
PB		 980
981 if (!(rxdw0 & CP_RX_OWN))
982 {
6cadb320
FB		 983 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
984
a41b2ff2
PB		 985 s->IntrStatus |= RxOverflow;
986 ++s->RxMissed;
6cadb320
FB		 987
988 /* update tally counter */
989 ++s->tally_counters.RxERR;
990 ++s->tally_counters.MissPkt;
991
a41b2ff2
PB		 992 rtl8139_update_irq(s);
993 return;
994 }
995
996 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
997
6cadb320
FB		 998 /* TODO: scatter the packet over available receive ring descriptors space */
999
a41b2ff2
PB		 1000 if (size+4 > rx_space)
1001 {
6cadb320
FB		 1002 DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1003 descriptor, rx_space, size));
1004
a41b2ff2
PB		 1005 s->IntrStatus |= RxOverflow;
1006 ++s->RxMissed;
6cadb320
FB		 1007
1008 /* update tally counter */
1009 ++s->tally_counters.RxERR;
1010 ++s->tally_counters.MissPkt;
1011
a41b2ff2
PB		 1012 rtl8139_update_irq(s);
1013 return;
1014 }
1015
1016 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1017
1018 /* receive/copy to target memory */
1019 cpu_physical_memory_write( rx_addr, buf, size );
1020
6cadb320
FB		 1021 if (s->CpCmd & CPlusRxChkSum)
1022 {
1023 /* do some packet checksumming */
1024 }
1025
a41b2ff2
PB		 1026 /* write checksum */
1027#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1028 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1029#else
1030 val = 0;
1031#endif
1032 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1033
1034/* first segment of received packet flag */
1035#define CP_RX_STATUS_FS (1<<29)
1036/* last segment of received packet flag */
1037#define CP_RX_STATUS_LS (1<<28)
1038/* multicast packet flag */
1039#define CP_RX_STATUS_MAR (1<<26)
1040/* physical-matching packet flag */
1041#define CP_RX_STATUS_PAM (1<<25)
1042/* broadcast packet flag */
1043#define CP_RX_STATUS_BAR (1<<24)
1044/* runt packet flag */
1045#define CP_RX_STATUS_RUNT (1<<19)
1046/* crc error flag */
1047#define CP_RX_STATUS_CRC (1<<18)
1048/* IP checksum error flag */
1049#define CP_RX_STATUS_IPF (1<<15)
1050/* UDP checksum error flag */
1051#define CP_RX_STATUS_UDPF (1<<14)
1052/* TCP checksum error flag */
1053#define CP_RX_STATUS_TCPF (1<<13)
1054
1055 /* transfer ownership to target */
1056 rxdw0 &= ~CP_RX_OWN;
1057
1058 /* set first segment bit */
1059 rxdw0 |= CP_RX_STATUS_FS;
1060
1061 /* set last segment bit */
1062 rxdw0 |= CP_RX_STATUS_LS;
1063
1064 /* set received packet type flags */
1065 if (packet_header & RxBroadcast)
1066 rxdw0 |= CP_RX_STATUS_BAR;
1067 if (packet_header & RxMulticast)
1068 rxdw0 |= CP_RX_STATUS_MAR;
1069 if (packet_header & RxPhysical)
1070 rxdw0 |= CP_RX_STATUS_PAM;
1071
1072 /* set received size */
1073 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1074 rxdw0 |= (size+4);
1075
1076 /* reset VLAN tag flag */
1077 rxdw1 &= ~CP_RX_TAVA;
1078
1079 /* update ring data */
1080 val = cpu_to_le32(rxdw0);
1081 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1082 val = cpu_to_le32(rxdw1);
1083 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1084
6cadb320
FB		 1085 /* update tally counter */
1086 ++s->tally_counters.RxOk;
1087
a41b2ff2
PB		 1088 /* seek to next Rx descriptor */
1089 if (rxdw0 & CP_RX_EOR)
1090 {
1091 s->currCPlusRxDesc = 0;
1092 }
1093 else
1094 {
1095 ++s->currCPlusRxDesc;
1096 }
1097
6cadb320 1098 DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
a41b2ff2
PB		 1099
1100 }
1101 else
1102 {
6cadb320
FB		 1103 DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1104
a41b2ff2
PB		 1105 /* begin ring receiver mode */
1106 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1107
1108 /* if receiver buffer is empty then avail == 0 */
1109
1110 if (avail != 0 && size + 8 >= avail)
1111 {
6cadb320
FB		 1112 DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1113 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1114
a41b2ff2
PB		 1115 s->IntrStatus |= RxOverflow;
1116 ++s->RxMissed;
1117 rtl8139_update_irq(s);
1118 return;
1119 }
1120
1121 packet_header |= RxStatusOK;
1122
1123 packet_header |= (((size+4) << 16) & 0xffff0000);
1124
1125 /* write header */
1126 uint32_t val = cpu_to_le32(packet_header);
1127
1128 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1129
1130 rtl8139_write_buffer(s, buf, size);
1131
1132 /* write checksum */
1133#if defined (RTL8139_CALCULATE_RXCRC)
ccf1d14a 1134 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1135#else
1136 val = 0;
1137#endif
1138
1139 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1140
1141 /* correct buffer write pointer */
1142 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1143
1144 /* now we can signal we have received something */
1145
6cadb320
FB		 1146 DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
1147 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 1148 }
1149
1150 s->IntrStatus |= RxOK;
6cadb320
FB		 1151
1152 if (do_interrupt)
1153 {
1154 rtl8139_update_irq(s);
1155 }
1156}
1157
1158static void rtl8139_receive(void *opaque, const uint8_t *buf, int size)
1159{
1160 rtl8139_do_receive(opaque, buf, size, 1);
a41b2ff2
PB		 1161}
1162
1163static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1164{
1165 s->RxBufferSize = bufferSize;
1166 s->RxBufPtr = 0;
1167 s->RxBufAddr = 0;
1168}
1169
1170static void rtl8139_reset(RTL8139State *s)
1171{
1172 int i;
1173
1174 /* restore MAC address */
1175 memcpy(s->phys, s->macaddr, 6);
1176
1177 /* reset interrupt mask */
1178 s->IntrStatus = 0;
1179 s->IntrMask = 0;
1180
1181 rtl8139_update_irq(s);
1182
1183 /* prepare eeprom */
1184 s->eeprom.contents[0] = 0x8129;
6cadb320
FB		 1185#if 1
1186 // PCI vendor and device ID should be mirrored here
1187 s->eeprom.contents[1] = 0x10ec;
1188 s->eeprom.contents[2] = 0x8139;
1189#endif
290a0933
TS		 1190
1191 s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8;
1192 s->eeprom.contents[8] = s->macaddr[2] | s->macaddr[3] << 8;
1193 s->eeprom.contents[9] = s->macaddr[4] | s->macaddr[5] << 8;
a41b2ff2
PB		 1194
1195 /* mark all status registers as owned by host */
1196 for (i = 0; i < 4; ++i)
1197 {
1198 s->TxStatus[i] = TxHostOwns;
1199 }
1200
1201 s->currTxDesc = 0;
1202 s->currCPlusRxDesc = 0;
1203 s->currCPlusTxDesc = 0;
1204
1205 s->RxRingAddrLO = 0;
1206 s->RxRingAddrHI = 0;
1207
1208 s->RxBuf = 0;
1209
1210 rtl8139_reset_rxring(s, 8192);
1211
1212 /* ACK the reset */
1213 s->TxConfig = 0;
1214
1215#if 0
1216// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1217 s->clock_enabled = 0;
1218#else
6cadb320 1219 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1220 s->clock_enabled = 1;
1221#endif
1222
1223 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1224
1225 /* set initial state data */
1226 s->Config0 = 0x0; /* No boot ROM */
1227 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1228 s->Config3 = 0x1; /* fast back-to-back compatible */
1229 s->Config5 = 0x0;
1230
5fafdf24 1231 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1232
1233 s->CpCmd = 0x0; /* reset C+ mode */
1234
1235// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1236// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1237 s->BasicModeCtrl = 0x1000; // autonegotiation
1238
1239 s->BasicModeStatus = 0x7809;
1240 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1241 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1242 s->BasicModeStatus |= 0x0004; /* link is up */
1243
1244 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1245 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1246 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1247
1248 /* also reset timer and disable timer interrupt */
1249 s->TCTR = 0;
1250 s->TimerInt = 0;
1251 s->TCTR_base = 0;
1252
1253 /* reset tally counters */
1254 RTL8139TallyCounters_clear(&s->tally_counters);
1255}
1256
1257void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1258{
1259 counters->TxOk = 0;
1260 counters->RxOk = 0;
1261 counters->TxERR = 0;
1262 counters->RxERR = 0;
1263 counters->MissPkt = 0;
1264 counters->FAE = 0;
1265 counters->Tx1Col = 0;
1266 counters->TxMCol = 0;
1267 counters->RxOkPhy = 0;
1268 counters->RxOkBrd = 0;
1269 counters->RxOkMul = 0;
1270 counters->TxAbt = 0;
1271 counters->TxUndrn = 0;
1272}
1273
1274static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1275{
1276 uint16_t val16;
1277 uint32_t val32;
1278 uint64_t val64;
1279
1280 val64 = cpu_to_le64(tally_counters->TxOk);
1281 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1282
1283 val64 = cpu_to_le64(tally_counters->RxOk);
1284 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1285
1286 val64 = cpu_to_le64(tally_counters->TxERR);
1287 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1288
1289 val32 = cpu_to_le32(tally_counters->RxERR);
1290 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1291
1292 val16 = cpu_to_le16(tally_counters->MissPkt);
1293 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1294
1295 val16 = cpu_to_le16(tally_counters->FAE);
1296 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1297
1298 val32 = cpu_to_le32(tally_counters->Tx1Col);
1299 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1300
1301 val32 = cpu_to_le32(tally_counters->TxMCol);
1302 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1303
1304 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1305 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1306
1307 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1308 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1309
1310 val32 = cpu_to_le32(tally_counters->RxOkMul);
1311 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1312
1313 val16 = cpu_to_le16(tally_counters->TxAbt);
1314 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1315
1316 val16 = cpu_to_le16(tally_counters->TxUndrn);
1317 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1318}
1319
1320/* Loads values of tally counters from VM state file */
1321static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1322{
1323 qemu_get_be64s(f, &tally_counters->TxOk);
1324 qemu_get_be64s(f, &tally_counters->RxOk);
1325 qemu_get_be64s(f, &tally_counters->TxERR);
1326 qemu_get_be32s(f, &tally_counters->RxERR);
1327 qemu_get_be16s(f, &tally_counters->MissPkt);
1328 qemu_get_be16s(f, &tally_counters->FAE);
1329 qemu_get_be32s(f, &tally_counters->Tx1Col);
1330 qemu_get_be32s(f, &tally_counters->TxMCol);
1331 qemu_get_be64s(f, &tally_counters->RxOkPhy);
1332 qemu_get_be64s(f, &tally_counters->RxOkBrd);
1333 qemu_get_be32s(f, &tally_counters->RxOkMul);
1334 qemu_get_be16s(f, &tally_counters->TxAbt);
1335 qemu_get_be16s(f, &tally_counters->TxUndrn);
1336}
1337
1338/* Saves values of tally counters to VM state file */
1339static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1340{
1341 qemu_put_be64s(f, &tally_counters->TxOk);
1342 qemu_put_be64s(f, &tally_counters->RxOk);
1343 qemu_put_be64s(f, &tally_counters->TxERR);
1344 qemu_put_be32s(f, &tally_counters->RxERR);
1345 qemu_put_be16s(f, &tally_counters->MissPkt);
1346 qemu_put_be16s(f, &tally_counters->FAE);
1347 qemu_put_be32s(f, &tally_counters->Tx1Col);
1348 qemu_put_be32s(f, &tally_counters->TxMCol);
1349 qemu_put_be64s(f, &tally_counters->RxOkPhy);
1350 qemu_put_be64s(f, &tally_counters->RxOkBrd);
1351 qemu_put_be32s(f, &tally_counters->RxOkMul);
1352 qemu_put_be16s(f, &tally_counters->TxAbt);
1353 qemu_put_be16s(f, &tally_counters->TxUndrn);
a41b2ff2
PB		 1354}
1355
1356static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1357{
1358 val &= 0xff;
1359
6cadb320 1360 DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
a41b2ff2
PB		 1361
1362 if (val & CmdReset)
1363 {
6cadb320 1364 DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
a41b2ff2
PB		 1365 rtl8139_reset(s);
1366 }
1367 if (val & CmdRxEnb)
1368 {
6cadb320 1369 DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
718da2b9
FB		 1370
1371 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1372 }
1373 if (val & CmdTxEnb)
1374 {
6cadb320 1375 DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
718da2b9
FB		 1376
1377 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1378 }
1379
1380 /* mask unwriteable bits */
1381 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1382
1383 /* Deassert reset pin before next read */
1384 val &= ~CmdReset;
1385
1386 s->bChipCmdState = val;
1387}
1388
1389static int rtl8139_RxBufferEmpty(RTL8139State *s)
1390{
1391 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1392
1393 if (unread != 0)
1394 {
6cadb320 1395 DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
a41b2ff2
PB		 1396 return 0;
1397 }
1398
6cadb320 1399 DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
a41b2ff2
PB		 1400
1401 return 1;
1402}
1403
1404static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1405{
1406 uint32_t ret = s->bChipCmdState;
1407
1408 if (rtl8139_RxBufferEmpty(s))
1409 ret |= RxBufEmpty;
1410
6cadb320 1411 DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
a41b2ff2
PB		 1412
1413 return ret;
1414}
1415
1416static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1417{
1418 val &= 0xffff;
1419
6cadb320 1420 DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1421
1422 /* mask unwriteable bits */
1423 val = SET_MASKED(val, 0xff84, s->CpCmd);
1424
1425 s->CpCmd = val;
1426}
1427
1428static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1429{
1430 uint32_t ret = s->CpCmd;
1431
6cadb320
FB		 1432 DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1433
1434 return ret;
1435}
1436
1437static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1438{
1439 DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1440}
1441
1442static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1443{
1444 uint32_t ret = 0;
1445
1446 DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1447
1448 return ret;
1449}
1450
1451int rtl8139_config_writeable(RTL8139State *s)
1452{
1453 if (s->Cfg9346 & Cfg9346_Unlock)
1454 {
1455 return 1;
1456 }
1457
6cadb320 1458 DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
a41b2ff2
PB		 1459
1460 return 0;
1461}
1462
1463static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1464{
1465 val &= 0xffff;
1466
6cadb320 1467 DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1468
1469 /* mask unwriteable bits */
e3d7e843 1470 uint32_t mask = 0x4cff;
a41b2ff2
PB		 1471
1472 if (1 || !rtl8139_config_writeable(s))
1473 {
1474 /* Speed setting and autonegotiation enable bits are read-only */
1475 mask |= 0x3000;
1476 /* Duplex mode setting is read-only */
1477 mask |= 0x0100;
1478 }
1479
1480 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1481
1482 s->BasicModeCtrl = val;
1483}
1484
1485static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1486{
1487 uint32_t ret = s->BasicModeCtrl;
1488
6cadb320 1489 DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1490
1491 return ret;
1492}
1493
1494static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1495{
1496 val &= 0xffff;
1497
6cadb320 1498 DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
a41b2ff2
PB		 1499
1500 /* mask unwriteable bits */
1501 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1502
1503 s->BasicModeStatus = val;
1504}
1505
1506static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1507{
1508 uint32_t ret = s->BasicModeStatus;
1509
6cadb320 1510 DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 1511
1512 return ret;
1513}
1514
1515static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1516{
1517 val &= 0xff;
1518
6cadb320 1519 DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
a41b2ff2
PB		 1520
1521 /* mask unwriteable bits */
1522 val = SET_MASKED(val, 0x31, s->Cfg9346);
1523
1524 uint32_t opmode = val & 0xc0;
1525 uint32_t eeprom_val = val & 0xf;
1526
1527 if (opmode == 0x80) {
1528 /* eeprom access */
1529 int eecs = (eeprom_val & 0x08)?1:0;
1530 int eesk = (eeprom_val & 0x04)?1:0;
1531 int eedi = (eeprom_val & 0x02)?1:0;
1532 prom9346_set_wire(s, eecs, eesk, eedi);
1533 } else if (opmode == 0x40) {
1534 /* Reset. */
1535 val = 0;
1536 rtl8139_reset(s);
1537 }
1538
1539 s->Cfg9346 = val;
1540}
1541
1542static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1543{
1544 uint32_t ret = s->Cfg9346;
1545
1546 uint32_t opmode = ret & 0xc0;
1547
1548 if (opmode == 0x80)
1549 {
1550 /* eeprom access */
1551 int eedo = prom9346_get_wire(s);
1552 if (eedo)
1553 {
1554 ret |= 0x01;
1555 }
1556 else
1557 {
1558 ret &= ~0x01;
1559 }
1560 }
1561
6cadb320 1562 DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
a41b2ff2
PB		 1563
1564 return ret;
1565}
1566
1567static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1568{
1569 val &= 0xff;
1570
6cadb320 1571 DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
a41b2ff2
PB		 1572
1573 if (!rtl8139_config_writeable(s))
1574 return;
1575
1576 /* mask unwriteable bits */
1577 val = SET_MASKED(val, 0xf8, s->Config0);
1578
1579 s->Config0 = val;
1580}
1581
1582static uint32_t rtl8139_Config0_read(RTL8139State *s)
1583{
1584 uint32_t ret = s->Config0;
1585
6cadb320 1586 DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
a41b2ff2
PB		 1587
1588 return ret;
1589}
1590
1591static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1592{
1593 val &= 0xff;
1594
6cadb320 1595 DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
a41b2ff2
PB		 1596
1597 if (!rtl8139_config_writeable(s))
1598 return;
1599
1600 /* mask unwriteable bits */
1601 val = SET_MASKED(val, 0xC, s->Config1);
1602
1603 s->Config1 = val;
1604}
1605
1606static uint32_t rtl8139_Config1_read(RTL8139State *s)
1607{
1608 uint32_t ret = s->Config1;
1609
6cadb320 1610 DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
a41b2ff2
PB		 1611
1612 return ret;
1613}
1614
1615static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1616{
1617 val &= 0xff;
1618
6cadb320 1619 DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
a41b2ff2
PB		 1620
1621 if (!rtl8139_config_writeable(s))
1622 return;
1623
1624 /* mask unwriteable bits */
1625 val = SET_MASKED(val, 0x8F, s->Config3);
1626
1627 s->Config3 = val;
1628}
1629
1630static uint32_t rtl8139_Config3_read(RTL8139State *s)
1631{
1632 uint32_t ret = s->Config3;
1633
6cadb320 1634 DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
a41b2ff2
PB		 1635
1636 return ret;
1637}
1638
1639static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1640{
1641 val &= 0xff;
1642
6cadb320 1643 DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
a41b2ff2
PB		 1644
1645 if (!rtl8139_config_writeable(s))
1646 return;
1647
1648 /* mask unwriteable bits */
1649 val = SET_MASKED(val, 0x0a, s->Config4);
1650
1651 s->Config4 = val;
1652}
1653
1654static uint32_t rtl8139_Config4_read(RTL8139State *s)
1655{
1656 uint32_t ret = s->Config4;
1657
6cadb320 1658 DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
a41b2ff2
PB		 1659
1660 return ret;
1661}
1662
1663static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1664{
1665 val &= 0xff;
1666
6cadb320 1667 DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
a41b2ff2
PB		 1668
1669 /* mask unwriteable bits */
1670 val = SET_MASKED(val, 0x80, s->Config5);
1671
1672 s->Config5 = val;
1673}
1674
1675static uint32_t rtl8139_Config5_read(RTL8139State *s)
1676{
1677 uint32_t ret = s->Config5;
1678
6cadb320 1679 DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
a41b2ff2
PB		 1680
1681 return ret;
1682}
1683
1684static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1685{
1686 if (!rtl8139_transmitter_enabled(s))
1687 {
6cadb320 1688 DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1689 return;
1690 }
1691
6cadb320 1692 DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1693
1694 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1695
1696 s->TxConfig = val;
1697}
1698
1699static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1700{
6cadb320
FB		 1701 DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1702
1703 uint32_t tc = s->TxConfig;
1704 tc &= 0xFFFFFF00;
1705 tc |= (val & 0x000000FF);
1706 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1707}
1708
1709static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1710{
1711 uint32_t ret = s->TxConfig;
1712
6cadb320 1713 DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
a41b2ff2
PB		 1714
1715 return ret;
1716}
1717
1718static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1719{
6cadb320 1720 DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
a41b2ff2
PB		 1721
1722 /* mask unwriteable bits */
1723 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1724
1725 s->RxConfig = val;
1726
1727 /* reset buffer size and read/write pointers */
1728 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1729
6cadb320 1730 DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
a41b2ff2
PB		 1731}
1732
1733static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1734{
1735 uint32_t ret = s->RxConfig;
1736
6cadb320 1737 DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
a41b2ff2
PB		 1738
1739 return ret;
1740}
1741
718da2b9
FB		 1742static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1743{
1744 if (!size)
1745 {
1746 DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1747 return;
1748 }
1749
1750 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1751 {
1752 DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1753 rtl8139_do_receive(s, buf, size, do_interrupt);
1754 }
1755 else
1756 {
1757 qemu_send_packet(s->vc, buf, size);
1758 }
1759}
1760
a41b2ff2
PB		 1761static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1762{
1763 if (!rtl8139_transmitter_enabled(s))
1764 {
6cadb320
FB		 1765 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1766 descriptor));
a41b2ff2
PB		 1767 return 0;
1768 }
1769
1770 if (s->TxStatus[descriptor] & TxHostOwns)
1771 {
6cadb320
FB		 1772 DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1773 descriptor, s->TxStatus[descriptor]));
a41b2ff2
PB		 1774 return 0;
1775 }
1776
6cadb320 1777 DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
a41b2ff2
PB		 1778
1779 int txsize = s->TxStatus[descriptor] & 0x1fff;
1780 uint8_t txbuffer[0x2000];
1781
6cadb320
FB		 1782 DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1783 txsize, s->TxAddr[descriptor]));
a41b2ff2 1784
6cadb320 1785 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1786
1787 /* Mark descriptor as transferred */
1788 s->TxStatus[descriptor] |= TxHostOwns;
1789 s->TxStatus[descriptor] |= TxStatOK;
1790
718da2b9 1791 rtl8139_transfer_frame(s, txbuffer, txsize, 0);
6cadb320
FB		 1792
1793 DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
a41b2ff2
PB		 1794
1795 /* update interrupt */
1796 s->IntrStatus |= TxOK;
1797 rtl8139_update_irq(s);
1798
1799 return 1;
1800}
1801
718da2b9
FB		 1802/* structures and macros for task offloading */
1803typedef struct ip_header
1804{
1805 uint8_t ip_ver_len; /* version and header length */
1806 uint8_t ip_tos; /* type of service */
1807 uint16_t ip_len; /* total length */
1808 uint16_t ip_id; /* identification */
1809 uint16_t ip_off; /* fragment offset field */
1810 uint8_t ip_ttl; /* time to live */
1811 uint8_t ip_p; /* protocol */
1812 uint16_t ip_sum; /* checksum */
1813 uint32_t ip_src,ip_dst; /* source and dest address */
1814} ip_header;
1815
1816#define IP_HEADER_VERSION_4 4
1817#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1818#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1819
1820typedef struct tcp_header
1821{
1822 uint16_t th_sport; /* source port */
1823 uint16_t th_dport; /* destination port */
1824 uint32_t th_seq; /* sequence number */
1825 uint32_t th_ack; /* acknowledgement number */
1826 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1827 uint16_t th_win; /* window */
1828 uint16_t th_sum; /* checksum */
1829 uint16_t th_urp; /* urgent pointer */
1830} tcp_header;
1831
1832typedef struct udp_header
1833{
1834 uint16_t uh_sport; /* source port */
1835 uint16_t uh_dport; /* destination port */
1836 uint16_t uh_ulen; /* udp length */
1837 uint16_t uh_sum; /* udp checksum */
1838} udp_header;
1839
1840typedef struct ip_pseudo_header
1841{
1842 uint32_t ip_src;
1843 uint32_t ip_dst;
1844 uint8_t zeros;
1845 uint8_t ip_proto;
1846 uint16_t ip_payload;
1847} ip_pseudo_header;
1848
1849#define IP_PROTO_TCP 6
1850#define IP_PROTO_UDP 17
1851
1852#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1853#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1854#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1855
1856#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1857
1858#define TCP_FLAG_FIN 0x01
1859#define TCP_FLAG_PUSH 0x08
1860
1861/* produces ones' complement sum of data */
1862static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1863{
1864 uint32_t result = 0;
1865
1866 for (; len > 1; data+=2, len-=2)
1867 {
1868 result += *(uint16_t*)data;
1869 }
1870
1871 /* add the remainder byte */
1872 if (len)
1873 {
1874 uint8_t odd[2] = {*data, 0};
1875 result += *(uint16_t*)odd;
1876 }
1877
1878 while (result>>16)
1879 result = (result & 0xffff) + (result >> 16);
1880
1881 return result;
1882}
1883
1884static uint16_t ip_checksum(void *data, size_t len)
1885{
1886 return ~ones_complement_sum((uint8_t*)data, len);
1887}
1888
a41b2ff2
PB		 1889static int rtl8139_cplus_transmit_one(RTL8139State *s)
1890{
1891 if (!rtl8139_transmitter_enabled(s))
1892 {
6cadb320 1893 DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
a41b2ff2
PB		 1894 return 0;
1895 }
1896
1897 if (!rtl8139_cp_transmitter_enabled(s))
1898 {
6cadb320 1899 DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
a41b2ff2
PB		 1900 return 0 ;
1901 }
1902
1903 int descriptor = s->currCPlusTxDesc;
1904
1905 target_phys_addr_t cplus_tx_ring_desc =
1906 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1907
1908 /* Normal priority ring */
1909 cplus_tx_ring_desc += 16 * descriptor;
1910
6cadb320
FB		 1911 DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1912 descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
a41b2ff2
PB		 1913
1914 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1915
1916 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1917 txdw0 = le32_to_cpu(val);
1918 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1919 txdw1 = le32_to_cpu(val);
1920 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1921 txbufLO = le32_to_cpu(val);
1922 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1923 txbufHI = le32_to_cpu(val);
1924
6cadb320 1925 DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
a41b2ff2 1926 descriptor,
6cadb320 1927 txdw0, txdw1, txbufLO, txbufHI));
a41b2ff2
PB		 1928
1929/* w0 ownership flag */
1930#define CP_TX_OWN (1<<31)
1931/* w0 end of ring flag */
1932#define CP_TX_EOR (1<<30)
1933/* first segment of received packet flag */
1934#define CP_TX_FS (1<<29)
1935/* last segment of received packet flag */
1936#define CP_TX_LS (1<<28)
1937/* large send packet flag */
1938#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1939/* large send MSS mask, bits 16...25 */
1940#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1941
a41b2ff2
PB		 1942/* IP checksum offload flag */
1943#define CP_TX_IPCS (1<<18)
1944/* UDP checksum offload flag */
1945#define CP_TX_UDPCS (1<<17)
1946/* TCP checksum offload flag */
1947#define CP_TX_TCPCS (1<<16)
1948
1949/* w0 bits 0...15 : buffer size */
1950#define CP_TX_BUFFER_SIZE (1<<16)
1951#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1952/* w1 tag available flag */
1953#define CP_RX_TAGC (1<<17)
1954/* w1 bits 0...15 : VLAN tag */
1955#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1956/* w2 low 32bit of Rx buffer ptr */
1957/* w3 high 32bit of Rx buffer ptr */
1958
1959/* set after transmission */
1960/* FIFO underrun flag */
1961#define CP_TX_STATUS_UNF (1<<25)
1962/* transmit error summary flag, valid if set any of three below */
1963#define CP_TX_STATUS_TES (1<<23)
1964/* out-of-window collision flag */
1965#define CP_TX_STATUS_OWC (1<<22)
1966/* link failure flag */
1967#define CP_TX_STATUS_LNKF (1<<21)
1968/* excessive collisions flag */
1969#define CP_TX_STATUS_EXC (1<<20)
1970
1971 if (!(txdw0 & CP_TX_OWN))
1972 {
6cadb320 1973 DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
a41b2ff2
PB		 1974 return 0 ;
1975 }
1976
6cadb320
FB		 1977 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1978
1979 if (txdw0 & CP_TX_FS)
1980 {
1981 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1982
1983 /* reset internal buffer offset */
1984 s->cplus_txbuffer_offset = 0;
1985 }
a41b2ff2
PB		 1986
1987 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1988 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1989
6cadb320
FB		 1990 /* make sure we have enough space to assemble the packet */
1991 if (!s->cplus_txbuffer)
1992 {
1993 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
1994 s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
1995 s->cplus_txbuffer_offset = 0;
718da2b9
FB		 1996
1997 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
6cadb320
FB		 1998 }
1999
2000 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2001 {
2002 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2003 s->cplus_txbuffer = realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2004
6cadb320
FB		 2005 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2006 }
2007
2008 if (!s->cplus_txbuffer)
2009 {
2010 /* out of memory */
a41b2ff2 2011
6cadb320
FB		 2012 DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2013
2014 /* update tally counter */
2015 ++s->tally_counters.TxERR;
2016 ++s->tally_counters.TxAbt;
2017
2018 return 0;
2019 }
2020
2021 /* append more data to the packet */
2022
2023 DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2024 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2025
2026 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2027 s->cplus_txbuffer_offset += txsize;
2028
2029 /* seek to next Rx descriptor */
2030 if (txdw0 & CP_TX_EOR)
2031 {
2032 s->currCPlusTxDesc = 0;
2033 }
2034 else
2035 {
2036 ++s->currCPlusTxDesc;
2037 if (s->currCPlusTxDesc >= 64)
2038 s->currCPlusTxDesc = 0;
2039 }
a41b2ff2
PB		 2040
2041 /* transfer ownership to target */
2042 txdw0 &= ~CP_RX_OWN;
2043
2044 /* reset error indicator bits */
2045 txdw0 &= ~CP_TX_STATUS_UNF;
2046 txdw0 &= ~CP_TX_STATUS_TES;
2047 txdw0 &= ~CP_TX_STATUS_OWC;
2048 txdw0 &= ~CP_TX_STATUS_LNKF;
2049 txdw0 &= ~CP_TX_STATUS_EXC;
2050
2051 /* update ring data */
2052 val = cpu_to_le32(txdw0);
2053 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
2054// val = cpu_to_le32(txdw1);
2055// cpu_physical_memory_write(cplus_tx_ring_desc+4, &val, 4);
2056
6cadb320
FB		 2057 /* Now decide if descriptor being processed is holding the last segment of packet */
2058 if (txdw0 & CP_TX_LS)
a41b2ff2 2059 {
6cadb320
FB		 2060 DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2061
2062 /* can transfer fully assembled packet */
2063
2064 uint8_t *saved_buffer = s->cplus_txbuffer;
2065 int saved_size = s->cplus_txbuffer_offset;
2066 int saved_buffer_len = s->cplus_txbuffer_len;
2067
2068 /* reset the card space to protect from recursive call */
2069 s->cplus_txbuffer = NULL;
2070 s->cplus_txbuffer_offset = 0;
2071 s->cplus_txbuffer_len = 0;
2072
718da2b9 2073 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320
FB		 2074 {
2075 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2076
2077 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
2078 #define ETH_HLEN 14
718da2b9 2079 #define ETH_MTU 1500
6cadb320
FB		 2080
2081 /* ip packet header */
718da2b9 2082 ip_header *ip = 0;
6cadb320 2083 int hlen = 0;
718da2b9
FB		 2084 uint8_t ip_protocol = 0;
2085 uint16_t ip_data_len = 0;
6cadb320 2086
718da2b9
FB		 2087 uint8_t *eth_payload_data = 0;
2088 size_t eth_payload_len = 0;
6cadb320 2089
718da2b9 2090 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2091 if (proto == ETH_P_IP)
2092 {
2093 DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2094
2095 /* not aligned */
718da2b9
FB		 2096 eth_payload_data = saved_buffer + ETH_HLEN;
2097 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2098
718da2b9 2099 ip = (ip_header*)eth_payload_data;
6cadb320 2100
718da2b9
FB		 2101 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2102 DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
6cadb320
FB		 2103 ip = NULL;
2104 } else {
718da2b9
FB		 2105 hlen = IP_HEADER_LENGTH(ip);
2106 ip_protocol = ip->ip_p;
2107 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2108 }
2109 }
2110
2111 if (ip)
2112 {
2113 if (txdw0 & CP_TX_IPCS)
2114 {
2115 DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2116
718da2b9 2117 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2118 /* bad packet header len */
2119 /* or packet too short */
2120 }
2121 else
2122 {
2123 ip->ip_sum = 0;
718da2b9 2124 ip->ip_sum = ip_checksum(ip, hlen);
6cadb320
FB		 2125 DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2126 }
2127 }
2128
718da2b9 2129 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2130 {
718da2b9
FB		 2131#if defined (DEBUG_RTL8139)
2132 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2133#endif
2134 DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2135 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
6cadb320 2136
718da2b9
FB		 2137 int tcp_send_offset = 0;
2138 int send_count = 0;
6cadb320
FB		 2139
2140 /* maximum IP header length is 60 bytes */
2141 uint8_t saved_ip_header[60];
6cadb320 2142
718da2b9
FB		 2143 /* save IP header template; data area is used in tcp checksum calculation */
2144 memcpy(saved_ip_header, eth_payload_data, hlen);
2145
2146 /* a placeholder for checksum calculation routine in tcp case */
2147 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2148 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2149
2150 /* pointer to TCP header */
2151 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2152
2153 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2154
2155 /* ETH_MTU = ip header len + tcp header len + payload */
2156 int tcp_data_len = ip_data_len - tcp_hlen;
2157 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2158
2159 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2160 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2161
2162 /* note the cycle below overwrites IP header data,
2163 but restores it from saved_ip_header before sending packet */
2164
2165 int is_last_frame = 0;
2166
2167 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2168 {
2169 uint16_t chunk_size = tcp_chunk_size;
2170
2171 /* check if this is the last frame */
2172 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2173 {
2174 is_last_frame = 1;
2175 chunk_size = tcp_data_len - tcp_send_offset;
2176 }
2177
2178 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2179
2180 /* add 4 TCP pseudoheader fields */
2181 /* copy IP source and destination fields */
2182 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2183
2184 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2185
2186 if (tcp_send_offset)
2187 {
2188 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2189 }
2190
2191 /* keep PUSH and FIN flags only for the last frame */
2192 if (!is_last_frame)
2193 {
2194 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2195 }
6cadb320 2196
718da2b9
FB		 2197 /* recalculate TCP checksum */
2198 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2199 p_tcpip_hdr->zeros = 0;
2200 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2201 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2202
2203 p_tcp_hdr->th_sum = 0;
2204
2205 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2206 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2207
2208 p_tcp_hdr->th_sum = tcp_checksum;
2209
2210 /* restore IP header */
2211 memcpy(eth_payload_data, saved_ip_header, hlen);
2212
2213 /* set IP data length and recalculate IP checksum */
2214 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2215
2216 /* increment IP id for subsequent frames */
2217 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2218
2219 ip->ip_sum = 0;
2220 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2221 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2222
2223 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2224 DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2225 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2226
2227 /* add transferred count to TCP sequence number */
2228 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2229 ++send_count;
2230 }
2231
2232 /* Stop sending this frame */
2233 saved_size = 0;
2234 }
2235 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2236 {
2237 DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2238
2239 /* maximum IP header length is 60 bytes */
2240 uint8_t saved_ip_header[60];
2241 memcpy(saved_ip_header, eth_payload_data, hlen);
2242
2243 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2244 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2245
2246 /* add 4 TCP pseudoheader fields */
2247 /* copy IP source and destination fields */
718da2b9 2248 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2249
718da2b9 2250 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320
FB		 2251 {
2252 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2253
718da2b9
FB		 2254 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2255 p_tcpip_hdr->zeros = 0;
2256 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2257 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2258
718da2b9 2259 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2260
2261 p_tcp_hdr->th_sum = 0;
2262
718da2b9 2263 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2264 DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2265
2266 p_tcp_hdr->th_sum = tcp_checksum;
2267 }
718da2b9 2268 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320
FB		 2269 {
2270 DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2271
718da2b9
FB		 2272 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2273 p_udpip_hdr->zeros = 0;
2274 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2275 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2276
718da2b9 2277 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2278
6cadb320
FB		 2279 p_udp_hdr->uh_sum = 0;
2280
718da2b9 2281 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
6cadb320
FB		 2282 DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2283
6cadb320
FB		 2284 p_udp_hdr->uh_sum = udp_checksum;
2285 }
2286
2287 /* restore IP header */
718da2b9 2288 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2289 }
2290 }
2291 }
2292
2293 /* update tally counter */
2294 ++s->tally_counters.TxOk;
2295
2296 DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2297
718da2b9 2298 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
6cadb320
FB		 2299
2300 /* restore card space if there was no recursion and reset offset */
2301 if (!s->cplus_txbuffer)
2302 {
2303 s->cplus_txbuffer = saved_buffer;
2304 s->cplus_txbuffer_len = saved_buffer_len;
2305 s->cplus_txbuffer_offset = 0;
2306 }
2307 else
2308 {
2309 free(saved_buffer);
2310 }
a41b2ff2
PB		 2311 }
2312 else
2313 {
6cadb320 2314 DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
a41b2ff2
PB		 2315 }
2316
a41b2ff2
PB		 2317 return 1;
2318}
2319
2320static void rtl8139_cplus_transmit(RTL8139State *s)
2321{
2322 int txcount = 0;
2323
2324 while (rtl8139_cplus_transmit_one(s))
2325 {
2326 ++txcount;
2327 }
2328
2329 /* Mark transfer completed */
2330 if (!txcount)
2331 {
6cadb320
FB		 2332 DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2333 s->currCPlusTxDesc));
a41b2ff2
PB		 2334 }
2335 else
2336 {
2337 /* update interrupt status */
2338 s->IntrStatus |= TxOK;
2339 rtl8139_update_irq(s);
2340 }
2341}
2342
2343static void rtl8139_transmit(RTL8139State *s)
2344{
2345 int descriptor = s->currTxDesc, txcount = 0;
2346
2347 /*while*/
2348 if (rtl8139_transmit_one(s, descriptor))
2349 {
2350 ++s->currTxDesc;
2351 s->currTxDesc %= 4;
2352 ++txcount;
2353 }
2354
2355 /* Mark transfer completed */
2356 if (!txcount)
2357 {
6cadb320 2358 DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
a41b2ff2
PB		 2359 }
2360}
2361
2362static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2363{
2364
2365 int descriptor = txRegOffset/4;
6cadb320
FB		 2366
2367 /* handle C+ transmit mode register configuration */
2368
2369 if (rtl8139_cp_transmitter_enabled(s))
2370 {
2371 DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2372
2373 /* handle Dump Tally Counters command */
2374 s->TxStatus[descriptor] = val;
2375
2376 if (descriptor == 0 && (val & 0x8))
2377 {
2378 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2379
2380 /* dump tally counters to specified memory location */
2381 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2382
2383 /* mark dump completed */
2384 s->TxStatus[0] &= ~0x8;
2385 }
2386
2387 return;
2388 }
2389
2390 DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
a41b2ff2
PB		 2391
2392 /* mask only reserved bits */
2393 val &= ~0xff00c000; /* these bits are reset on write */
2394 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2395
2396 s->TxStatus[descriptor] = val;
2397
2398 /* attempt to start transmission */
2399 rtl8139_transmit(s);
2400}
2401
2402static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2403{
2404 uint32_t ret = s->TxStatus[txRegOffset/4];
2405
6cadb320 2406 DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
a41b2ff2
PB		 2407
2408 return ret;
2409}
2410
2411static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2412{
2413 uint16_t ret = 0;
2414
2415 /* Simulate TSAD, it is read only anyway */
2416
2417 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2418 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2419 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2420 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2421
2422 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2423 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2424 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2425 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2426
a41b2ff2
PB		 2427 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2428 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2429 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2430 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2431
a41b2ff2
PB		 2432 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2433 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2434 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2435 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2436
a41b2ff2 2437
6cadb320 2438 DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
a41b2ff2
PB		 2439
2440 return ret;
2441}
2442
2443static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2444{
2445 uint16_t ret = s->CSCR;
2446
6cadb320 2447 DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
a41b2ff2
PB		 2448
2449 return ret;
2450}
2451
2452static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2453{
6cadb320 2454 DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
a41b2ff2 2455
290a0933 2456 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2457}
2458
2459static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2460{
290a0933 2461 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2462
6cadb320 2463 DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
a41b2ff2
PB		 2464
2465 return ret;
2466}
2467
2468static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2469{
6cadb320 2470 DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
a41b2ff2
PB		 2471
2472 /* this value is off by 16 */
2473 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2474
6cadb320
FB		 2475 DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2476 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
a41b2ff2
PB		 2477}
2478
2479static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2480{
2481 /* this value is off by 16 */
2482 uint32_t ret = s->RxBufPtr - 0x10;
2483
6cadb320
FB		 2484 DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2485
2486 return ret;
2487}
2488
2489static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2490{
2491 /* this value is NOT off by 16 */
2492 uint32_t ret = s->RxBufAddr;
2493
2494 DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
a41b2ff2
PB		 2495
2496 return ret;
2497}
2498
2499static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2500{
6cadb320 2501 DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
a41b2ff2
PB		 2502
2503 s->RxBuf = val;
2504
2505 /* may need to reset rxring here */
2506}
2507
2508static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2509{
2510 uint32_t ret = s->RxBuf;
2511
6cadb320 2512 DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
a41b2ff2
PB		 2513
2514 return ret;
2515}
2516
2517static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2518{
6cadb320 2519 DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2520
2521 /* mask unwriteable bits */
2522 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2523
2524 s->IntrMask = val;
2525
2526 rtl8139_update_irq(s);
2527}
2528
2529static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2530{
2531 uint32_t ret = s->IntrMask;
2532
6cadb320 2533 DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2534
2535 return ret;
2536}
2537
2538static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2539{
6cadb320 2540 DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2541
2542#if 0
2543
2544 /* writing to ISR has no effect */
2545
2546 return;
2547
2548#else
2549 uint16_t newStatus = s->IntrStatus & ~val;
2550
2551 /* mask unwriteable bits */
2552 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2553
2554 /* writing 1 to interrupt status register bit clears it */
2555 s->IntrStatus = 0;
2556 rtl8139_update_irq(s);
2557
2558 s->IntrStatus = newStatus;
2559 rtl8139_update_irq(s);
2560#endif
2561}
2562
2563static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2564{
2565 uint32_t ret = s->IntrStatus;
2566
6cadb320 2567 DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2568
2569#if 0
2570
2571 /* reading ISR clears all interrupts */
2572 s->IntrStatus = 0;
2573
2574 rtl8139_update_irq(s);
2575
2576#endif
2577
2578 return ret;
2579}
2580
2581static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2582{
6cadb320 2583 DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2584
2585 /* mask unwriteable bits */
2586 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2587
2588 s->MultiIntr = val;
2589}
2590
2591static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2592{
2593 uint32_t ret = s->MultiIntr;
2594
6cadb320 2595 DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2596
2597 return ret;
2598}
2599
2600static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2601{
2602 RTL8139State *s = opaque;
2603
2604 addr &= 0xff;
2605
2606 switch (addr)
2607 {
2608 case MAC0 ... MAC0+5:
2609 s->phys[addr - MAC0] = val;
2610 break;
2611 case MAC0+6 ... MAC0+7:
2612 /* reserved */
2613 break;
2614 case MAR0 ... MAR0+7:
2615 s->mult[addr - MAR0] = val;
2616 break;
2617 case ChipCmd:
2618 rtl8139_ChipCmd_write(s, val);
2619 break;
2620 case Cfg9346:
2621 rtl8139_Cfg9346_write(s, val);
2622 break;
2623 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2624 rtl8139_TxConfig_writeb(s, val);
2625 break;
2626 case Config0:
2627 rtl8139_Config0_write(s, val);
2628 break;
2629 case Config1:
2630 rtl8139_Config1_write(s, val);
2631 break;
2632 case Config3:
2633 rtl8139_Config3_write(s, val);
2634 break;
2635 case Config4:
2636 rtl8139_Config4_write(s, val);
2637 break;
2638 case Config5:
2639 rtl8139_Config5_write(s, val);
2640 break;
2641 case MediaStatus:
2642 /* ignore */
6cadb320 2643 DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
a41b2ff2
PB		 2644 break;
2645
2646 case HltClk:
6cadb320 2647 DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
a41b2ff2
PB		 2648 if (val == 'R')
2649 {
2650 s->clock_enabled = 1;
2651 }
2652 else if (val == 'H')
2653 {
2654 s->clock_enabled = 0;
2655 }
2656 break;
2657
2658 case TxThresh:
6cadb320 2659 DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2660 s->TxThresh = val;
2661 break;
2662
2663 case TxPoll:
6cadb320 2664 DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
a41b2ff2
PB		 2665 if (val & (1 << 7))
2666 {
6cadb320 2667 DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
a41b2ff2
PB		 2668 //rtl8139_cplus_transmit(s);
2669 }
2670 if (val & (1 << 6))
2671 {
6cadb320 2672 DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
a41b2ff2
PB		 2673 rtl8139_cplus_transmit(s);
2674 }
2675
2676 break;
2677
2678 default:
6cadb320 2679 DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
a41b2ff2
PB		 2680 break;
2681 }
2682}
2683
2684static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2685{
2686 RTL8139State *s = opaque;
2687
2688 addr &= 0xfe;
2689
2690 switch (addr)
2691 {
2692 case IntrMask:
2693 rtl8139_IntrMask_write(s, val);
2694 break;
2695
2696 case IntrStatus:
2697 rtl8139_IntrStatus_write(s, val);
2698 break;
2699
2700 case MultiIntr:
2701 rtl8139_MultiIntr_write(s, val);
2702 break;
2703
2704 case RxBufPtr:
2705 rtl8139_RxBufPtr_write(s, val);
2706 break;
2707
2708 case BasicModeCtrl:
2709 rtl8139_BasicModeCtrl_write(s, val);
2710 break;
2711 case BasicModeStatus:
2712 rtl8139_BasicModeStatus_write(s, val);
2713 break;
2714 case NWayAdvert:
6cadb320 2715 DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2716 s->NWayAdvert = val;
2717 break;
2718 case NWayLPAR:
6cadb320 2719 DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2720 break;
2721 case NWayExpansion:
6cadb320 2722 DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
a41b2ff2
PB		 2723 s->NWayExpansion = val;
2724 break;
2725
2726 case CpCmd:
2727 rtl8139_CpCmd_write(s, val);
2728 break;
2729
6cadb320
FB		 2730 case IntrMitigate:
2731 rtl8139_IntrMitigate_write(s, val);
2732 break;
2733
a41b2ff2 2734 default:
6cadb320 2735 DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
a41b2ff2
PB		 2736
2737#ifdef TARGET_WORDS_BIGENDIAN
2738 rtl8139_io_writeb(opaque, addr, (val >> 8) & 0xff);
2739 rtl8139_io_writeb(opaque, addr + 1, val & 0xff);
2740#else
2741 rtl8139_io_writeb(opaque, addr, val & 0xff);
2742 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2743#endif
2744 break;
2745 }
2746}
2747
2748static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2749{
2750 RTL8139State *s = opaque;
2751
2752 addr &= 0xfc;
2753
2754 switch (addr)
2755 {
2756 case RxMissed:
6cadb320 2757 DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
a41b2ff2
PB		 2758 s->RxMissed = 0;
2759 break;
2760
2761 case TxConfig:
2762 rtl8139_TxConfig_write(s, val);
2763 break;
2764
2765 case RxConfig:
2766 rtl8139_RxConfig_write(s, val);
2767 break;
2768
2769 case TxStatus0 ... TxStatus0+4*4-1:
2770 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2771 break;
2772
2773 case TxAddr0 ... TxAddr0+4*4-1:
2774 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2775 break;
2776
2777 case RxBuf:
2778 rtl8139_RxBuf_write(s, val);
2779 break;
2780
2781 case RxRingAddrLO:
6cadb320 2782 DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
a41b2ff2
PB		 2783 s->RxRingAddrLO = val;
2784 break;
2785
2786 case RxRingAddrHI:
6cadb320 2787 DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
a41b2ff2
PB		 2788 s->RxRingAddrHI = val;
2789 break;
2790
6cadb320
FB		 2791 case Timer:
2792 DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2793 s->TCTR = 0;
2794 s->TCTR_base = qemu_get_clock(vm_clock);
2795 break;
2796
2797 case FlashReg:
2798 DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2799 s->TimerInt = val;
2800 break;
2801
a41b2ff2 2802 default:
6cadb320 2803 DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
a41b2ff2
PB		 2804#ifdef TARGET_WORDS_BIGENDIAN
2805 rtl8139_io_writeb(opaque, addr, (val >> 24) & 0xff);
2806 rtl8139_io_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2807 rtl8139_io_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2808 rtl8139_io_writeb(opaque, addr + 3, val & 0xff);
2809#else
2810 rtl8139_io_writeb(opaque, addr, val & 0xff);
2811 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2812 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2813 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2814#endif
2815 break;
2816 }
2817}
2818
2819static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2820{
2821 RTL8139State *s = opaque;
2822 int ret;
2823
2824 addr &= 0xff;
2825
2826 switch (addr)
2827 {
2828 case MAC0 ... MAC0+5:
2829 ret = s->phys[addr - MAC0];
2830 break;
2831 case MAC0+6 ... MAC0+7:
2832 ret = 0;
2833 break;
2834 case MAR0 ... MAR0+7:
2835 ret = s->mult[addr - MAR0];
2836 break;
2837 case ChipCmd:
2838 ret = rtl8139_ChipCmd_read(s);
2839 break;
2840 case Cfg9346:
2841 ret = rtl8139_Cfg9346_read(s);
2842 break;
2843 case Config0:
2844 ret = rtl8139_Config0_read(s);
2845 break;
2846 case Config1:
2847 ret = rtl8139_Config1_read(s);
2848 break;
2849 case Config3:
2850 ret = rtl8139_Config3_read(s);
2851 break;
2852 case Config4:
2853 ret = rtl8139_Config4_read(s);
2854 break;
2855 case Config5:
2856 ret = rtl8139_Config5_read(s);
2857 break;
2858
2859 case MediaStatus:
2860 ret = 0xd0;
6cadb320 2861 DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
a41b2ff2
PB		 2862 break;
2863
2864 case HltClk:
2865 ret = s->clock_enabled;
6cadb320 2866 DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
a41b2ff2
PB		 2867 break;
2868
2869 case PCIRevisionID:
6cadb320
FB		 2870 ret = RTL8139_PCI_REVID;
2871 DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
a41b2ff2
PB		 2872 break;
2873
2874 case TxThresh:
2875 ret = s->TxThresh;
6cadb320 2876 DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2877 break;
2878
2879 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2880 ret = s->TxConfig >> 24;
6cadb320 2881 DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
a41b2ff2
PB		 2882 break;
2883
2884 default:
6cadb320 2885 DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
a41b2ff2
PB		 2886 ret = 0;
2887 break;
2888 }
2889
2890 return ret;
2891}
2892
2893static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2894{
2895 RTL8139State *s = opaque;
2896 uint32_t ret;
2897
2898 addr &= 0xfe; /* mask lower bit */
2899
2900 switch (addr)
2901 {
2902 case IntrMask:
2903 ret = rtl8139_IntrMask_read(s);
2904 break;
2905
2906 case IntrStatus:
2907 ret = rtl8139_IntrStatus_read(s);
2908 break;
2909
2910 case MultiIntr:
2911 ret = rtl8139_MultiIntr_read(s);
2912 break;
2913
2914 case RxBufPtr:
2915 ret = rtl8139_RxBufPtr_read(s);
2916 break;
2917
6cadb320
FB		 2918 case RxBufAddr:
2919 ret = rtl8139_RxBufAddr_read(s);
2920 break;
2921
a41b2ff2
PB		 2922 case BasicModeCtrl:
2923 ret = rtl8139_BasicModeCtrl_read(s);
2924 break;
2925 case BasicModeStatus:
2926 ret = rtl8139_BasicModeStatus_read(s);
2927 break;
2928 case NWayAdvert:
2929 ret = s->NWayAdvert;
6cadb320 2930 DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2931 break;
2932 case NWayLPAR:
2933 ret = s->NWayLPAR;
6cadb320 2934 DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2935 break;
2936 case NWayExpansion:
2937 ret = s->NWayExpansion;
6cadb320 2938 DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
a41b2ff2
PB		 2939 break;
2940
2941 case CpCmd:
2942 ret = rtl8139_CpCmd_read(s);
2943 break;
2944
6cadb320
FB		 2945 case IntrMitigate:
2946 ret = rtl8139_IntrMitigate_read(s);
2947 break;
2948
a41b2ff2
PB		 2949 case TxSummary:
2950 ret = rtl8139_TSAD_read(s);
2951 break;
2952
2953 case CSCR:
2954 ret = rtl8139_CSCR_read(s);
2955 break;
2956
2957 default:
6cadb320 2958 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
a41b2ff2
PB		 2959
2960#ifdef TARGET_WORDS_BIGENDIAN
2961 ret = rtl8139_io_readb(opaque, addr) << 8;
2962 ret |= rtl8139_io_readb(opaque, addr + 1);
2963#else
2964 ret = rtl8139_io_readb(opaque, addr);
2965 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2966#endif
2967
6cadb320 2968 DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
a41b2ff2
PB		 2969 break;
2970 }
2971
2972 return ret;
2973}
2974
2975static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2976{
2977 RTL8139State *s = opaque;
2978 uint32_t ret;
2979
2980 addr &= 0xfc; /* also mask low 2 bits */
2981
2982 switch (addr)
2983 {
2984 case RxMissed:
2985 ret = s->RxMissed;
2986
6cadb320 2987 DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
a41b2ff2
PB		 2988 break;
2989
2990 case TxConfig:
2991 ret = rtl8139_TxConfig_read(s);
2992 break;
2993
2994 case RxConfig:
2995 ret = rtl8139_RxConfig_read(s);
2996 break;
2997
2998 case TxStatus0 ... TxStatus0+4*4-1:
2999 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3000 break;
3001
3002 case TxAddr0 ... TxAddr0+4*4-1:
3003 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3004 break;
3005
3006 case RxBuf:
3007 ret = rtl8139_RxBuf_read(s);
3008 break;
3009
3010 case RxRingAddrLO:
3011 ret = s->RxRingAddrLO;
6cadb320 3012 DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
a41b2ff2
PB		 3013 break;
3014
3015 case RxRingAddrHI:
3016 ret = s->RxRingAddrHI;
6cadb320
FB		 3017 DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3018 break;
3019
3020 case Timer:
3021 ret = s->TCTR;
3022 DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3023 break;
3024
3025 case FlashReg:
3026 ret = s->TimerInt;
3027 DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
a41b2ff2
PB		 3028 break;
3029
3030 default:
6cadb320 3031 DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
a41b2ff2
PB		 3032
3033#ifdef TARGET_WORDS_BIGENDIAN
3034 ret = rtl8139_io_readb(opaque, addr) << 24;
3035 ret |= rtl8139_io_readb(opaque, addr + 1) << 16;
3036 ret |= rtl8139_io_readb(opaque, addr + 2) << 8;
3037 ret |= rtl8139_io_readb(opaque, addr + 3);
3038#else
3039 ret = rtl8139_io_readb(opaque, addr);
3040 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3041 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3042 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3043#endif
3044
6cadb320 3045 DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
a41b2ff2
PB		 3046 break;
3047 }
3048
3049 return ret;
3050}
3051
3052/* */
3053
3054static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3055{
3056 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3057}
3058
3059static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3060{
3061 rtl8139_io_writew(opaque, addr & 0xFF, val);
3062}
3063
3064static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3065{
3066 rtl8139_io_writel(opaque, addr & 0xFF, val);
3067}
3068
3069static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3070{
3071 return rtl8139_io_readb(opaque, addr & 0xFF);
3072}
3073
3074static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3075{
3076 return rtl8139_io_readw(opaque, addr & 0xFF);
3077}
3078
3079static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3080{
3081 return rtl8139_io_readl(opaque, addr & 0xFF);
3082}
3083
3084/* */
3085
3086static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3087{
3088 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3089}
3090
3091static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3092{
3093 rtl8139_io_writew(opaque, addr & 0xFF, val);
3094}
3095
3096static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3097{
3098 rtl8139_io_writel(opaque, addr & 0xFF, val);
3099}
3100
3101static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3102{
3103 return rtl8139_io_readb(opaque, addr & 0xFF);
3104}
3105
3106static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3107{
3108 return rtl8139_io_readw(opaque, addr & 0xFF);
3109}
3110
3111static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3112{
3113 return rtl8139_io_readl(opaque, addr & 0xFF);
3114}
3115
3116/* */
3117
3118static void rtl8139_save(QEMUFile* f,void* opaque)
3119{
3120 RTL8139State* s=(RTL8139State*)opaque;
3121 int i;
3122
1941d19c
FB		 3123 pci_device_save(s->pci_dev, f);
3124
a41b2ff2
PB		 3125 qemu_put_buffer(f, s->phys, 6);
3126 qemu_put_buffer(f, s->mult, 8);
3127
3128 for (i=0; i<4; ++i)
3129 {
3130 qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3131 }
3132 for (i=0; i<4; ++i)
3133 {
3134 qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3135 }
3136
3137 qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
3138 qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3139 qemu_put_be32s(f, &s->RxBufPtr);
3140 qemu_put_be32s(f, &s->RxBufAddr);
3141
3142 qemu_put_be16s(f, &s->IntrStatus);
3143 qemu_put_be16s(f, &s->IntrMask);
3144
3145 qemu_put_be32s(f, &s->TxConfig);
3146 qemu_put_be32s(f, &s->RxConfig);
3147 qemu_put_be32s(f, &s->RxMissed);
3148 qemu_put_be16s(f, &s->CSCR);
3149
3150 qemu_put_8s(f, &s->Cfg9346);
3151 qemu_put_8s(f, &s->Config0);
3152 qemu_put_8s(f, &s->Config1);
3153 qemu_put_8s(f, &s->Config3);
3154 qemu_put_8s(f, &s->Config4);
3155 qemu_put_8s(f, &s->Config5);
3156
3157 qemu_put_8s(f, &s->clock_enabled);
3158 qemu_put_8s(f, &s->bChipCmdState);
3159
3160 qemu_put_be16s(f, &s->MultiIntr);
3161
3162 qemu_put_be16s(f, &s->BasicModeCtrl);
3163 qemu_put_be16s(f, &s->BasicModeStatus);
3164 qemu_put_be16s(f, &s->NWayAdvert);
3165 qemu_put_be16s(f, &s->NWayLPAR);
3166 qemu_put_be16s(f, &s->NWayExpansion);
3167
3168 qemu_put_be16s(f, &s->CpCmd);
3169 qemu_put_8s(f, &s->TxThresh);
3170
80a34d67
PB		 3171 i = 0;
3172 qemu_put_be32s(f, &i); /* unused. */
a41b2ff2
PB		 3173 qemu_put_buffer(f, s->macaddr, 6);
3174 qemu_put_be32s(f, &s->rtl8139_mmio_io_addr);
3175
3176 qemu_put_be32s(f, &s->currTxDesc);
3177 qemu_put_be32s(f, &s->currCPlusRxDesc);
3178 qemu_put_be32s(f, &s->currCPlusTxDesc);
3179 qemu_put_be32s(f, &s->RxRingAddrLO);
3180 qemu_put_be32s(f, &s->RxRingAddrHI);
3181
3182 for (i=0; i<EEPROM_9346_SIZE; ++i)
3183 {
3184 qemu_put_be16s(f, &s->eeprom.contents[i]);
3185 }
3186 qemu_put_be32s(f, &s->eeprom.mode);
3187 qemu_put_be32s(f, &s->eeprom.tick);
3188 qemu_put_8s(f, &s->eeprom.address);
3189 qemu_put_be16s(f, &s->eeprom.input);
3190 qemu_put_be16s(f, &s->eeprom.output);
3191
3192 qemu_put_8s(f, &s->eeprom.eecs);
3193 qemu_put_8s(f, &s->eeprom.eesk);
3194 qemu_put_8s(f, &s->eeprom.eedi);
3195 qemu_put_8s(f, &s->eeprom.eedo);
6cadb320
FB		 3196
3197 qemu_put_be32s(f, &s->TCTR);
3198 qemu_put_be32s(f, &s->TimerInt);
3199 qemu_put_be64s(f, &s->TCTR_base);
3200
3201 RTL8139TallyCounters_save(f, &s->tally_counters);
a41b2ff2
PB		 3202}
3203
3204static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
3205{
3206 RTL8139State* s=(RTL8139State*)opaque;
1941d19c 3207 int i, ret;
a41b2ff2 3208
6cadb320 3209 /* just 2 versions for now */
1941d19c 3210 if (version_id > 3)
a41b2ff2
PB		 3211 return -EINVAL;
3212
1941d19c
FB		 3213 if (version_id >= 3) {
3214 ret = pci_device_load(s->pci_dev, f);
3215 if (ret < 0)
3216 return ret;
3217 }
3218
6cadb320 3219 /* saved since version 1 */
a41b2ff2
PB		 3220 qemu_get_buffer(f, s->phys, 6);
3221 qemu_get_buffer(f, s->mult, 8);
3222
3223 for (i=0; i<4; ++i)
3224 {
3225 qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3226 }
3227 for (i=0; i<4; ++i)
3228 {
3229 qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3230 }
3231
3232 qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
3233 qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3234 qemu_get_be32s(f, &s->RxBufPtr);
3235 qemu_get_be32s(f, &s->RxBufAddr);
3236
3237 qemu_get_be16s(f, &s->IntrStatus);
3238 qemu_get_be16s(f, &s->IntrMask);
3239
3240 qemu_get_be32s(f, &s->TxConfig);
3241 qemu_get_be32s(f, &s->RxConfig);
3242 qemu_get_be32s(f, &s->RxMissed);
3243 qemu_get_be16s(f, &s->CSCR);
3244
3245 qemu_get_8s(f, &s->Cfg9346);
3246 qemu_get_8s(f, &s->Config0);
3247 qemu_get_8s(f, &s->Config1);
3248 qemu_get_8s(f, &s->Config3);
3249 qemu_get_8s(f, &s->Config4);
3250 qemu_get_8s(f, &s->Config5);
3251
3252 qemu_get_8s(f, &s->clock_enabled);
3253 qemu_get_8s(f, &s->bChipCmdState);
3254
3255 qemu_get_be16s(f, &s->MultiIntr);
3256
3257 qemu_get_be16s(f, &s->BasicModeCtrl);
3258 qemu_get_be16s(f, &s->BasicModeStatus);
3259 qemu_get_be16s(f, &s->NWayAdvert);
3260 qemu_get_be16s(f, &s->NWayLPAR);
3261 qemu_get_be16s(f, &s->NWayExpansion);
3262
3263 qemu_get_be16s(f, &s->CpCmd);
3264 qemu_get_8s(f, &s->TxThresh);
3265
80a34d67 3266 qemu_get_be32s(f, &i); /* unused. */
a41b2ff2
PB		 3267 qemu_get_buffer(f, s->macaddr, 6);
3268 qemu_get_be32s(f, &s->rtl8139_mmio_io_addr);
3269
3270 qemu_get_be32s(f, &s->currTxDesc);
3271 qemu_get_be32s(f, &s->currCPlusRxDesc);
3272 qemu_get_be32s(f, &s->currCPlusTxDesc);
3273 qemu_get_be32s(f, &s->RxRingAddrLO);
3274 qemu_get_be32s(f, &s->RxRingAddrHI);
3275
3276 for (i=0; i<EEPROM_9346_SIZE; ++i)
3277 {
3278 qemu_get_be16s(f, &s->eeprom.contents[i]);
3279 }
3280 qemu_get_be32s(f, &s->eeprom.mode);
3281 qemu_get_be32s(f, &s->eeprom.tick);
3282 qemu_get_8s(f, &s->eeprom.address);
3283 qemu_get_be16s(f, &s->eeprom.input);
3284 qemu_get_be16s(f, &s->eeprom.output);
3285
3286 qemu_get_8s(f, &s->eeprom.eecs);
3287 qemu_get_8s(f, &s->eeprom.eesk);
3288 qemu_get_8s(f, &s->eeprom.eedi);
3289 qemu_get_8s(f, &s->eeprom.eedo);
3290
6cadb320
FB		 3291 /* saved since version 2 */
3292 if (version_id >= 2)
3293 {
3294 qemu_get_be32s(f, &s->TCTR);
3295 qemu_get_be32s(f, &s->TimerInt);
3296 qemu_get_be64s(f, &s->TCTR_base);
3297
3298 RTL8139TallyCounters_load(f, &s->tally_counters);
3299 }
3300 else
3301 {
3302 /* not saved, use default */
3303 s->TCTR = 0;
3304 s->TimerInt = 0;
3305 s->TCTR_base = 0;
3306
3307 RTL8139TallyCounters_clear(&s->tally_counters);
3308 }
3309
a41b2ff2
PB		 3310 return 0;
3311}
3312
3313/***********************************************************/
3314/* PCI RTL8139 definitions */
3315
3316typedef struct PCIRTL8139State {
3317 PCIDevice dev;
3318 RTL8139State rtl8139;
3319} PCIRTL8139State;
3320
5fafdf24 3321static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
a41b2ff2
PB		 3322 uint32_t addr, uint32_t size, int type)
3323{
3324 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3325 RTL8139State *s = &d->rtl8139;
3326
3327 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3328}
3329
5fafdf24 3330static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
a41b2ff2
PB		 3331 uint32_t addr, uint32_t size, int type)
3332{
3333 PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3334 RTL8139State *s = &d->rtl8139;
3335
3336 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3337 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3338
3339 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3340 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3341
3342 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3343 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3344}
3345
3346static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
3347 rtl8139_mmio_readb,
3348 rtl8139_mmio_readw,
3349 rtl8139_mmio_readl,
3350};
3351
3352static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
3353 rtl8139_mmio_writeb,
3354 rtl8139_mmio_writew,
3355 rtl8139_mmio_writel,
3356};
3357
6cadb320
FB		 3358static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3359{
5fafdf24 3360 int64_t next_time = current_time +
6cadb320
FB		 3361 muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
3362 if (next_time <= current_time)
3363 next_time = current_time + 1;
3364 return next_time;
3365}
3366
3367#if RTL8139_ONBOARD_TIMER
3368static void rtl8139_timer(void *opaque)
3369{
3370 RTL8139State *s = opaque;
3371
3372 int is_timeout = 0;
3373
3374 int64_t curr_time;
3375 uint32_t curr_tick;
3376
3377 if (!s->clock_enabled)
3378 {
3379 DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3380 return;
3381 }
3382
3383 curr_time = qemu_get_clock(vm_clock);
3384
3385 curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
3386
3387 if (s->TimerInt && curr_tick >= s->TimerInt)
3388 {
3389 if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3390 {
3391 is_timeout = 1;
3392 }
3393 }
3394
3395 s->TCTR = curr_tick;
3396
3397// DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3398
3399 if (is_timeout)
3400 {
3401 DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3402 s->IntrStatus |= PCSTimeout;
3403 rtl8139_update_irq(s);
3404 }
3405
5fafdf24 3406 qemu_mod_timer(s->timer,
6cadb320
FB		 3407 rtl8139_get_next_tctr_time(s,curr_time));
3408}
3409#endif /* RTL8139_ONBOARD_TIMER */
3410
abcebc7e 3411void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
a41b2ff2
PB		 3412{
3413 PCIRTL8139State *d;
3414 RTL8139State *s;
3415 uint8_t *pci_conf;
3b46e624 3416
a41b2ff2
PB		 3417 d = (PCIRTL8139State *)pci_register_device(bus,
3418 "RTL8139", sizeof(PCIRTL8139State),
5fafdf24 3419 devfn,
a41b2ff2
PB		 3420 NULL, NULL);
3421 pci_conf = d->dev.config;
3422 pci_conf[0x00] = 0xec; /* Realtek 8139 */
3423 pci_conf[0x01] = 0x10;
3424 pci_conf[0x02] = 0x39;
3425 pci_conf[0x03] = 0x81;
3426 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
6cadb320 3427 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
a41b2ff2
PB		 3428 pci_conf[0x0a] = 0x00; /* ethernet network controller */
3429 pci_conf[0x0b] = 0x02;
3430 pci_conf[0x0e] = 0x00; /* header_type */
3431 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3432 pci_conf[0x34] = 0xdc;
3433
3434 s = &d->rtl8139;
3435
3436 /* I/O handler for memory-mapped I/O */
3437 s->rtl8139_mmio_io_addr =
3438 cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
3439
5fafdf24 3440 pci_register_io_region(&d->dev, 0, 0x100,
a41b2ff2
PB		 3441 PCI_ADDRESS_SPACE_IO, rtl8139_ioport_map);
3442
5fafdf24 3443 pci_register_io_region(&d->dev, 1, 0x100,
a41b2ff2
PB		 3444 PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
3445
a41b2ff2
PB		 3446 s->pci_dev = (PCIDevice *)d;
3447 memcpy(s->macaddr, nd->macaddr, 6);
3448 rtl8139_reset(s);
3449 s->vc = qemu_new_vlan_client(nd->vlan, rtl8139_receive,
3450 rtl8139_can_receive, s);
3451
3452 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
3453 "rtl8139 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
3454 s->macaddr[0],
3455 s->macaddr[1],
3456 s->macaddr[2],
3457 s->macaddr[3],
3458 s->macaddr[4],
3459 s->macaddr[5]);
6cadb320
FB		 3460
3461 s->cplus_txbuffer = NULL;
3462 s->cplus_txbuffer_len = 0;
3463 s->cplus_txbuffer_offset = 0;
3b46e624 3464
a41b2ff2 3465 /* XXX: instance number ? */
1941d19c 3466 register_savevm("rtl8139", 0, 3, rtl8139_save, rtl8139_load, s);
6cadb320
FB		 3467
3468#if RTL8139_ONBOARD_TIMER
3469 s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3470
5fafdf24 3471 qemu_mod_timer(s->timer,
6cadb320
FB		 3472 rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3473#endif /* RTL8139_ONBOARD_TIMER */
a41b2ff2 3474}
6cadb320 3475
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