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rtl8139: Fix compilation for w32/w64
[mirror_qemu.git] / hw / rtl8139.c
CommitLineData
a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f
BP		 51/* For crc32 */
52#include <zlib.h>
53
87ecb68b
PB		 54#include "hw.h"
55#include "pci.h"
56#include "qemu-timer.h"
57#include "net.h"
254111ec 58#include "loader.h"
1ca4d09a 59#include "sysemu.h"
bf6b87a8 60#include "iov.h"
a41b2ff2 61
a41b2ff2
PB		 62/* debug RTL8139 card */
63//#define DEBUG_RTL8139 1
64
6cadb320
FB		 65#define PCI_FREQUENCY 33000000L
66
a41b2ff2
PB		 67/* debug RTL8139 card C+ mode only */
68//#define DEBUG_RTL8139CP 1
69
a41b2ff2
PB		 70#define SET_MASKED(input, mask, curr) \
71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72
73/* arg % size for size which is a power of 2 */
74#define MOD2(input, size) \
75 ( ( input ) & ( size - 1 ) )
76
18dabfd1
BP		 77#define ETHER_ADDR_LEN 6
78#define ETHER_TYPE_LEN 2
79#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
80#define ETH_P_IP 0x0800 /* Internet Protocol packet */
81#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
82#define ETH_MTU 1500
83
84#define VLAN_TCI_LEN 2
85#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
86
6cadb320 87#if defined (DEBUG_RTL8139)
7cdeb319
BP		 88# define DPRINTF(fmt, ...) \
89 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 90#else
c6a0487b 91static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
ec48c774
BP		 92{
93 return 0;
94}
6cadb320
FB		 95#endif
96
a41b2ff2
PB		 97/* Symbolic offsets to registers. */
98enum RTL8139_registers {
99 MAC0 = 0, /* Ethernet hardware address. */
100 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 101 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
102 /* Dump Tally Conter control register(64bit). C+ mode only */
103 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 104 RxBuf = 0x30,
105 ChipCmd = 0x37,
106 RxBufPtr = 0x38,
107 RxBufAddr = 0x3A,
108 IntrMask = 0x3C,
109 IntrStatus = 0x3E,
110 TxConfig = 0x40,
111 RxConfig = 0x44,
112 Timer = 0x48, /* A general-purpose counter. */
113 RxMissed = 0x4C, /* 24 bits valid, write clears. */
114 Cfg9346 = 0x50,
115 Config0 = 0x51,
116 Config1 = 0x52,
117 FlashReg = 0x54,
118 MediaStatus = 0x58,
119 Config3 = 0x59,
120 Config4 = 0x5A, /* absent on RTL-8139A */
121 HltClk = 0x5B,
122 MultiIntr = 0x5C,
123 PCIRevisionID = 0x5E,
124 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
125 BasicModeCtrl = 0x62,
126 BasicModeStatus = 0x64,
127 NWayAdvert = 0x66,
128 NWayLPAR = 0x68,
129 NWayExpansion = 0x6A,
130 /* Undocumented registers, but required for proper operation. */
131 FIFOTMS = 0x70, /* FIFO Control and test. */
132 CSCR = 0x74, /* Chip Status and Configuration Register. */
133 PARA78 = 0x78,
134 PARA7c = 0x7c, /* Magic transceiver parameter register. */
135 Config5 = 0xD8, /* absent on RTL-8139A */
136 /* C+ mode */
137 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
138 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
139 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
140 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
141 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
142 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
143 TxThresh = 0xEC, /* Early Tx threshold */
144};
145
146enum ClearBitMasks {
147 MultiIntrClear = 0xF000,
148 ChipCmdClear = 0xE2,
149 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
150};
151
152enum ChipCmdBits {
153 CmdReset = 0x10,
154 CmdRxEnb = 0x08,
155 CmdTxEnb = 0x04,
156 RxBufEmpty = 0x01,
157};
158
159/* C+ mode */
160enum CplusCmdBits {
6cadb320
FB		 161 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
162 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
163 CPlusRxEnb = 0x0002,
164 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 165};
166
167/* Interrupt register bits, using my own meaningful names. */
168enum IntrStatusBits {
169 PCIErr = 0x8000,
170 PCSTimeout = 0x4000,
171 RxFIFOOver = 0x40,
172 RxUnderrun = 0x20,
173 RxOverflow = 0x10,
174 TxErr = 0x08,
175 TxOK = 0x04,
176 RxErr = 0x02,
177 RxOK = 0x01,
178
179 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
180};
181
182enum TxStatusBits {
183 TxHostOwns = 0x2000,
184 TxUnderrun = 0x4000,
185 TxStatOK = 0x8000,
186 TxOutOfWindow = 0x20000000,
187 TxAborted = 0x40000000,
188 TxCarrierLost = 0x80000000,
189};
190enum RxStatusBits {
191 RxMulticast = 0x8000,
192 RxPhysical = 0x4000,
193 RxBroadcast = 0x2000,
194 RxBadSymbol = 0x0020,
195 RxRunt = 0x0010,
196 RxTooLong = 0x0008,
197 RxCRCErr = 0x0004,
198 RxBadAlign = 0x0002,
199 RxStatusOK = 0x0001,
200};
201
202/* Bits in RxConfig. */
203enum rx_mode_bits {
204 AcceptErr = 0x20,
205 AcceptRunt = 0x10,
206 AcceptBroadcast = 0x08,
207 AcceptMulticast = 0x04,
208 AcceptMyPhys = 0x02,
209 AcceptAllPhys = 0x01,
210};
211
212/* Bits in TxConfig. */
213enum tx_config_bits {
214
215 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
216 TxIFGShift = 24,
217 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
218 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
219 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
220 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
221
222 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
223 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
224 TxClearAbt = (1 << 0), /* Clear abort (WO) */
225 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
226 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
227
228 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
229};
230
231
232/* Transmit Status of All Descriptors (TSAD) Register */
233enum TSAD_bits {
234 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
235 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
236 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
237 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
238 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
239 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
240 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
241 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
242 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
243 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
244 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
245 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
246 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
247 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
248 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
249 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
250};
251
252
253/* Bits in Config1 */
254enum Config1Bits {
255 Cfg1_PM_Enable = 0x01,
256 Cfg1_VPD_Enable = 0x02,
257 Cfg1_PIO = 0x04,
258 Cfg1_MMIO = 0x08,
259 LWAKE = 0x10, /* not on 8139, 8139A */
260 Cfg1_Driver_Load = 0x20,
261 Cfg1_LED0 = 0x40,
262 Cfg1_LED1 = 0x80,
263 SLEEP = (1 << 1), /* only on 8139, 8139A */
264 PWRDN = (1 << 0), /* only on 8139, 8139A */
265};
266
267/* Bits in Config3 */
268enum Config3Bits {
269 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
270 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
271 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
272 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
273 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
274 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
275 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
276 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
277};
278
279/* Bits in Config4 */
280enum Config4Bits {
281 LWPTN = (1 << 2), /* not on 8139, 8139A */
282};
283
284/* Bits in Config5 */
285enum Config5Bits {
286 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
287 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
288 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
289 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
290 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
291 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
292 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
293};
294
295enum RxConfigBits {
296 /* rx fifo threshold */
297 RxCfgFIFOShift = 13,
298 RxCfgFIFONone = (7 << RxCfgFIFOShift),
299
300 /* Max DMA burst */
301 RxCfgDMAShift = 8,
302 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
303
304 /* rx ring buffer length */
305 RxCfgRcv8K = 0,
306 RxCfgRcv16K = (1 << 11),
307 RxCfgRcv32K = (1 << 12),
308 RxCfgRcv64K = (1 << 11) | (1 << 12),
309
310 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
311 RxNoWrap = (1 << 7),
312};
313
314/* Twister tuning parameters from RealTek.
315 Completely undocumented, but required to tune bad links on some boards. */
316/*
317enum CSCRBits {
318 CSCR_LinkOKBit = 0x0400,
319 CSCR_LinkChangeBit = 0x0800,
320 CSCR_LinkStatusBits = 0x0f000,
321 CSCR_LinkDownOffCmd = 0x003c0,
322 CSCR_LinkDownCmd = 0x0f3c0,
323*/
324enum CSCRBits {
5fafdf24 325 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 326 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
327 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
328 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 329 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 330 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
331 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
332 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
333 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
334};
335
336enum Cfg9346Bits {
337 Cfg9346_Lock = 0x00,
338 Cfg9346_Unlock = 0xC0,
339};
340
341typedef enum {
342 CH_8139 = 0,
343 CH_8139_K,
344 CH_8139A,
345 CH_8139A_G,
346 CH_8139B,
347 CH_8130,
348 CH_8139C,
349 CH_8100,
350 CH_8100B_8139D,
351 CH_8101,
c227f099 352} chip_t;
a41b2ff2
PB		 353
354enum chip_flags {
355 HasHltClk = (1 << 0),
356 HasLWake = (1 << 1),
357};
358
359#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
360 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
361#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
362
6cadb320
FB		 363#define RTL8139_PCI_REVID_8139 0x10
364#define RTL8139_PCI_REVID_8139CPLUS 0x20
365
366#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
367
a41b2ff2
PB		 368/* Size is 64 * 16bit words */
369#define EEPROM_9346_ADDR_BITS 6
370#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
371#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
372
373enum Chip9346Operation
374{
375 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
376 Chip9346_op_read = 0x80, /* 10 AAAAAA */
377 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
378 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
379 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
380 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
381 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
382};
383
384enum Chip9346Mode
385{
386 Chip9346_none = 0,
387 Chip9346_enter_command_mode,
388 Chip9346_read_command,
389 Chip9346_data_read, /* from output register */
390 Chip9346_data_write, /* to input register, then to contents at specified address */
391 Chip9346_data_write_all, /* to input register, then filling contents */
392};
393
394typedef struct EEprom9346
395{
396 uint16_t contents[EEPROM_9346_SIZE];
397 int mode;
398 uint32_t tick;
399 uint8_t address;
400 uint16_t input;
401 uint16_t output;
402
403 uint8_t eecs;
404 uint8_t eesk;
405 uint8_t eedi;
406 uint8_t eedo;
407} EEprom9346;
408
6cadb320
FB		 409typedef struct RTL8139TallyCounters
410{
411 /* Tally counters */
412 uint64_t TxOk;
413 uint64_t RxOk;
414 uint64_t TxERR;
415 uint32_t RxERR;
416 uint16_t MissPkt;
417 uint16_t FAE;
418 uint32_t Tx1Col;
419 uint32_t TxMCol;
420 uint64_t RxOkPhy;
421 uint64_t RxOkBrd;
422 uint32_t RxOkMul;
423 uint16_t TxAbt;
424 uint16_t TxUndrn;
425} RTL8139TallyCounters;
426
427/* Clears all tally counters */
428static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
429
430/* Writes tally counters to specified physical memory address */
c227f099 431static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
6cadb320 432
a41b2ff2 433typedef struct RTL8139State {
efd6dd45 434 PCIDevice dev;
a41b2ff2
PB		 435 uint8_t phys[8]; /* mac address */
436 uint8_t mult[8]; /* multicast mask array */
437
6cadb320 438 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 439 uint32_t TxAddr[4]; /* TxAddr0 */
440 uint32_t RxBuf; /* Receive buffer */
441 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
442 uint32_t RxBufPtr;
443 uint32_t RxBufAddr;
444
445 uint16_t IntrStatus;
446 uint16_t IntrMask;
447
448 uint32_t TxConfig;
449 uint32_t RxConfig;
450 uint32_t RxMissed;
451
452 uint16_t CSCR;
453
454 uint8_t Cfg9346;
455 uint8_t Config0;
456 uint8_t Config1;
457 uint8_t Config3;
458 uint8_t Config4;
459 uint8_t Config5;
460
461 uint8_t clock_enabled;
462 uint8_t bChipCmdState;
463
464 uint16_t MultiIntr;
465
466 uint16_t BasicModeCtrl;
467 uint16_t BasicModeStatus;
468 uint16_t NWayAdvert;
469 uint16_t NWayLPAR;
470 uint16_t NWayExpansion;
471
472 uint16_t CpCmd;
473 uint8_t TxThresh;
474
1673ad51 475 NICState *nic;
254111ec 476 NICConf conf;
a41b2ff2
PB		 477 int rtl8139_mmio_io_addr;
478
479 /* C ring mode */
480 uint32_t currTxDesc;
481
482 /* C+ mode */
2c3891ab
AL		 483 uint32_t cplus_enabled;
484
a41b2ff2
PB		 485 uint32_t currCPlusRxDesc;
486 uint32_t currCPlusTxDesc;
487
488 uint32_t RxRingAddrLO;
489 uint32_t RxRingAddrHI;
490
491 EEprom9346 eeprom;
6cadb320
FB		 492
493 uint32_t TCTR;
494 uint32_t TimerInt;
495 int64_t TCTR_base;
496
497 /* Tally counters */
498 RTL8139TallyCounters tally_counters;
499
500 /* Non-persistent data */
501 uint8_t *cplus_txbuffer;
502 int cplus_txbuffer_len;
503 int cplus_txbuffer_offset;
504
505 /* PCI interrupt timer */
506 QEMUTimer *timer;
05447803 507 int64_t TimerExpire;
6cadb320 508
c574ba5a
AW		 509 /* Support migration to/from old versions */
510 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 511} RTL8139State;
512
05447803
FZ		 513static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
514
9596ebb7 515static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 516{
7cdeb319 517 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 518
519 switch (command & Chip9346_op_mask)
520 {
521 case Chip9346_op_read:
522 {
523 eeprom->address = command & EEPROM_9346_ADDR_MASK;
524 eeprom->output = eeprom->contents[eeprom->address];
525 eeprom->eedo = 0;
526 eeprom->tick = 0;
527 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 528 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
529 eeprom->address, eeprom->output);
a41b2ff2
PB		 530 }
531 break;
532
533 case Chip9346_op_write:
534 {
535 eeprom->address = command & EEPROM_9346_ADDR_MASK;
536 eeprom->input = 0;
537 eeprom->tick = 0;
538 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 539 DPRINTF("eeprom begin write to address 0x%02x\n",
540 eeprom->address);
a41b2ff2
PB		 541 }
542 break;
543 default:
544 eeprom->mode = Chip9346_none;
545 switch (command & Chip9346_op_ext_mask)
546 {
547 case Chip9346_op_write_enable:
7cdeb319 548 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 549 break;
550 case Chip9346_op_write_all:
7cdeb319 551 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 552 break;
553 case Chip9346_op_write_disable:
7cdeb319 554 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 555 break;
556 }
557 break;
558 }
559}
560
9596ebb7 561static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 562{
563 int bit = eeprom->eedi?1:0;
564
565 ++ eeprom->tick;
566
7cdeb319
BP		 567 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
568 eeprom->eedo);
a41b2ff2
PB		 569
570 switch (eeprom->mode)
571 {
572 case Chip9346_enter_command_mode:
573 if (bit)
574 {
575 eeprom->mode = Chip9346_read_command;
576 eeprom->tick = 0;
577 eeprom->input = 0;
7cdeb319 578 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 579 }
580 break;
581
582 case Chip9346_read_command:
583 eeprom->input = (eeprom->input << 1) | (bit & 1);
584 if (eeprom->tick == 8)
585 {
586 prom9346_decode_command(eeprom, eeprom->input & 0xff);
587 }
588 break;
589
590 case Chip9346_data_read:
591 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
592 eeprom->output <<= 1;
593 if (eeprom->tick == 16)
594 {
6cadb320
FB		 595#if 1
596 // the FreeBSD drivers (rl and re) don't explicitly toggle
597 // CS between reads (or does setting Cfg9346 to 0 count too?),
598 // so we need to enter wait-for-command state here
599 eeprom->mode = Chip9346_enter_command_mode;
600 eeprom->input = 0;
601 eeprom->tick = 0;
602
7cdeb319 603 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 604#else
605 // original behaviour
a41b2ff2
PB		 606 ++eeprom->address;
607 eeprom->address &= EEPROM_9346_ADDR_MASK;
608 eeprom->output = eeprom->contents[eeprom->address];
609 eeprom->tick = 0;
610
7cdeb319
BP		 611 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
612 eeprom->address, eeprom->output);
a41b2ff2
PB		 613#endif
614 }
615 break;
616
617 case Chip9346_data_write:
618 eeprom->input = (eeprom->input << 1) | (bit & 1);
619 if (eeprom->tick == 16)
620 {
7cdeb319
BP		 621 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
622 eeprom->address, eeprom->input);
6cadb320 623
a41b2ff2
PB		 624 eeprom->contents[eeprom->address] = eeprom->input;
625 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
626 eeprom->tick = 0;
627 eeprom->input = 0;
628 }
629 break;
630
631 case Chip9346_data_write_all:
632 eeprom->input = (eeprom->input << 1) | (bit & 1);
633 if (eeprom->tick == 16)
634 {
635 int i;
636 for (i = 0; i < EEPROM_9346_SIZE; i++)
637 {
638 eeprom->contents[i] = eeprom->input;
639 }
7cdeb319 640 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 641
a41b2ff2
PB		 642 eeprom->mode = Chip9346_enter_command_mode;
643 eeprom->tick = 0;
644 eeprom->input = 0;
645 }
646 break;
647
648 default:
649 break;
650 }
651}
652
9596ebb7 653static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 654{
655 EEprom9346 *eeprom = &s->eeprom;
656 if (!eeprom->eecs)
657 return 0;
658
659 return eeprom->eedo;
660}
661
9596ebb7
PB		 662/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
663static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 664{
665 EEprom9346 *eeprom = &s->eeprom;
666 uint8_t old_eecs = eeprom->eecs;
667 uint8_t old_eesk = eeprom->eesk;
668
669 eeprom->eecs = eecs;
670 eeprom->eesk = eesk;
671 eeprom->eedi = eedi;
672
7cdeb319
BP		 673 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
674 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 675
676 if (!old_eecs && eecs)
677 {
678 /* Synchronize start */
679 eeprom->tick = 0;
680 eeprom->input = 0;
681 eeprom->output = 0;
682 eeprom->mode = Chip9346_enter_command_mode;
683
7cdeb319 684 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 685 }
686
687 if (!eecs)
688 {
7cdeb319 689 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 690 return;
691 }
692
693 if (!old_eesk && eesk)
694 {
695 /* SK front rules */
696 prom9346_shift_clock(eeprom);
697 }
698}
699
700static void rtl8139_update_irq(RTL8139State *s)
701{
702 int isr;
703 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 704
7cdeb319
BP		 705 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
706 s->IntrMask);
6cadb320 707
efd6dd45 708 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 709}
710
711#define POLYNOMIAL 0x04c11db6
712
713/* From FreeBSD */
714/* XXX: optimize */
715static int compute_mcast_idx(const uint8_t *ep)
716{
717 uint32_t crc;
718 int carry, i, j;
719 uint8_t b;
720
721 crc = 0xffffffff;
722 for (i = 0; i < 6; i++) {
723 b = *ep++;
724 for (j = 0; j < 8; j++) {
725 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
726 crc <<= 1;
727 b >>= 1;
728 if (carry)
729 crc = ((crc ^ POLYNOMIAL) | carry);
730 }
731 }
732 return (crc >> 26);
733}
734
735static int rtl8139_RxWrap(RTL8139State *s)
736{
737 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
738 return (s->RxConfig & (1 << 7));
739}
740
741static int rtl8139_receiver_enabled(RTL8139State *s)
742{
743 return s->bChipCmdState & CmdRxEnb;
744}
745
746static int rtl8139_transmitter_enabled(RTL8139State *s)
747{
748 return s->bChipCmdState & CmdTxEnb;
749}
750
751static int rtl8139_cp_receiver_enabled(RTL8139State *s)
752{
753 return s->CpCmd & CPlusRxEnb;
754}
755
756static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
757{
758 return s->CpCmd & CPlusTxEnb;
759}
760
761static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
762{
763 if (s->RxBufAddr + size > s->RxBufferSize)
764 {
765 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
766
767 /* write packet data */
ccf1d14a 768 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 769 {
7cdeb319 770 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 771
772 if (size > wrapped)
773 {
774 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
775 buf, size-wrapped );
776 }
777
778 /* reset buffer pointer */
779 s->RxBufAddr = 0;
780
781 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
782 buf + (size-wrapped), wrapped );
783
784 s->RxBufAddr = wrapped;
785
786 return;
787 }
788 }
789
790 /* non-wrapping path or overwrapping enabled */
791 cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
792
793 s->RxBufAddr += size;
794}
795
796#define MIN_BUF_SIZE 60
c227f099 797static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2
PB		 798{
799#if TARGET_PHYS_ADDR_BITS > 32
c227f099 800 return low | ((target_phys_addr_t)high << 32);
a41b2ff2
PB		 801#else
802 return low;
803#endif
804}
805
1673ad51 806static int rtl8139_can_receive(VLANClientState *nc)
a41b2ff2 807{
1673ad51 808 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 809 int avail;
810
aa1f17c1 811 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 812 if (!s->clock_enabled)
813 return 1;
814 if (!rtl8139_receiver_enabled(s))
815 return 1;
816
817 if (rtl8139_cp_receiver_enabled(s)) {
818 /* ??? Flow control not implemented in c+ mode.
819 This is a hack to work around slirp deficiencies anyway. */
820 return 1;
821 } else {
822 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
823 s->RxBufferSize);
824 return (avail == 0 || avail >= 1514);
825 }
826}
827
1673ad51 828static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 829{
1673ad51 830 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
18dabfd1 831 /* size is the length of the buffer passed to the driver */
4f1c942b 832 int size = size_;
18dabfd1 833 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 834
835 uint32_t packet_header = 0;
836
18dabfd1 837 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 838 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 839 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
840
7cdeb319 841 DPRINTF(">>> received len=%d\n", size);
a41b2ff2
PB		 842
843 /* test if board clock is stopped */
844 if (!s->clock_enabled)
845 {
7cdeb319 846 DPRINTF("stopped ==========================\n");
4f1c942b 847 return -1;
a41b2ff2
PB		 848 }
849
850 /* first check if receiver is enabled */
851
852 if (!rtl8139_receiver_enabled(s))
853 {
7cdeb319 854 DPRINTF("receiver disabled ================\n");
4f1c942b 855 return -1;
a41b2ff2
PB		 856 }
857
858 /* XXX: check this */
859 if (s->RxConfig & AcceptAllPhys) {
860 /* promiscuous: receive all */
7cdeb319 861 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 862
863 } else {
864 if (!memcmp(buf, broadcast_macaddr, 6)) {
865 /* broadcast address */
866 if (!(s->RxConfig & AcceptBroadcast))
867 {
7cdeb319 868 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 869
870 /* update tally counter */
871 ++s->tally_counters.RxERR;
872
4f1c942b 873 return size;
a41b2ff2
PB		 874 }
875
876 packet_header |= RxBroadcast;
877
7cdeb319 878 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 879
880 /* update tally counter */
881 ++s->tally_counters.RxOkBrd;
882
a41b2ff2
PB		 883 } else if (buf[0] & 0x01) {
884 /* multicast */
885 if (!(s->RxConfig & AcceptMulticast))
886 {
7cdeb319 887 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 888
889 /* update tally counter */
890 ++s->tally_counters.RxERR;
891
4f1c942b 892 return size;
a41b2ff2
PB		 893 }
894
895 int mcast_idx = compute_mcast_idx(buf);
896
897 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
898 {
7cdeb319 899 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 900
901 /* update tally counter */
902 ++s->tally_counters.RxERR;
903
4f1c942b 904 return size;
a41b2ff2
PB		 905 }
906
907 packet_header |= RxMulticast;
908
7cdeb319 909 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 910
911 /* update tally counter */
912 ++s->tally_counters.RxOkMul;
913
a41b2ff2 914 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 915 s->phys[1] == buf[1] &&
916 s->phys[2] == buf[2] &&
917 s->phys[3] == buf[3] &&
918 s->phys[4] == buf[4] &&
a41b2ff2
PB		 919 s->phys[5] == buf[5]) {
920 /* match */
921 if (!(s->RxConfig & AcceptMyPhys))
922 {
7cdeb319 923 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 924
925 /* update tally counter */
926 ++s->tally_counters.RxERR;
927
4f1c942b 928 return size;
a41b2ff2
PB		 929 }
930
931 packet_header |= RxPhysical;
932
7cdeb319 933 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 934
935 /* update tally counter */
936 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 937
938 } else {
939
7cdeb319 940 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 941
942 /* update tally counter */
943 ++s->tally_counters.RxERR;
944
4f1c942b 945 return size;
a41b2ff2
PB		 946 }
947 }
948
18dabfd1
BP		 949 /* if too small buffer, then expand it
950 * Include some tailroom in case a vlan tag is later removed. */
951 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 952 memcpy(buf1, buf, size);
18dabfd1 953 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 954 buf = buf1;
18dabfd1
BP		 955 if (size < MIN_BUF_SIZE) {
956 size = MIN_BUF_SIZE;
957 }
a41b2ff2
PB		 958 }
959
960 if (rtl8139_cp_receiver_enabled(s))
961 {
7cdeb319 962 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 963
964 /* begin C+ receiver mode */
965
966/* w0 ownership flag */
967#define CP_RX_OWN (1<<31)
968/* w0 end of ring flag */
969#define CP_RX_EOR (1<<30)
970/* w0 bits 0...12 : buffer size */
971#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
972/* w1 tag available flag */
973#define CP_RX_TAVA (1<<16)
974/* w1 bits 0...15 : VLAN tag */
975#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
976/* w2 low 32bit of Rx buffer ptr */
977/* w3 high 32bit of Rx buffer ptr */
978
979 int descriptor = s->currCPlusRxDesc;
c227f099 980 target_phys_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 981
982 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
983 cplus_rx_ring_desc += 16 * descriptor;
984
7cdeb319
BP		 985 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
986 "%08x %08x = "TARGET_FMT_plx"\n", descriptor, s->RxRingAddrHI,
987 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 988
989 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
990
991 cpu_physical_memory_read(cplus_rx_ring_desc, (uint8_t *)&val, 4);
992 rxdw0 = le32_to_cpu(val);
993 cpu_physical_memory_read(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
994 rxdw1 = le32_to_cpu(val);
995 cpu_physical_memory_read(cplus_rx_ring_desc+8, (uint8_t *)&val, 4);
996 rxbufLO = le32_to_cpu(val);
997 cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
998 rxbufHI = le32_to_cpu(val);
999
7cdeb319
BP		 1000 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
1001 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 1002
1003 if (!(rxdw0 & CP_RX_OWN))
1004 {
7cdeb319
BP		 1005 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1006 descriptor);
6cadb320 1007
a41b2ff2
PB		 1008 s->IntrStatus |= RxOverflow;
1009 ++s->RxMissed;
6cadb320
FB		 1010
1011 /* update tally counter */
1012 ++s->tally_counters.RxERR;
1013 ++s->tally_counters.MissPkt;
1014
a41b2ff2 1015 rtl8139_update_irq(s);
4f1c942b 1016 return size_;
a41b2ff2
PB		 1017 }
1018
1019 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1020
18dabfd1
BP		 1021 /* write VLAN info to descriptor variables. */
1022 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1023 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1024 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1025 size -= VLAN_HLEN;
1026 /* if too small buffer, use the tailroom added duing expansion */
1027 if (size < MIN_BUF_SIZE) {
1028 size = MIN_BUF_SIZE;
1029 }
1030
1031 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1032 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1033 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1034 &dot1q_buf[ETHER_TYPE_LEN]);
1035
7cdeb319
BP		 1036 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1037 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1038 } else {
1039 /* reset VLAN tag flag */
1040 rxdw1 &= ~CP_RX_TAVA;
1041 }
1042
6cadb320
FB		 1043 /* TODO: scatter the packet over available receive ring descriptors space */
1044
a41b2ff2
PB		 1045 if (size+4 > rx_space)
1046 {
7cdeb319
BP		 1047 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1048 descriptor, rx_space, size);
6cadb320 1049
a41b2ff2
PB		 1050 s->IntrStatus |= RxOverflow;
1051 ++s->RxMissed;
6cadb320
FB		 1052
1053 /* update tally counter */
1054 ++s->tally_counters.RxERR;
1055 ++s->tally_counters.MissPkt;
1056
a41b2ff2 1057 rtl8139_update_irq(s);
4f1c942b 1058 return size_;
a41b2ff2
PB		 1059 }
1060
c227f099 1061 target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1062
1063 /* receive/copy to target memory */
18dabfd1
BP		 1064 if (dot1q_buf) {
1065 cpu_physical_memory_write(rx_addr, buf, 2 * ETHER_ADDR_LEN);
1066 cpu_physical_memory_write(rx_addr + 2 * ETHER_ADDR_LEN,
1067 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1068 size - 2 * ETHER_ADDR_LEN);
1069 } else {
1070 cpu_physical_memory_write(rx_addr, buf, size);
1071 }
a41b2ff2 1072
6cadb320
FB		 1073 if (s->CpCmd & CPlusRxChkSum)
1074 {
1075 /* do some packet checksumming */
1076 }
1077
a41b2ff2 1078 /* write checksum */
18dabfd1 1079 val = cpu_to_le32(crc32(0, buf, size_));
a41b2ff2
PB		 1080 cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1081
1082/* first segment of received packet flag */
1083#define CP_RX_STATUS_FS (1<<29)
1084/* last segment of received packet flag */
1085#define CP_RX_STATUS_LS (1<<28)
1086/* multicast packet flag */
1087#define CP_RX_STATUS_MAR (1<<26)
1088/* physical-matching packet flag */
1089#define CP_RX_STATUS_PAM (1<<25)
1090/* broadcast packet flag */
1091#define CP_RX_STATUS_BAR (1<<24)
1092/* runt packet flag */
1093#define CP_RX_STATUS_RUNT (1<<19)
1094/* crc error flag */
1095#define CP_RX_STATUS_CRC (1<<18)
1096/* IP checksum error flag */
1097#define CP_RX_STATUS_IPF (1<<15)
1098/* UDP checksum error flag */
1099#define CP_RX_STATUS_UDPF (1<<14)
1100/* TCP checksum error flag */
1101#define CP_RX_STATUS_TCPF (1<<13)
1102
1103 /* transfer ownership to target */
1104 rxdw0 &= ~CP_RX_OWN;
1105
1106 /* set first segment bit */
1107 rxdw0 |= CP_RX_STATUS_FS;
1108
1109 /* set last segment bit */
1110 rxdw0 |= CP_RX_STATUS_LS;
1111
1112 /* set received packet type flags */
1113 if (packet_header & RxBroadcast)
1114 rxdw0 |= CP_RX_STATUS_BAR;
1115 if (packet_header & RxMulticast)
1116 rxdw0 |= CP_RX_STATUS_MAR;
1117 if (packet_header & RxPhysical)
1118 rxdw0 |= CP_RX_STATUS_PAM;
1119
1120 /* set received size */
1121 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1122 rxdw0 |= (size+4);
1123
a41b2ff2
PB		 1124 /* update ring data */
1125 val = cpu_to_le32(rxdw0);
1126 cpu_physical_memory_write(cplus_rx_ring_desc, (uint8_t *)&val, 4);
1127 val = cpu_to_le32(rxdw1);
1128 cpu_physical_memory_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1129
6cadb320
FB		 1130 /* update tally counter */
1131 ++s->tally_counters.RxOk;
1132
a41b2ff2
PB		 1133 /* seek to next Rx descriptor */
1134 if (rxdw0 & CP_RX_EOR)
1135 {
1136 s->currCPlusRxDesc = 0;
1137 }
1138 else
1139 {
1140 ++s->currCPlusRxDesc;
1141 }
1142
7cdeb319 1143 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1144
1145 }
1146 else
1147 {
7cdeb319 1148 DPRINTF("in ring Rx mode ================\n");
6cadb320 1149
a41b2ff2
PB		 1150 /* begin ring receiver mode */
1151 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1152
1153 /* if receiver buffer is empty then avail == 0 */
1154
1155 if (avail != 0 && size + 8 >= avail)
1156 {
7cdeb319
BP		 1157 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1158 "read 0x%04x === available 0x%04x need 0x%04x\n",
1159 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1160
a41b2ff2
PB		 1161 s->IntrStatus |= RxOverflow;
1162 ++s->RxMissed;
1163 rtl8139_update_irq(s);
4f1c942b 1164 return size_;
a41b2ff2
PB		 1165 }
1166
1167 packet_header |= RxStatusOK;
1168
1169 packet_header |= (((size+4) << 16) & 0xffff0000);
1170
1171 /* write header */
1172 uint32_t val = cpu_to_le32(packet_header);
1173
1174 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1175
1176 rtl8139_write_buffer(s, buf, size);
1177
1178 /* write checksum */
ccf1d14a 1179 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1180 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1181
1182 /* correct buffer write pointer */
1183 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1184
1185 /* now we can signal we have received something */
1186
7cdeb319
BP		 1187 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1188 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1189 }
1190
1191 s->IntrStatus |= RxOK;
6cadb320
FB		 1192
1193 if (do_interrupt)
1194 {
1195 rtl8139_update_irq(s);
1196 }
4f1c942b
MM		 1197
1198 return size_;
6cadb320
FB		 1199}
1200
1673ad51 1201static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1202{
1673ad51 1203 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1204}
1205
1206static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1207{
1208 s->RxBufferSize = bufferSize;
1209 s->RxBufPtr = 0;
1210 s->RxBufAddr = 0;
1211}
1212
7f23f812 1213static void rtl8139_reset(DeviceState *d)
a41b2ff2 1214{
7f23f812 1215 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1216 int i;
1217
1218 /* restore MAC address */
254111ec 1219 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1220
1221 /* reset interrupt mask */
1222 s->IntrStatus = 0;
1223 s->IntrMask = 0;
1224
1225 rtl8139_update_irq(s);
1226
a41b2ff2
PB		 1227 /* mark all status registers as owned by host */
1228 for (i = 0; i < 4; ++i)
1229 {
1230 s->TxStatus[i] = TxHostOwns;
1231 }
1232
1233 s->currTxDesc = 0;
1234 s->currCPlusRxDesc = 0;
1235 s->currCPlusTxDesc = 0;
1236
1237 s->RxRingAddrLO = 0;
1238 s->RxRingAddrHI = 0;
1239
1240 s->RxBuf = 0;
1241
1242 rtl8139_reset_rxring(s, 8192);
1243
1244 /* ACK the reset */
1245 s->TxConfig = 0;
1246
1247#if 0
1248// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1249 s->clock_enabled = 0;
1250#else
6cadb320 1251 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1252 s->clock_enabled = 1;
1253#endif
1254
1255 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1256
1257 /* set initial state data */
1258 s->Config0 = 0x0; /* No boot ROM */
1259 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1260 s->Config3 = 0x1; /* fast back-to-back compatible */
1261 s->Config5 = 0x0;
1262
5fafdf24 1263 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1264
1265 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1266 s->cplus_enabled = 0;
1267
a41b2ff2
PB		 1268
1269// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1270// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1271 s->BasicModeCtrl = 0x1000; // autonegotiation
1272
1273 s->BasicModeStatus = 0x7809;
1274 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1275 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1276 s->BasicModeStatus |= 0x0004; /* link is up */
1277
1278 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1279 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1280 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1281
1282 /* also reset timer and disable timer interrupt */
1283 s->TCTR = 0;
1284 s->TimerInt = 0;
1285 s->TCTR_base = 0;
1286
1287 /* reset tally counters */
1288 RTL8139TallyCounters_clear(&s->tally_counters);
1289}
1290
b1d8e52e 1291static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1292{
1293 counters->TxOk = 0;
1294 counters->RxOk = 0;
1295 counters->TxERR = 0;
1296 counters->RxERR = 0;
1297 counters->MissPkt = 0;
1298 counters->FAE = 0;
1299 counters->Tx1Col = 0;
1300 counters->TxMCol = 0;
1301 counters->RxOkPhy = 0;
1302 counters->RxOkBrd = 0;
1303 counters->RxOkMul = 0;
1304 counters->TxAbt = 0;
1305 counters->TxUndrn = 0;
1306}
1307
c227f099 1308static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
6cadb320
FB		 1309{
1310 uint16_t val16;
1311 uint32_t val32;
1312 uint64_t val64;
1313
1314 val64 = cpu_to_le64(tally_counters->TxOk);
1315 cpu_physical_memory_write(tc_addr + 0, (uint8_t *)&val64, 8);
1316
1317 val64 = cpu_to_le64(tally_counters->RxOk);
1318 cpu_physical_memory_write(tc_addr + 8, (uint8_t *)&val64, 8);
1319
1320 val64 = cpu_to_le64(tally_counters->TxERR);
1321 cpu_physical_memory_write(tc_addr + 16, (uint8_t *)&val64, 8);
1322
1323 val32 = cpu_to_le32(tally_counters->RxERR);
1324 cpu_physical_memory_write(tc_addr + 24, (uint8_t *)&val32, 4);
1325
1326 val16 = cpu_to_le16(tally_counters->MissPkt);
1327 cpu_physical_memory_write(tc_addr + 28, (uint8_t *)&val16, 2);
1328
1329 val16 = cpu_to_le16(tally_counters->FAE);
1330 cpu_physical_memory_write(tc_addr + 30, (uint8_t *)&val16, 2);
1331
1332 val32 = cpu_to_le32(tally_counters->Tx1Col);
1333 cpu_physical_memory_write(tc_addr + 32, (uint8_t *)&val32, 4);
1334
1335 val32 = cpu_to_le32(tally_counters->TxMCol);
1336 cpu_physical_memory_write(tc_addr + 36, (uint8_t *)&val32, 4);
1337
1338 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1339 cpu_physical_memory_write(tc_addr + 40, (uint8_t *)&val64, 8);
1340
1341 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1342 cpu_physical_memory_write(tc_addr + 48, (uint8_t *)&val64, 8);
1343
1344 val32 = cpu_to_le32(tally_counters->RxOkMul);
1345 cpu_physical_memory_write(tc_addr + 56, (uint8_t *)&val32, 4);
1346
1347 val16 = cpu_to_le16(tally_counters->TxAbt);
1348 cpu_physical_memory_write(tc_addr + 60, (uint8_t *)&val16, 2);
1349
1350 val16 = cpu_to_le16(tally_counters->TxUndrn);
1351 cpu_physical_memory_write(tc_addr + 62, (uint8_t *)&val16, 2);
1352}
1353
1354/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1355
1356static const VMStateDescription vmstate_tally_counters = {
1357 .name = "tally_counters",
1358 .version_id = 1,
1359 .minimum_version_id = 1,
1360 .minimum_version_id_old = 1,
1361 .fields = (VMStateField []) {
1362 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1363 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1364 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1365 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1366 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1367 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1368 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1369 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1370 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1371 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1372 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1373 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1374 VMSTATE_END_OF_LIST()
1375 }
1376};
a41b2ff2
PB		 1377
1378static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1379{
1380 val &= 0xff;
1381
7cdeb319 1382 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1383
1384 if (val & CmdReset)
1385 {
7cdeb319 1386 DPRINTF("ChipCmd reset\n");
7f23f812 1387 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1388 }
1389 if (val & CmdRxEnb)
1390 {
7cdeb319 1391 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1392
1393 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1394 }
1395 if (val & CmdTxEnb)
1396 {
7cdeb319 1397 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1398
1399 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1400 }
1401
1402 /* mask unwriteable bits */
1403 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1404
1405 /* Deassert reset pin before next read */
1406 val &= ~CmdReset;
1407
1408 s->bChipCmdState = val;
1409}
1410
1411static int rtl8139_RxBufferEmpty(RTL8139State *s)
1412{
1413 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1414
1415 if (unread != 0)
1416 {
7cdeb319 1417 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1418 return 0;
1419 }
1420
7cdeb319 1421 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1422
1423 return 1;
1424}
1425
1426static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1427{
1428 uint32_t ret = s->bChipCmdState;
1429
1430 if (rtl8139_RxBufferEmpty(s))
1431 ret |= RxBufEmpty;
1432
7cdeb319 1433 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1434
1435 return ret;
1436}
1437
1438static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1439{
1440 val &= 0xffff;
1441
7cdeb319 1442 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1443
2c3891ab
AL		 1444 s->cplus_enabled = 1;
1445
a41b2ff2
PB		 1446 /* mask unwriteable bits */
1447 val = SET_MASKED(val, 0xff84, s->CpCmd);
1448
1449 s->CpCmd = val;
1450}
1451
1452static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1453{
1454 uint32_t ret = s->CpCmd;
1455
7cdeb319 1456 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1457
1458 return ret;
1459}
1460
1461static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1462{
7cdeb319 1463 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1464}
1465
1466static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1467{
1468 uint32_t ret = 0;
1469
7cdeb319 1470 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1471
1472 return ret;
1473}
1474
9596ebb7 1475static int rtl8139_config_writeable(RTL8139State *s)
a41b2ff2
PB		 1476{
1477 if (s->Cfg9346 & Cfg9346_Unlock)
1478 {
1479 return 1;
1480 }
1481
7cdeb319 1482 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1483
1484 return 0;
1485}
1486
1487static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1488{
1489 val &= 0xffff;
1490
7cdeb319 1491 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2
PB		 1492
1493 /* mask unwriteable bits */
e3d7e843 1494 uint32_t mask = 0x4cff;
a41b2ff2
PB		 1495
1496 if (1 || !rtl8139_config_writeable(s))
1497 {
1498 /* Speed setting and autonegotiation enable bits are read-only */
1499 mask |= 0x3000;
1500 /* Duplex mode setting is read-only */
1501 mask |= 0x0100;
1502 }
1503
1504 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1505
1506 s->BasicModeCtrl = val;
1507}
1508
1509static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1510{
1511 uint32_t ret = s->BasicModeCtrl;
1512
7cdeb319 1513 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1514
1515 return ret;
1516}
1517
1518static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1519{
1520 val &= 0xffff;
1521
7cdeb319 1522 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2
PB		 1523
1524 /* mask unwriteable bits */
1525 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1526
1527 s->BasicModeStatus = val;
1528}
1529
1530static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1531{
1532 uint32_t ret = s->BasicModeStatus;
1533
7cdeb319 1534 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1535
1536 return ret;
1537}
1538
1539static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1540{
1541 val &= 0xff;
1542
7cdeb319 1543 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2
PB		 1544
1545 /* mask unwriteable bits */
1546 val = SET_MASKED(val, 0x31, s->Cfg9346);
1547
1548 uint32_t opmode = val & 0xc0;
1549 uint32_t eeprom_val = val & 0xf;
1550
1551 if (opmode == 0x80) {
1552 /* eeprom access */
1553 int eecs = (eeprom_val & 0x08)?1:0;
1554 int eesk = (eeprom_val & 0x04)?1:0;
1555 int eedi = (eeprom_val & 0x02)?1:0;
1556 prom9346_set_wire(s, eecs, eesk, eedi);
1557 } else if (opmode == 0x40) {
1558 /* Reset. */
1559 val = 0;
7f23f812 1560 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1561 }
1562
1563 s->Cfg9346 = val;
1564}
1565
1566static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1567{
1568 uint32_t ret = s->Cfg9346;
1569
1570 uint32_t opmode = ret & 0xc0;
1571
1572 if (opmode == 0x80)
1573 {
1574 /* eeprom access */
1575 int eedo = prom9346_get_wire(s);
1576 if (eedo)
1577 {
1578 ret |= 0x01;
1579 }
1580 else
1581 {
1582 ret &= ~0x01;
1583 }
1584 }
1585
7cdeb319 1586 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1587
1588 return ret;
1589}
1590
1591static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1592{
1593 val &= 0xff;
1594
7cdeb319 1595 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2
PB		 1596
1597 if (!rtl8139_config_writeable(s))
1598 return;
1599
1600 /* mask unwriteable bits */
1601 val = SET_MASKED(val, 0xf8, s->Config0);
1602
1603 s->Config0 = val;
1604}
1605
1606static uint32_t rtl8139_Config0_read(RTL8139State *s)
1607{
1608 uint32_t ret = s->Config0;
1609
7cdeb319 1610 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1611
1612 return ret;
1613}
1614
1615static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1616{
1617 val &= 0xff;
1618
7cdeb319 1619 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2
PB		 1620
1621 if (!rtl8139_config_writeable(s))
1622 return;
1623
1624 /* mask unwriteable bits */
1625 val = SET_MASKED(val, 0xC, s->Config1);
1626
1627 s->Config1 = val;
1628}
1629
1630static uint32_t rtl8139_Config1_read(RTL8139State *s)
1631{
1632 uint32_t ret = s->Config1;
1633
7cdeb319 1634 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1635
1636 return ret;
1637}
1638
1639static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1640{
1641 val &= 0xff;
1642
7cdeb319 1643 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2
PB		 1644
1645 if (!rtl8139_config_writeable(s))
1646 return;
1647
1648 /* mask unwriteable bits */
1649 val = SET_MASKED(val, 0x8F, s->Config3);
1650
1651 s->Config3 = val;
1652}
1653
1654static uint32_t rtl8139_Config3_read(RTL8139State *s)
1655{
1656 uint32_t ret = s->Config3;
1657
7cdeb319 1658 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1659
1660 return ret;
1661}
1662
1663static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1664{
1665 val &= 0xff;
1666
7cdeb319 1667 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2
PB		 1668
1669 if (!rtl8139_config_writeable(s))
1670 return;
1671
1672 /* mask unwriteable bits */
1673 val = SET_MASKED(val, 0x0a, s->Config4);
1674
1675 s->Config4 = val;
1676}
1677
1678static uint32_t rtl8139_Config4_read(RTL8139State *s)
1679{
1680 uint32_t ret = s->Config4;
1681
7cdeb319 1682 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1683
1684 return ret;
1685}
1686
1687static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1688{
1689 val &= 0xff;
1690
7cdeb319 1691 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2
PB		 1692
1693 /* mask unwriteable bits */
1694 val = SET_MASKED(val, 0x80, s->Config5);
1695
1696 s->Config5 = val;
1697}
1698
1699static uint32_t rtl8139_Config5_read(RTL8139State *s)
1700{
1701 uint32_t ret = s->Config5;
1702
7cdeb319 1703 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1704
1705 return ret;
1706}
1707
1708static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1709{
1710 if (!rtl8139_transmitter_enabled(s))
1711 {
7cdeb319 1712 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1713 return;
1714 }
1715
7cdeb319 1716 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1717
1718 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1719
1720 s->TxConfig = val;
1721}
1722
1723static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1724{
7cdeb319 1725 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1726
1727 uint32_t tc = s->TxConfig;
1728 tc &= 0xFFFFFF00;
1729 tc |= (val & 0x000000FF);
1730 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1731}
1732
1733static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1734{
1735 uint32_t ret = s->TxConfig;
1736
7cdeb319 1737 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1738
1739 return ret;
1740}
1741
1742static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1743{
7cdeb319 1744 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1745
1746 /* mask unwriteable bits */
1747 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1748
1749 s->RxConfig = val;
1750
1751 /* reset buffer size and read/write pointers */
1752 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1753
7cdeb319 1754 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1755}
1756
1757static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1758{
1759 uint32_t ret = s->RxConfig;
1760
7cdeb319 1761 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1762
1763 return ret;
1764}
1765
bf6b87a8
BP		 1766static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1767 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1768{
bf6b87a8
BP		 1769 struct iovec *iov = NULL;
1770
718da2b9
FB		 1771 if (!size)
1772 {
7cdeb319 1773 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1774 return;
1775 }
1776
bf6b87a8
BP		 1777 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1778 iov = (struct iovec[3]) {
1779 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1780 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1781 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1782 .iov_len = size - ETHER_ADDR_LEN * 2 },
1783 };
1784 }
1785
718da2b9
FB		 1786 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1787 {
bf6b87a8
BP		 1788 size_t buf2_size;
1789 uint8_t *buf2;
1790
1791 if (iov) {
1792 buf2_size = iov_size(iov, 3);
1793 buf2 = qemu_malloc(buf2_size);
1794 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1795 buf = buf2;
1796 }
1797
7cdeb319 1798 DPRINTF("+++ transmit loopback mode\n");
1673ad51 1799 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
bf6b87a8
BP		 1800
1801 if (iov) {
1802 qemu_free(buf2);
1803 }
718da2b9
FB		 1804 }
1805 else
1806 {
bf6b87a8
BP		 1807 if (iov) {
1808 qemu_sendv_packet(&s->nic->nc, iov, 3);
1809 } else {
1810 qemu_send_packet(&s->nic->nc, buf, size);
1811 }
718da2b9
FB		 1812 }
1813}
1814
a41b2ff2
PB		 1815static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1816{
1817 if (!rtl8139_transmitter_enabled(s))
1818 {
7cdeb319
BP		 1819 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1820 "disabled\n", descriptor);
a41b2ff2
PB		 1821 return 0;
1822 }
1823
1824 if (s->TxStatus[descriptor] & TxHostOwns)
1825 {
7cdeb319
BP		 1826 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1827 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1828 return 0;
1829 }
1830
7cdeb319 1831 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2
PB		 1832
1833 int txsize = s->TxStatus[descriptor] & 0x1fff;
1834 uint8_t txbuffer[0x2000];
1835
7cdeb319
BP		 1836 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1837 txsize, s->TxAddr[descriptor]);
a41b2ff2 1838
6cadb320 1839 cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1840
1841 /* Mark descriptor as transferred */
1842 s->TxStatus[descriptor] |= TxHostOwns;
1843 s->TxStatus[descriptor] |= TxStatOK;
1844
bf6b87a8 1845 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1846
7cdeb319
BP		 1847 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1848 descriptor);
a41b2ff2
PB		 1849
1850 /* update interrupt */
1851 s->IntrStatus |= TxOK;
1852 rtl8139_update_irq(s);
1853
1854 return 1;
1855}
1856
718da2b9
FB		 1857/* structures and macros for task offloading */
1858typedef struct ip_header
1859{
1860 uint8_t ip_ver_len; /* version and header length */
1861 uint8_t ip_tos; /* type of service */
1862 uint16_t ip_len; /* total length */
1863 uint16_t ip_id; /* identification */
1864 uint16_t ip_off; /* fragment offset field */
1865 uint8_t ip_ttl; /* time to live */
1866 uint8_t ip_p; /* protocol */
1867 uint16_t ip_sum; /* checksum */
1868 uint32_t ip_src,ip_dst; /* source and dest address */
1869} ip_header;
1870
1871#define IP_HEADER_VERSION_4 4
1872#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1873#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1874
1875typedef struct tcp_header
1876{
1877 uint16_t th_sport; /* source port */
1878 uint16_t th_dport; /* destination port */
1879 uint32_t th_seq; /* sequence number */
1880 uint32_t th_ack; /* acknowledgement number */
1881 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1882 uint16_t th_win; /* window */
1883 uint16_t th_sum; /* checksum */
1884 uint16_t th_urp; /* urgent pointer */
1885} tcp_header;
1886
1887typedef struct udp_header
1888{
1889 uint16_t uh_sport; /* source port */
1890 uint16_t uh_dport; /* destination port */
1891 uint16_t uh_ulen; /* udp length */
1892 uint16_t uh_sum; /* udp checksum */
1893} udp_header;
1894
1895typedef struct ip_pseudo_header
1896{
1897 uint32_t ip_src;
1898 uint32_t ip_dst;
1899 uint8_t zeros;
1900 uint8_t ip_proto;
1901 uint16_t ip_payload;
1902} ip_pseudo_header;
1903
1904#define IP_PROTO_TCP 6
1905#define IP_PROTO_UDP 17
1906
1907#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1908#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1909#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1910
1911#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1912
1913#define TCP_FLAG_FIN 0x01
1914#define TCP_FLAG_PUSH 0x08
1915
1916/* produces ones' complement sum of data */
1917static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1918{
1919 uint32_t result = 0;
1920
1921 for (; len > 1; data+=2, len-=2)
1922 {
1923 result += *(uint16_t*)data;
1924 }
1925
1926 /* add the remainder byte */
1927 if (len)
1928 {
1929 uint8_t odd[2] = {*data, 0};
1930 result += *(uint16_t*)odd;
1931 }
1932
1933 while (result>>16)
1934 result = (result & 0xffff) + (result >> 16);
1935
1936 return result;
1937}
1938
1939static uint16_t ip_checksum(void *data, size_t len)
1940{
1941 return ~ones_complement_sum((uint8_t*)data, len);
1942}
1943
a41b2ff2
PB		 1944static int rtl8139_cplus_transmit_one(RTL8139State *s)
1945{
1946 if (!rtl8139_transmitter_enabled(s))
1947 {
7cdeb319 1948 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1949 return 0;
1950 }
1951
1952 if (!rtl8139_cp_transmitter_enabled(s))
1953 {
7cdeb319 1954 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1955 return 0 ;
1956 }
1957
1958 int descriptor = s->currCPlusTxDesc;
1959
c227f099 1960 target_phys_addr_t cplus_tx_ring_desc =
a41b2ff2
PB		 1961 rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1962
1963 /* Normal priority ring */
1964 cplus_tx_ring_desc += 16 * descriptor;
1965
7cdeb319
BP		 1966 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1967 "%08x0x%08x = 0x"TARGET_FMT_plx"\n", descriptor, s->TxAddr[1],
1968 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1969
1970 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1971
1972 cpu_physical_memory_read(cplus_tx_ring_desc, (uint8_t *)&val, 4);
1973 txdw0 = le32_to_cpu(val);
1974 cpu_physical_memory_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1975 txdw1 = le32_to_cpu(val);
1976 cpu_physical_memory_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1977 txbufLO = le32_to_cpu(val);
1978 cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1979 txbufHI = le32_to_cpu(val);
1980
7cdeb319
BP		 1981 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1982 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1983
1984/* w0 ownership flag */
1985#define CP_TX_OWN (1<<31)
1986/* w0 end of ring flag */
1987#define CP_TX_EOR (1<<30)
1988/* first segment of received packet flag */
1989#define CP_TX_FS (1<<29)
1990/* last segment of received packet flag */
1991#define CP_TX_LS (1<<28)
1992/* large send packet flag */
1993#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1994/* large send MSS mask, bits 16...25 */
1995#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1996
a41b2ff2
PB		 1997/* IP checksum offload flag */
1998#define CP_TX_IPCS (1<<18)
1999/* UDP checksum offload flag */
2000#define CP_TX_UDPCS (1<<17)
2001/* TCP checksum offload flag */
2002#define CP_TX_TCPCS (1<<16)
2003
2004/* w0 bits 0...15 : buffer size */
2005#define CP_TX_BUFFER_SIZE (1<<16)
2006#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 2007/* w1 add tag flag */
2008#define CP_TX_TAGC (1<<17)
2009/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 2010#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2011/* w2 low 32bit of Rx buffer ptr */
2012/* w3 high 32bit of Rx buffer ptr */
2013
2014/* set after transmission */
2015/* FIFO underrun flag */
2016#define CP_TX_STATUS_UNF (1<<25)
2017/* transmit error summary flag, valid if set any of three below */
2018#define CP_TX_STATUS_TES (1<<23)
2019/* out-of-window collision flag */
2020#define CP_TX_STATUS_OWC (1<<22)
2021/* link failure flag */
2022#define CP_TX_STATUS_LNKF (1<<21)
2023/* excessive collisions flag */
2024#define CP_TX_STATUS_EXC (1<<20)
2025
2026 if (!(txdw0 & CP_TX_OWN))
2027 {
7cdeb319 2028 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 2029 return 0 ;
2030 }
2031
7cdeb319 2032 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 2033
2034 if (txdw0 & CP_TX_FS)
2035 {
7cdeb319
BP		 2036 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2037 "descriptor\n", descriptor);
6cadb320
FB		 2038
2039 /* reset internal buffer offset */
2040 s->cplus_txbuffer_offset = 0;
2041 }
a41b2ff2
PB		 2042
2043 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
c227f099 2044 target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 2045
6cadb320
FB		 2046 /* make sure we have enough space to assemble the packet */
2047 if (!s->cplus_txbuffer)
2048 {
2049 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2bc6f59b 2050 s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
6cadb320 2051 s->cplus_txbuffer_offset = 0;
718da2b9 2052
7cdeb319
BP		 2053 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2054 s->cplus_txbuffer_len);
6cadb320
FB		 2055 }
2056
2057 while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2058 {
2059 s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2137b4cc 2060 s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
a41b2ff2 2061
7cdeb319
BP		 2062 DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
2063 s->cplus_txbuffer_len);
6cadb320
FB		 2064 }
2065
2066 if (!s->cplus_txbuffer)
2067 {
2068 /* out of memory */
a41b2ff2 2069
7cdeb319
BP		 2070 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2071 s->cplus_txbuffer_len);
6cadb320
FB		 2072
2073 /* update tally counter */
2074 ++s->tally_counters.TxERR;
2075 ++s->tally_counters.TxAbt;
2076
2077 return 0;
2078 }
2079
2080 /* append more data to the packet */
2081
7cdeb319
BP		 2082 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2083 TARGET_FMT_plx" to offset %d\n", txsize, tx_addr,
2084 s->cplus_txbuffer_offset);
6cadb320
FB		 2085
2086 cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2087 s->cplus_txbuffer_offset += txsize;
2088
2089 /* seek to next Rx descriptor */
2090 if (txdw0 & CP_TX_EOR)
2091 {
2092 s->currCPlusTxDesc = 0;
2093 }
2094 else
2095 {
2096 ++s->currCPlusTxDesc;
2097 if (s->currCPlusTxDesc >= 64)
2098 s->currCPlusTxDesc = 0;
2099 }
a41b2ff2
PB		 2100
2101 /* transfer ownership to target */
2102 txdw0 &= ~CP_RX_OWN;
2103
2104 /* reset error indicator bits */
2105 txdw0 &= ~CP_TX_STATUS_UNF;
2106 txdw0 &= ~CP_TX_STATUS_TES;
2107 txdw0 &= ~CP_TX_STATUS_OWC;
2108 txdw0 &= ~CP_TX_STATUS_LNKF;
2109 txdw0 &= ~CP_TX_STATUS_EXC;
2110
2111 /* update ring data */
2112 val = cpu_to_le32(txdw0);
2113 cpu_physical_memory_write(cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2114
6cadb320
FB		 2115 /* Now decide if descriptor being processed is holding the last segment of packet */
2116 if (txdw0 & CP_TX_LS)
a41b2ff2 2117 {
bf6b87a8
BP		 2118 uint8_t dot1q_buffer_space[VLAN_HLEN];
2119 uint16_t *dot1q_buffer;
2120
7cdeb319
BP		 2121 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2122 descriptor);
6cadb320
FB		 2123
2124 /* can transfer fully assembled packet */
2125
2126 uint8_t *saved_buffer = s->cplus_txbuffer;
2127 int saved_size = s->cplus_txbuffer_offset;
2128 int saved_buffer_len = s->cplus_txbuffer_len;
2129
bf6b87a8
BP		 2130 /* create vlan tag */
2131 if (txdw1 & CP_TX_TAGC) {
2132 /* the vlan tag is in BE byte order in the descriptor
2133 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2134 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2135 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2136
2137 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2138 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2139 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2140 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2141 } else {
2142 dot1q_buffer = NULL;
2143 }
2144
6cadb320
FB		 2145 /* reset the card space to protect from recursive call */
2146 s->cplus_txbuffer = NULL;
2147 s->cplus_txbuffer_offset = 0;
2148 s->cplus_txbuffer_len = 0;
2149
718da2b9 2150 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2151 {
7cdeb319 2152 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2153
6cadb320 2154 /* ip packet header */
660f11be 2155 ip_header *ip = NULL;
6cadb320 2156 int hlen = 0;
718da2b9
FB		 2157 uint8_t ip_protocol = 0;
2158 uint16_t ip_data_len = 0;
6cadb320 2159
660f11be 2160 uint8_t *eth_payload_data = NULL;
718da2b9 2161 size_t eth_payload_len = 0;
6cadb320 2162
718da2b9 2163 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2164 if (proto == ETH_P_IP)
2165 {
7cdeb319 2166 DPRINTF("+++ C+ mode has IP packet\n");
6cadb320
FB		 2167
2168 /* not aligned */
718da2b9
FB		 2169 eth_payload_data = saved_buffer + ETH_HLEN;
2170 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2171
718da2b9 2172 ip = (ip_header*)eth_payload_data;
6cadb320 2173
718da2b9 2174 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
7cdeb319
BP		 2175 DPRINTF("+++ C+ mode packet has bad IP version %d "
2176 "expected %d\n", IP_HEADER_VERSION(ip),
2177 IP_HEADER_VERSION_4);
6cadb320
FB		 2178 ip = NULL;
2179 } else {
718da2b9
FB		 2180 hlen = IP_HEADER_LENGTH(ip);
2181 ip_protocol = ip->ip_p;
2182 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2183 }
2184 }
2185
2186 if (ip)
2187 {
2188 if (txdw0 & CP_TX_IPCS)
2189 {
7cdeb319 2190 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2191
718da2b9 2192 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2193 /* bad packet header len */
2194 /* or packet too short */
2195 }
2196 else
2197 {
2198 ip->ip_sum = 0;
718da2b9 2199 ip->ip_sum = ip_checksum(ip, hlen);
7cdeb319
BP		 2200 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2201 hlen, ip->ip_sum);
6cadb320
FB		 2202 }
2203 }
2204
718da2b9 2205 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2206 {
718da2b9 2207 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
ec48c774 2208
7cdeb319
BP		 2209 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2210 "frame data %d specified MSS=%d\n", ETH_MTU,
2211 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2212
718da2b9
FB		 2213 int tcp_send_offset = 0;
2214 int send_count = 0;
6cadb320
FB		 2215
2216 /* maximum IP header length is 60 bytes */
2217 uint8_t saved_ip_header[60];
6cadb320 2218
718da2b9
FB		 2219 /* save IP header template; data area is used in tcp checksum calculation */
2220 memcpy(saved_ip_header, eth_payload_data, hlen);
2221
2222 /* a placeholder for checksum calculation routine in tcp case */
2223 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2224 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2225
2226 /* pointer to TCP header */
2227 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2228
2229 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2230
2231 /* ETH_MTU = ip header len + tcp header len + payload */
2232 int tcp_data_len = ip_data_len - tcp_hlen;
2233 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2234
7cdeb319
BP		 2235 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2236 "data len %d TCP chunk size %d\n", ip_data_len,
2237 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9
FB		 2238
2239 /* note the cycle below overwrites IP header data,
2240 but restores it from saved_ip_header before sending packet */
2241
2242 int is_last_frame = 0;
2243
2244 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2245 {
2246 uint16_t chunk_size = tcp_chunk_size;
2247
2248 /* check if this is the last frame */
2249 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2250 {
2251 is_last_frame = 1;
2252 chunk_size = tcp_data_len - tcp_send_offset;
2253 }
2254
7cdeb319
BP		 2255 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2256 be32_to_cpu(p_tcp_hdr->th_seq));
718da2b9
FB		 2257
2258 /* add 4 TCP pseudoheader fields */
2259 /* copy IP source and destination fields */
2260 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2261
7cdeb319
BP		 2262 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2263 "packet with %d bytes data\n", tcp_hlen +
2264 chunk_size);
718da2b9
FB		 2265
2266 if (tcp_send_offset)
2267 {
2268 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2269 }
2270
2271 /* keep PUSH and FIN flags only for the last frame */
2272 if (!is_last_frame)
2273 {
2274 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2275 }
6cadb320 2276
718da2b9
FB		 2277 /* recalculate TCP checksum */
2278 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2279 p_tcpip_hdr->zeros = 0;
2280 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2281 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2282
2283 p_tcp_hdr->th_sum = 0;
2284
2285 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
7cdeb319
BP		 2286 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2287 tcp_checksum);
718da2b9
FB		 2288
2289 p_tcp_hdr->th_sum = tcp_checksum;
2290
2291 /* restore IP header */
2292 memcpy(eth_payload_data, saved_ip_header, hlen);
2293
2294 /* set IP data length and recalculate IP checksum */
2295 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2296
2297 /* increment IP id for subsequent frames */
2298 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2299
2300 ip->ip_sum = 0;
2301 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
7cdeb319
BP		 2302 DPRINTF("+++ C+ mode TSO IP header len=%d "
2303 "checksum=%04x\n", hlen, ip->ip_sum);
718da2b9
FB		 2304
2305 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
7cdeb319
BP		 2306 DPRINTF("+++ C+ mode TSO transferring packet size "
2307 "%d\n", tso_send_size);
bf6b87a8
BP		 2308 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2309 0, (uint8_t *) dot1q_buffer);
718da2b9
FB		 2310
2311 /* add transferred count to TCP sequence number */
2312 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2313 ++send_count;
2314 }
2315
2316 /* Stop sending this frame */
2317 saved_size = 0;
2318 }
2319 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2320 {
7cdeb319 2321 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
718da2b9
FB		 2322
2323 /* maximum IP header length is 60 bytes */
2324 uint8_t saved_ip_header[60];
2325 memcpy(saved_ip_header, eth_payload_data, hlen);
2326
2327 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2328 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2329
2330 /* add 4 TCP pseudoheader fields */
2331 /* copy IP source and destination fields */
718da2b9 2332 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2333
718da2b9 2334 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320 2335 {
7cdeb319
BP		 2336 DPRINTF("+++ C+ mode calculating TCP checksum for "
2337 "packet with %d bytes data\n", ip_data_len);
6cadb320 2338
718da2b9
FB		 2339 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2340 p_tcpip_hdr->zeros = 0;
2341 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2342 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2343
718da2b9 2344 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2345
2346 p_tcp_hdr->th_sum = 0;
2347
718da2b9 2348 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2349 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2350 tcp_checksum);
6cadb320
FB		 2351
2352 p_tcp_hdr->th_sum = tcp_checksum;
2353 }
718da2b9 2354 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320 2355 {
7cdeb319
BP		 2356 DPRINTF("+++ C+ mode calculating UDP checksum for "
2357 "packet with %d bytes data\n", ip_data_len);
6cadb320 2358
718da2b9
FB		 2359 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2360 p_udpip_hdr->zeros = 0;
2361 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2362 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2363
718da2b9 2364 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2365
6cadb320
FB		 2366 p_udp_hdr->uh_sum = 0;
2367
718da2b9 2368 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2369 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2370 udp_checksum);
6cadb320 2371
6cadb320
FB		 2372 p_udp_hdr->uh_sum = udp_checksum;
2373 }
2374
2375 /* restore IP header */
718da2b9 2376 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2377 }
2378 }
2379 }
2380
2381 /* update tally counter */
2382 ++s->tally_counters.TxOk;
2383
7cdeb319 2384 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2385
bf6b87a8
BP		 2386 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2387 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2388
2389 /* restore card space if there was no recursion and reset offset */
2390 if (!s->cplus_txbuffer)
2391 {
2392 s->cplus_txbuffer = saved_buffer;
2393 s->cplus_txbuffer_len = saved_buffer_len;
2394 s->cplus_txbuffer_offset = 0;
2395 }
2396 else
2397 {
2bc6f59b 2398 qemu_free(saved_buffer);
6cadb320 2399 }
a41b2ff2
PB		 2400 }
2401 else
2402 {
7cdeb319 2403 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2404 }
2405
a41b2ff2
PB		 2406 return 1;
2407}
2408
2409static void rtl8139_cplus_transmit(RTL8139State *s)
2410{
2411 int txcount = 0;
2412
2413 while (rtl8139_cplus_transmit_one(s))
2414 {
2415 ++txcount;
2416 }
2417
2418 /* Mark transfer completed */
2419 if (!txcount)
2420 {
7cdeb319
BP		 2421 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2422 s->currCPlusTxDesc);
a41b2ff2
PB		 2423 }
2424 else
2425 {
2426 /* update interrupt status */
2427 s->IntrStatus |= TxOK;
2428 rtl8139_update_irq(s);
2429 }
2430}
2431
2432static void rtl8139_transmit(RTL8139State *s)
2433{
2434 int descriptor = s->currTxDesc, txcount = 0;
2435
2436 /*while*/
2437 if (rtl8139_transmit_one(s, descriptor))
2438 {
2439 ++s->currTxDesc;
2440 s->currTxDesc %= 4;
2441 ++txcount;
2442 }
2443
2444 /* Mark transfer completed */
2445 if (!txcount)
2446 {
7cdeb319
BP		 2447 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2448 s->currTxDesc);
a41b2ff2
PB		 2449 }
2450}
2451
2452static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2453{
2454
2455 int descriptor = txRegOffset/4;
6cadb320
FB		 2456
2457 /* handle C+ transmit mode register configuration */
2458
2c3891ab 2459 if (s->cplus_enabled)
6cadb320 2460 {
7cdeb319
BP		 2461 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2462 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2463
2464 /* handle Dump Tally Counters command */
2465 s->TxStatus[descriptor] = val;
2466
2467 if (descriptor == 0 && (val & 0x8))
2468 {
c227f099 2469 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2470
2471 /* dump tally counters to specified memory location */
2472 RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2473
2474 /* mark dump completed */
2475 s->TxStatus[0] &= ~0x8;
2476 }
2477
2478 return;
2479 }
2480
7cdeb319
BP		 2481 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2482 txRegOffset, val, descriptor);
a41b2ff2
PB		 2483
2484 /* mask only reserved bits */
2485 val &= ~0xff00c000; /* these bits are reset on write */
2486 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2487
2488 s->TxStatus[descriptor] = val;
2489
2490 /* attempt to start transmission */
2491 rtl8139_transmit(s);
2492}
2493
2494static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2495{
2496 uint32_t ret = s->TxStatus[txRegOffset/4];
2497
7cdeb319 2498 DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
a41b2ff2
PB		 2499
2500 return ret;
2501}
2502
2503static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2504{
2505 uint16_t ret = 0;
2506
2507 /* Simulate TSAD, it is read only anyway */
2508
2509 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2510 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2511 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2512 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2513
2514 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2515 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2516 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2517 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2518
a41b2ff2
PB		 2519 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2520 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2521 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2522 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2523
a41b2ff2
PB		 2524 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2525 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2526 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2527 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2528
a41b2ff2 2529
7cdeb319 2530 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2531
2532 return ret;
2533}
2534
2535static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2536{
2537 uint16_t ret = s->CSCR;
2538
7cdeb319 2539 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2540
2541 return ret;
2542}
2543
2544static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2545{
7cdeb319 2546 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2547
290a0933 2548 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2549}
2550
2551static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2552{
290a0933 2553 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2554
7cdeb319 2555 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2556
2557 return ret;
2558}
2559
2560static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2561{
7cdeb319 2562 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2563
2564 /* this value is off by 16 */
2565 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2566
7cdeb319
BP		 2567 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2568 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2569}
2570
2571static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2572{
2573 /* this value is off by 16 */
2574 uint32_t ret = s->RxBufPtr - 0x10;
2575
7cdeb319 2576 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2577
2578 return ret;
2579}
2580
2581static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2582{
2583 /* this value is NOT off by 16 */
2584 uint32_t ret = s->RxBufAddr;
2585
7cdeb319 2586 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2587
2588 return ret;
2589}
2590
2591static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2592{
7cdeb319 2593 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2594
2595 s->RxBuf = val;
2596
2597 /* may need to reset rxring here */
2598}
2599
2600static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2601{
2602 uint32_t ret = s->RxBuf;
2603
7cdeb319 2604 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2605
2606 return ret;
2607}
2608
2609static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2610{
7cdeb319 2611 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2612
2613 /* mask unwriteable bits */
2614 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2615
2616 s->IntrMask = val;
2617
74475455 2618 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2619 rtl8139_update_irq(s);
05447803 2620
a41b2ff2
PB		 2621}
2622
2623static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2624{
2625 uint32_t ret = s->IntrMask;
2626
7cdeb319 2627 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2628
2629 return ret;
2630}
2631
2632static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2633{
7cdeb319 2634 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2635
2636#if 0
2637
2638 /* writing to ISR has no effect */
2639
2640 return;
2641
2642#else
2643 uint16_t newStatus = s->IntrStatus & ~val;
2644
2645 /* mask unwriteable bits */
2646 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2647
2648 /* writing 1 to interrupt status register bit clears it */
2649 s->IntrStatus = 0;
2650 rtl8139_update_irq(s);
2651
2652 s->IntrStatus = newStatus;
05447803
FZ		 2653 /*
2654 * Computing if we miss an interrupt here is not that correct but
2655 * considered that we should have had already an interrupt
2656 * and probably emulated is slower is better to assume this resetting was
2657 * done before testing on previous rtl8139_update_irq lead to IRQ loosing
2658 */
74475455 2659 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2660 rtl8139_update_irq(s);
05447803 2661
a41b2ff2
PB		 2662#endif
2663}
2664
2665static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2666{
74475455 2667 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2668
a41b2ff2
PB		 2669 uint32_t ret = s->IntrStatus;
2670
7cdeb319 2671 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2672
2673#if 0
2674
2675 /* reading ISR clears all interrupts */
2676 s->IntrStatus = 0;
2677
2678 rtl8139_update_irq(s);
2679
2680#endif
2681
2682 return ret;
2683}
2684
2685static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2686{
7cdeb319 2687 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2688
2689 /* mask unwriteable bits */
2690 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2691
2692 s->MultiIntr = val;
2693}
2694
2695static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2696{
2697 uint32_t ret = s->MultiIntr;
2698
7cdeb319 2699 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2700
2701 return ret;
2702}
2703
2704static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2705{
2706 RTL8139State *s = opaque;
2707
2708 addr &= 0xff;
2709
2710 switch (addr)
2711 {
2712 case MAC0 ... MAC0+5:
2713 s->phys[addr - MAC0] = val;
2714 break;
2715 case MAC0+6 ... MAC0+7:
2716 /* reserved */
2717 break;
2718 case MAR0 ... MAR0+7:
2719 s->mult[addr - MAR0] = val;
2720 break;
2721 case ChipCmd:
2722 rtl8139_ChipCmd_write(s, val);
2723 break;
2724 case Cfg9346:
2725 rtl8139_Cfg9346_write(s, val);
2726 break;
2727 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2728 rtl8139_TxConfig_writeb(s, val);
2729 break;
2730 case Config0:
2731 rtl8139_Config0_write(s, val);
2732 break;
2733 case Config1:
2734 rtl8139_Config1_write(s, val);
2735 break;
2736 case Config3:
2737 rtl8139_Config3_write(s, val);
2738 break;
2739 case Config4:
2740 rtl8139_Config4_write(s, val);
2741 break;
2742 case Config5:
2743 rtl8139_Config5_write(s, val);
2744 break;
2745 case MediaStatus:
2746 /* ignore */
7cdeb319
BP		 2747 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2748 val);
a41b2ff2
PB		 2749 break;
2750
2751 case HltClk:
7cdeb319 2752 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2753 if (val == 'R')
2754 {
2755 s->clock_enabled = 1;
2756 }
2757 else if (val == 'H')
2758 {
2759 s->clock_enabled = 0;
2760 }
2761 break;
2762
2763 case TxThresh:
7cdeb319 2764 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2765 s->TxThresh = val;
2766 break;
2767
2768 case TxPoll:
7cdeb319 2769 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2770 if (val & (1 << 7))
2771 {
7cdeb319
BP		 2772 DPRINTF("C+ TxPoll high priority transmission (not "
2773 "implemented)\n");
a41b2ff2
PB		 2774 //rtl8139_cplus_transmit(s);
2775 }
2776 if (val & (1 << 6))
2777 {
7cdeb319 2778 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2779 rtl8139_cplus_transmit(s);
2780 }
2781
2782 break;
2783
2784 default:
7cdeb319
BP		 2785 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2786 val);
a41b2ff2
PB		 2787 break;
2788 }
2789}
2790
2791static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2792{
2793 RTL8139State *s = opaque;
2794
2795 addr &= 0xfe;
2796
2797 switch (addr)
2798 {
2799 case IntrMask:
2800 rtl8139_IntrMask_write(s, val);
2801 break;
2802
2803 case IntrStatus:
2804 rtl8139_IntrStatus_write(s, val);
2805 break;
2806
2807 case MultiIntr:
2808 rtl8139_MultiIntr_write(s, val);
2809 break;
2810
2811 case RxBufPtr:
2812 rtl8139_RxBufPtr_write(s, val);
2813 break;
2814
2815 case BasicModeCtrl:
2816 rtl8139_BasicModeCtrl_write(s, val);
2817 break;
2818 case BasicModeStatus:
2819 rtl8139_BasicModeStatus_write(s, val);
2820 break;
2821 case NWayAdvert:
7cdeb319 2822 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2823 s->NWayAdvert = val;
2824 break;
2825 case NWayLPAR:
7cdeb319 2826 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2827 break;
2828 case NWayExpansion:
7cdeb319 2829 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2830 s->NWayExpansion = val;
2831 break;
2832
2833 case CpCmd:
2834 rtl8139_CpCmd_write(s, val);
2835 break;
2836
6cadb320
FB		 2837 case IntrMitigate:
2838 rtl8139_IntrMitigate_write(s, val);
2839 break;
2840
a41b2ff2 2841 default:
7cdeb319
BP		 2842 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2843 addr, val);
a41b2ff2 2844
a41b2ff2
PB		 2845 rtl8139_io_writeb(opaque, addr, val & 0xff);
2846 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2847 break;
2848 }
2849}
2850
05447803
FZ		 2851static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2852{
2853 int64_t pci_time, next_time;
2854 uint32_t low_pci;
2855
7cdeb319 2856 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803
FZ		 2857
2858 if (s->TimerExpire && current_time >= s->TimerExpire) {
2859 s->IntrStatus |= PCSTimeout;
2860 rtl8139_update_irq(s);
2861 }
2862
2863 /* Set QEMU timer only if needed that is
2864 * - TimerInt <> 0 (we have a timer)
2865 * - mask = 1 (we want an interrupt timer)
2866 * - irq = 0 (irq is not already active)
2867 * If any of above change we need to compute timer again
2868 * Also we must check if timer is passed without QEMU timer
2869 */
2870 s->TimerExpire = 0;
2871 if (!s->TimerInt) {
2872 return;
2873 }
2874
2875 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2876 get_ticks_per_sec());
2877 low_pci = pci_time & 0xffffffff;
2878 pci_time = pci_time - low_pci + s->TimerInt;
2879 if (low_pci >= s->TimerInt) {
2880 pci_time += 0x100000000LL;
2881 }
2882 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2883 PCI_FREQUENCY);
2884 s->TimerExpire = next_time;
2885
2886 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2887 qemu_mod_timer(s->timer, next_time);
2888 }
2889}
2890
a41b2ff2
PB		 2891static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2892{
2893 RTL8139State *s = opaque;
2894
2895 addr &= 0xfc;
2896
2897 switch (addr)
2898 {
2899 case RxMissed:
7cdeb319 2900 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2901 s->RxMissed = 0;
2902 break;
2903
2904 case TxConfig:
2905 rtl8139_TxConfig_write(s, val);
2906 break;
2907
2908 case RxConfig:
2909 rtl8139_RxConfig_write(s, val);
2910 break;
2911
2912 case TxStatus0 ... TxStatus0+4*4-1:
2913 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2914 break;
2915
2916 case TxAddr0 ... TxAddr0+4*4-1:
2917 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2918 break;
2919
2920 case RxBuf:
2921 rtl8139_RxBuf_write(s, val);
2922 break;
2923
2924 case RxRingAddrLO:
7cdeb319 2925 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2926 s->RxRingAddrLO = val;
2927 break;
2928
2929 case RxRingAddrHI:
7cdeb319 2930 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2931 s->RxRingAddrHI = val;
2932 break;
2933
6cadb320 2934 case Timer:
7cdeb319 2935 DPRINTF("TCTR Timer reset on write\n");
74475455 2936 s->TCTR_base = qemu_get_clock_ns(vm_clock);
05447803 2937 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2938 break;
2939
2940 case FlashReg:
7cdeb319 2941 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2942 if (s->TimerInt != val) {
2943 s->TimerInt = val;
74475455 2944 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2945 }
6cadb320
FB		 2946 break;
2947
a41b2ff2 2948 default:
7cdeb319
BP		 2949 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2950 addr, val);
a41b2ff2
PB		 2951 rtl8139_io_writeb(opaque, addr, val & 0xff);
2952 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2953 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2954 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2955 break;
2956 }
2957}
2958
2959static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2960{
2961 RTL8139State *s = opaque;
2962 int ret;
2963
2964 addr &= 0xff;
2965
2966 switch (addr)
2967 {
2968 case MAC0 ... MAC0+5:
2969 ret = s->phys[addr - MAC0];
2970 break;
2971 case MAC0+6 ... MAC0+7:
2972 ret = 0;
2973 break;
2974 case MAR0 ... MAR0+7:
2975 ret = s->mult[addr - MAR0];
2976 break;
2977 case ChipCmd:
2978 ret = rtl8139_ChipCmd_read(s);
2979 break;
2980 case Cfg9346:
2981 ret = rtl8139_Cfg9346_read(s);
2982 break;
2983 case Config0:
2984 ret = rtl8139_Config0_read(s);
2985 break;
2986 case Config1:
2987 ret = rtl8139_Config1_read(s);
2988 break;
2989 case Config3:
2990 ret = rtl8139_Config3_read(s);
2991 break;
2992 case Config4:
2993 ret = rtl8139_Config4_read(s);
2994 break;
2995 case Config5:
2996 ret = rtl8139_Config5_read(s);
2997 break;
2998
2999 case MediaStatus:
3000 ret = 0xd0;
7cdeb319 3001 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 3002 break;
3003
3004 case HltClk:
3005 ret = s->clock_enabled;
7cdeb319 3006 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 3007 break;
3008
3009 case PCIRevisionID:
6cadb320 3010 ret = RTL8139_PCI_REVID;
7cdeb319 3011 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 3012 break;
3013
3014 case TxThresh:
3015 ret = s->TxThresh;
7cdeb319 3016 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3017 break;
3018
3019 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3020 ret = s->TxConfig >> 24;
7cdeb319 3021 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3022 break;
3023
3024 default:
7cdeb319 3025 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 3026 ret = 0;
3027 break;
3028 }
3029
3030 return ret;
3031}
3032
3033static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3034{
3035 RTL8139State *s = opaque;
3036 uint32_t ret;
3037
3038 addr &= 0xfe; /* mask lower bit */
3039
3040 switch (addr)
3041 {
3042 case IntrMask:
3043 ret = rtl8139_IntrMask_read(s);
3044 break;
3045
3046 case IntrStatus:
3047 ret = rtl8139_IntrStatus_read(s);
3048 break;
3049
3050 case MultiIntr:
3051 ret = rtl8139_MultiIntr_read(s);
3052 break;
3053
3054 case RxBufPtr:
3055 ret = rtl8139_RxBufPtr_read(s);
3056 break;
3057
6cadb320
FB		 3058 case RxBufAddr:
3059 ret = rtl8139_RxBufAddr_read(s);
3060 break;
3061
a41b2ff2
PB		 3062 case BasicModeCtrl:
3063 ret = rtl8139_BasicModeCtrl_read(s);
3064 break;
3065 case BasicModeStatus:
3066 ret = rtl8139_BasicModeStatus_read(s);
3067 break;
3068 case NWayAdvert:
3069 ret = s->NWayAdvert;
7cdeb319 3070 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3071 break;
3072 case NWayLPAR:
3073 ret = s->NWayLPAR;
7cdeb319 3074 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3075 break;
3076 case NWayExpansion:
3077 ret = s->NWayExpansion;
7cdeb319 3078 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3079 break;
3080
3081 case CpCmd:
3082 ret = rtl8139_CpCmd_read(s);
3083 break;
3084
6cadb320
FB		 3085 case IntrMitigate:
3086 ret = rtl8139_IntrMitigate_read(s);
3087 break;
3088
a41b2ff2
PB		 3089 case TxSummary:
3090 ret = rtl8139_TSAD_read(s);
3091 break;
3092
3093 case CSCR:
3094 ret = rtl8139_CSCR_read(s);
3095 break;
3096
3097 default:
7cdeb319 3098 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3099
a41b2ff2
PB		 3100 ret = rtl8139_io_readb(opaque, addr);
3101 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3102
7cdeb319 3103 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3104 break;
3105 }
3106
3107 return ret;
3108}
3109
3110static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3111{
3112 RTL8139State *s = opaque;
3113 uint32_t ret;
3114
3115 addr &= 0xfc; /* also mask low 2 bits */
3116
3117 switch (addr)
3118 {
3119 case RxMissed:
3120 ret = s->RxMissed;
3121
7cdeb319 3122 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3123 break;
3124
3125 case TxConfig:
3126 ret = rtl8139_TxConfig_read(s);
3127 break;
3128
3129 case RxConfig:
3130 ret = rtl8139_RxConfig_read(s);
3131 break;
3132
3133 case TxStatus0 ... TxStatus0+4*4-1:
3134 ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
3135 break;
3136
3137 case TxAddr0 ... TxAddr0+4*4-1:
3138 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3139 break;
3140
3141 case RxBuf:
3142 ret = rtl8139_RxBuf_read(s);
3143 break;
3144
3145 case RxRingAddrLO:
3146 ret = s->RxRingAddrLO;
7cdeb319 3147 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3148 break;
3149
3150 case RxRingAddrHI:
3151 ret = s->RxRingAddrHI;
7cdeb319 3152 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3153 break;
3154
3155 case Timer:
74475455 3156 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
05447803 3157 PCI_FREQUENCY, get_ticks_per_sec());
7cdeb319 3158 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3159 break;
3160
3161 case FlashReg:
3162 ret = s->TimerInt;
7cdeb319 3163 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3164 break;
3165
3166 default:
7cdeb319 3167 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3168
a41b2ff2
PB		 3169 ret = rtl8139_io_readb(opaque, addr);
3170 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3171 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3172 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3173
7cdeb319 3174 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3175 break;
3176 }
3177
3178 return ret;
3179}
3180
3181/* */
3182
3183static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3184{
3185 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3186}
3187
3188static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3189{
3190 rtl8139_io_writew(opaque, addr & 0xFF, val);
3191}
3192
3193static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3194{
3195 rtl8139_io_writel(opaque, addr & 0xFF, val);
3196}
3197
3198static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3199{
3200 return rtl8139_io_readb(opaque, addr & 0xFF);
3201}
3202
3203static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3204{
3205 return rtl8139_io_readw(opaque, addr & 0xFF);
3206}
3207
3208static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3209{
3210 return rtl8139_io_readl(opaque, addr & 0xFF);
3211}
3212
3213/* */
3214
c227f099 3215static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3216{
3217 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3218}
3219
c227f099 3220static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3221{
3222 rtl8139_io_writew(opaque, addr & 0xFF, val);
3223}
3224
c227f099 3225static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
a41b2ff2
PB		 3226{
3227 rtl8139_io_writel(opaque, addr & 0xFF, val);
3228}
3229
c227f099 3230static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
a41b2ff2
PB		 3231{
3232 return rtl8139_io_readb(opaque, addr & 0xFF);
3233}
3234
c227f099 3235static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
a41b2ff2 3236{
5fedc612 3237 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3238 return val;
a41b2ff2
PB		 3239}
3240
c227f099 3241static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
a41b2ff2 3242{
5fedc612 3243 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3244 return val;
a41b2ff2
PB		 3245}
3246
060110c3 3247static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3248{
6597ebbb 3249 RTL8139State* s = opaque;
74475455 3250 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
060110c3 3251 if (version_id < 4) {
2c3891ab
AL		 3252 s->cplus_enabled = s->CpCmd != 0;
3253 }
3254
a41b2ff2
PB		 3255 return 0;
3256}
3257
c574ba5a
AW		 3258static bool rtl8139_hotplug_ready_needed(void *opaque)
3259{
3260 return qdev_machine_modified();
3261}
3262
3263static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3264 .name = "rtl8139/hotplug_ready",
3265 .version_id = 1,
3266 .minimum_version_id = 1,
3267 .minimum_version_id_old = 1,
3268 .fields = (VMStateField []) {
3269 VMSTATE_END_OF_LIST()
3270 }
3271};
3272
05447803
FZ		 3273static void rtl8139_pre_save(void *opaque)
3274{
3275 RTL8139State* s = opaque;
74475455 3276 int64_t current_time = qemu_get_clock_ns(vm_clock);
05447803
FZ		 3277
3278 /* set IntrStatus correctly */
3279 rtl8139_set_next_tctr_time(s, current_time);
3280 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3281 get_ticks_per_sec());
c574ba5a 3282 s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr;
05447803
FZ		 3283}
3284
060110c3
JQ		 3285static const VMStateDescription vmstate_rtl8139 = {
3286 .name = "rtl8139",
3287 .version_id = 4,
3288 .minimum_version_id = 3,
3289 .minimum_version_id_old = 3,
3290 .post_load = rtl8139_post_load,
05447803 3291 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3292 .fields = (VMStateField []) {
3293 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3294 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3295 VMSTATE_BUFFER(mult, RTL8139State),
3296 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3297 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3298
3299 VMSTATE_UINT32(RxBuf, RTL8139State),
3300 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3301 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3302 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3303
3304 VMSTATE_UINT16(IntrStatus, RTL8139State),
3305 VMSTATE_UINT16(IntrMask, RTL8139State),
3306
3307 VMSTATE_UINT32(TxConfig, RTL8139State),
3308 VMSTATE_UINT32(RxConfig, RTL8139State),
3309 VMSTATE_UINT32(RxMissed, RTL8139State),
3310 VMSTATE_UINT16(CSCR, RTL8139State),
3311
3312 VMSTATE_UINT8(Cfg9346, RTL8139State),
3313 VMSTATE_UINT8(Config0, RTL8139State),
3314 VMSTATE_UINT8(Config1, RTL8139State),
3315 VMSTATE_UINT8(Config3, RTL8139State),
3316 VMSTATE_UINT8(Config4, RTL8139State),
3317 VMSTATE_UINT8(Config5, RTL8139State),
3318
3319 VMSTATE_UINT8(clock_enabled, RTL8139State),
3320 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3321
3322 VMSTATE_UINT16(MultiIntr, RTL8139State),
3323
3324 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3325 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3326 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3327 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3328 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3329
3330 VMSTATE_UINT16(CpCmd, RTL8139State),
3331 VMSTATE_UINT8(TxThresh, RTL8139State),
3332
3333 VMSTATE_UNUSED(4),
3334 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3335 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3336
3337 VMSTATE_UINT32(currTxDesc, RTL8139State),
3338 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3339 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3340 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3341 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3342
3343 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3344 VMSTATE_INT32(eeprom.mode, RTL8139State),
3345 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3346 VMSTATE_UINT8(eeprom.address, RTL8139State),
3347 VMSTATE_UINT16(eeprom.input, RTL8139State),
3348 VMSTATE_UINT16(eeprom.output, RTL8139State),
3349
3350 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3351 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3352 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3353 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3354
3355 VMSTATE_UINT32(TCTR, RTL8139State),
3356 VMSTATE_UINT32(TimerInt, RTL8139State),
3357 VMSTATE_INT64(TCTR_base, RTL8139State),
3358
3359 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3360 vmstate_tally_counters, RTL8139TallyCounters),
3361
3362 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3363 VMSTATE_END_OF_LIST()
c574ba5a
AW		 3364 },
3365 .subsections = (VMStateSubsection []) {
3366 {
3367 .vmsd = &vmstate_rtl8139_hotplug_ready,
3368 .needed = rtl8139_hotplug_ready_needed,
3369 }, {
3370 /* empty */
3371 }
060110c3
JQ		 3372 }
3373};
3374
a41b2ff2
PB		 3375/***********************************************************/
3376/* PCI RTL8139 definitions */
3377
5fafdf24 3378static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
6e355d90 3379 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3380{
efd6dd45 3381 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3382
3383 cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3384}
3385
5fafdf24 3386static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
6e355d90 3387 pcibus_t addr, pcibus_t size, int type)
a41b2ff2 3388{
efd6dd45 3389 RTL8139State *s = DO_UPCAST(RTL8139State, dev, pci_dev);
a41b2ff2
PB		 3390
3391 register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3392 register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb, s);
3393
3394 register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3395 register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw, s);
3396
3397 register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3398 register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
3399}
3400
d60efc6b 3401static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
a41b2ff2
PB		 3402 rtl8139_mmio_readb,
3403 rtl8139_mmio_readw,
3404 rtl8139_mmio_readl,
3405};
3406
d60efc6b 3407static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
a41b2ff2
PB		 3408 rtl8139_mmio_writeb,
3409 rtl8139_mmio_writew,
3410 rtl8139_mmio_writel,
3411};
3412
6cadb320
FB		 3413static void rtl8139_timer(void *opaque)
3414{
3415 RTL8139State *s = opaque;
3416
6cadb320
FB		 3417 if (!s->clock_enabled)
3418 {
7cdeb319 3419 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3420 return;
3421 }
3422
05447803
FZ		 3423 s->IntrStatus |= PCSTimeout;
3424 rtl8139_update_irq(s);
74475455 3425 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
6cadb320 3426}
6cadb320 3427
1673ad51 3428static void rtl8139_cleanup(VLANClientState *nc)
b946a153 3429{
1673ad51 3430 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3431
1673ad51 3432 s->nic = NULL;
254111ec
GH		 3433}
3434
3435static int pci_rtl8139_uninit(PCIDevice *dev)
3436{
3437 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3438
3439 cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
b946a153
AL		 3440 if (s->cplus_txbuffer) {
3441 qemu_free(s->cplus_txbuffer);
3442 s->cplus_txbuffer = NULL;
3443 }
b946a153
AL		 3444 qemu_del_timer(s->timer);
3445 qemu_free_timer(s->timer);
1673ad51 3446 qemu_del_vlan_client(&s->nic->nc);
b946a153
AL		 3447 return 0;
3448}
3449
1673ad51
MM		 3450static NetClientInfo net_rtl8139_info = {
3451 .type = NET_CLIENT_TYPE_NIC,
3452 .size = sizeof(NICState),
3453 .can_receive = rtl8139_can_receive,
3454 .receive = rtl8139_receive,
3455 .cleanup = rtl8139_cleanup,
3456};
3457
81a322d4 3458static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3459{
efd6dd45 3460 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3461 uint8_t *pci_conf;
3b46e624 3462
efd6dd45 3463 pci_conf = s->dev.config;
deb54399
AL		 3464 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3465 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
0b5b3547 3466 pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
173a543b 3467 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
0b5b3547
MT		 3468 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
3469 /* TODO: start of capability list, but no capability
3470 * list bit in status register, and offset 0xdc seems unused. */
3471 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3472
a41b2ff2
PB		 3473 /* I/O handler for memory-mapped I/O */
3474 s->rtl8139_mmio_io_addr =
2507c12a 3475 cpu_register_io_memory(rtl8139_mmio_read, rtl8139_mmio_write, s,
5cf7a3ca 3476 DEVICE_LITTLE_ENDIAN);
a41b2ff2 3477
efd6dd45 3478 pci_register_bar(&s->dev, 0, 0x100,
0392a017 3479 PCI_BASE_ADDRESS_SPACE_IO, rtl8139_ioport_map);
a41b2ff2 3480
efd6dd45 3481 pci_register_bar(&s->dev, 1, 0x100,
0392a017 3482 PCI_BASE_ADDRESS_SPACE_MEMORY, rtl8139_mmio_map);
a41b2ff2 3483
254111ec 3484 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3485
7165448a
WD		 3486 /* prepare eeprom */
3487 s->eeprom.contents[0] = 0x8129;
3488#if 1
3489 /* PCI vendor and device ID should be mirrored here */
3490 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3491 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3492#endif
3493 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3494 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3495 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3496
1673ad51
MM		 3497 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3498 dev->qdev.info->name, dev->qdev.id, s);
3499 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3500
3501 s->cplus_txbuffer = NULL;
3502 s->cplus_txbuffer_len = 0;
3503 s->cplus_txbuffer_offset = 0;
3b46e624 3504
05447803 3505 s->TimerExpire = 0;
74475455
PB		 3506 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3507 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
1ca4d09a
GN		 3508
3509 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3510
81a322d4 3511 return 0;
a41b2ff2 3512}
9d07d757 3513
0aab0d3a 3514static PCIDeviceInfo rtl8139_info = {
f82de8f0
GH		 3515 .qdev.name = "rtl8139",
3516 .qdev.size = sizeof(RTL8139State),
3517 .qdev.reset = rtl8139_reset,
be73cfe2 3518 .qdev.vmsd = &vmstate_rtl8139,
f82de8f0 3519 .init = pci_rtl8139_init,
e3936fa5 3520 .exit = pci_rtl8139_uninit,
5ee8ad71 3521 .romfile = "pxe-rtl8139.rom",
254111ec
GH		 3522 .qdev.props = (Property[]) {
3523 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3524 DEFINE_PROP_END_OF_LIST(),
3525 }
0aab0d3a
GH		 3526};
3527
9d07d757
PB		 3528static void rtl8139_register_devices(void)
3529{
0aab0d3a 3530 pci_qdev_register(&rtl8139_info);
9d07d757
PB		 3531}
3532
3533device_init(rtl8139_register_devices)
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