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bda19d7b YS |
1 | /* |
2 | * RX QEMU GDB simulator | |
3 | * | |
4 | * Copyright (c) 2019 Yoshinori Sato | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2 or later, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include "qemu/osdep.h" | |
20 | #include "qemu/cutils.h" | |
21 | #include "qemu/error-report.h" | |
22 | #include "qapi/error.h" | |
23 | #include "qemu-common.h" | |
bda19d7b YS |
24 | #include "hw/loader.h" |
25 | #include "hw/rx/rx62n.h" | |
bda19d7b YS |
26 | #include "sysemu/qtest.h" |
27 | #include "sysemu/device_tree.h" | |
28 | #include "hw/boards.h" | |
db1015e9 | 29 | #include "qom/object.h" |
bda19d7b YS |
30 | |
31 | /* Same address of GDB integrated simulator */ | |
32 | #define SDRAM_BASE EXT_CS_BASE | |
33 | ||
db1015e9 | 34 | struct RxGdbSimMachineClass { |
bda19d7b YS |
35 | /*< private >*/ |
36 | MachineClass parent_class; | |
37 | /*< public >*/ | |
38 | const char *mcu_name; | |
39 | uint32_t xtal_freq_hz; | |
db1015e9 EH |
40 | }; |
41 | typedef struct RxGdbSimMachineClass RxGdbSimMachineClass; | |
bda19d7b | 42 | |
db1015e9 | 43 | struct RxGdbSimMachineState { |
bda19d7b YS |
44 | /*< private >*/ |
45 | MachineState parent_obj; | |
46 | /*< public >*/ | |
47 | RX62NState mcu; | |
db1015e9 EH |
48 | }; |
49 | typedef struct RxGdbSimMachineState RxGdbSimMachineState; | |
bda19d7b YS |
50 | |
51 | #define TYPE_RX_GDBSIM_MACHINE MACHINE_TYPE_NAME("rx62n-common") | |
52 | ||
8110fa1d EH |
53 | DECLARE_OBJ_CHECKERS(RxGdbSimMachineState, RxGdbSimMachineClass, |
54 | RX_GDBSIM_MACHINE, TYPE_RX_GDBSIM_MACHINE) | |
bda19d7b | 55 | |
bda19d7b YS |
56 | |
57 | static void rx_load_image(RXCPU *cpu, const char *filename, | |
58 | uint32_t start, uint32_t size) | |
59 | { | |
60 | static uint32_t extable[32]; | |
61 | long kernel_size; | |
62 | int i; | |
63 | ||
64 | kernel_size = load_image_targphys(filename, start, size); | |
65 | if (kernel_size < 0) { | |
66 | fprintf(stderr, "qemu: could not load kernel '%s'\n", filename); | |
67 | exit(1); | |
68 | } | |
69 | cpu->env.pc = start; | |
70 | ||
71 | /* setup exception trap trampoline */ | |
72 | /* linux kernel only works little-endian mode */ | |
73 | for (i = 0; i < ARRAY_SIZE(extable); i++) { | |
74 | extable[i] = cpu_to_le32(0x10 + i * 4); | |
75 | } | |
76 | rom_add_blob_fixed("extable", extable, sizeof(extable), VECTOR_TABLE_BASE); | |
77 | } | |
78 | ||
79 | static void rx_gdbsim_init(MachineState *machine) | |
80 | { | |
81 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
82 | RxGdbSimMachineState *s = RX_GDBSIM_MACHINE(machine); | |
83 | RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_GET_CLASS(machine); | |
84 | MemoryRegion *sysmem = get_system_memory(); | |
85 | const char *kernel_filename = machine->kernel_filename; | |
86 | const char *dtb_filename = machine->dtb; | |
87 | ||
88 | if (machine->ram_size < mc->default_ram_size) { | |
89 | char *sz = size_to_str(mc->default_ram_size); | |
90 | error_report("Invalid RAM size, should be more than %s", sz); | |
91 | g_free(sz); | |
92 | } | |
93 | ||
94 | /* Allocate memory space */ | |
95 | memory_region_add_subregion(sysmem, SDRAM_BASE, machine->ram); | |
96 | ||
97 | /* Initialize MCU */ | |
98 | object_initialize_child(OBJECT(machine), "mcu", &s->mcu, rxc->mcu_name); | |
5325cc34 MA |
99 | object_property_set_link(OBJECT(&s->mcu), "main-bus", OBJECT(sysmem), |
100 | &error_abort); | |
101 | object_property_set_uint(OBJECT(&s->mcu), "xtal-frequency-hz", | |
102 | rxc->xtal_freq_hz, &error_abort); | |
103 | object_property_set_bool(OBJECT(&s->mcu), "load-kernel", | |
104 | kernel_filename != NULL, &error_abort); | |
ac6dd9b9 PB |
105 | |
106 | if (!kernel_filename) { | |
107 | if (machine->firmware) { | |
108 | rom_add_file_fixed(machine->firmware, RX62N_CFLASH_BASE, 0); | |
109 | } else if (!qtest_enabled()) { | |
110 | error_report("No bios or kernel specified"); | |
111 | exit(1); | |
112 | } | |
113 | } | |
114 | ||
bda19d7b YS |
115 | qdev_realize(DEVICE(&s->mcu), NULL, &error_abort); |
116 | ||
117 | /* Load kernel and dtb */ | |
118 | if (kernel_filename) { | |
119 | ram_addr_t kernel_offset; | |
120 | ||
121 | /* | |
122 | * The kernel image is loaded into | |
123 | * the latter half of the SDRAM space. | |
124 | */ | |
125 | kernel_offset = machine->ram_size / 2; | |
38688fdb | 126 | rx_load_image(RX_CPU(first_cpu), kernel_filename, |
bda19d7b YS |
127 | SDRAM_BASE + kernel_offset, kernel_offset); |
128 | if (dtb_filename) { | |
129 | ram_addr_t dtb_offset; | |
130 | int dtb_size; | |
60f6de8f | 131 | g_autofree void *dtb = load_device_tree(dtb_filename, &dtb_size); |
bda19d7b | 132 | |
bda19d7b YS |
133 | if (dtb == NULL) { |
134 | error_report("Couldn't open dtb file %s", dtb_filename); | |
135 | exit(1); | |
136 | } | |
137 | if (machine->kernel_cmdline && | |
138 | qemu_fdt_setprop_string(dtb, "/chosen", "bootargs", | |
139 | machine->kernel_cmdline) < 0) { | |
140 | error_report("Couldn't set /chosen/bootargs"); | |
141 | exit(1); | |
142 | } | |
143 | /* DTB is located at the end of SDRAM space. */ | |
144 | dtb_offset = machine->ram_size - dtb_size; | |
145 | rom_add_blob_fixed("dtb", dtb, dtb_size, | |
146 | SDRAM_BASE + dtb_offset); | |
147 | /* Set dtb address to R1 */ | |
38688fdb | 148 | RX_CPU(first_cpu)->env.regs[1] = SDRAM_BASE + dtb_offset; |
bda19d7b YS |
149 | } |
150 | } | |
151 | } | |
152 | ||
153 | static void rx_gdbsim_class_init(ObjectClass *oc, void *data) | |
154 | { | |
155 | MachineClass *mc = MACHINE_CLASS(oc); | |
156 | ||
157 | mc->init = rx_gdbsim_init; | |
158 | mc->default_cpu_type = TYPE_RX62N_CPU; | |
159 | mc->default_ram_size = 16 * MiB; | |
160 | mc->default_ram_id = "ext-sdram"; | |
161 | } | |
162 | ||
163 | static void rx62n7_class_init(ObjectClass *oc, void *data) | |
164 | { | |
165 | RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc); | |
166 | MachineClass *mc = MACHINE_CLASS(oc); | |
167 | ||
168 | rxc->mcu_name = TYPE_R5F562N7_MCU; | |
169 | rxc->xtal_freq_hz = 12 * 1000 * 1000; | |
170 | mc->desc = "gdb simulator (R5F562N7 MCU and external RAM)"; | |
171 | }; | |
172 | ||
173 | static void rx62n8_class_init(ObjectClass *oc, void *data) | |
174 | { | |
175 | RxGdbSimMachineClass *rxc = RX_GDBSIM_MACHINE_CLASS(oc); | |
176 | MachineClass *mc = MACHINE_CLASS(oc); | |
177 | ||
178 | rxc->mcu_name = TYPE_R5F562N8_MCU; | |
179 | rxc->xtal_freq_hz = 12 * 1000 * 1000; | |
180 | mc->desc = "gdb simulator (R5F562N8 MCU and external RAM)"; | |
181 | }; | |
182 | ||
183 | static const TypeInfo rx_gdbsim_types[] = { | |
184 | { | |
185 | .name = MACHINE_TYPE_NAME("gdbsim-r5f562n7"), | |
186 | .parent = TYPE_RX_GDBSIM_MACHINE, | |
187 | .class_init = rx62n7_class_init, | |
188 | }, { | |
189 | .name = MACHINE_TYPE_NAME("gdbsim-r5f562n8"), | |
190 | .parent = TYPE_RX_GDBSIM_MACHINE, | |
191 | .class_init = rx62n8_class_init, | |
192 | }, { | |
193 | .name = TYPE_RX_GDBSIM_MACHINE, | |
194 | .parent = TYPE_MACHINE, | |
195 | .instance_size = sizeof(RxGdbSimMachineState), | |
196 | .class_size = sizeof(RxGdbSimMachineClass), | |
197 | .class_init = rx_gdbsim_class_init, | |
198 | .abstract = true, | |
199 | } | |
200 | }; | |
201 | ||
202 | DEFINE_TYPES(rx_gdbsim_types) |