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hw/s390x/ipl: Fix alignment problems of S390IPLState members
[mirror_qemu.git] / hw / s390x / css.c
CommitLineData
df1fe5bb
CH		 1/*
2 * Channel subsystem base support.
3 *
4 * Copyright 2012 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
9 * directory.
10 */
11
9615495a 12#include "qemu/osdep.h"
c1755b14 13#include "qapi/error.h"
06e686ea 14#include "qapi/visitor.h"
a9c94277 15#include "hw/qdev.h"
df1fe5bb 16#include "qemu/bitops.h"
8ed179c9 17#include "qemu/error-report.h"
fdfba1a2 18#include "exec/address-spaces.h"
df1fe5bb 19#include "cpu.h"
bd3f16ac
PB		 20#include "hw/s390x/ioinst.h"
21#include "hw/s390x/css.h"
df1fe5bb 22#include "trace.h"
03cf077a 23#include "hw/s390x/s390_flic.h"
517ff12c 24#include "hw/s390x/s390-virtio-ccw.h"
df1fe5bb
CH		 25
26typedef struct CrwContainer {
27 CRW crw;
28 QTAILQ_ENTRY(CrwContainer) sibling;
29} CrwContainer;
30
457af626
HP		 31static const VMStateDescription vmstate_crw = {
32 .name = "s390_crw",
33 .version_id = 1,
34 .minimum_version_id = 1,
35 .fields = (VMStateField[]) {
36 VMSTATE_UINT16(flags, CRW),
37 VMSTATE_UINT16(rsid, CRW),
38 VMSTATE_END_OF_LIST()
39 },
40};
41
42static const VMStateDescription vmstate_crw_container = {
43 .name = "s390_crw_container",
44 .version_id = 1,
45 .minimum_version_id = 1,
46 .fields = (VMStateField[]) {
47 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW),
48 VMSTATE_END_OF_LIST()
49 },
50};
51
df1fe5bb
CH		 52typedef struct ChpInfo {
53 uint8_t in_use;
54 uint8_t type;
55 uint8_t is_virtual;
56} ChpInfo;
57
457af626
HP		 58static const VMStateDescription vmstate_chp_info = {
59 .name = "s390_chp_info",
60 .version_id = 1,
61 .minimum_version_id = 1,
62 .fields = (VMStateField[]) {
63 VMSTATE_UINT8(in_use, ChpInfo),
64 VMSTATE_UINT8(type, ChpInfo),
65 VMSTATE_UINT8(is_virtual, ChpInfo),
66 VMSTATE_END_OF_LIST()
67 }
68};
69
df1fe5bb
CH		 70typedef struct SubchSet {
71 SubchDev *sch[MAX_SCHID + 1];
72 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)];
73 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)];
74} SubchSet;
75
517ff12c
HP		 76static const VMStateDescription vmstate_scsw = {
77 .name = "s390_scsw",
78 .version_id = 1,
79 .minimum_version_id = 1,
80 .fields = (VMStateField[]) {
81 VMSTATE_UINT16(flags, SCSW),
82 VMSTATE_UINT16(ctrl, SCSW),
83 VMSTATE_UINT32(cpa, SCSW),
84 VMSTATE_UINT8(dstat, SCSW),
85 VMSTATE_UINT8(cstat, SCSW),
86 VMSTATE_UINT16(count, SCSW),
87 VMSTATE_END_OF_LIST()
88 }
89};
90
91static const VMStateDescription vmstate_pmcw = {
92 .name = "s390_pmcw",
93 .version_id = 1,
94 .minimum_version_id = 1,
95 .fields = (VMStateField[]) {
96 VMSTATE_UINT32(intparm, PMCW),
97 VMSTATE_UINT16(flags, PMCW),
98 VMSTATE_UINT16(devno, PMCW),
99 VMSTATE_UINT8(lpm, PMCW),
100 VMSTATE_UINT8(pnom, PMCW),
101 VMSTATE_UINT8(lpum, PMCW),
102 VMSTATE_UINT8(pim, PMCW),
103 VMSTATE_UINT16(mbi, PMCW),
104 VMSTATE_UINT8(pom, PMCW),
105 VMSTATE_UINT8(pam, PMCW),
106 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8),
107 VMSTATE_UINT32(chars, PMCW),
108 VMSTATE_END_OF_LIST()
109 }
110};
111
112static const VMStateDescription vmstate_schib = {
113 .name = "s390_schib",
114 .version_id = 1,
115 .minimum_version_id = 1,
116 .fields = (VMStateField[]) {
117 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW),
118 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW),
119 VMSTATE_UINT64(mba, SCHIB),
120 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4),
121 VMSTATE_END_OF_LIST()
122 }
123};
124
125
126static const VMStateDescription vmstate_ccw1 = {
127 .name = "s390_ccw1",
128 .version_id = 1,
129 .minimum_version_id = 1,
130 .fields = (VMStateField[]) {
131 VMSTATE_UINT8(cmd_code, CCW1),
132 VMSTATE_UINT8(flags, CCW1),
133 VMSTATE_UINT16(count, CCW1),
134 VMSTATE_UINT32(cda, CCW1),
135 VMSTATE_END_OF_LIST()
136 }
137};
138
139static const VMStateDescription vmstate_ciw = {
140 .name = "s390_ciw",
141 .version_id = 1,
142 .minimum_version_id = 1,
143 .fields = (VMStateField[]) {
144 VMSTATE_UINT8(type, CIW),
145 VMSTATE_UINT8(command, CIW),
146 VMSTATE_UINT16(count, CIW),
147 VMSTATE_END_OF_LIST()
148 }
149};
150
151static const VMStateDescription vmstate_sense_id = {
152 .name = "s390_sense_id",
153 .version_id = 1,
154 .minimum_version_id = 1,
155 .fields = (VMStateField[]) {
156 VMSTATE_UINT8(reserved, SenseId),
157 VMSTATE_UINT16(cu_type, SenseId),
158 VMSTATE_UINT8(cu_model, SenseId),
159 VMSTATE_UINT16(dev_type, SenseId),
160 VMSTATE_UINT8(dev_model, SenseId),
161 VMSTATE_UINT8(unused, SenseId),
162 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW),
163 VMSTATE_END_OF_LIST()
164 }
165};
166
ff443fe6
HP		 167static const VMStateDescription vmstate_orb = {
168 .name = "s390_orb",
169 .version_id = 1,
170 .minimum_version_id = 1,
171 .fields = (VMStateField[]) {
172 VMSTATE_UINT32(intparm, ORB),
173 VMSTATE_UINT16(ctrl0, ORB),
174 VMSTATE_UINT8(lpm, ORB),
175 VMSTATE_UINT8(ctrl1, ORB),
176 VMSTATE_UINT32(cpa, ORB),
177 VMSTATE_END_OF_LIST()
178 }
179};
180
181static bool vmstate_schdev_orb_needed(void *opaque)
182{
183 return css_migration_enabled();
184}
185
186static const VMStateDescription vmstate_schdev_orb = {
187 .name = "s390_subch_dev/orb",
188 .version_id = 1,
189 .minimum_version_id = 1,
190 .needed = vmstate_schdev_orb_needed,
191 .fields = (VMStateField[]) {
192 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB),
193 VMSTATE_END_OF_LIST()
194 }
195};
196
517ff12c 197static int subch_dev_post_load(void *opaque, int version_id);
44b1ff31 198static int subch_dev_pre_save(void *opaque);
517ff12c
HP		 199
200const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!"
201 " Likely reason: some sequences of plug and unplug can break"
202 " migration for machine versions prior to 2.7 (known design flaw).";
203
204const VMStateDescription vmstate_subch_dev = {
205 .name = "s390_subch_dev",
206 .version_id = 1,
207 .minimum_version_id = 1,
208 .post_load = subch_dev_post_load,
209 .pre_save = subch_dev_pre_save,
210 .fields = (VMStateField[]) {
211 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"),
212 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"),
213 VMSTATE_UINT16(migrated_schid, SubchDev),
214 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno),
215 VMSTATE_BOOL(thinint_active, SubchDev),
216 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB),
217 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32),
218 VMSTATE_UINT64(channel_prog, SubchDev),
219 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1),
220 VMSTATE_BOOL(last_cmd_valid, SubchDev),
221 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId),
222 VMSTATE_BOOL(ccw_fmt_1, SubchDev),
223 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev),
224 VMSTATE_END_OF_LIST()
ff443fe6
HP		 225 },
226 .subsections = (const VMStateDescription * []) {
227 &vmstate_schdev_orb,
228 NULL
517ff12c
HP		 229 }
230};
231
232typedef struct IndAddrPtrTmp {
233 IndAddr **parent;
234 uint64_t addr;
235 int32_t len;
236} IndAddrPtrTmp;
237
238static int post_load_ind_addr(void *opaque, int version_id)
239{
240 IndAddrPtrTmp *ptmp = opaque;
241 IndAddr **ind_addr = ptmp->parent;
242
243 if (ptmp->len != 0) {
244 *ind_addr = get_indicator(ptmp->addr, ptmp->len);
245 } else {
246 *ind_addr = NULL;
247 }
248 return 0;
249}
250
44b1ff31 251static int pre_save_ind_addr(void *opaque)
517ff12c
HP		 252{
253 IndAddrPtrTmp *ptmp = opaque;
254 IndAddr *ind_addr = *(ptmp->parent);
255
256 if (ind_addr != NULL) {
257 ptmp->len = ind_addr->len;
258 ptmp->addr = ind_addr->addr;
259 } else {
260 ptmp->len = 0;
261 ptmp->addr = 0L;
262 }
44b1ff31
DDAG		 263
264 return 0;
517ff12c
HP		 265}
266
267const VMStateDescription vmstate_ind_addr_tmp = {
268 .name = "s390_ind_addr_tmp",
269 .pre_save = pre_save_ind_addr,
270 .post_load = post_load_ind_addr,
271
272 .fields = (VMStateField[]) {
273 VMSTATE_INT32(len, IndAddrPtrTmp),
274 VMSTATE_UINT64(addr, IndAddrPtrTmp),
275 VMSTATE_END_OF_LIST()
276 }
277};
278
279const VMStateDescription vmstate_ind_addr = {
280 .name = "s390_ind_addr_tmp",
281 .fields = (VMStateField[]) {
282 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp),
283 VMSTATE_END_OF_LIST()
284 }
285};
286
df1fe5bb
CH		 287typedef struct CssImage {
288 SubchSet *sch_set[MAX_SSID + 1];
289 ChpInfo chpids[MAX_CHPID + 1];
290} CssImage;
291
457af626
HP		 292static const VMStateDescription vmstate_css_img = {
293 .name = "s390_css_img",
294 .version_id = 1,
295 .minimum_version_id = 1,
296 .fields = (VMStateField[]) {
297 /* Subchannel sets have no relevant state. */
298 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0,
299 vmstate_chp_info, ChpInfo),
300 VMSTATE_END_OF_LIST()
301 }
302
303};
304
03cf077a
CH		 305typedef struct IoAdapter {
306 uint32_t id;
307 uint8_t type;
308 uint8_t isc;
1497c160 309 uint8_t flags;
03cf077a
CH		 310} IoAdapter;
311
df1fe5bb
CH		 312typedef struct ChannelSubSys {
313 QTAILQ_HEAD(, CrwContainer) pending_crws;
c81b4f89 314 bool sei_pending;
df1fe5bb
CH		 315 bool do_crw_mchk;
316 bool crws_lost;
317 uint8_t max_cssid;
318 uint8_t max_ssid;
319 bool chnmon_active;
320 uint64_t chnmon_area;
321 CssImage *css[MAX_CSSID + 1];
322 uint8_t default_cssid;
457af626 323 /* don't migrate, see css_register_io_adapters */
dde522bb 324 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1];
457af626 325 /* don't migrate, see get_indicator and IndAddrPtrTmp */
a28d8391 326 QTAILQ_HEAD(, IndAddr) indicator_addresses;
df1fe5bb
CH		 327} ChannelSubSys;
328
457af626
HP		 329static const VMStateDescription vmstate_css = {
330 .name = "s390_css",
331 .version_id = 1,
332 .minimum_version_id = 1,
333 .fields = (VMStateField[]) {
334 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container,
335 CrwContainer, sibling),
336 VMSTATE_BOOL(sei_pending, ChannelSubSys),
337 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys),
338 VMSTATE_BOOL(crws_lost, ChannelSubSys),
339 /* These were kind of migrated by virtio */
340 VMSTATE_UINT8(max_cssid, ChannelSubSys),
341 VMSTATE_UINT8(max_ssid, ChannelSubSys),
342 VMSTATE_BOOL(chnmon_active, ChannelSubSys),
343 VMSTATE_UINT64(chnmon_area, ChannelSubSys),
344 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1,
345 0, vmstate_css_img, CssImage),
346 VMSTATE_UINT8(default_cssid, ChannelSubSys),
347 VMSTATE_END_OF_LIST()
348 }
349};
350
bc994b74
EH		 351static ChannelSubSys channel_subsys = {
352 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws),
353 .do_crw_mchk = true,
354 .sei_pending = false,
355 .do_crw_mchk = true,
356 .crws_lost = false,
357 .chnmon_active = false,
bc994b74
EH		 358 .indicator_addresses =
359 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses),
360};
df1fe5bb 361
44b1ff31 362static int subch_dev_pre_save(void *opaque)
517ff12c
HP		 363{
364 SubchDev *s = opaque;
365
366 /* Prepare remote_schid for save */
367 s->migrated_schid = s->schid;
44b1ff31
DDAG		 368
369 return 0;
517ff12c
HP		 370}
371
372static int subch_dev_post_load(void *opaque, int version_id)
373{
374
375 SubchDev *s = opaque;
376
377 /* Re-assign the subchannel to remote_schid if necessary */
378 if (s->migrated_schid != s->schid) {
379 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) {
380 /*
381 * Cleanup the slot before moving to s->migrated_schid provided
382 * it still belongs to us, i.e. it was not changed by previous
383 * invocation of this function.
384 */
385 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL);
386 }
387 /* It's OK to re-assign without a prior de-assign. */
388 s->schid = s->migrated_schid;
389 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s);
390 }
391
457af626
HP		 392 if (css_migration_enabled()) {
393 /* No compat voodoo to do ;) */
394 return 0;
395 }
517ff12c
HP		 396 /*
397 * Hack alert. If we don't migrate the channel subsystem status
398 * we still need to find out if the guest enabled mss/mcss-e.
399 * If the subchannel is enabled, it certainly was able to access it,
400 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid
401 * values. This is not watertight, but better than nothing.
402 */
403 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) {
404 if (s->ssid) {
405 channel_subsys.max_ssid = MAX_SSID;
406 }
407 if (s->cssid != channel_subsys.default_cssid) {
408 channel_subsys.max_cssid = MAX_CSSID;
409 }
410 }
411 return 0;
412}
413
e996583e
HP		 414void css_register_vmstate(void)
415{
416 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys);
417}
418
a28d8391
YMZ		 419IndAddr *get_indicator(hwaddr ind_addr, int len)
420{
421 IndAddr *indicator;
422
562f5e0b 423 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) {
a28d8391
YMZ		 424 if (indicator->addr == ind_addr) {
425 indicator->refcnt++;
426 return indicator;
427 }
428 }
429 indicator = g_new0(IndAddr, 1);
430 indicator->addr = ind_addr;
431 indicator->len = len;
432 indicator->refcnt = 1;
562f5e0b 433 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses,
a28d8391
YMZ		 434 indicator, sibling);
435 return indicator;
436}
437
438static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr,
439 bool do_map)
440{
441 S390FLICState *fs = s390_get_flic();
6762808f 442 S390FLICStateClass *fsc = s390_get_flic_class(fs);
a28d8391
YMZ		 443
444 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map);
445}
446
447void release_indicator(AdapterInfo *adapter, IndAddr *indicator)
448{
449 assert(indicator->refcnt > 0);
450 indicator->refcnt--;
451 if (indicator->refcnt > 0) {
452 return;
453 }
562f5e0b 454 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling);
a28d8391
YMZ		 455 if (indicator->map) {
456 s390_io_adapter_map(adapter, indicator->map, false);
457 }
458 g_free(indicator);
459}
460
461int map_indicator(AdapterInfo *adapter, IndAddr *indicator)
462{
463 int ret;
464
465 if (indicator->map) {
466 return 0; /* already mapped is not an error */
467 }
468 indicator->map = indicator->addr;
469 ret = s390_io_adapter_map(adapter, indicator->map, true);
470 if ((ret != 0) && (ret != -ENOSYS)) {
471 goto out_err;
472 }
473 return 0;
474
475out_err:
476 indicator->map = 0;
477 return ret;
478}
479
df1fe5bb
CH		 480int css_create_css_image(uint8_t cssid, bool default_image)
481{
482 trace_css_new_image(cssid, default_image ? "(default)" : "");
882b3b97
CH		 483 /* 255 is reserved */
484 if (cssid == 255) {
df1fe5bb
CH		 485 return -EINVAL;
486 }
562f5e0b 487 if (channel_subsys.css[cssid]) {
df1fe5bb
CH		 488 return -EBUSY;
489 }
96f64aa8 490 channel_subsys.css[cssid] = g_new0(CssImage, 1);
df1fe5bb 491 if (default_image) {
562f5e0b 492 channel_subsys.default_cssid = cssid;
df1fe5bb
CH		 493 }
494 return 0;
495}
496
dde522bb 497uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc)
03cf077a 498{
dde522bb
FL		 499 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC ||
500 !channel_subsys.io_adapters[type][isc]) {
501 return -1;
502 }
503
504 return channel_subsys.io_adapters[type][isc]->id;
505}
506
507/**
508 * css_register_io_adapters: Register I/O adapters per ISC during init
509 *
510 * @swap: an indication if byte swap is needed.
511 * @maskable: an indication if the adapter is subject to the mask operation.
1497c160
FL		 512 * @flags: further characteristics of the adapter.
513 * e.g. suppressible, an indication if the adapter is subject to AIS.
dde522bb
FL		 514 * @errp: location to store error information.
515 */
516void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
1497c160 517 uint8_t flags, Error **errp)
dde522bb
FL		 518{
519 uint32_t id;
520 int ret, isc;
03cf077a 521 IoAdapter *adapter;
03cf077a 522 S390FLICState *fs = s390_get_flic();
6762808f 523 S390FLICStateClass *fsc = s390_get_flic_class(fs);
03cf077a 524
dde522bb
FL		 525 /*
526 * Disallow multiple registrations for the same device type.
527 * Report an error if registering for an already registered type.
528 */
529 if (channel_subsys.io_adapters[type][0]) {
530 error_setg(errp, "Adapters for type %d already registered", type);
531 }
532
533 for (isc = 0; isc <= MAX_ISC; isc++) {
534 id = (type << 3) | isc;
1497c160 535 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags);
dde522bb
FL		 536 if (ret == 0) {
537 adapter = g_new0(IoAdapter, 1);
538 adapter->id = id;
539 adapter->isc = isc;
540 adapter->type = type;
1497c160 541 adapter->flags = flags;
dde522bb
FL		 542 channel_subsys.io_adapters[type][isc] = adapter;
543 } else {
544 error_setg_errno(errp, -ret, "Unexpected error %d when "
545 "registering adapter %d", ret, id);
03cf077a
CH		 546 break;
547 }
03cf077a 548 }
dde522bb
FL		 549
550 /*
551 * No need to free registered adapters in kvm: kvm will clean up
552 * when the machine goes away.
553 */
554 if (ret) {
555 for (isc--; isc >= 0; isc--) {
556 g_free(channel_subsys.io_adapters[type][isc]);
557 channel_subsys.io_adapters[type][isc] = NULL;
558 }
03cf077a 559 }
dde522bb 560
03cf077a
CH		 561}
562
c1755b14
HP		 563static void css_clear_io_interrupt(uint16_t subchannel_id,
564 uint16_t subchannel_nr)
565{
566 Error *err = NULL;
567 static bool no_clear_irq;
568 S390FLICState *fs = s390_get_flic();
6762808f 569 S390FLICStateClass *fsc = s390_get_flic_class(fs);
c1755b14
HP		 570 int r;
571
572 if (unlikely(no_clear_irq)) {
573 return;
574 }
575 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr);
576 switch (r) {
577 case 0:
578 break;
579 case -ENOSYS:
580 no_clear_irq = true;
581 /*
582 * Ignore unavailability, as the user can't do anything
583 * about it anyway.
584 */
585 break;
586 default:
587 error_setg_errno(&err, -r, "unexpected error condition");
588 error_propagate(&error_abort, err);
589 }
590}
591
592static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid)
df1fe5bb 593{
562f5e0b 594 if (channel_subsys.max_cssid > 0) {
c1755b14 595 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1;
df1fe5bb 596 }
c1755b14
HP		 597 return (ssid << 1) | 1;
598}
599
600uint16_t css_build_subchannel_id(SubchDev *sch)
601{
602 return css_do_build_subchannel_id(sch->cssid, sch->ssid);
df1fe5bb
CH		 603}
604
8ca2b376 605void css_inject_io_interrupt(SubchDev *sch)
df1fe5bb 606{
df1fe5bb
CH		 607 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
608
609 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
610 sch->curr_status.pmcw.intparm, isc, "");
de13d216 611 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 612 sch->schid,
613 sch->curr_status.pmcw.intparm,
91b0a8f3 614 isc << 27);
df1fe5bb
CH		 615}
616
617void css_conditional_io_interrupt(SubchDev *sch)
618{
6e9c893e
CH		 619 /*
620 * If the subchannel is not enabled, it is not made status pending
621 * (see PoP p. 16-17, "Status Control").
622 */
623 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA)) {
624 return;
625 }
626
df1fe5bb
CH		 627 /*
628 * If the subchannel is not currently status pending, make it pending
629 * with alert status.
630 */
631 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) {
df1fe5bb
CH		 632 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
633
634 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
635 sch->curr_status.pmcw.intparm, isc,
636 "(unsolicited)");
637 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
638 sch->curr_status.scsw.ctrl |=
639 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
640 /* Inject an I/O interrupt. */
de13d216 641 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 642 sch->schid,
643 sch->curr_status.pmcw.intparm,
91b0a8f3 644 isc << 27);
df1fe5bb
CH		 645 }
646}
647
2283f4d6
FL		 648int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
649{
650 S390FLICState *fs = s390_get_flic();
6762808f 651 S390FLICStateClass *fsc = s390_get_flic_class(fs);
2283f4d6
FL		 652 int r;
653
654 if (env->psw.mask & PSW_MASK_PSTATE) {
655 r = -PGM_PRIVILEGED;
656 goto out;
657 }
658
659 trace_css_do_sic(mode, isc);
660 switch (mode) {
661 case SIC_IRQ_MODE_ALL:
662 case SIC_IRQ_MODE_SINGLE:
663 break;
664 default:
665 r = -PGM_OPERAND;
666 goto out;
667 }
668
669 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0;
670out:
671 return r;
672}
673
25a08b8d 674void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc)
7e749462 675{
25a08b8d 676 S390FLICState *fs = s390_get_flic();
6762808f 677 S390FLICStateClass *fsc = s390_get_flic_class(fs);
7e749462 678 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;
25a08b8d
YMZ		 679 IoAdapter *adapter = channel_subsys.io_adapters[type][isc];
680
681 if (!adapter) {
682 return;
683 }
7e749462
CH		 684
685 trace_css_adapter_interrupt(isc);
25a08b8d
YMZ		 686 if (fs->ais_supported) {
687 if (fsc->inject_airq(fs, type, isc, adapter->flags)) {
688 error_report("Failed to inject airq with AIS supported");
689 exit(1);
690 }
691 } else {
692 s390_io_interrupt(0, 0, 0, io_int_word);
693 }
7e749462
CH		 694}
695
df1fe5bb
CH		 696static void sch_handle_clear_func(SubchDev *sch)
697{
698 PMCW *p = &sch->curr_status.pmcw;
699 SCSW *s = &sch->curr_status.scsw;
700 int path;
701
702 /* Path management: In our simple css, we always choose the only path. */
703 path = 0x80;
704
4c293dc6 705 /* Reset values prior to 'issuing the clear signal'. */
df1fe5bb
CH		 706 p->lpum = 0;
707 p->pom = 0xff;
708 s->flags &= ~SCSW_FLAGS_MASK_PNO;
709
710 /* We always 'attempt to issue the clear signal', and we always succeed. */
df1fe5bb
CH		 711 sch->channel_prog = 0x0;
712 sch->last_cmd_valid = false;
713 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND;
714 s->ctrl |= SCSW_STCTL_STATUS_PEND;
715
716 s->dstat = 0;
717 s->cstat = 0;
718 p->lpum = path;
719
720}
721
722static void sch_handle_halt_func(SubchDev *sch)
723{
724
725 PMCW *p = &sch->curr_status.pmcw;
726 SCSW *s = &sch->curr_status.scsw;
2ed982b6 727 hwaddr curr_ccw = sch->channel_prog;
df1fe5bb
CH		 728 int path;
729
730 /* Path management: In our simple css, we always choose the only path. */
731 path = 0x80;
732
733 /* We always 'attempt to issue the halt signal', and we always succeed. */
df1fe5bb
CH		 734 sch->channel_prog = 0x0;
735 sch->last_cmd_valid = false;
736 s->ctrl &= ~SCSW_ACTL_HALT_PEND;
737 s->ctrl |= SCSW_STCTL_STATUS_PEND;
738
739 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
740 !((s->ctrl & SCSW_ACTL_START_PEND) ||
741 (s->ctrl & SCSW_ACTL_SUSP))) {
742 s->dstat = SCSW_DSTAT_DEVICE_END;
743 }
2ed982b6
CH		 744 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
745 (s->ctrl & SCSW_ACTL_SUSP)) {
746 s->cpa = curr_ccw + 8;
747 }
df1fe5bb
CH		 748 s->cstat = 0;
749 p->lpum = path;
750
751}
752
753static void copy_sense_id_to_guest(SenseId *dest, SenseId *src)
754{
755 int i;
756
757 dest->reserved = src->reserved;
758 dest->cu_type = cpu_to_be16(src->cu_type);
759 dest->cu_model = src->cu_model;
760 dest->dev_type = cpu_to_be16(src->dev_type);
761 dest->dev_model = src->dev_model;
762 dest->unused = src->unused;
763 for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) {
764 dest->ciw[i].type = src->ciw[i].type;
765 dest->ciw[i].command = src->ciw[i].command;
766 dest->ciw[i].count = cpu_to_be16(src->ciw[i].count);
767 }
768}
769
a327c921 770static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
df1fe5bb 771{
a327c921
CH		 772 CCW0 tmp0;
773 CCW1 tmp1;
df1fe5bb
CH		 774 CCW1 ret;
775
a327c921
CH		 776 if (fmt1) {
777 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1));
778 ret.cmd_code = tmp1.cmd_code;
779 ret.flags = tmp1.flags;
780 ret.count = be16_to_cpu(tmp1.count);
781 ret.cda = be32_to_cpu(tmp1.cda);
782 } else {
783 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0));
9f94f84c
DJS		 784 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) {
785 ret.cmd_code = CCW_CMD_TIC;
786 ret.flags = 0;
787 ret.count = 0;
788 } else {
789 ret.cmd_code = tmp0.cmd_code;
790 ret.flags = tmp0.flags;
791 ret.count = be16_to_cpu(tmp0.count);
fde8206b 792 }
9f94f84c 793 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
a327c921 794 }
df1fe5bb
CH		 795 return ret;
796}
57065a70
HP		 797/**
798 * If out of bounds marks the stream broken. If broken returns -EINVAL,
799 * otherwise the requested length (may be zero)
800 */
801static inline int cds_check_len(CcwDataStream *cds, int len)
802{
803 if (cds->at_byte + len > cds->count) {
804 cds->flags |= CDS_F_STREAM_BROKEN;
805 }
806 return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len;
807}
808
62a2554e
HP		 809static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1)
810{
811 return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24));
812}
813
57065a70
HP		 814static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len,
815 CcwDataStreamOp op)
816{
817 int ret;
818
819 ret = cds_check_len(cds, len);
820 if (ret <= 0) {
821 return ret;
822 }
62a2554e
HP		 823 if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) {
824 return -EINVAL; /* channel program check */
825 }
57065a70
HP		 826 if (op == CDS_OP_A) {
827 goto incr;
828 }
829 ret = address_space_rw(&address_space_memory, cds->cda,
830 MEMTXATTRS_UNSPECIFIED, buff, len, op);
831 if (ret != MEMTX_OK) {
832 cds->flags |= CDS_F_STREAM_BROKEN;
833 return -EINVAL;
834 }
835incr:
836 cds->at_byte += len;
837 cds->cda += len;
838 return 0;
839}
840
93973f8f
HP		 841/* returns values between 1 and bsz, where bsz is a power of 2 */
842static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz)
843{
844 return bsz - (cda & (bsz - 1));
845}
846
847static inline uint64_t ccw_ida_block_size(uint8_t flags)
848{
849 if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) {
850 return 1ULL << 12;
851 }
852 return 1ULL << 11;
853}
854
855static inline int ida_read_next_idaw(CcwDataStream *cds)
856{
857 union {uint64_t fmt2; uint32_t fmt1; } idaw;
858 int ret;
859 hwaddr idaw_addr;
860 bool idaw_fmt2 = cds->flags & CDS_F_C64;
861 bool ccw_fmt1 = cds->flags & CDS_F_FMT;
862
863 if (idaw_fmt2) {
864 idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw;
865 if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
866 return -EINVAL; /* channel program check */
867 }
868 ret = address_space_rw(&address_space_memory, idaw_addr,
869 MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2,
870 sizeof(idaw.fmt2), false);
871 cds->cda = be64_to_cpu(idaw.fmt2);
872 } else {
873 idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw;
874 if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
875 return -EINVAL; /* channel program check */
876 }
877 ret = address_space_rw(&address_space_memory, idaw_addr,
878 MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1,
879 sizeof(idaw.fmt1), false);
880 cds->cda = be64_to_cpu(idaw.fmt1);
881 if (cds->cda & 0x80000000) {
882 return -EINVAL; /* channel program check */
883 }
884 }
885 ++(cds->at_idaw);
886 if (ret != MEMTX_OK) {
887 /* assume inaccessible address */
888 return -EINVAL; /* channel program check */
889 }
890 return 0;
891}
892
893static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len,
894 CcwDataStreamOp op)
895{
896 uint64_t bsz = ccw_ida_block_size(cds->flags);
897 int ret = 0;
898 uint16_t cont_left, iter_len;
899
900 ret = cds_check_len(cds, len);
901 if (ret <= 0) {
902 return ret;
903 }
904 if (!cds->at_idaw) {
905 /* read first idaw */
906 ret = ida_read_next_idaw(cds);
907 if (ret) {
908 goto err;
909 }
910 cont_left = ida_continuous_left(cds->cda, bsz);
911 } else {
912 cont_left = ida_continuous_left(cds->cda, bsz);
913 if (cont_left == bsz) {
914 ret = ida_read_next_idaw(cds);
915 if (ret) {
916 goto err;
917 }
918 if (cds->cda & (bsz - 1)) {
919 ret = -EINVAL; /* channel program check */
920 goto err;
921 }
922 }
923 }
924 do {
925 iter_len = MIN(len, cont_left);
926 if (op != CDS_OP_A) {
927 ret = address_space_rw(&address_space_memory, cds->cda,
928 MEMTXATTRS_UNSPECIFIED, buff, iter_len, op);
929 if (ret != MEMTX_OK) {
930 /* assume inaccessible address */
931 ret = -EINVAL; /* channel program check */
932 goto err;
933 }
934 }
935 cds->at_byte += iter_len;
936 cds->cda += iter_len;
937 len -= iter_len;
938 if (!len) {
939 break;
940 }
941 ret = ida_read_next_idaw(cds);
942 if (ret) {
943 goto err;
944 }
945 cont_left = bsz;
946 } while (true);
947 return ret;
948err:
949 cds->flags |= CDS_F_STREAM_BROKEN;
950 return ret;
951}
952
57065a70
HP		 953void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb)
954{
955 /*
956 * We don't support MIDA (an optional facility) yet and we
957 * catch this earlier. Just for expressing the precondition.
958 */
959 g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW));
960 cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) |
961 (orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) |
62a2554e 962 (orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) |
57065a70 963 (ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0);
62a2554e 964
57065a70
HP		 965 cds->count = ccw->count;
966 cds->cda_orig = ccw->cda;
967 ccw_dstream_rewind(cds);
968 if (!(cds->flags & CDS_F_IDA)) {
969 cds->op_handler = ccw_dstream_rw_noflags;
970 } else {
93973f8f 971 cds->op_handler = ccw_dstream_rw_ida;
57065a70
HP		 972 }
973}
df1fe5bb 974
ce350f32
CH		 975static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr,
976 bool suspend_allowed)
df1fe5bb
CH		 977{
978 int ret;
979 bool check_len;
980 int len;
981 CCW1 ccw;
982
983 if (!ccw_addr) {
cc6a9f8d 984 return -EINVAL; /* channel-program check */
df1fe5bb 985 }
198c0d1f
HP		 986 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */
987 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) {
988 return -EINVAL;
989 }
df1fe5bb 990
a327c921
CH		 991 /* Translate everything to format-1 ccws - the information is the same. */
992 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1);
df1fe5bb
CH		 993
994 /* Check for invalid command codes. */
995 if ((ccw.cmd_code & 0x0f) == 0) {
996 return -EINVAL;
997 }
998 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) &&
999 ((ccw.cmd_code & 0xf0) != 0)) {
1000 return -EINVAL;
1001 }
fa4463e0
CH		 1002 if (!sch->ccw_fmt_1 && (ccw.count == 0) &&
1003 (ccw.cmd_code != CCW_CMD_TIC)) {
1004 return -EINVAL;
1005 }
df1fe5bb 1006
4e19b57b
CH		 1007 /* We don't support MIDA. */
1008 if (ccw.flags & CCW_FLAG_MIDA) {
1009 return -EINVAL;
1010 }
1011
df1fe5bb 1012 if (ccw.flags & CCW_FLAG_SUSPEND) {
ce350f32 1013 return suspend_allowed ? -EINPROGRESS : -EINVAL;
df1fe5bb
CH		 1014 }
1015
1016 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC));
1017
e8601dd5
CH		 1018 if (!ccw.cda) {
1019 if (sch->ccw_no_data_cnt == 255) {
1020 return -EINVAL;
1021 }
1022 sch->ccw_no_data_cnt++;
1023 }
1024
df1fe5bb 1025 /* Look at the command. */
0a22eac5 1026 ccw_dstream_init(&sch->cds, &ccw, &(sch->orb));
df1fe5bb
CH		 1027 switch (ccw.cmd_code) {
1028 case CCW_CMD_NOOP:
1029 /* Nothing to do. */
1030 ret = 0;
1031 break;
1032 case CCW_CMD_BASIC_SENSE:
1033 if (check_len) {
1034 if (ccw.count != sizeof(sch->sense_data)) {
1035 ret = -EINVAL;
1036 break;
1037 }
1038 }
1039 len = MIN(ccw.count, sizeof(sch->sense_data));
0a22eac5
HP		 1040 ccw_dstream_write_buf(&sch->cds, sch->sense_data, len);
1041 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds);
df1fe5bb
CH		 1042 memset(sch->sense_data, 0, sizeof(sch->sense_data));
1043 ret = 0;
1044 break;
1045 case CCW_CMD_SENSE_ID:
1046 {
1047 SenseId sense_id;
1048
1049 copy_sense_id_to_guest(&sense_id, &sch->id);
1050 /* Sense ID information is device specific. */
1051 if (check_len) {
1052 if (ccw.count != sizeof(sense_id)) {
1053 ret = -EINVAL;
1054 break;
1055 }
1056 }
1057 len = MIN(ccw.count, sizeof(sense_id));
1058 /*
1059 * Only indicate 0xff in the first sense byte if we actually
1060 * have enough place to store at least bytes 0-3.
1061 */
1062 if (len >= 4) {
1063 sense_id.reserved = 0xff;
1064 } else {
1065 sense_id.reserved = 0;
1066 }
0a22eac5
HP		 1067 ccw_dstream_write_buf(&sch->cds, &sense_id, len);
1068 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds);
df1fe5bb
CH		 1069 ret = 0;
1070 break;
1071 }
1072 case CCW_CMD_TIC:
1073 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) {
1074 ret = -EINVAL;
1075 break;
1076 }
4add0da6
HP		 1077 if (ccw.flags || ccw.count) {
1078 /* We have already sanitized these if converted from fmt 0. */
df1fe5bb
CH		 1079 ret = -EINVAL;
1080 break;
1081 }
1082 sch->channel_prog = ccw.cda;
1083 ret = -EAGAIN;
1084 break;
1085 default:
1086 if (sch->ccw_cb) {
1087 /* Handle device specific commands. */
1088 ret = sch->ccw_cb(sch, ccw);
1089 } else {
8d034a6f 1090 ret = -ENOSYS;
df1fe5bb
CH		 1091 }
1092 break;
1093 }
1094 sch->last_cmd = ccw;
1095 sch->last_cmd_valid = true;
1096 if (ret == 0) {
1097 if (ccw.flags & CCW_FLAG_CC) {
1098 sch->channel_prog += 8;
1099 ret = -EAGAIN;
1100 }
1101 }
1102
1103 return ret;
1104}
1105
b5f5a3af 1106static void sch_handle_start_func_virtual(SubchDev *sch)
df1fe5bb
CH		 1107{
1108
1109 PMCW *p = &sch->curr_status.pmcw;
1110 SCSW *s = &sch->curr_status.scsw;
df1fe5bb
CH		 1111 int path;
1112 int ret;
ce350f32 1113 bool suspend_allowed;
df1fe5bb
CH		 1114
1115 /* Path management: In our simple css, we always choose the only path. */
1116 path = 0x80;
1117
1118 if (!(s->ctrl & SCSW_ACTL_SUSP)) {
727a0424 1119 /* Start Function triggered via ssch, i.e. we have an ORB */
b5f5a3af 1120 ORB *orb = &sch->orb;
6b7741c2
CH		 1121 s->cstat = 0;
1122 s->dstat = 0;
df1fe5bb
CH		 1123 /* Look at the orb and try to execute the channel program. */
1124 p->intparm = orb->intparm;
1125 if (!(orb->lpm & path)) {
1126 /* Generate a deferred cc 3 condition. */
1127 s->flags |= SCSW_FLAGS_MASK_CC;
1128 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1129 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND);
1130 return;
1131 }
a327c921 1132 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT);
485dd690 1133 s->flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0;
e8601dd5 1134 sch->ccw_no_data_cnt = 0;
ce350f32 1135 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND);
df1fe5bb 1136 } else {
b5f5a3af 1137 /* Start Function resumed via rsch */
df1fe5bb 1138 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND);
ce350f32
CH		 1139 /* The channel program had been suspended before. */
1140 suspend_allowed = true;
df1fe5bb
CH		 1141 }
1142 sch->last_cmd_valid = false;
1143 do {
ce350f32 1144 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed);
df1fe5bb
CH		 1145 switch (ret) {
1146 case -EAGAIN:
1147 /* ccw chain, continue processing */
1148 break;
1149 case 0:
1150 /* success */
1151 s->ctrl &= ~SCSW_ACTL_START_PEND;
1152 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1153 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
1154 SCSW_STCTL_STATUS_PEND;
1155 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END;
2ed982b6 1156 s->cpa = sch->channel_prog + 8;
df1fe5bb 1157 break;
2dc95b4c
JL		 1158 case -EIO:
1159 /* I/O errors, status depends on specific devices */
1160 break;
8d034a6f 1161 case -ENOSYS:
df1fe5bb
CH		 1162 /* unsupported command, generate unit check (command reject) */
1163 s->ctrl &= ~SCSW_ACTL_START_PEND;
1164 s->dstat = SCSW_DSTAT_UNIT_CHECK;
1165 /* Set sense bit 0 in ecw0. */
1166 sch->sense_data[0] = 0x80;
1167 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1168 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
1169 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
2ed982b6 1170 s->cpa = sch->channel_prog + 8;
df1fe5bb 1171 break;
8d034a6f 1172 case -EINPROGRESS:
df1fe5bb
CH		 1173 /* channel program has been suspended */
1174 s->ctrl &= ~SCSW_ACTL_START_PEND;
1175 s->ctrl |= SCSW_ACTL_SUSP;
1176 break;
1177 default:
1178 /* error, generate channel program check */
1179 s->ctrl &= ~SCSW_ACTL_START_PEND;
1180 s->cstat = SCSW_CSTAT_PROG_CHECK;
1181 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1182 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
1183 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
2ed982b6 1184 s->cpa = sch->channel_prog + 8;
df1fe5bb
CH		 1185 break;
1186 }
1187 } while (ret == -EAGAIN);
1188
1189}
1190
66dc50f7 1191static IOInstEnding sch_handle_start_func_passthrough(SubchDev *sch)
bab482d7
XFR		 1192{
1193
1194 PMCW *p = &sch->curr_status.pmcw;
1195 SCSW *s = &sch->curr_status.scsw;
bab482d7 1196
b5f5a3af 1197 ORB *orb = &sch->orb;
bab482d7
XFR		 1198 if (!(s->ctrl & SCSW_ACTL_SUSP)) {
1199 assert(orb != NULL);
1200 p->intparm = orb->intparm;
1201 }
66dc50f7 1202 return s390_ccw_cmd_request(sch);
bab482d7
XFR		 1203}
1204
df1fe5bb
CH		 1205/*
1206 * On real machines, this would run asynchronously to the main vcpus.
1207 * We might want to make some parts of the ssch handling (interpreting
1208 * read/writes) asynchronous later on if we start supporting more than
1209 * our current very simple devices.
1210 */
66dc50f7 1211IOInstEnding do_subchannel_work_virtual(SubchDev *sch)
df1fe5bb
CH		 1212{
1213
1214 SCSW *s = &sch->curr_status.scsw;
1215
1216 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) {
1217 sch_handle_clear_func(sch);
1218 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) {
1219 sch_handle_halt_func(sch);
1220 } else if (s->ctrl & SCSW_FCTL_START_FUNC) {
727a0424 1221 /* Triggered by both ssch and rsch. */
b5f5a3af 1222 sch_handle_start_func_virtual(sch);
df1fe5bb
CH		 1223 }
1224 css_inject_io_interrupt(sch);
66dc50f7
HP		 1225 /* inst must succeed if this func is called */
1226 return IOINST_CC_EXPECTED;
bab482d7
XFR		 1227}
1228
66dc50f7 1229IOInstEnding do_subchannel_work_passthrough(SubchDev *sch)
bab482d7 1230{
bab482d7
XFR		 1231 SCSW *s = &sch->curr_status.scsw;
1232
1233 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) {
1234 /* TODO: Clear handling */
1235 sch_handle_clear_func(sch);
bab482d7
XFR		 1236 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) {
1237 /* TODO: Halt handling */
1238 sch_handle_halt_func(sch);
bab482d7 1239 } else if (s->ctrl & SCSW_FCTL_START_FUNC) {
66dc50f7 1240 return sch_handle_start_func_passthrough(sch);
bab482d7 1241 }
66dc50f7 1242 return IOINST_CC_EXPECTED;
bab482d7
XFR		 1243}
1244
66dc50f7 1245static IOInstEnding do_subchannel_work(SubchDev *sch)
bab482d7 1246{
9ea63c05 1247 if (!sch->do_subchannel_work) {
66dc50f7 1248 return IOINST_CC_STATUS_PRESENT;
bab482d7 1249 }
9ea63c05
HP		 1250 g_assert(sch->curr_status.scsw.ctrl & SCSW_CTRL_MASK_FCTL);
1251 return sch->do_subchannel_work(sch);
df1fe5bb
CH		 1252}
1253
1254static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src)
1255{
1256 int i;
1257
1258 dest->intparm = cpu_to_be32(src->intparm);
1259 dest->flags = cpu_to_be16(src->flags);
1260 dest->devno = cpu_to_be16(src->devno);
1261 dest->lpm = src->lpm;
1262 dest->pnom = src->pnom;
1263 dest->lpum = src->lpum;
1264 dest->pim = src->pim;
1265 dest->mbi = cpu_to_be16(src->mbi);
1266 dest->pom = src->pom;
1267 dest->pam = src->pam;
1268 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1269 dest->chpid[i] = src->chpid[i];
1270 }
1271 dest->chars = cpu_to_be32(src->chars);
1272}
1273
8ca2b376 1274void copy_scsw_to_guest(SCSW *dest, const SCSW *src)
df1fe5bb
CH		 1275{
1276 dest->flags = cpu_to_be16(src->flags);
1277 dest->ctrl = cpu_to_be16(src->ctrl);
1278 dest->cpa = cpu_to_be32(src->cpa);
1279 dest->dstat = src->dstat;
1280 dest->cstat = src->cstat;
1281 dest->count = cpu_to_be16(src->count);
1282}
1283
1284static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src)
1285{
1286 int i;
1287
1288 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw);
1289 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1290 dest->mba = cpu_to_be64(src->mba);
1291 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1292 dest->mda[i] = src->mda[i];
1293 }
1294}
1295
1296int css_do_stsch(SubchDev *sch, SCHIB *schib)
1297{
1298 /* Use current status. */
1299 copy_schib_to_guest(schib, &sch->curr_status);
1300 return 0;
1301}
1302
1303static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src)
1304{
1305 int i;
1306
1307 dest->intparm = be32_to_cpu(src->intparm);
1308 dest->flags = be16_to_cpu(src->flags);
1309 dest->devno = be16_to_cpu(src->devno);
1310 dest->lpm = src->lpm;
1311 dest->pnom = src->pnom;
1312 dest->lpum = src->lpum;
1313 dest->pim = src->pim;
1314 dest->mbi = be16_to_cpu(src->mbi);
1315 dest->pom = src->pom;
1316 dest->pam = src->pam;
1317 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1318 dest->chpid[i] = src->chpid[i];
1319 }
1320 dest->chars = be32_to_cpu(src->chars);
1321}
1322
1323static void copy_scsw_from_guest(SCSW *dest, const SCSW *src)
1324{
1325 dest->flags = be16_to_cpu(src->flags);
1326 dest->ctrl = be16_to_cpu(src->ctrl);
1327 dest->cpa = be32_to_cpu(src->cpa);
1328 dest->dstat = src->dstat;
1329 dest->cstat = src->cstat;
1330 dest->count = be16_to_cpu(src->count);
1331}
1332
1333static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src)
1334{
1335 int i;
1336
1337 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw);
1338 copy_scsw_from_guest(&dest->scsw, &src->scsw);
1339 dest->mba = be64_to_cpu(src->mba);
1340 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1341 dest->mda[i] = src->mda[i];
1342 }
1343}
1344
6bb6f194 1345IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib)
df1fe5bb
CH		 1346{
1347 SCSW *s = &sch->curr_status.scsw;
1348 PMCW *p = &sch->curr_status.pmcw;
62ac4a52 1349 uint16_t oldflags;
df1fe5bb
CH		 1350 SCHIB schib;
1351
1352 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) {
6bb6f194 1353 return IOINST_CC_EXPECTED;
df1fe5bb
CH		 1354 }
1355
1356 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
6bb6f194 1357 return IOINST_CC_STATUS_PRESENT;
df1fe5bb
CH		 1358 }
1359
1360 if (s->ctrl &
1361 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) {
6bb6f194 1362 return IOINST_CC_BUSY;
df1fe5bb
CH		 1363 }
1364
1365 copy_schib_from_guest(&schib, orig_schib);
1366 /* Only update the program-modifiable fields. */
1367 p->intparm = schib.pmcw.intparm;
62ac4a52 1368 oldflags = p->flags;
df1fe5bb
CH		 1369 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1370 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1371 PMCW_FLAGS_MASK_MP);
1372 p->flags |= schib.pmcw.flags &
1373 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1374 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1375 PMCW_FLAGS_MASK_MP);
1376 p->lpm = schib.pmcw.lpm;
1377 p->mbi = schib.pmcw.mbi;
1378 p->pom = schib.pmcw.pom;
1379 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1380 p->chars |= schib.pmcw.chars &
1381 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1382 sch->curr_status.mba = schib.mba;
1383
62ac4a52
TH		 1384 /* Has the channel been disabled? */
1385 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0
1386 && (p->flags & PMCW_FLAGS_MASK_ENA) == 0) {
1387 sch->disable_cb(sch);
1388 }
6bb6f194 1389 return IOINST_CC_EXPECTED;
df1fe5bb
CH		 1390}
1391
96376408 1392IOInstEnding css_do_xsch(SubchDev *sch)
df1fe5bb
CH		 1393{
1394 SCSW *s = &sch->curr_status.scsw;
1395 PMCW *p = &sch->curr_status.pmcw;
df1fe5bb 1396
c679e74d 1397 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
96376408 1398 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1399 }
1400
6c864622 1401 if (s->ctrl & SCSW_CTRL_MASK_STCTL) {
96376408 1402 return IOINST_CC_STATUS_PRESENT;
6c864622
HP		 1403 }
1404
df1fe5bb
CH		 1405 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) ||
1406 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1407 (!(s->ctrl &
1408 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) ||
1409 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) {
96376408 1410 return IOINST_CC_BUSY;
df1fe5bb
CH		 1411 }
1412
1413 /* Cancel the current operation. */
1414 s->ctrl &= ~(SCSW_FCTL_START_FUNC |
1415 SCSW_ACTL_RESUME_PEND |
1416 SCSW_ACTL_START_PEND |
1417 SCSW_ACTL_SUSP);
1418 sch->channel_prog = 0x0;
1419 sch->last_cmd_valid = false;
df1fe5bb
CH		 1420 s->dstat = 0;
1421 s->cstat = 0;
96376408 1422 return IOINST_CC_EXPECTED;
df1fe5bb
CH		 1423}
1424
77331442 1425IOInstEnding css_do_csch(SubchDev *sch)
df1fe5bb
CH		 1426{
1427 SCSW *s = &sch->curr_status.scsw;
1428 PMCW *p = &sch->curr_status.pmcw;
df1fe5bb 1429
c679e74d 1430 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
77331442 1431 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1432 }
1433
1434 /* Trigger the clear function. */
1435 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL);
4c6bf79a 1436 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND;
df1fe5bb 1437
77331442 1438 return do_subchannel_work(sch);
df1fe5bb
CH		 1439}
1440
ae9f1be3 1441IOInstEnding css_do_hsch(SubchDev *sch)
df1fe5bb
CH		 1442{
1443 SCSW *s = &sch->curr_status.scsw;
1444 PMCW *p = &sch->curr_status.pmcw;
df1fe5bb 1445
c679e74d 1446 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
ae9f1be3 1447 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1448 }
1449
1450 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) ||
1451 (s->ctrl & (SCSW_STCTL_PRIMARY |
1452 SCSW_STCTL_SECONDARY |
1453 SCSW_STCTL_ALERT))) {
ae9f1be3 1454 return IOINST_CC_STATUS_PRESENT;
df1fe5bb
CH		 1455 }
1456
1457 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) {
ae9f1be3 1458 return IOINST_CC_BUSY;
df1fe5bb
CH		 1459 }
1460
1461 /* Trigger the halt function. */
1462 s->ctrl |= SCSW_FCTL_HALT_FUNC;
1463 s->ctrl &= ~SCSW_FCTL_START_FUNC;
1464 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) ==
1465 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) &&
1466 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) {
1467 s->ctrl &= ~SCSW_STCTL_STATUS_PEND;
1468 }
1469 s->ctrl |= SCSW_ACTL_HALT_PEND;
1470
ae9f1be3 1471 return do_subchannel_work(sch);
df1fe5bb
CH		 1472}
1473
1474static void css_update_chnmon(SubchDev *sch)
1475{
1476 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) {
1477 /* Not active. */
1478 return;
1479 }
1480 /* The counter is conveniently located at the beginning of the struct. */
1481 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) {
1482 /* Format 1, per-subchannel area. */
1483 uint32_t count;
1484
42874d3a
PM		 1485 count = address_space_ldl(&address_space_memory,
1486 sch->curr_status.mba,
1487 MEMTXATTRS_UNSPECIFIED,
1488 NULL);
df1fe5bb 1489 count++;
42874d3a
PM		 1490 address_space_stl(&address_space_memory, sch->curr_status.mba, count,
1491 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1492 } else {
1493 /* Format 0, global area. */
1494 uint32_t offset;
1495 uint16_t count;
1496
1497 offset = sch->curr_status.pmcw.mbi << 5;
42874d3a 1498 count = address_space_lduw(&address_space_memory,
562f5e0b 1499 channel_subsys.chnmon_area + offset,
42874d3a
PM		 1500 MEMTXATTRS_UNSPECIFIED,
1501 NULL);
df1fe5bb 1502 count++;
42874d3a 1503 address_space_stw(&address_space_memory,
562f5e0b 1504 channel_subsys.chnmon_area + offset, count,
42874d3a 1505 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1506 }
1507}
1508
66dc50f7 1509IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb)
df1fe5bb
CH		 1510{
1511 SCSW *s = &sch->curr_status.scsw;
1512 PMCW *p = &sch->curr_status.pmcw;
df1fe5bb 1513
c679e74d 1514 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
66dc50f7 1515 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1516 }
1517
1518 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
66dc50f7 1519 return IOINST_CC_STATUS_PRESENT;
df1fe5bb
CH		 1520 }
1521
1522 if (s->ctrl & (SCSW_FCTL_START_FUNC |
1523 SCSW_FCTL_HALT_FUNC |
1524 SCSW_FCTL_CLEAR_FUNC)) {
66dc50f7 1525 return IOINST_CC_BUSY;
df1fe5bb
CH		 1526 }
1527
1528 /* If monitoring is active, update counter. */
562f5e0b 1529 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1530 css_update_chnmon(sch);
1531 }
ff443fe6 1532 sch->orb = *orb;
df1fe5bb
CH		 1533 sch->channel_prog = orb->cpa;
1534 /* Trigger the start function. */
1535 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND);
1536 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1537
66dc50f7 1538 return do_subchannel_work(sch);
df1fe5bb
CH		 1539}
1540
b7b6348a
TH		 1541static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw,
1542 int *irb_len)
df1fe5bb
CH		 1543{
1544 int i;
f068d320
CH		 1545 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1546 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1547
1548 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1549
1550 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) {
1551 dest->esw[i] = cpu_to_be32(src->esw[i]);
1552 }
1553 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) {
1554 dest->ecw[i] = cpu_to_be32(src->ecw[i]);
1555 }
b7b6348a
TH		 1556 *irb_len = sizeof(*dest) - sizeof(dest->emw);
1557
f068d320
CH		 1558 /* extended measurements enabled? */
1559 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) ||
1560 !(pmcw->flags & PMCW_FLAGS_MASK_TF) ||
1561 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) {
1562 return;
1563 }
1564 /* extended measurements pending? */
1565 if (!(stctl & SCSW_STCTL_STATUS_PEND)) {
1566 return;
1567 }
1568 if ((stctl & SCSW_STCTL_PRIMARY) ||
1569 (stctl == SCSW_STCTL_SECONDARY) ||
1570 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) {
1571 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) {
1572 dest->emw[i] = cpu_to_be32(src->emw[i]);
1573 }
df1fe5bb 1574 }
b7b6348a 1575 *irb_len = sizeof(*dest);
df1fe5bb
CH		 1576}
1577
b7b6348a 1578int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len)
df1fe5bb
CH		 1579{
1580 SCSW *s = &sch->curr_status.scsw;
1581 PMCW *p = &sch->curr_status.pmcw;
1582 uint16_t stctl;
df1fe5bb 1583 IRB irb;
df1fe5bb 1584
c679e74d 1585 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
b7b6348a 1586 return 3;
df1fe5bb
CH		 1587 }
1588
1589 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
df1fe5bb
CH		 1590
1591 /* Prepare the irb for the guest. */
1592 memset(&irb, 0, sizeof(IRB));
1593
1594 /* Copy scsw from current status. */
1595 memcpy(&irb.scsw, s, sizeof(SCSW));
1596 if (stctl & SCSW_STCTL_STATUS_PEND) {
1597 if (s->cstat & (SCSW_CSTAT_DATA_CHECK |
1598 SCSW_CSTAT_CHN_CTRL_CHK |
1599 SCSW_CSTAT_INTF_CTRL_CHK)) {
1600 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF;
1601 irb.esw[0] = 0x04804000;
1602 } else {
1603 irb.esw[0] = 0x00800000;
1604 }
1605 /* If a unit check is pending, copy sense data. */
1606 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) &&
1607 (p->chars & PMCW_CHARS_MASK_CSENSE)) {
b498484e
CH		 1608 int i;
1609
df1fe5bb 1610 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL;
b498484e 1611 /* Attention: sense_data is already BE! */
df1fe5bb 1612 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data));
b498484e
CH		 1613 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) {
1614 irb.ecw[i] = be32_to_cpu(irb.ecw[i]);
1615 }
8312976e 1616 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8);
df1fe5bb
CH		 1617 }
1618 }
1619 /* Store the irb to the guest. */
b7b6348a
TH		 1620 copy_irb_to_guest(target_irb, &irb, p, irb_len);
1621
1622 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
1623}
1624
1625void css_do_tsch_update_subch(SubchDev *sch)
1626{
1627 SCSW *s = &sch->curr_status.scsw;
1628 PMCW *p = &sch->curr_status.pmcw;
1629 uint16_t stctl;
1630 uint16_t fctl;
1631 uint16_t actl;
1632
1633 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
1634 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL;
1635 actl = s->ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1636
1637 /* Clear conditions on subchannel, if applicable. */
1638 if (stctl & SCSW_STCTL_STATUS_PEND) {
1639 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1640 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) ||
1641 ((fctl & SCSW_FCTL_HALT_FUNC) &&
1642 (actl & SCSW_ACTL_SUSP))) {
1643 s->ctrl &= ~SCSW_CTRL_MASK_FCTL;
1644 }
1645 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) {
1646 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1647 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1648 SCSW_ACTL_START_PEND |
1649 SCSW_ACTL_HALT_PEND |
1650 SCSW_ACTL_CLEAR_PEND |
1651 SCSW_ACTL_SUSP);
1652 } else {
1653 if ((actl & SCSW_ACTL_SUSP) &&
1654 (fctl & SCSW_FCTL_START_FUNC)) {
1655 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1656 if (fctl & SCSW_FCTL_HALT_FUNC) {
1657 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1658 SCSW_ACTL_START_PEND |
1659 SCSW_ACTL_HALT_PEND |
1660 SCSW_ACTL_CLEAR_PEND |
1661 SCSW_ACTL_SUSP);
1662 } else {
1663 s->ctrl &= ~SCSW_ACTL_RESUME_PEND;
1664 }
1665 }
1666 }
1667 /* Clear pending sense data. */
1668 if (p->chars & PMCW_CHARS_MASK_CSENSE) {
1669 memset(sch->sense_data, 0 , sizeof(sch->sense_data));
1670 }
1671 }
df1fe5bb
CH		 1672}
1673
1674static void copy_crw_to_guest(CRW *dest, const CRW *src)
1675{
1676 dest->flags = cpu_to_be16(src->flags);
1677 dest->rsid = cpu_to_be16(src->rsid);
1678}
1679
1680int css_do_stcrw(CRW *crw)
1681{
1682 CrwContainer *crw_cont;
1683 int ret;
1684
562f5e0b 1685 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws);
df1fe5bb 1686 if (crw_cont) {
562f5e0b 1687 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 1688 copy_crw_to_guest(crw, &crw_cont->crw);
1689 g_free(crw_cont);
1690 ret = 0;
1691 } else {
1692 /* List was empty, turn crw machine checks on again. */
1693 memset(crw, 0, sizeof(*crw));
562f5e0b 1694 channel_subsys.do_crw_mchk = true;
df1fe5bb
CH		 1695 ret = 1;
1696 }
1697
1698 return ret;
1699}
1700
7f74f0aa
TH		 1701static void copy_crw_from_guest(CRW *dest, const CRW *src)
1702{
1703 dest->flags = be16_to_cpu(src->flags);
1704 dest->rsid = be16_to_cpu(src->rsid);
1705}
1706
1707void css_undo_stcrw(CRW *crw)
1708{
1709 CrwContainer *crw_cont;
1710
96f64aa8 1711 crw_cont = g_try_new0(CrwContainer, 1);
7f74f0aa 1712 if (!crw_cont) {
562f5e0b 1713 channel_subsys.crws_lost = true;
7f74f0aa
TH		 1714 return;
1715 }
1716 copy_crw_from_guest(&crw_cont->crw, crw);
1717
562f5e0b 1718 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling);
7f74f0aa
TH		 1719}
1720
df1fe5bb
CH		 1721int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
1722 int rfmt, void *buf)
1723{
1724 int i, desc_size;
1725 uint32_t words[8];
1726 uint32_t chpid_type_word;
1727 CssImage *css;
1728
1729 if (!m && !cssid) {
562f5e0b 1730 css = channel_subsys.css[channel_subsys.default_cssid];
df1fe5bb 1731 } else {
562f5e0b 1732 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1733 }
1734 if (!css) {
1735 return 0;
1736 }
1737 desc_size = 0;
1738 for (i = f_chpid; i <= l_chpid; i++) {
1739 if (css->chpids[i].in_use) {
1740 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i;
1741 if (rfmt == 0) {
1742 words[0] = cpu_to_be32(chpid_type_word);
1743 words[1] = 0;
1744 memcpy(buf + desc_size, words, 8);
1745 desc_size += 8;
1746 } else if (rfmt == 1) {
1747 words[0] = cpu_to_be32(chpid_type_word);
1748 words[1] = 0;
1749 words[2] = 0;
1750 words[3] = 0;
1751 words[4] = 0;
1752 words[5] = 0;
1753 words[6] = 0;
1754 words[7] = 0;
1755 memcpy(buf + desc_size, words, 32);
1756 desc_size += 32;
1757 }
1758 }
1759 }
1760 return desc_size;
1761}
1762
1763void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
1764{
1765 /* dct is currently ignored (not really meaningful for our devices) */
1766 /* TODO: Don't ignore mbk. */
562f5e0b 1767 if (update && !channel_subsys.chnmon_active) {
df1fe5bb 1768 /* Enable measuring. */
562f5e0b
EH		 1769 channel_subsys.chnmon_area = mbo;
1770 channel_subsys.chnmon_active = true;
df1fe5bb 1771 }
562f5e0b 1772 if (!update && channel_subsys.chnmon_active) {
df1fe5bb 1773 /* Disable measuring. */
562f5e0b
EH		 1774 channel_subsys.chnmon_area = 0;
1775 channel_subsys.chnmon_active = false;
df1fe5bb
CH		 1776 }
1777}
1778
66dc50f7 1779IOInstEnding css_do_rsch(SubchDev *sch)
df1fe5bb
CH		 1780{
1781 SCSW *s = &sch->curr_status.scsw;
1782 PMCW *p = &sch->curr_status.pmcw;
df1fe5bb 1783
c679e74d 1784 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
66dc50f7 1785 return IOINST_CC_NOT_OPERATIONAL;
df1fe5bb
CH		 1786 }
1787
1788 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
66dc50f7 1789 return IOINST_CC_STATUS_PRESENT;
df1fe5bb
CH		 1790 }
1791
1792 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1793 (s->ctrl & SCSW_ACTL_RESUME_PEND) ||
1794 (!(s->ctrl & SCSW_ACTL_SUSP))) {
66dc50f7 1795 return IOINST_CC_BUSY;
df1fe5bb
CH		 1796 }
1797
1798 /* If monitoring is active, update counter. */
562f5e0b 1799 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1800 css_update_chnmon(sch);
1801 }
1802
1803 s->ctrl |= SCSW_ACTL_RESUME_PEND;
66dc50f7 1804 return do_subchannel_work(sch);
df1fe5bb
CH		 1805}
1806
1807int css_do_rchp(uint8_t cssid, uint8_t chpid)
1808{
1809 uint8_t real_cssid;
1810
562f5e0b 1811 if (cssid > channel_subsys.max_cssid) {
df1fe5bb
CH		 1812 return -EINVAL;
1813 }
562f5e0b
EH		 1814 if (channel_subsys.max_cssid == 0) {
1815 real_cssid = channel_subsys.default_cssid;
df1fe5bb
CH		 1816 } else {
1817 real_cssid = cssid;
1818 }
562f5e0b 1819 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1820 return -EINVAL;
1821 }
1822
562f5e0b 1823 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) {
df1fe5bb
CH		 1824 return -ENODEV;
1825 }
1826
562f5e0b 1827 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) {
df1fe5bb
CH		 1828 fprintf(stderr,
1829 "rchp unsupported for non-virtual chpid %x.%02x!\n",
1830 real_cssid, chpid);
1831 return -ENODEV;
1832 }
1833
1834 /* We don't really use a channel path, so we're done here. */
5c8d6f00 1835 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1,
562f5e0b
EH		 1836 channel_subsys.max_cssid > 0 ? 1 : 0, chpid);
1837 if (channel_subsys.max_cssid > 0) {
5c8d6f00 1838 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8);
df1fe5bb
CH		 1839 }
1840 return 0;
1841}
1842
38dd7cc7 1843bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid)
df1fe5bb
CH		 1844{
1845 SubchSet *set;
38dd7cc7 1846 uint8_t real_cssid;
df1fe5bb 1847
562f5e0b 1848 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
882b3b97 1849 if (ssid > MAX_SSID ||
562f5e0b
EH		 1850 !channel_subsys.css[real_cssid] ||
1851 !channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1852 return true;
1853 }
562f5e0b 1854 set = channel_subsys.css[real_cssid]->sch_set[ssid];
df1fe5bb
CH		 1855 return schid > find_last_bit(set->schids_used,
1856 (MAX_SCHID + 1) / sizeof(unsigned long));
1857}
1858
6c15e9bf
JL		 1859unsigned int css_find_free_chpid(uint8_t cssid)
1860{
1861 CssImage *css = channel_subsys.css[cssid];
1862 unsigned int chpid;
1863
1864 if (!css) {
1865 return MAX_CHPID + 1;
1866 }
1867
1868 for (chpid = 0; chpid <= MAX_CHPID; chpid++) {
1869 /* skip reserved chpid */
1870 if (chpid == VIRTIO_CCW_CHPID) {
1871 continue;
1872 }
1873 if (!css->chpids[chpid].in_use) {
1874 return chpid;
1875 }
1876 }
1877 return MAX_CHPID + 1;
1878}
1879
8f3cf012
XFR		 1880static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type,
1881 bool is_virt)
df1fe5bb
CH		 1882{
1883 CssImage *css;
1884
1885 trace_css_chpid_add(cssid, chpid, type);
562f5e0b 1886 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1887 if (!css) {
1888 return -EINVAL;
1889 }
1890 if (css->chpids[chpid].in_use) {
1891 return -EEXIST;
1892 }
1893 css->chpids[chpid].in_use = 1;
1894 css->chpids[chpid].type = type;
8f3cf012 1895 css->chpids[chpid].is_virtual = is_virt;
df1fe5bb
CH		 1896
1897 css_generate_chp_crws(cssid, chpid);
1898
1899 return 0;
1900}
1901
1902void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type)
1903{
1904 PMCW *p = &sch->curr_status.pmcw;
1905 SCSW *s = &sch->curr_status.scsw;
1906 int i;
562f5e0b 1907 CssImage *css = channel_subsys.css[sch->cssid];
df1fe5bb
CH		 1908
1909 assert(css != NULL);
1910 memset(p, 0, sizeof(PMCW));
1911 p->flags |= PMCW_FLAGS_MASK_DNV;
1912 p->devno = sch->devno;
1913 /* single path */
1914 p->pim = 0x80;
1915 p->pom = 0xff;
1916 p->pam = 0x80;
1917 p->chpid[0] = chpid;
1918 if (!css->chpids[chpid].in_use) {
8f3cf012 1919 css_add_chpid(sch->cssid, chpid, type, true);
df1fe5bb
CH		 1920 }
1921
1922 memset(s, 0, sizeof(SCSW));
1923 sch->curr_status.mba = 0;
1924 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) {
1925 sch->curr_status.mda[i] = 0;
1926 }
1927}
1928
1929SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid)
1930{
1931 uint8_t real_cssid;
1932
562f5e0b 1933 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
df1fe5bb 1934
562f5e0b 1935 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1936 return NULL;
1937 }
1938
562f5e0b 1939 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1940 return NULL;
1941 }
1942
562f5e0b 1943 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid];
df1fe5bb
CH		 1944}
1945
cf249935
SS		 1946/**
1947 * Return free device number in subchannel set.
1948 *
1949 * Return index of the first free device number in the subchannel set
1950 * identified by @p cssid and @p ssid, beginning the search at @p
1951 * start and wrapping around at MAX_DEVNO. Return a value exceeding
1952 * MAX_SCHID if there are no free device numbers in the subchannel
1953 * set.
1954 */
1955static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid,
1956 uint16_t start)
1957{
1958 uint32_t round;
1959
1960 for (round = 0; round <= MAX_DEVNO; round++) {
1961 uint16_t devno = (start + round) % MAX_DEVNO;
1962
1963 if (!css_devno_used(cssid, ssid, devno)) {
1964 return devno;
1965 }
1966 }
1967 return MAX_DEVNO + 1;
1968}
1969
1970/**
1971 * Return first free subchannel (id) in subchannel set.
1972 *
1973 * Return index of the first free subchannel in the subchannel set
1974 * identified by @p cssid and @p ssid, if there is any. Return a value
1975 * exceeding MAX_SCHID if there are no free subchannels in the
1976 * subchannel set.
1977 */
1978static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid)
1979{
1980 uint32_t schid;
1981
1982 for (schid = 0; schid <= MAX_SCHID; schid++) {
1983 if (!css_find_subch(1, cssid, ssid, schid)) {
1984 return schid;
1985 }
1986 }
1987 return MAX_SCHID + 1;
1988}
1989
1990/**
1991 * Return first free subchannel (id) in subchannel set for a device number
1992 *
1993 * Verify the device number @p devno is not used yet in the subchannel
1994 * set identified by @p cssid and @p ssid. Set @p schid to the index
1995 * of the first free subchannel in the subchannel set, if there is
1996 * any. Return true if everything succeeded and false otherwise.
1997 */
1998static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid,
1999 uint16_t devno, uint16_t *schid,
2000 Error **errp)
2001{
2002 uint32_t free_schid;
2003
2004 assert(schid);
2005 if (css_devno_used(cssid, ssid, devno)) {
2006 error_setg(errp, "Device %x.%x.%04x already exists",
2007 cssid, ssid, devno);
2008 return false;
2009 }
2010 free_schid = css_find_free_subch(cssid, ssid);
2011 if (free_schid > MAX_SCHID) {
2012 error_setg(errp, "No free subchannel found for %x.%x.%04x",
2013 cssid, ssid, devno);
2014 return false;
2015 }
2016 *schid = free_schid;
2017 return true;
2018}
2019
2020/**
2021 * Return first free subchannel (id) and device number
2022 *
2023 * Locate the first free subchannel and first free device number in
2024 * any of the subchannel sets of the channel subsystem identified by
2025 * @p cssid. Return false if no free subchannel / device number could
2026 * be found. Otherwise set @p ssid, @p devno and @p schid to identify
2027 * the available subchannel and device number and return true.
2028 *
2029 * May modify @p ssid, @p devno and / or @p schid even if no free
2030 * subchannel / device number could be found.
2031 */
2032static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid,
2033 uint16_t *devno, uint16_t *schid,
2034 Error **errp)
2035{
2036 uint32_t free_schid, free_devno;
2037
2038 assert(ssid && devno && schid);
2039 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) {
2040 free_schid = css_find_free_subch(cssid, *ssid);
2041 if (free_schid > MAX_SCHID) {
2042 continue;
2043 }
2044 free_devno = css_find_free_devno(cssid, *ssid, free_schid);
2045 if (free_devno > MAX_DEVNO) {
2046 continue;
2047 }
2048 *schid = free_schid;
2049 *devno = free_devno;
2050 return true;
2051 }
2052 error_setg(errp, "Virtual channel subsystem is full!");
2053 return false;
2054}
2055
df1fe5bb
CH		 2056bool css_subch_visible(SubchDev *sch)
2057{
562f5e0b 2058 if (sch->ssid > channel_subsys.max_ssid) {
df1fe5bb
CH		 2059 return false;
2060 }
2061
562f5e0b
EH		 2062 if (sch->cssid != channel_subsys.default_cssid) {
2063 return (channel_subsys.max_cssid > 0);
df1fe5bb
CH		 2064 }
2065
2066 return true;
2067}
2068
2069bool css_present(uint8_t cssid)
2070{
562f5e0b 2071 return (channel_subsys.css[cssid] != NULL);
df1fe5bb
CH		 2072}
2073
2074bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno)
2075{
562f5e0b 2076 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 2077 return false;
2078 }
562f5e0b 2079 if (!channel_subsys.css[cssid]->sch_set[ssid]) {
df1fe5bb
CH		 2080 return false;
2081 }
2082
2083 return !!test_bit(devno,
562f5e0b 2084 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used);
df1fe5bb
CH		 2085}
2086
2087void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
2088 uint16_t devno, SubchDev *sch)
2089{
2090 CssImage *css;
2091 SubchSet *s_set;
2092
2093 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid,
2094 devno);
562f5e0b 2095 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 2096 fprintf(stderr,
2097 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n",
2098 __func__, cssid, ssid, schid);
2099 return;
2100 }
562f5e0b 2101 css = channel_subsys.css[cssid];
df1fe5bb
CH		 2102
2103 if (!css->sch_set[ssid]) {
96f64aa8 2104 css->sch_set[ssid] = g_new0(SubchSet, 1);
df1fe5bb
CH		 2105 }
2106 s_set = css->sch_set[ssid];
2107
2108 s_set->sch[schid] = sch;
2109 if (sch) {
2110 set_bit(schid, s_set->schids_used);
2111 set_bit(devno, s_set->devnos_used);
2112 } else {
2113 clear_bit(schid, s_set->schids_used);
2114 clear_bit(devno, s_set->devnos_used);
2115 }
2116}
2117
5c8d6f00
DJS		 2118void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
2119 int chain, uint16_t rsid)
df1fe5bb
CH		 2120{
2121 CrwContainer *crw_cont;
2122
2123 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : "");
2124 /* TODO: Maybe use a static crw pool? */
96f64aa8 2125 crw_cont = g_try_new0(CrwContainer, 1);
df1fe5bb 2126 if (!crw_cont) {
562f5e0b 2127 channel_subsys.crws_lost = true;
df1fe5bb
CH		 2128 return;
2129 }
2130 crw_cont->crw.flags = (rsc << 8) | erc;
5c8d6f00
DJS		 2131 if (solicited) {
2132 crw_cont->crw.flags |= CRW_FLAGS_MASK_S;
2133 }
df1fe5bb
CH		 2134 if (chain) {
2135 crw_cont->crw.flags |= CRW_FLAGS_MASK_C;
2136 }
2137 crw_cont->crw.rsid = rsid;
562f5e0b 2138 if (channel_subsys.crws_lost) {
df1fe5bb 2139 crw_cont->crw.flags |= CRW_FLAGS_MASK_R;
562f5e0b 2140 channel_subsys.crws_lost = false;
df1fe5bb
CH		 2141 }
2142
562f5e0b 2143 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb 2144
562f5e0b
EH		 2145 if (channel_subsys.do_crw_mchk) {
2146 channel_subsys.do_crw_mchk = false;
df1fe5bb 2147 /* Inject crw pending machine check. */
de13d216 2148 s390_crw_mchk();
df1fe5bb
CH		 2149 }
2150}
2151
2152void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
2153 int hotplugged, int add)
2154{
2155 uint8_t guest_cssid;
2156 bool chain_crw;
2157
2158 if (add && !hotplugged) {
2159 return;
2160 }
562f5e0b 2161 if (channel_subsys.max_cssid == 0) {
df1fe5bb 2162 /* Default cssid shows up as 0. */
562f5e0b 2163 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid;
df1fe5bb
CH		 2164 } else {
2165 /* Show real cssid to the guest. */
2166 guest_cssid = cssid;
2167 }
2168 /*
2169 * Only notify for higher subchannel sets/channel subsystems if the
2170 * guest has enabled it.
2171 */
562f5e0b
EH		 2172 if ((ssid > channel_subsys.max_ssid) ||
2173 (guest_cssid > channel_subsys.max_cssid) ||
2174 ((channel_subsys.max_cssid == 0) &&
2175 (cssid != channel_subsys.default_cssid))) {
df1fe5bb
CH		 2176 return;
2177 }
562f5e0b
EH		 2178 chain_crw = (channel_subsys.max_ssid > 0) ||
2179 (channel_subsys.max_cssid > 0);
5c8d6f00 2180 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid);
df1fe5bb 2181 if (chain_crw) {
5c8d6f00 2182 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0,
df1fe5bb
CH		 2183 (guest_cssid << 8) | (ssid << 4));
2184 }
c1755b14
HP		 2185 /* RW_ERC_IPI --> clear pending interrupts */
2186 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid);
df1fe5bb
CH		 2187}
2188
2189void css_generate_chp_crws(uint8_t cssid, uint8_t chpid)
2190{
2191 /* TODO */
2192}
2193
8cba80c3
FB		 2194void css_generate_css_crws(uint8_t cssid)
2195{
562f5e0b 2196 if (!channel_subsys.sei_pending) {
5c8d6f00 2197 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid);
c81b4f89 2198 }
562f5e0b 2199 channel_subsys.sei_pending = true;
c81b4f89
SSG		 2200}
2201
2202void css_clear_sei_pending(void)
2203{
562f5e0b 2204 channel_subsys.sei_pending = false;
8cba80c3
FB		 2205}
2206
df1fe5bb
CH		 2207int css_enable_mcsse(void)
2208{
2209 trace_css_enable_facility("mcsse");
562f5e0b 2210 channel_subsys.max_cssid = MAX_CSSID;
df1fe5bb
CH		 2211 return 0;
2212}
2213
2214int css_enable_mss(void)
2215{
2216 trace_css_enable_facility("mss");
562f5e0b 2217 channel_subsys.max_ssid = MAX_SSID;
df1fe5bb
CH		 2218 return 0;
2219}
2220
df1fe5bb
CH		 2221void css_reset_sch(SubchDev *sch)
2222{
2223 PMCW *p = &sch->curr_status.pmcw;
2224
62ac4a52
TH		 2225 if ((p->flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) {
2226 sch->disable_cb(sch);
2227 }
2228
df1fe5bb
CH		 2229 p->intparm = 0;
2230 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
2231 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
2232 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF);
2233 p->flags |= PMCW_FLAGS_MASK_DNV;
2234 p->devno = sch->devno;
2235 p->pim = 0x80;
2236 p->lpm = p->pim;
2237 p->pnom = 0;
2238 p->lpum = 0;
2239 p->mbi = 0;
2240 p->pom = 0xff;
2241 p->pam = 0x80;
2242 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME |
2243 PMCW_CHARS_MASK_CSENSE);
2244
2245 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw));
2246 sch->curr_status.mba = 0;
2247
2248 sch->channel_prog = 0x0;
2249 sch->last_cmd_valid = false;
7e749462 2250 sch->thinint_active = false;
df1fe5bb
CH		 2251}
2252
2253void css_reset(void)
2254{
2255 CrwContainer *crw_cont;
2256
2257 /* Clean up monitoring. */
562f5e0b
EH		 2258 channel_subsys.chnmon_active = false;
2259 channel_subsys.chnmon_area = 0;
df1fe5bb
CH		 2260
2261 /* Clear pending CRWs. */
562f5e0b
EH		 2262 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) {
2263 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 2264 g_free(crw_cont);
2265 }
562f5e0b
EH		 2266 channel_subsys.sei_pending = false;
2267 channel_subsys.do_crw_mchk = true;
2268 channel_subsys.crws_lost = false;
df1fe5bb
CH		 2269
2270 /* Reset maximum ids. */
562f5e0b
EH		 2271 channel_subsys.max_cssid = 0;
2272 channel_subsys.max_ssid = 0;
df1fe5bb 2273}
06e686ea
CH		 2274
2275static void get_css_devid(Object *obj, Visitor *v, const char *name,
2276 void *opaque, Error **errp)
2277{
2278 DeviceState *dev = DEVICE(obj);
2279 Property *prop = opaque;
2280 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
2281 char buffer[] = "xx.x.xxxx";
2282 char *p = buffer;
2283 int r;
2284
2285 if (dev_id->valid) {
2286
2287 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid,
2288 dev_id->ssid, dev_id->devid);
2289 assert(r == sizeof(buffer) - 1);
2290
2291 /* drop leading zero */
2292 if (dev_id->cssid <= 0xf) {
2293 p++;
2294 }
2295 } else {
2296 snprintf(buffer, sizeof(buffer), "<unset>");
2297 }
2298
2299 visit_type_str(v, name, &p, errp);
2300}
2301
2302/*
2303 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid
2304 */
2305static void set_css_devid(Object *obj, Visitor *v, const char *name,
2306 void *opaque, Error **errp)
2307{
2308 DeviceState *dev = DEVICE(obj);
2309 Property *prop = opaque;
2310 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
2311 Error *local_err = NULL;
2312 char *str;
2313 int num, n1, n2;
2314 unsigned int cssid, ssid, devid;
2315
2316 if (dev->realized) {
2317 qdev_prop_set_after_realize(dev, name, errp);
2318 return;
2319 }
2320
2321 visit_type_str(v, name, &str, &local_err);
2322 if (local_err) {
2323 error_propagate(errp, local_err);
2324 return;
2325 }
2326
2327 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2);
2328 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) {
2329 error_set_from_qdev_prop_error(errp, EINVAL, dev, prop, str);
2330 goto out;
2331 }
2332 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) {
2333 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x",
2334 cssid, ssid);
2335 goto out;
2336 }
2337
2338 dev_id->cssid = cssid;
2339 dev_id->ssid = ssid;
2340 dev_id->devid = devid;
2341 dev_id->valid = true;
2342
2343out:
2344 g_free(str);
2345}
2346
1b6b7d10 2347const PropertyInfo css_devid_propinfo = {
06e686ea
CH		 2348 .name = "str",
2349 .description = "Identifier of an I/O device in the channel "
2350 "subsystem, example: fe.1.23ab",
2351 .get = get_css_devid,
2352 .set = set_css_devid,
2353};
cf249935 2354
1b6b7d10 2355const PropertyInfo css_devid_ro_propinfo = {
c35fc6aa
DJS		 2356 .name = "str",
2357 .description = "Read-only identifier of an I/O device in the channel "
2358 "subsystem, example: fe.1.23ab",
2359 .get = get_css_devid,
2360};
2361
36699ab4 2362SubchDev *css_create_sch(CssDevId bus_id, Error **errp)
cf249935
SS		 2363{
2364 uint16_t schid = 0;
2365 SubchDev *sch;
2366
817d4a6b 2367 if (bus_id.valid) {
36699ab4 2368 if (!channel_subsys.css[bus_id.cssid]) {
817d4a6b
DJS		 2369 css_create_css_image(bus_id.cssid, false);
2370 }
2371
cf249935
SS		 2372 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid,
2373 bus_id.devid, &schid, errp)) {
2374 return NULL;
2375 }
817d4a6b 2376 } else {
99577c49 2377 for (bus_id.cssid = channel_subsys.default_cssid;;) {
817d4a6b
DJS		 2378 if (!channel_subsys.css[bus_id.cssid]) {
2379 css_create_css_image(bus_id.cssid, false);
2380 }
2381
2382 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid,
2383 &bus_id.devid, &schid,
2384 NULL)) {
2385 break;
2386 }
99577c49
HP		 2387 bus_id.cssid = (bus_id.cssid + 1) % MAX_CSSID;
2388 if (bus_id.cssid == channel_subsys.default_cssid) {
817d4a6b
DJS		 2389 error_setg(errp, "Virtual channel subsystem is full!");
2390 return NULL;
2391 }
2392 }
cf249935
SS		 2393 }
2394
96f64aa8 2395 sch = g_new0(SubchDev, 1);
cf249935
SS		 2396 sch->cssid = bus_id.cssid;
2397 sch->ssid = bus_id.ssid;
2398 sch->devno = bus_id.devid;
2399 sch->schid = schid;
2400 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch);
2401 return sch;
2402}
8f3cf012
XFR		 2403
2404static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id)
2405{
2406 char *fid_path;
2407 FILE *fd;
2408 uint32_t chpid[8];
2409 int i;
2410 PMCW *p = &sch->curr_status.pmcw;
2411
2412 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids",
2413 dev_id->cssid, dev_id->ssid, dev_id->devid);
2414 fd = fopen(fid_path, "r");
2415 if (fd == NULL) {
2416 error_report("%s: open %s failed", __func__, fid_path);
2417 g_free(fid_path);
2418 return -EINVAL;
2419 }
2420
2421 if (fscanf(fd, "%x %x %x %x %x %x %x %x",
2422 &chpid[0], &chpid[1], &chpid[2], &chpid[3],
2423 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) {
2424 fclose(fd);
2425 g_free(fid_path);
2426 return -EINVAL;
2427 }
2428
2429 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) {
2430 p->chpid[i] = chpid[i];
2431 }
2432
2433 fclose(fd);
2434 g_free(fid_path);
2435
2436 return 0;
2437}
2438
2439static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id)
2440{
2441 char *fid_path;
2442 FILE *fd;
2443 uint32_t pim, pam, pom;
2444 PMCW *p = &sch->curr_status.pmcw;
2445
2446 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom",
2447 dev_id->cssid, dev_id->ssid, dev_id->devid);
2448 fd = fopen(fid_path, "r");
2449 if (fd == NULL) {
2450 error_report("%s: open %s failed", __func__, fid_path);
2451 g_free(fid_path);
2452 return -EINVAL;
2453 }
2454
2455 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) {
2456 fclose(fd);
2457 g_free(fid_path);
2458 return -EINVAL;
2459 }
2460
2461 p->pim = pim;
2462 p->pam = pam;
2463 p->pom = pom;
2464 fclose(fd);
2465 g_free(fid_path);
2466
2467 return 0;
2468}
2469
2470static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type,
2471 CssDevId *dev_id)
2472{
2473 char *fid_path;
2474 FILE *fd;
2475
2476 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type",
2477 dev_id->cssid, chpid);
2478 fd = fopen(fid_path, "r");
2479 if (fd == NULL) {
2480 error_report("%s: open %s failed", __func__, fid_path);
2481 g_free(fid_path);
2482 return -EINVAL;
2483 }
2484
2485 if (fscanf(fd, "%x", type) != 1) {
2486 fclose(fd);
2487 g_free(fid_path);
2488 return -EINVAL;
2489 }
2490
2491 fclose(fd);
2492 g_free(fid_path);
2493
2494 return 0;
2495}
2496
2497/*
2498 * We currently retrieve the real device information from sysfs to build the
2499 * guest subchannel information block without considering the migration feature.
2500 * We need to revisit this problem when we want to add migration support.
2501 */
2502int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id)
2503{
2504 CssImage *css = channel_subsys.css[sch->cssid];
2505 PMCW *p = &sch->curr_status.pmcw;
2506 SCSW *s = &sch->curr_status.scsw;
2507 uint32_t type;
2508 int i, ret;
2509
2510 assert(css != NULL);
2511 memset(p, 0, sizeof(PMCW));
2512 p->flags |= PMCW_FLAGS_MASK_DNV;
2513 /* We are dealing with I/O subchannels only. */
2514 p->devno = sch->devno;
2515
2516 /* Grab path mask from sysfs. */
2517 ret = css_sch_get_path_masks(sch, dev_id);
2518 if (ret) {
2519 return ret;
2520 }
2521
2522 /* Grab chpids from sysfs. */
2523 ret = css_sch_get_chpids(sch, dev_id);
2524 if (ret) {
2525 return ret;
2526 }
2527
2528 /* Build chpid type. */
2529 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) {
2530 if (p->chpid[i] && !css->chpids[p->chpid[i]].in_use) {
2531 ret = css_sch_get_chpid_type(p->chpid[i], &type, dev_id);
2532 if (ret) {
2533 return ret;
2534 }
2535 css_add_chpid(sch->cssid, p->chpid[i], type, false);
2536 }
2537 }
2538
2539 memset(s, 0, sizeof(SCSW));
2540 sch->curr_status.mba = 0;
2541 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) {
2542 sch->curr_status.mda[i] = 0;
2543 }
2544
2545 return 0;
2546}
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