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390x/css: introduce maximum data address checking
[mirror_qemu.git] / hw / s390x / css.c
CommitLineData
df1fe5bb
CH		 1/*
2 * Channel subsystem base support.
3 *
4 * Copyright 2012 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
8 * your option) any later version. See the COPYING file in the top-level
9 * directory.
10 */
11
9615495a 12#include "qemu/osdep.h"
c1755b14 13#include "qapi/error.h"
06e686ea 14#include "qapi/visitor.h"
a9c94277 15#include "hw/qdev.h"
8f3cf012 16#include "qemu/error-report.h"
df1fe5bb 17#include "qemu/bitops.h"
8ed179c9 18#include "qemu/error-report.h"
fdfba1a2 19#include "exec/address-spaces.h"
df1fe5bb 20#include "cpu.h"
bd3f16ac
PB		 21#include "hw/s390x/ioinst.h"
22#include "hw/s390x/css.h"
df1fe5bb 23#include "trace.h"
03cf077a 24#include "hw/s390x/s390_flic.h"
517ff12c 25#include "hw/s390x/s390-virtio-ccw.h"
df1fe5bb
CH		 26
27typedef struct CrwContainer {
28 CRW crw;
29 QTAILQ_ENTRY(CrwContainer) sibling;
30} CrwContainer;
31
457af626
HP		 32static const VMStateDescription vmstate_crw = {
33 .name = "s390_crw",
34 .version_id = 1,
35 .minimum_version_id = 1,
36 .fields = (VMStateField[]) {
37 VMSTATE_UINT16(flags, CRW),
38 VMSTATE_UINT16(rsid, CRW),
39 VMSTATE_END_OF_LIST()
40 },
41};
42
43static const VMStateDescription vmstate_crw_container = {
44 .name = "s390_crw_container",
45 .version_id = 1,
46 .minimum_version_id = 1,
47 .fields = (VMStateField[]) {
48 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW),
49 VMSTATE_END_OF_LIST()
50 },
51};
52
df1fe5bb
CH		 53typedef struct ChpInfo {
54 uint8_t in_use;
55 uint8_t type;
56 uint8_t is_virtual;
57} ChpInfo;
58
457af626
HP		 59static const VMStateDescription vmstate_chp_info = {
60 .name = "s390_chp_info",
61 .version_id = 1,
62 .minimum_version_id = 1,
63 .fields = (VMStateField[]) {
64 VMSTATE_UINT8(in_use, ChpInfo),
65 VMSTATE_UINT8(type, ChpInfo),
66 VMSTATE_UINT8(is_virtual, ChpInfo),
67 VMSTATE_END_OF_LIST()
68 }
69};
70
df1fe5bb
CH		 71typedef struct SubchSet {
72 SubchDev *sch[MAX_SCHID + 1];
73 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)];
74 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)];
75} SubchSet;
76
517ff12c
HP		 77static const VMStateDescription vmstate_scsw = {
78 .name = "s390_scsw",
79 .version_id = 1,
80 .minimum_version_id = 1,
81 .fields = (VMStateField[]) {
82 VMSTATE_UINT16(flags, SCSW),
83 VMSTATE_UINT16(ctrl, SCSW),
84 VMSTATE_UINT32(cpa, SCSW),
85 VMSTATE_UINT8(dstat, SCSW),
86 VMSTATE_UINT8(cstat, SCSW),
87 VMSTATE_UINT16(count, SCSW),
88 VMSTATE_END_OF_LIST()
89 }
90};
91
92static const VMStateDescription vmstate_pmcw = {
93 .name = "s390_pmcw",
94 .version_id = 1,
95 .minimum_version_id = 1,
96 .fields = (VMStateField[]) {
97 VMSTATE_UINT32(intparm, PMCW),
98 VMSTATE_UINT16(flags, PMCW),
99 VMSTATE_UINT16(devno, PMCW),
100 VMSTATE_UINT8(lpm, PMCW),
101 VMSTATE_UINT8(pnom, PMCW),
102 VMSTATE_UINT8(lpum, PMCW),
103 VMSTATE_UINT8(pim, PMCW),
104 VMSTATE_UINT16(mbi, PMCW),
105 VMSTATE_UINT8(pom, PMCW),
106 VMSTATE_UINT8(pam, PMCW),
107 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8),
108 VMSTATE_UINT32(chars, PMCW),
109 VMSTATE_END_OF_LIST()
110 }
111};
112
113static const VMStateDescription vmstate_schib = {
114 .name = "s390_schib",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .fields = (VMStateField[]) {
118 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW),
119 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW),
120 VMSTATE_UINT64(mba, SCHIB),
121 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4),
122 VMSTATE_END_OF_LIST()
123 }
124};
125
126
127static const VMStateDescription vmstate_ccw1 = {
128 .name = "s390_ccw1",
129 .version_id = 1,
130 .minimum_version_id = 1,
131 .fields = (VMStateField[]) {
132 VMSTATE_UINT8(cmd_code, CCW1),
133 VMSTATE_UINT8(flags, CCW1),
134 VMSTATE_UINT16(count, CCW1),
135 VMSTATE_UINT32(cda, CCW1),
136 VMSTATE_END_OF_LIST()
137 }
138};
139
140static const VMStateDescription vmstate_ciw = {
141 .name = "s390_ciw",
142 .version_id = 1,
143 .minimum_version_id = 1,
144 .fields = (VMStateField[]) {
145 VMSTATE_UINT8(type, CIW),
146 VMSTATE_UINT8(command, CIW),
147 VMSTATE_UINT16(count, CIW),
148 VMSTATE_END_OF_LIST()
149 }
150};
151
152static const VMStateDescription vmstate_sense_id = {
153 .name = "s390_sense_id",
154 .version_id = 1,
155 .minimum_version_id = 1,
156 .fields = (VMStateField[]) {
157 VMSTATE_UINT8(reserved, SenseId),
158 VMSTATE_UINT16(cu_type, SenseId),
159 VMSTATE_UINT8(cu_model, SenseId),
160 VMSTATE_UINT16(dev_type, SenseId),
161 VMSTATE_UINT8(dev_model, SenseId),
162 VMSTATE_UINT8(unused, SenseId),
163 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW),
164 VMSTATE_END_OF_LIST()
165 }
166};
167
ff443fe6
HP		 168static const VMStateDescription vmstate_orb = {
169 .name = "s390_orb",
170 .version_id = 1,
171 .minimum_version_id = 1,
172 .fields = (VMStateField[]) {
173 VMSTATE_UINT32(intparm, ORB),
174 VMSTATE_UINT16(ctrl0, ORB),
175 VMSTATE_UINT8(lpm, ORB),
176 VMSTATE_UINT8(ctrl1, ORB),
177 VMSTATE_UINT32(cpa, ORB),
178 VMSTATE_END_OF_LIST()
179 }
180};
181
182static bool vmstate_schdev_orb_needed(void *opaque)
183{
184 return css_migration_enabled();
185}
186
187static const VMStateDescription vmstate_schdev_orb = {
188 .name = "s390_subch_dev/orb",
189 .version_id = 1,
190 .minimum_version_id = 1,
191 .needed = vmstate_schdev_orb_needed,
192 .fields = (VMStateField[]) {
193 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB),
194 VMSTATE_END_OF_LIST()
195 }
196};
197
517ff12c 198static int subch_dev_post_load(void *opaque, int version_id);
44b1ff31 199static int subch_dev_pre_save(void *opaque);
517ff12c
HP		 200
201const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!"
202 " Likely reason: some sequences of plug and unplug can break"
203 " migration for machine versions prior to 2.7 (known design flaw).";
204
205const VMStateDescription vmstate_subch_dev = {
206 .name = "s390_subch_dev",
207 .version_id = 1,
208 .minimum_version_id = 1,
209 .post_load = subch_dev_post_load,
210 .pre_save = subch_dev_pre_save,
211 .fields = (VMStateField[]) {
212 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"),
213 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"),
214 VMSTATE_UINT16(migrated_schid, SubchDev),
215 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno),
216 VMSTATE_BOOL(thinint_active, SubchDev),
217 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB),
218 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32),
219 VMSTATE_UINT64(channel_prog, SubchDev),
220 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1),
221 VMSTATE_BOOL(last_cmd_valid, SubchDev),
222 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId),
223 VMSTATE_BOOL(ccw_fmt_1, SubchDev),
224 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev),
225 VMSTATE_END_OF_LIST()
ff443fe6
HP		 226 },
227 .subsections = (const VMStateDescription * []) {
228 &vmstate_schdev_orb,
229 NULL
517ff12c
HP		 230 }
231};
232
233typedef struct IndAddrPtrTmp {
234 IndAddr **parent;
235 uint64_t addr;
236 int32_t len;
237} IndAddrPtrTmp;
238
239static int post_load_ind_addr(void *opaque, int version_id)
240{
241 IndAddrPtrTmp *ptmp = opaque;
242 IndAddr **ind_addr = ptmp->parent;
243
244 if (ptmp->len != 0) {
245 *ind_addr = get_indicator(ptmp->addr, ptmp->len);
246 } else {
247 *ind_addr = NULL;
248 }
249 return 0;
250}
251
44b1ff31 252static int pre_save_ind_addr(void *opaque)
517ff12c
HP		 253{
254 IndAddrPtrTmp *ptmp = opaque;
255 IndAddr *ind_addr = *(ptmp->parent);
256
257 if (ind_addr != NULL) {
258 ptmp->len = ind_addr->len;
259 ptmp->addr = ind_addr->addr;
260 } else {
261 ptmp->len = 0;
262 ptmp->addr = 0L;
263 }
44b1ff31
DDAG		 264
265 return 0;
517ff12c
HP		 266}
267
268const VMStateDescription vmstate_ind_addr_tmp = {
269 .name = "s390_ind_addr_tmp",
270 .pre_save = pre_save_ind_addr,
271 .post_load = post_load_ind_addr,
272
273 .fields = (VMStateField[]) {
274 VMSTATE_INT32(len, IndAddrPtrTmp),
275 VMSTATE_UINT64(addr, IndAddrPtrTmp),
276 VMSTATE_END_OF_LIST()
277 }
278};
279
280const VMStateDescription vmstate_ind_addr = {
281 .name = "s390_ind_addr_tmp",
282 .fields = (VMStateField[]) {
283 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp),
284 VMSTATE_END_OF_LIST()
285 }
286};
287
df1fe5bb
CH		 288typedef struct CssImage {
289 SubchSet *sch_set[MAX_SSID + 1];
290 ChpInfo chpids[MAX_CHPID + 1];
291} CssImage;
292
457af626
HP		 293static const VMStateDescription vmstate_css_img = {
294 .name = "s390_css_img",
295 .version_id = 1,
296 .minimum_version_id = 1,
297 .fields = (VMStateField[]) {
298 /* Subchannel sets have no relevant state. */
299 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0,
300 vmstate_chp_info, ChpInfo),
301 VMSTATE_END_OF_LIST()
302 }
303
304};
305
03cf077a
CH		 306typedef struct IoAdapter {
307 uint32_t id;
308 uint8_t type;
309 uint8_t isc;
1497c160 310 uint8_t flags;
03cf077a
CH		 311} IoAdapter;
312
df1fe5bb
CH		 313typedef struct ChannelSubSys {
314 QTAILQ_HEAD(, CrwContainer) pending_crws;
c81b4f89 315 bool sei_pending;
df1fe5bb
CH		 316 bool do_crw_mchk;
317 bool crws_lost;
318 uint8_t max_cssid;
319 uint8_t max_ssid;
320 bool chnmon_active;
321 uint64_t chnmon_area;
322 CssImage *css[MAX_CSSID + 1];
323 uint8_t default_cssid;
457af626 324 /* don't migrate, see css_register_io_adapters */
dde522bb 325 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1];
457af626 326 /* don't migrate, see get_indicator and IndAddrPtrTmp */
a28d8391 327 QTAILQ_HEAD(, IndAddr) indicator_addresses;
df1fe5bb
CH		 328} ChannelSubSys;
329
457af626
HP		 330static const VMStateDescription vmstate_css = {
331 .name = "s390_css",
332 .version_id = 1,
333 .minimum_version_id = 1,
334 .fields = (VMStateField[]) {
335 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container,
336 CrwContainer, sibling),
337 VMSTATE_BOOL(sei_pending, ChannelSubSys),
338 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys),
339 VMSTATE_BOOL(crws_lost, ChannelSubSys),
340 /* These were kind of migrated by virtio */
341 VMSTATE_UINT8(max_cssid, ChannelSubSys),
342 VMSTATE_UINT8(max_ssid, ChannelSubSys),
343 VMSTATE_BOOL(chnmon_active, ChannelSubSys),
344 VMSTATE_UINT64(chnmon_area, ChannelSubSys),
345 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1,
346 0, vmstate_css_img, CssImage),
347 VMSTATE_UINT8(default_cssid, ChannelSubSys),
348 VMSTATE_END_OF_LIST()
349 }
350};
351
bc994b74
EH		 352static ChannelSubSys channel_subsys = {
353 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws),
354 .do_crw_mchk = true,
355 .sei_pending = false,
356 .do_crw_mchk = true,
357 .crws_lost = false,
358 .chnmon_active = false,
bc994b74
EH		 359 .indicator_addresses =
360 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses),
361};
df1fe5bb 362
44b1ff31 363static int subch_dev_pre_save(void *opaque)
517ff12c
HP		 364{
365 SubchDev *s = opaque;
366
367 /* Prepare remote_schid for save */
368 s->migrated_schid = s->schid;
44b1ff31
DDAG		 369
370 return 0;
517ff12c
HP		 371}
372
373static int subch_dev_post_load(void *opaque, int version_id)
374{
375
376 SubchDev *s = opaque;
377
378 /* Re-assign the subchannel to remote_schid if necessary */
379 if (s->migrated_schid != s->schid) {
380 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) {
381 /*
382 * Cleanup the slot before moving to s->migrated_schid provided
383 * it still belongs to us, i.e. it was not changed by previous
384 * invocation of this function.
385 */
386 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL);
387 }
388 /* It's OK to re-assign without a prior de-assign. */
389 s->schid = s->migrated_schid;
390 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s);
391 }
392
457af626
HP		 393 if (css_migration_enabled()) {
394 /* No compat voodoo to do ;) */
395 return 0;
396 }
517ff12c
HP		 397 /*
398 * Hack alert. If we don't migrate the channel subsystem status
399 * we still need to find out if the guest enabled mss/mcss-e.
400 * If the subchannel is enabled, it certainly was able to access it,
401 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid
402 * values. This is not watertight, but better than nothing.
403 */
404 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) {
405 if (s->ssid) {
406 channel_subsys.max_ssid = MAX_SSID;
407 }
408 if (s->cssid != channel_subsys.default_cssid) {
409 channel_subsys.max_cssid = MAX_CSSID;
410 }
411 }
412 return 0;
413}
414
e996583e
HP		 415void css_register_vmstate(void)
416{
417 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys);
418}
419
a28d8391
YMZ		 420IndAddr *get_indicator(hwaddr ind_addr, int len)
421{
422 IndAddr *indicator;
423
562f5e0b 424 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) {
a28d8391
YMZ		 425 if (indicator->addr == ind_addr) {
426 indicator->refcnt++;
427 return indicator;
428 }
429 }
430 indicator = g_new0(IndAddr, 1);
431 indicator->addr = ind_addr;
432 indicator->len = len;
433 indicator->refcnt = 1;
562f5e0b 434 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses,
a28d8391
YMZ		 435 indicator, sibling);
436 return indicator;
437}
438
439static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr,
440 bool do_map)
441{
442 S390FLICState *fs = s390_get_flic();
443 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
444
445 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map);
446}
447
448void release_indicator(AdapterInfo *adapter, IndAddr *indicator)
449{
450 assert(indicator->refcnt > 0);
451 indicator->refcnt--;
452 if (indicator->refcnt > 0) {
453 return;
454 }
562f5e0b 455 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling);
a28d8391
YMZ		 456 if (indicator->map) {
457 s390_io_adapter_map(adapter, indicator->map, false);
458 }
459 g_free(indicator);
460}
461
462int map_indicator(AdapterInfo *adapter, IndAddr *indicator)
463{
464 int ret;
465
466 if (indicator->map) {
467 return 0; /* already mapped is not an error */
468 }
469 indicator->map = indicator->addr;
470 ret = s390_io_adapter_map(adapter, indicator->map, true);
471 if ((ret != 0) && (ret != -ENOSYS)) {
472 goto out_err;
473 }
474 return 0;
475
476out_err:
477 indicator->map = 0;
478 return ret;
479}
480
df1fe5bb
CH		 481int css_create_css_image(uint8_t cssid, bool default_image)
482{
483 trace_css_new_image(cssid, default_image ? "(default)" : "");
882b3b97
CH		 484 /* 255 is reserved */
485 if (cssid == 255) {
df1fe5bb
CH		 486 return -EINVAL;
487 }
562f5e0b 488 if (channel_subsys.css[cssid]) {
df1fe5bb
CH		 489 return -EBUSY;
490 }
562f5e0b 491 channel_subsys.css[cssid] = g_malloc0(sizeof(CssImage));
df1fe5bb 492 if (default_image) {
562f5e0b 493 channel_subsys.default_cssid = cssid;
df1fe5bb
CH		 494 }
495 return 0;
496}
497
dde522bb 498uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc)
03cf077a 499{
dde522bb
FL		 500 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC ||
501 !channel_subsys.io_adapters[type][isc]) {
502 return -1;
503 }
504
505 return channel_subsys.io_adapters[type][isc]->id;
506}
507
508/**
509 * css_register_io_adapters: Register I/O adapters per ISC during init
510 *
511 * @swap: an indication if byte swap is needed.
512 * @maskable: an indication if the adapter is subject to the mask operation.
1497c160
FL		 513 * @flags: further characteristics of the adapter.
514 * e.g. suppressible, an indication if the adapter is subject to AIS.
dde522bb
FL		 515 * @errp: location to store error information.
516 */
517void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
1497c160 518 uint8_t flags, Error **errp)
dde522bb
FL		 519{
520 uint32_t id;
521 int ret, isc;
03cf077a 522 IoAdapter *adapter;
03cf077a
CH		 523 S390FLICState *fs = s390_get_flic();
524 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
525
dde522bb
FL		 526 /*
527 * Disallow multiple registrations for the same device type.
528 * Report an error if registering for an already registered type.
529 */
530 if (channel_subsys.io_adapters[type][0]) {
531 error_setg(errp, "Adapters for type %d already registered", type);
532 }
533
534 for (isc = 0; isc <= MAX_ISC; isc++) {
535 id = (type << 3) | isc;
1497c160 536 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags);
dde522bb
FL		 537 if (ret == 0) {
538 adapter = g_new0(IoAdapter, 1);
539 adapter->id = id;
540 adapter->isc = isc;
541 adapter->type = type;
1497c160 542 adapter->flags = flags;
dde522bb
FL		 543 channel_subsys.io_adapters[type][isc] = adapter;
544 } else {
545 error_setg_errno(errp, -ret, "Unexpected error %d when "
546 "registering adapter %d", ret, id);
03cf077a
CH		 547 break;
548 }
03cf077a 549 }
dde522bb
FL		 550
551 /*
552 * No need to free registered adapters in kvm: kvm will clean up
553 * when the machine goes away.
554 */
555 if (ret) {
556 for (isc--; isc >= 0; isc--) {
557 g_free(channel_subsys.io_adapters[type][isc]);
558 channel_subsys.io_adapters[type][isc] = NULL;
559 }
03cf077a 560 }
dde522bb 561
03cf077a
CH		 562}
563
c1755b14
HP		 564static void css_clear_io_interrupt(uint16_t subchannel_id,
565 uint16_t subchannel_nr)
566{
567 Error *err = NULL;
568 static bool no_clear_irq;
569 S390FLICState *fs = s390_get_flic();
570 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
571 int r;
572
573 if (unlikely(no_clear_irq)) {
574 return;
575 }
576 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr);
577 switch (r) {
578 case 0:
579 break;
580 case -ENOSYS:
581 no_clear_irq = true;
582 /*
583 * Ignore unavailability, as the user can't do anything
584 * about it anyway.
585 */
586 break;
587 default:
588 error_setg_errno(&err, -r, "unexpected error condition");
589 error_propagate(&error_abort, err);
590 }
591}
592
593static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid)
df1fe5bb 594{
562f5e0b 595 if (channel_subsys.max_cssid > 0) {
c1755b14 596 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1;
df1fe5bb 597 }
c1755b14
HP		 598 return (ssid << 1) | 1;
599}
600
601uint16_t css_build_subchannel_id(SubchDev *sch)
602{
603 return css_do_build_subchannel_id(sch->cssid, sch->ssid);
df1fe5bb
CH		 604}
605
8ca2b376 606void css_inject_io_interrupt(SubchDev *sch)
df1fe5bb 607{
df1fe5bb
CH		 608 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
609
610 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
611 sch->curr_status.pmcw.intparm, isc, "");
de13d216 612 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 613 sch->schid,
614 sch->curr_status.pmcw.intparm,
91b0a8f3 615 isc << 27);
df1fe5bb
CH		 616}
617
618void css_conditional_io_interrupt(SubchDev *sch)
619{
620 /*
621 * If the subchannel is not currently status pending, make it pending
622 * with alert status.
623 */
624 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) {
df1fe5bb
CH		 625 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
626
627 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
628 sch->curr_status.pmcw.intparm, isc,
629 "(unsolicited)");
630 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
631 sch->curr_status.scsw.ctrl |=
632 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
633 /* Inject an I/O interrupt. */
de13d216 634 s390_io_interrupt(css_build_subchannel_id(sch),
df1fe5bb
CH		 635 sch->schid,
636 sch->curr_status.pmcw.intparm,
91b0a8f3 637 isc << 27);
df1fe5bb
CH		 638 }
639}
640
2283f4d6
FL		 641int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
642{
643 S390FLICState *fs = s390_get_flic();
644 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
645 int r;
646
647 if (env->psw.mask & PSW_MASK_PSTATE) {
648 r = -PGM_PRIVILEGED;
649 goto out;
650 }
651
652 trace_css_do_sic(mode, isc);
653 switch (mode) {
654 case SIC_IRQ_MODE_ALL:
655 case SIC_IRQ_MODE_SINGLE:
656 break;
657 default:
658 r = -PGM_OPERAND;
659 goto out;
660 }
661
662 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0;
663out:
664 return r;
665}
666
25a08b8d 667void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc)
7e749462 668{
25a08b8d
YMZ		 669 S390FLICState *fs = s390_get_flic();
670 S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
7e749462 671 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;
25a08b8d
YMZ		 672 IoAdapter *adapter = channel_subsys.io_adapters[type][isc];
673
674 if (!adapter) {
675 return;
676 }
7e749462
CH		 677
678 trace_css_adapter_interrupt(isc);
25a08b8d
YMZ		 679 if (fs->ais_supported) {
680 if (fsc->inject_airq(fs, type, isc, adapter->flags)) {
681 error_report("Failed to inject airq with AIS supported");
682 exit(1);
683 }
684 } else {
685 s390_io_interrupt(0, 0, 0, io_int_word);
686 }
7e749462
CH		 687}
688
df1fe5bb
CH		 689static void sch_handle_clear_func(SubchDev *sch)
690{
691 PMCW *p = &sch->curr_status.pmcw;
692 SCSW *s = &sch->curr_status.scsw;
693 int path;
694
695 /* Path management: In our simple css, we always choose the only path. */
696 path = 0x80;
697
4c293dc6 698 /* Reset values prior to 'issuing the clear signal'. */
df1fe5bb
CH		 699 p->lpum = 0;
700 p->pom = 0xff;
701 s->flags &= ~SCSW_FLAGS_MASK_PNO;
702
703 /* We always 'attempt to issue the clear signal', and we always succeed. */
df1fe5bb
CH		 704 sch->channel_prog = 0x0;
705 sch->last_cmd_valid = false;
706 s->ctrl &= ~SCSW_ACTL_CLEAR_PEND;
707 s->ctrl |= SCSW_STCTL_STATUS_PEND;
708
709 s->dstat = 0;
710 s->cstat = 0;
711 p->lpum = path;
712
713}
714
715static void sch_handle_halt_func(SubchDev *sch)
716{
717
718 PMCW *p = &sch->curr_status.pmcw;
719 SCSW *s = &sch->curr_status.scsw;
2ed982b6 720 hwaddr curr_ccw = sch->channel_prog;
df1fe5bb
CH		 721 int path;
722
723 /* Path management: In our simple css, we always choose the only path. */
724 path = 0x80;
725
726 /* We always 'attempt to issue the halt signal', and we always succeed. */
df1fe5bb
CH		 727 sch->channel_prog = 0x0;
728 sch->last_cmd_valid = false;
729 s->ctrl &= ~SCSW_ACTL_HALT_PEND;
730 s->ctrl |= SCSW_STCTL_STATUS_PEND;
731
732 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
733 !((s->ctrl & SCSW_ACTL_START_PEND) ||
734 (s->ctrl & SCSW_ACTL_SUSP))) {
735 s->dstat = SCSW_DSTAT_DEVICE_END;
736 }
2ed982b6
CH		 737 if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
738 (s->ctrl & SCSW_ACTL_SUSP)) {
739 s->cpa = curr_ccw + 8;
740 }
df1fe5bb
CH		 741 s->cstat = 0;
742 p->lpum = path;
743
744}
745
746static void copy_sense_id_to_guest(SenseId *dest, SenseId *src)
747{
748 int i;
749
750 dest->reserved = src->reserved;
751 dest->cu_type = cpu_to_be16(src->cu_type);
752 dest->cu_model = src->cu_model;
753 dest->dev_type = cpu_to_be16(src->dev_type);
754 dest->dev_model = src->dev_model;
755 dest->unused = src->unused;
756 for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) {
757 dest->ciw[i].type = src->ciw[i].type;
758 dest->ciw[i].command = src->ciw[i].command;
759 dest->ciw[i].count = cpu_to_be16(src->ciw[i].count);
760 }
761}
762
a327c921 763static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
df1fe5bb 764{
a327c921
CH		 765 CCW0 tmp0;
766 CCW1 tmp1;
df1fe5bb
CH		 767 CCW1 ret;
768
a327c921
CH		 769 if (fmt1) {
770 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1));
771 ret.cmd_code = tmp1.cmd_code;
772 ret.flags = tmp1.flags;
773 ret.count = be16_to_cpu(tmp1.count);
774 ret.cda = be32_to_cpu(tmp1.cda);
775 } else {
776 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0));
9f94f84c
DJS		 777 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) {
778 ret.cmd_code = CCW_CMD_TIC;
779 ret.flags = 0;
780 ret.count = 0;
781 } else {
782 ret.cmd_code = tmp0.cmd_code;
783 ret.flags = tmp0.flags;
784 ret.count = be16_to_cpu(tmp0.count);
fde8206b 785 }
9f94f84c 786 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
a327c921 787 }
df1fe5bb
CH		 788 return ret;
789}
57065a70
HP		 790/**
791 * If out of bounds marks the stream broken. If broken returns -EINVAL,
792 * otherwise the requested length (may be zero)
793 */
794static inline int cds_check_len(CcwDataStream *cds, int len)
795{
796 if (cds->at_byte + len > cds->count) {
797 cds->flags |= CDS_F_STREAM_BROKEN;
798 }
799 return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len;
800}
801
62a2554e
HP		 802static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1)
803{
804 return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24));
805}
806
57065a70
HP		 807static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len,
808 CcwDataStreamOp op)
809{
810 int ret;
811
812 ret = cds_check_len(cds, len);
813 if (ret <= 0) {
814 return ret;
815 }
62a2554e
HP		 816 if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) {
817 return -EINVAL; /* channel program check */
818 }
57065a70
HP		 819 if (op == CDS_OP_A) {
820 goto incr;
821 }
822 ret = address_space_rw(&address_space_memory, cds->cda,
823 MEMTXATTRS_UNSPECIFIED, buff, len, op);
824 if (ret != MEMTX_OK) {
825 cds->flags |= CDS_F_STREAM_BROKEN;
826 return -EINVAL;
827 }
828incr:
829 cds->at_byte += len;
830 cds->cda += len;
831 return 0;
832}
833
834void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb)
835{
836 /*
837 * We don't support MIDA (an optional facility) yet and we
838 * catch this earlier. Just for expressing the precondition.
839 */
840 g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW));
841 cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) |
842 (orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) |
62a2554e 843 (orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) |
57065a70 844 (ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0);
62a2554e 845
57065a70
HP		 846 cds->count = ccw->count;
847 cds->cda_orig = ccw->cda;
848 ccw_dstream_rewind(cds);
849 if (!(cds->flags & CDS_F_IDA)) {
850 cds->op_handler = ccw_dstream_rw_noflags;
851 } else {
852 assert(false);
853 }
854}
df1fe5bb 855
ce350f32
CH		 856static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr,
857 bool suspend_allowed)
df1fe5bb
CH		 858{
859 int ret;
860 bool check_len;
861 int len;
862 CCW1 ccw;
863
864 if (!ccw_addr) {
cc6a9f8d 865 return -EINVAL; /* channel-program check */
df1fe5bb 866 }
198c0d1f
HP		 867 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */
868 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) {
869 return -EINVAL;
870 }
df1fe5bb 871
a327c921
CH		 872 /* Translate everything to format-1 ccws - the information is the same. */
873 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1);
df1fe5bb
CH		 874
875 /* Check for invalid command codes. */
876 if ((ccw.cmd_code & 0x0f) == 0) {
877 return -EINVAL;
878 }
879 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) &&
880 ((ccw.cmd_code & 0xf0) != 0)) {
881 return -EINVAL;
882 }
fa4463e0
CH		 883 if (!sch->ccw_fmt_1 && (ccw.count == 0) &&
884 (ccw.cmd_code != CCW_CMD_TIC)) {
885 return -EINVAL;
886 }
df1fe5bb 887
4e19b57b
CH		 888 /* We don't support MIDA. */
889 if (ccw.flags & CCW_FLAG_MIDA) {
890 return -EINVAL;
891 }
892
df1fe5bb 893 if (ccw.flags & CCW_FLAG_SUSPEND) {
ce350f32 894 return suspend_allowed ? -EINPROGRESS : -EINVAL;
df1fe5bb
CH		 895 }
896
897 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC));
898
e8601dd5
CH		 899 if (!ccw.cda) {
900 if (sch->ccw_no_data_cnt == 255) {
901 return -EINVAL;
902 }
903 sch->ccw_no_data_cnt++;
904 }
905
df1fe5bb 906 /* Look at the command. */
0a22eac5 907 ccw_dstream_init(&sch->cds, &ccw, &(sch->orb));
df1fe5bb
CH		 908 switch (ccw.cmd_code) {
909 case CCW_CMD_NOOP:
910 /* Nothing to do. */
911 ret = 0;
912 break;
913 case CCW_CMD_BASIC_SENSE:
914 if (check_len) {
915 if (ccw.count != sizeof(sch->sense_data)) {
916 ret = -EINVAL;
917 break;
918 }
919 }
920 len = MIN(ccw.count, sizeof(sch->sense_data));
0a22eac5
HP		 921 ccw_dstream_write_buf(&sch->cds, sch->sense_data, len);
922 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds);
df1fe5bb
CH		 923 memset(sch->sense_data, 0, sizeof(sch->sense_data));
924 ret = 0;
925 break;
926 case CCW_CMD_SENSE_ID:
927 {
928 SenseId sense_id;
929
930 copy_sense_id_to_guest(&sense_id, &sch->id);
931 /* Sense ID information is device specific. */
932 if (check_len) {
933 if (ccw.count != sizeof(sense_id)) {
934 ret = -EINVAL;
935 break;
936 }
937 }
938 len = MIN(ccw.count, sizeof(sense_id));
939 /*
940 * Only indicate 0xff in the first sense byte if we actually
941 * have enough place to store at least bytes 0-3.
942 */
943 if (len >= 4) {
944 sense_id.reserved = 0xff;
945 } else {
946 sense_id.reserved = 0;
947 }
0a22eac5
HP		 948 ccw_dstream_write_buf(&sch->cds, &sense_id, len);
949 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds);
df1fe5bb
CH		 950 ret = 0;
951 break;
952 }
953 case CCW_CMD_TIC:
954 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) {
955 ret = -EINVAL;
956 break;
957 }
4add0da6
HP		 958 if (ccw.flags || ccw.count) {
959 /* We have already sanitized these if converted from fmt 0. */
df1fe5bb
CH		 960 ret = -EINVAL;
961 break;
962 }
963 sch->channel_prog = ccw.cda;
964 ret = -EAGAIN;
965 break;
966 default:
967 if (sch->ccw_cb) {
968 /* Handle device specific commands. */
969 ret = sch->ccw_cb(sch, ccw);
970 } else {
8d034a6f 971 ret = -ENOSYS;
df1fe5bb
CH		 972 }
973 break;
974 }
975 sch->last_cmd = ccw;
976 sch->last_cmd_valid = true;
977 if (ret == 0) {
978 if (ccw.flags & CCW_FLAG_CC) {
979 sch->channel_prog += 8;
980 ret = -EAGAIN;
981 }
982 }
983
984 return ret;
985}
986
b5f5a3af 987static void sch_handle_start_func_virtual(SubchDev *sch)
df1fe5bb
CH		 988{
989
990 PMCW *p = &sch->curr_status.pmcw;
991 SCSW *s = &sch->curr_status.scsw;
df1fe5bb
CH		 992 int path;
993 int ret;
ce350f32 994 bool suspend_allowed;
df1fe5bb
CH		 995
996 /* Path management: In our simple css, we always choose the only path. */
997 path = 0x80;
998
999 if (!(s->ctrl & SCSW_ACTL_SUSP)) {
727a0424 1000 /* Start Function triggered via ssch, i.e. we have an ORB */
b5f5a3af 1001 ORB *orb = &sch->orb;
6b7741c2
CH		 1002 s->cstat = 0;
1003 s->dstat = 0;
df1fe5bb
CH		 1004 /* Look at the orb and try to execute the channel program. */
1005 p->intparm = orb->intparm;
1006 if (!(orb->lpm & path)) {
1007 /* Generate a deferred cc 3 condition. */
1008 s->flags |= SCSW_FLAGS_MASK_CC;
1009 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1010 s->ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND);
1011 return;
1012 }
a327c921 1013 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT);
485dd690 1014 s->flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0;
e8601dd5 1015 sch->ccw_no_data_cnt = 0;
ce350f32 1016 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND);
df1fe5bb 1017 } else {
b5f5a3af 1018 /* Start Function resumed via rsch */
df1fe5bb 1019 s->ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND);
ce350f32
CH		 1020 /* The channel program had been suspended before. */
1021 suspend_allowed = true;
df1fe5bb
CH		 1022 }
1023 sch->last_cmd_valid = false;
1024 do {
ce350f32 1025 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed);
df1fe5bb
CH		 1026 switch (ret) {
1027 case -EAGAIN:
1028 /* ccw chain, continue processing */
1029 break;
1030 case 0:
1031 /* success */
1032 s->ctrl &= ~SCSW_ACTL_START_PEND;
1033 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1034 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
1035 SCSW_STCTL_STATUS_PEND;
1036 s->dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END;
2ed982b6 1037 s->cpa = sch->channel_prog + 8;
df1fe5bb 1038 break;
2dc95b4c
JL		 1039 case -EIO:
1040 /* I/O errors, status depends on specific devices */
1041 break;
8d034a6f 1042 case -ENOSYS:
df1fe5bb
CH		 1043 /* unsupported command, generate unit check (command reject) */
1044 s->ctrl &= ~SCSW_ACTL_START_PEND;
1045 s->dstat = SCSW_DSTAT_UNIT_CHECK;
1046 /* Set sense bit 0 in ecw0. */
1047 sch->sense_data[0] = 0x80;
1048 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1049 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
1050 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
2ed982b6 1051 s->cpa = sch->channel_prog + 8;
df1fe5bb 1052 break;
8d034a6f 1053 case -EINPROGRESS:
df1fe5bb
CH		 1054 /* channel program has been suspended */
1055 s->ctrl &= ~SCSW_ACTL_START_PEND;
1056 s->ctrl |= SCSW_ACTL_SUSP;
1057 break;
1058 default:
1059 /* error, generate channel program check */
1060 s->ctrl &= ~SCSW_ACTL_START_PEND;
1061 s->cstat = SCSW_CSTAT_PROG_CHECK;
1062 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1063 s->ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY |
1064 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
2ed982b6 1065 s->cpa = sch->channel_prog + 8;
df1fe5bb
CH		 1066 break;
1067 }
1068 } while (ret == -EAGAIN);
1069
1070}
1071
b5f5a3af 1072static int sch_handle_start_func_passthrough(SubchDev *sch)
bab482d7
XFR		 1073{
1074
1075 PMCW *p = &sch->curr_status.pmcw;
1076 SCSW *s = &sch->curr_status.scsw;
1077 int ret;
1078
b5f5a3af 1079 ORB *orb = &sch->orb;
bab482d7
XFR		 1080 if (!(s->ctrl & SCSW_ACTL_SUSP)) {
1081 assert(orb != NULL);
1082 p->intparm = orb->intparm;
1083 }
1084
1085 /*
1086 * Only support prefetch enable mode.
1087 * Only support 64bit addressing idal.
1088 */
1089 if (!(orb->ctrl0 & ORB_CTRL0_MASK_PFCH) ||
1090 !(orb->ctrl0 & ORB_CTRL0_MASK_C64)) {
1091 return -EINVAL;
1092 }
1093
1094 ret = s390_ccw_cmd_request(orb, s, sch->driver_data);
1095 switch (ret) {
1096 /* Currently we don't update control block and just return the cc code. */
1097 case 0:
1098 break;
1099 case -EBUSY:
1100 break;
1101 case -ENODEV:
1102 break;
1103 case -EACCES:
1104 /* Let's reflect an inaccessible host device by cc 3. */
1105 ret = -ENODEV;
1106 break;
1107 default:
1108 /*
1109 * All other return codes will trigger a program check,
1110 * or set cc to 1.
1111 */
1112 break;
1113 };
1114
1115 return ret;
1116}
1117
df1fe5bb
CH		 1118/*
1119 * On real machines, this would run asynchronously to the main vcpus.
1120 * We might want to make some parts of the ssch handling (interpreting
1121 * read/writes) asynchronous later on if we start supporting more than
1122 * our current very simple devices.
1123 */
b5f5a3af 1124int do_subchannel_work_virtual(SubchDev *sch)
df1fe5bb
CH		 1125{
1126
1127 SCSW *s = &sch->curr_status.scsw;
1128
1129 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) {
1130 sch_handle_clear_func(sch);
1131 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) {
1132 sch_handle_halt_func(sch);
1133 } else if (s->ctrl & SCSW_FCTL_START_FUNC) {
727a0424 1134 /* Triggered by both ssch and rsch. */
b5f5a3af 1135 sch_handle_start_func_virtual(sch);
df1fe5bb
CH		 1136 } else {
1137 /* Cannot happen. */
bab482d7 1138 return 0;
df1fe5bb
CH		 1139 }
1140 css_inject_io_interrupt(sch);
bab482d7
XFR		 1141 return 0;
1142}
1143
b5f5a3af 1144int do_subchannel_work_passthrough(SubchDev *sch)
bab482d7
XFR		 1145{
1146 int ret;
1147 SCSW *s = &sch->curr_status.scsw;
1148
1149 if (s->ctrl & SCSW_FCTL_CLEAR_FUNC) {
1150 /* TODO: Clear handling */
1151 sch_handle_clear_func(sch);
1152 ret = 0;
1153 } else if (s->ctrl & SCSW_FCTL_HALT_FUNC) {
1154 /* TODO: Halt handling */
1155 sch_handle_halt_func(sch);
1156 ret = 0;
1157 } else if (s->ctrl & SCSW_FCTL_START_FUNC) {
b5f5a3af 1158 ret = sch_handle_start_func_passthrough(sch);
bab482d7
XFR		 1159 } else {
1160 /* Cannot happen. */
1161 return -ENODEV;
1162 }
1163
1164 return ret;
1165}
1166
b5f5a3af 1167static int do_subchannel_work(SubchDev *sch)
bab482d7
XFR		 1168{
1169 if (sch->do_subchannel_work) {
b5f5a3af 1170 return sch->do_subchannel_work(sch);
bab482d7
XFR		 1171 } else {
1172 return -EINVAL;
1173 }
df1fe5bb
CH		 1174}
1175
1176static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src)
1177{
1178 int i;
1179
1180 dest->intparm = cpu_to_be32(src->intparm);
1181 dest->flags = cpu_to_be16(src->flags);
1182 dest->devno = cpu_to_be16(src->devno);
1183 dest->lpm = src->lpm;
1184 dest->pnom = src->pnom;
1185 dest->lpum = src->lpum;
1186 dest->pim = src->pim;
1187 dest->mbi = cpu_to_be16(src->mbi);
1188 dest->pom = src->pom;
1189 dest->pam = src->pam;
1190 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1191 dest->chpid[i] = src->chpid[i];
1192 }
1193 dest->chars = cpu_to_be32(src->chars);
1194}
1195
8ca2b376 1196void copy_scsw_to_guest(SCSW *dest, const SCSW *src)
df1fe5bb
CH		 1197{
1198 dest->flags = cpu_to_be16(src->flags);
1199 dest->ctrl = cpu_to_be16(src->ctrl);
1200 dest->cpa = cpu_to_be32(src->cpa);
1201 dest->dstat = src->dstat;
1202 dest->cstat = src->cstat;
1203 dest->count = cpu_to_be16(src->count);
1204}
1205
1206static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src)
1207{
1208 int i;
1209
1210 copy_pmcw_to_guest(&dest->pmcw, &src->pmcw);
1211 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1212 dest->mba = cpu_to_be64(src->mba);
1213 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1214 dest->mda[i] = src->mda[i];
1215 }
1216}
1217
1218int css_do_stsch(SubchDev *sch, SCHIB *schib)
1219{
1220 /* Use current status. */
1221 copy_schib_to_guest(schib, &sch->curr_status);
1222 return 0;
1223}
1224
1225static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src)
1226{
1227 int i;
1228
1229 dest->intparm = be32_to_cpu(src->intparm);
1230 dest->flags = be16_to_cpu(src->flags);
1231 dest->devno = be16_to_cpu(src->devno);
1232 dest->lpm = src->lpm;
1233 dest->pnom = src->pnom;
1234 dest->lpum = src->lpum;
1235 dest->pim = src->pim;
1236 dest->mbi = be16_to_cpu(src->mbi);
1237 dest->pom = src->pom;
1238 dest->pam = src->pam;
1239 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) {
1240 dest->chpid[i] = src->chpid[i];
1241 }
1242 dest->chars = be32_to_cpu(src->chars);
1243}
1244
1245static void copy_scsw_from_guest(SCSW *dest, const SCSW *src)
1246{
1247 dest->flags = be16_to_cpu(src->flags);
1248 dest->ctrl = be16_to_cpu(src->ctrl);
1249 dest->cpa = be32_to_cpu(src->cpa);
1250 dest->dstat = src->dstat;
1251 dest->cstat = src->cstat;
1252 dest->count = be16_to_cpu(src->count);
1253}
1254
1255static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src)
1256{
1257 int i;
1258
1259 copy_pmcw_from_guest(&dest->pmcw, &src->pmcw);
1260 copy_scsw_from_guest(&dest->scsw, &src->scsw);
1261 dest->mba = be64_to_cpu(src->mba);
1262 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) {
1263 dest->mda[i] = src->mda[i];
1264 }
1265}
1266
bffd09cd 1267int css_do_msch(SubchDev *sch, const SCHIB *orig_schib)
df1fe5bb
CH		 1268{
1269 SCSW *s = &sch->curr_status.scsw;
1270 PMCW *p = &sch->curr_status.pmcw;
62ac4a52 1271 uint16_t oldflags;
df1fe5bb
CH		 1272 int ret;
1273 SCHIB schib;
1274
1275 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_DNV)) {
1276 ret = 0;
1277 goto out;
1278 }
1279
1280 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
1281 ret = -EINPROGRESS;
1282 goto out;
1283 }
1284
1285 if (s->ctrl &
1286 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) {
1287 ret = -EBUSY;
1288 goto out;
1289 }
1290
1291 copy_schib_from_guest(&schib, orig_schib);
1292 /* Only update the program-modifiable fields. */
1293 p->intparm = schib.pmcw.intparm;
62ac4a52 1294 oldflags = p->flags;
df1fe5bb
CH		 1295 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1296 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1297 PMCW_FLAGS_MASK_MP);
1298 p->flags |= schib.pmcw.flags &
1299 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
1300 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
1301 PMCW_FLAGS_MASK_MP);
1302 p->lpm = schib.pmcw.lpm;
1303 p->mbi = schib.pmcw.mbi;
1304 p->pom = schib.pmcw.pom;
1305 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1306 p->chars |= schib.pmcw.chars &
1307 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE);
1308 sch->curr_status.mba = schib.mba;
1309
62ac4a52
TH		 1310 /* Has the channel been disabled? */
1311 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0
1312 && (p->flags & PMCW_FLAGS_MASK_ENA) == 0) {
1313 sch->disable_cb(sch);
1314 }
1315
df1fe5bb
CH		 1316 ret = 0;
1317
1318out:
1319 return ret;
1320}
1321
1322int css_do_xsch(SubchDev *sch)
1323{
1324 SCSW *s = &sch->curr_status.scsw;
1325 PMCW *p = &sch->curr_status.pmcw;
1326 int ret;
1327
c679e74d 1328 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1329 ret = -ENODEV;
1330 goto out;
1331 }
1332
6c864622
HP		 1333 if (s->ctrl & SCSW_CTRL_MASK_STCTL) {
1334 ret = -EINPROGRESS;
1335 goto out;
1336 }
1337
df1fe5bb
CH		 1338 if (!(s->ctrl & SCSW_CTRL_MASK_FCTL) ||
1339 ((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1340 (!(s->ctrl &
1341 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) ||
1342 (s->ctrl & SCSW_ACTL_SUBCH_ACTIVE)) {
df1fe5bb
CH		 1343 ret = -EBUSY;
1344 goto out;
1345 }
1346
1347 /* Cancel the current operation. */
1348 s->ctrl &= ~(SCSW_FCTL_START_FUNC |
1349 SCSW_ACTL_RESUME_PEND |
1350 SCSW_ACTL_START_PEND |
1351 SCSW_ACTL_SUSP);
1352 sch->channel_prog = 0x0;
1353 sch->last_cmd_valid = false;
df1fe5bb
CH		 1354 s->dstat = 0;
1355 s->cstat = 0;
1356 ret = 0;
1357
1358out:
1359 return ret;
1360}
1361
1362int css_do_csch(SubchDev *sch)
1363{
1364 SCSW *s = &sch->curr_status.scsw;
1365 PMCW *p = &sch->curr_status.pmcw;
1366 int ret;
1367
c679e74d 1368 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1369 ret = -ENODEV;
1370 goto out;
1371 }
1372
1373 /* Trigger the clear function. */
1374 s->ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL);
4c6bf79a 1375 s->ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND;
df1fe5bb 1376
b5f5a3af 1377 do_subchannel_work(sch);
df1fe5bb
CH		 1378 ret = 0;
1379
1380out:
1381 return ret;
1382}
1383
1384int css_do_hsch(SubchDev *sch)
1385{
1386 SCSW *s = &sch->curr_status.scsw;
1387 PMCW *p = &sch->curr_status.pmcw;
1388 int ret;
1389
c679e74d 1390 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1391 ret = -ENODEV;
1392 goto out;
1393 }
1394
1395 if (((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) ||
1396 (s->ctrl & (SCSW_STCTL_PRIMARY |
1397 SCSW_STCTL_SECONDARY |
1398 SCSW_STCTL_ALERT))) {
1399 ret = -EINPROGRESS;
1400 goto out;
1401 }
1402
1403 if (s->ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) {
1404 ret = -EBUSY;
1405 goto out;
1406 }
1407
1408 /* Trigger the halt function. */
1409 s->ctrl |= SCSW_FCTL_HALT_FUNC;
1410 s->ctrl &= ~SCSW_FCTL_START_FUNC;
1411 if (((s->ctrl & SCSW_CTRL_MASK_ACTL) ==
1412 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) &&
1413 ((s->ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_INTERMEDIATE)) {
1414 s->ctrl &= ~SCSW_STCTL_STATUS_PEND;
1415 }
1416 s->ctrl |= SCSW_ACTL_HALT_PEND;
1417
b5f5a3af 1418 do_subchannel_work(sch);
df1fe5bb
CH		 1419 ret = 0;
1420
1421out:
1422 return ret;
1423}
1424
1425static void css_update_chnmon(SubchDev *sch)
1426{
1427 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) {
1428 /* Not active. */
1429 return;
1430 }
1431 /* The counter is conveniently located at the beginning of the struct. */
1432 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) {
1433 /* Format 1, per-subchannel area. */
1434 uint32_t count;
1435
42874d3a
PM		 1436 count = address_space_ldl(&address_space_memory,
1437 sch->curr_status.mba,
1438 MEMTXATTRS_UNSPECIFIED,
1439 NULL);
df1fe5bb 1440 count++;
42874d3a
PM		 1441 address_space_stl(&address_space_memory, sch->curr_status.mba, count,
1442 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1443 } else {
1444 /* Format 0, global area. */
1445 uint32_t offset;
1446 uint16_t count;
1447
1448 offset = sch->curr_status.pmcw.mbi << 5;
42874d3a 1449 count = address_space_lduw(&address_space_memory,
562f5e0b 1450 channel_subsys.chnmon_area + offset,
42874d3a
PM		 1451 MEMTXATTRS_UNSPECIFIED,
1452 NULL);
df1fe5bb 1453 count++;
42874d3a 1454 address_space_stw(&address_space_memory,
562f5e0b 1455 channel_subsys.chnmon_area + offset, count,
42874d3a 1456 MEMTXATTRS_UNSPECIFIED, NULL);
df1fe5bb
CH		 1457 }
1458}
1459
1460int css_do_ssch(SubchDev *sch, ORB *orb)
1461{
1462 SCSW *s = &sch->curr_status.scsw;
1463 PMCW *p = &sch->curr_status.pmcw;
1464 int ret;
1465
c679e74d 1466 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1467 ret = -ENODEV;
1468 goto out;
1469 }
1470
1471 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
1472 ret = -EINPROGRESS;
1473 goto out;
1474 }
1475
1476 if (s->ctrl & (SCSW_FCTL_START_FUNC |
1477 SCSW_FCTL_HALT_FUNC |
1478 SCSW_FCTL_CLEAR_FUNC)) {
1479 ret = -EBUSY;
1480 goto out;
1481 }
1482
1483 /* If monitoring is active, update counter. */
562f5e0b 1484 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1485 css_update_chnmon(sch);
1486 }
ff443fe6 1487 sch->orb = *orb;
df1fe5bb
CH		 1488 sch->channel_prog = orb->cpa;
1489 /* Trigger the start function. */
1490 s->ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND);
1491 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1492
b5f5a3af 1493 ret = do_subchannel_work(sch);
df1fe5bb
CH		 1494
1495out:
1496 return ret;
1497}
1498
b7b6348a
TH		 1499static void copy_irb_to_guest(IRB *dest, const IRB *src, PMCW *pmcw,
1500 int *irb_len)
df1fe5bb
CH		 1501{
1502 int i;
f068d320
CH		 1503 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL;
1504 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1505
1506 copy_scsw_to_guest(&dest->scsw, &src->scsw);
1507
1508 for (i = 0; i < ARRAY_SIZE(dest->esw); i++) {
1509 dest->esw[i] = cpu_to_be32(src->esw[i]);
1510 }
1511 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) {
1512 dest->ecw[i] = cpu_to_be32(src->ecw[i]);
1513 }
b7b6348a
TH		 1514 *irb_len = sizeof(*dest) - sizeof(dest->emw);
1515
f068d320
CH		 1516 /* extended measurements enabled? */
1517 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) ||
1518 !(pmcw->flags & PMCW_FLAGS_MASK_TF) ||
1519 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) {
1520 return;
1521 }
1522 /* extended measurements pending? */
1523 if (!(stctl & SCSW_STCTL_STATUS_PEND)) {
1524 return;
1525 }
1526 if ((stctl & SCSW_STCTL_PRIMARY) ||
1527 (stctl == SCSW_STCTL_SECONDARY) ||
1528 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) {
1529 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) {
1530 dest->emw[i] = cpu_to_be32(src->emw[i]);
1531 }
df1fe5bb 1532 }
b7b6348a 1533 *irb_len = sizeof(*dest);
df1fe5bb
CH		 1534}
1535
b7b6348a 1536int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len)
df1fe5bb
CH		 1537{
1538 SCSW *s = &sch->curr_status.scsw;
1539 PMCW *p = &sch->curr_status.pmcw;
1540 uint16_t stctl;
df1fe5bb 1541 IRB irb;
df1fe5bb 1542
c679e74d 1543 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
b7b6348a 1544 return 3;
df1fe5bb
CH		 1545 }
1546
1547 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
df1fe5bb
CH		 1548
1549 /* Prepare the irb for the guest. */
1550 memset(&irb, 0, sizeof(IRB));
1551
1552 /* Copy scsw from current status. */
1553 memcpy(&irb.scsw, s, sizeof(SCSW));
1554 if (stctl & SCSW_STCTL_STATUS_PEND) {
1555 if (s->cstat & (SCSW_CSTAT_DATA_CHECK |
1556 SCSW_CSTAT_CHN_CTRL_CHK |
1557 SCSW_CSTAT_INTF_CTRL_CHK)) {
1558 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF;
1559 irb.esw[0] = 0x04804000;
1560 } else {
1561 irb.esw[0] = 0x00800000;
1562 }
1563 /* If a unit check is pending, copy sense data. */
1564 if ((s->dstat & SCSW_DSTAT_UNIT_CHECK) &&
1565 (p->chars & PMCW_CHARS_MASK_CSENSE)) {
b498484e
CH		 1566 int i;
1567
df1fe5bb 1568 irb.scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL;
b498484e 1569 /* Attention: sense_data is already BE! */
df1fe5bb 1570 memcpy(irb.ecw, sch->sense_data, sizeof(sch->sense_data));
b498484e
CH		 1571 for (i = 0; i < ARRAY_SIZE(irb.ecw); i++) {
1572 irb.ecw[i] = be32_to_cpu(irb.ecw[i]);
1573 }
8312976e 1574 irb.esw[1] = 0x01000000 | (sizeof(sch->sense_data) << 8);
df1fe5bb
CH		 1575 }
1576 }
1577 /* Store the irb to the guest. */
b7b6348a
TH		 1578 copy_irb_to_guest(target_irb, &irb, p, irb_len);
1579
1580 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0);
1581}
1582
1583void css_do_tsch_update_subch(SubchDev *sch)
1584{
1585 SCSW *s = &sch->curr_status.scsw;
1586 PMCW *p = &sch->curr_status.pmcw;
1587 uint16_t stctl;
1588 uint16_t fctl;
1589 uint16_t actl;
1590
1591 stctl = s->ctrl & SCSW_CTRL_MASK_STCTL;
1592 fctl = s->ctrl & SCSW_CTRL_MASK_FCTL;
1593 actl = s->ctrl & SCSW_CTRL_MASK_ACTL;
df1fe5bb
CH		 1594
1595 /* Clear conditions on subchannel, if applicable. */
1596 if (stctl & SCSW_STCTL_STATUS_PEND) {
1597 s->ctrl &= ~SCSW_CTRL_MASK_STCTL;
1598 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) ||
1599 ((fctl & SCSW_FCTL_HALT_FUNC) &&
1600 (actl & SCSW_ACTL_SUSP))) {
1601 s->ctrl &= ~SCSW_CTRL_MASK_FCTL;
1602 }
1603 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) {
1604 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1605 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1606 SCSW_ACTL_START_PEND |
1607 SCSW_ACTL_HALT_PEND |
1608 SCSW_ACTL_CLEAR_PEND |
1609 SCSW_ACTL_SUSP);
1610 } else {
1611 if ((actl & SCSW_ACTL_SUSP) &&
1612 (fctl & SCSW_FCTL_START_FUNC)) {
1613 s->flags &= ~SCSW_FLAGS_MASK_PNO;
1614 if (fctl & SCSW_FCTL_HALT_FUNC) {
1615 s->ctrl &= ~(SCSW_ACTL_RESUME_PEND |
1616 SCSW_ACTL_START_PEND |
1617 SCSW_ACTL_HALT_PEND |
1618 SCSW_ACTL_CLEAR_PEND |
1619 SCSW_ACTL_SUSP);
1620 } else {
1621 s->ctrl &= ~SCSW_ACTL_RESUME_PEND;
1622 }
1623 }
1624 }
1625 /* Clear pending sense data. */
1626 if (p->chars & PMCW_CHARS_MASK_CSENSE) {
1627 memset(sch->sense_data, 0 , sizeof(sch->sense_data));
1628 }
1629 }
df1fe5bb
CH		 1630}
1631
1632static void copy_crw_to_guest(CRW *dest, const CRW *src)
1633{
1634 dest->flags = cpu_to_be16(src->flags);
1635 dest->rsid = cpu_to_be16(src->rsid);
1636}
1637
1638int css_do_stcrw(CRW *crw)
1639{
1640 CrwContainer *crw_cont;
1641 int ret;
1642
562f5e0b 1643 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws);
df1fe5bb 1644 if (crw_cont) {
562f5e0b 1645 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 1646 copy_crw_to_guest(crw, &crw_cont->crw);
1647 g_free(crw_cont);
1648 ret = 0;
1649 } else {
1650 /* List was empty, turn crw machine checks on again. */
1651 memset(crw, 0, sizeof(*crw));
562f5e0b 1652 channel_subsys.do_crw_mchk = true;
df1fe5bb
CH		 1653 ret = 1;
1654 }
1655
1656 return ret;
1657}
1658
7f74f0aa
TH		 1659static void copy_crw_from_guest(CRW *dest, const CRW *src)
1660{
1661 dest->flags = be16_to_cpu(src->flags);
1662 dest->rsid = be16_to_cpu(src->rsid);
1663}
1664
1665void css_undo_stcrw(CRW *crw)
1666{
1667 CrwContainer *crw_cont;
1668
1669 crw_cont = g_try_malloc0(sizeof(CrwContainer));
1670 if (!crw_cont) {
562f5e0b 1671 channel_subsys.crws_lost = true;
7f74f0aa
TH		 1672 return;
1673 }
1674 copy_crw_from_guest(&crw_cont->crw, crw);
1675
562f5e0b 1676 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling);
7f74f0aa
TH		 1677}
1678
50c8d9bf 1679int css_do_tpi(IOIntCode *int_code, int lowcore)
df1fe5bb
CH		 1680{
1681 /* No pending interrupts for !KVM. */
1682 return 0;
1683 }
1684
1685int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
1686 int rfmt, void *buf)
1687{
1688 int i, desc_size;
1689 uint32_t words[8];
1690 uint32_t chpid_type_word;
1691 CssImage *css;
1692
1693 if (!m && !cssid) {
562f5e0b 1694 css = channel_subsys.css[channel_subsys.default_cssid];
df1fe5bb 1695 } else {
562f5e0b 1696 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1697 }
1698 if (!css) {
1699 return 0;
1700 }
1701 desc_size = 0;
1702 for (i = f_chpid; i <= l_chpid; i++) {
1703 if (css->chpids[i].in_use) {
1704 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i;
1705 if (rfmt == 0) {
1706 words[0] = cpu_to_be32(chpid_type_word);
1707 words[1] = 0;
1708 memcpy(buf + desc_size, words, 8);
1709 desc_size += 8;
1710 } else if (rfmt == 1) {
1711 words[0] = cpu_to_be32(chpid_type_word);
1712 words[1] = 0;
1713 words[2] = 0;
1714 words[3] = 0;
1715 words[4] = 0;
1716 words[5] = 0;
1717 words[6] = 0;
1718 words[7] = 0;
1719 memcpy(buf + desc_size, words, 32);
1720 desc_size += 32;
1721 }
1722 }
1723 }
1724 return desc_size;
1725}
1726
1727void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
1728{
1729 /* dct is currently ignored (not really meaningful for our devices) */
1730 /* TODO: Don't ignore mbk. */
562f5e0b 1731 if (update && !channel_subsys.chnmon_active) {
df1fe5bb 1732 /* Enable measuring. */
562f5e0b
EH		 1733 channel_subsys.chnmon_area = mbo;
1734 channel_subsys.chnmon_active = true;
df1fe5bb 1735 }
562f5e0b 1736 if (!update && channel_subsys.chnmon_active) {
df1fe5bb 1737 /* Disable measuring. */
562f5e0b
EH		 1738 channel_subsys.chnmon_area = 0;
1739 channel_subsys.chnmon_active = false;
df1fe5bb
CH		 1740 }
1741}
1742
1743int css_do_rsch(SubchDev *sch)
1744{
1745 SCSW *s = &sch->curr_status.scsw;
1746 PMCW *p = &sch->curr_status.pmcw;
1747 int ret;
1748
c679e74d 1749 if (~(p->flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) {
df1fe5bb
CH		 1750 ret = -ENODEV;
1751 goto out;
1752 }
1753
1754 if (s->ctrl & SCSW_STCTL_STATUS_PEND) {
1755 ret = -EINPROGRESS;
1756 goto out;
1757 }
1758
1759 if (((s->ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) ||
1760 (s->ctrl & SCSW_ACTL_RESUME_PEND) ||
1761 (!(s->ctrl & SCSW_ACTL_SUSP))) {
1762 ret = -EINVAL;
1763 goto out;
1764 }
1765
1766 /* If monitoring is active, update counter. */
562f5e0b 1767 if (channel_subsys.chnmon_active) {
df1fe5bb
CH		 1768 css_update_chnmon(sch);
1769 }
1770
1771 s->ctrl |= SCSW_ACTL_RESUME_PEND;
b5f5a3af 1772 do_subchannel_work(sch);
df1fe5bb
CH		 1773 ret = 0;
1774
1775out:
1776 return ret;
1777}
1778
1779int css_do_rchp(uint8_t cssid, uint8_t chpid)
1780{
1781 uint8_t real_cssid;
1782
562f5e0b 1783 if (cssid > channel_subsys.max_cssid) {
df1fe5bb
CH		 1784 return -EINVAL;
1785 }
562f5e0b
EH		 1786 if (channel_subsys.max_cssid == 0) {
1787 real_cssid = channel_subsys.default_cssid;
df1fe5bb
CH		 1788 } else {
1789 real_cssid = cssid;
1790 }
562f5e0b 1791 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1792 return -EINVAL;
1793 }
1794
562f5e0b 1795 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) {
df1fe5bb
CH		 1796 return -ENODEV;
1797 }
1798
562f5e0b 1799 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) {
df1fe5bb
CH		 1800 fprintf(stderr,
1801 "rchp unsupported for non-virtual chpid %x.%02x!\n",
1802 real_cssid, chpid);
1803 return -ENODEV;
1804 }
1805
1806 /* We don't really use a channel path, so we're done here. */
5c8d6f00 1807 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1,
562f5e0b
EH		 1808 channel_subsys.max_cssid > 0 ? 1 : 0, chpid);
1809 if (channel_subsys.max_cssid > 0) {
5c8d6f00 1810 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8);
df1fe5bb
CH		 1811 }
1812 return 0;
1813}
1814
38dd7cc7 1815bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid)
df1fe5bb
CH		 1816{
1817 SubchSet *set;
38dd7cc7 1818 uint8_t real_cssid;
df1fe5bb 1819
562f5e0b 1820 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
882b3b97 1821 if (ssid > MAX_SSID ||
562f5e0b
EH		 1822 !channel_subsys.css[real_cssid] ||
1823 !channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1824 return true;
1825 }
562f5e0b 1826 set = channel_subsys.css[real_cssid]->sch_set[ssid];
df1fe5bb
CH		 1827 return schid > find_last_bit(set->schids_used,
1828 (MAX_SCHID + 1) / sizeof(unsigned long));
1829}
1830
6c15e9bf
JL		 1831unsigned int css_find_free_chpid(uint8_t cssid)
1832{
1833 CssImage *css = channel_subsys.css[cssid];
1834 unsigned int chpid;
1835
1836 if (!css) {
1837 return MAX_CHPID + 1;
1838 }
1839
1840 for (chpid = 0; chpid <= MAX_CHPID; chpid++) {
1841 /* skip reserved chpid */
1842 if (chpid == VIRTIO_CCW_CHPID) {
1843 continue;
1844 }
1845 if (!css->chpids[chpid].in_use) {
1846 return chpid;
1847 }
1848 }
1849 return MAX_CHPID + 1;
1850}
1851
8f3cf012
XFR		 1852static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type,
1853 bool is_virt)
df1fe5bb
CH		 1854{
1855 CssImage *css;
1856
1857 trace_css_chpid_add(cssid, chpid, type);
562f5e0b 1858 css = channel_subsys.css[cssid];
df1fe5bb
CH		 1859 if (!css) {
1860 return -EINVAL;
1861 }
1862 if (css->chpids[chpid].in_use) {
1863 return -EEXIST;
1864 }
1865 css->chpids[chpid].in_use = 1;
1866 css->chpids[chpid].type = type;
8f3cf012 1867 css->chpids[chpid].is_virtual = is_virt;
df1fe5bb
CH		 1868
1869 css_generate_chp_crws(cssid, chpid);
1870
1871 return 0;
1872}
1873
1874void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type)
1875{
1876 PMCW *p = &sch->curr_status.pmcw;
1877 SCSW *s = &sch->curr_status.scsw;
1878 int i;
562f5e0b 1879 CssImage *css = channel_subsys.css[sch->cssid];
df1fe5bb
CH		 1880
1881 assert(css != NULL);
1882 memset(p, 0, sizeof(PMCW));
1883 p->flags |= PMCW_FLAGS_MASK_DNV;
1884 p->devno = sch->devno;
1885 /* single path */
1886 p->pim = 0x80;
1887 p->pom = 0xff;
1888 p->pam = 0x80;
1889 p->chpid[0] = chpid;
1890 if (!css->chpids[chpid].in_use) {
8f3cf012 1891 css_add_chpid(sch->cssid, chpid, type, true);
df1fe5bb
CH		 1892 }
1893
1894 memset(s, 0, sizeof(SCSW));
1895 sch->curr_status.mba = 0;
1896 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) {
1897 sch->curr_status.mda[i] = 0;
1898 }
1899}
1900
1901SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid)
1902{
1903 uint8_t real_cssid;
1904
562f5e0b 1905 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid;
df1fe5bb 1906
562f5e0b 1907 if (!channel_subsys.css[real_cssid]) {
df1fe5bb
CH		 1908 return NULL;
1909 }
1910
562f5e0b 1911 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) {
df1fe5bb
CH		 1912 return NULL;
1913 }
1914
562f5e0b 1915 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid];
df1fe5bb
CH		 1916}
1917
cf249935
SS		 1918/**
1919 * Return free device number in subchannel set.
1920 *
1921 * Return index of the first free device number in the subchannel set
1922 * identified by @p cssid and @p ssid, beginning the search at @p
1923 * start and wrapping around at MAX_DEVNO. Return a value exceeding
1924 * MAX_SCHID if there are no free device numbers in the subchannel
1925 * set.
1926 */
1927static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid,
1928 uint16_t start)
1929{
1930 uint32_t round;
1931
1932 for (round = 0; round <= MAX_DEVNO; round++) {
1933 uint16_t devno = (start + round) % MAX_DEVNO;
1934
1935 if (!css_devno_used(cssid, ssid, devno)) {
1936 return devno;
1937 }
1938 }
1939 return MAX_DEVNO + 1;
1940}
1941
1942/**
1943 * Return first free subchannel (id) in subchannel set.
1944 *
1945 * Return index of the first free subchannel in the subchannel set
1946 * identified by @p cssid and @p ssid, if there is any. Return a value
1947 * exceeding MAX_SCHID if there are no free subchannels in the
1948 * subchannel set.
1949 */
1950static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid)
1951{
1952 uint32_t schid;
1953
1954 for (schid = 0; schid <= MAX_SCHID; schid++) {
1955 if (!css_find_subch(1, cssid, ssid, schid)) {
1956 return schid;
1957 }
1958 }
1959 return MAX_SCHID + 1;
1960}
1961
1962/**
1963 * Return first free subchannel (id) in subchannel set for a device number
1964 *
1965 * Verify the device number @p devno is not used yet in the subchannel
1966 * set identified by @p cssid and @p ssid. Set @p schid to the index
1967 * of the first free subchannel in the subchannel set, if there is
1968 * any. Return true if everything succeeded and false otherwise.
1969 */
1970static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid,
1971 uint16_t devno, uint16_t *schid,
1972 Error **errp)
1973{
1974 uint32_t free_schid;
1975
1976 assert(schid);
1977 if (css_devno_used(cssid, ssid, devno)) {
1978 error_setg(errp, "Device %x.%x.%04x already exists",
1979 cssid, ssid, devno);
1980 return false;
1981 }
1982 free_schid = css_find_free_subch(cssid, ssid);
1983 if (free_schid > MAX_SCHID) {
1984 error_setg(errp, "No free subchannel found for %x.%x.%04x",
1985 cssid, ssid, devno);
1986 return false;
1987 }
1988 *schid = free_schid;
1989 return true;
1990}
1991
1992/**
1993 * Return first free subchannel (id) and device number
1994 *
1995 * Locate the first free subchannel and first free device number in
1996 * any of the subchannel sets of the channel subsystem identified by
1997 * @p cssid. Return false if no free subchannel / device number could
1998 * be found. Otherwise set @p ssid, @p devno and @p schid to identify
1999 * the available subchannel and device number and return true.
2000 *
2001 * May modify @p ssid, @p devno and / or @p schid even if no free
2002 * subchannel / device number could be found.
2003 */
2004static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid,
2005 uint16_t *devno, uint16_t *schid,
2006 Error **errp)
2007{
2008 uint32_t free_schid, free_devno;
2009
2010 assert(ssid && devno && schid);
2011 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) {
2012 free_schid = css_find_free_subch(cssid, *ssid);
2013 if (free_schid > MAX_SCHID) {
2014 continue;
2015 }
2016 free_devno = css_find_free_devno(cssid, *ssid, free_schid);
2017 if (free_devno > MAX_DEVNO) {
2018 continue;
2019 }
2020 *schid = free_schid;
2021 *devno = free_devno;
2022 return true;
2023 }
2024 error_setg(errp, "Virtual channel subsystem is full!");
2025 return false;
2026}
2027
df1fe5bb
CH		 2028bool css_subch_visible(SubchDev *sch)
2029{
562f5e0b 2030 if (sch->ssid > channel_subsys.max_ssid) {
df1fe5bb
CH		 2031 return false;
2032 }
2033
562f5e0b
EH		 2034 if (sch->cssid != channel_subsys.default_cssid) {
2035 return (channel_subsys.max_cssid > 0);
df1fe5bb
CH		 2036 }
2037
2038 return true;
2039}
2040
2041bool css_present(uint8_t cssid)
2042{
562f5e0b 2043 return (channel_subsys.css[cssid] != NULL);
df1fe5bb
CH		 2044}
2045
2046bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno)
2047{
562f5e0b 2048 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 2049 return false;
2050 }
562f5e0b 2051 if (!channel_subsys.css[cssid]->sch_set[ssid]) {
df1fe5bb
CH		 2052 return false;
2053 }
2054
2055 return !!test_bit(devno,
562f5e0b 2056 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used);
df1fe5bb
CH		 2057}
2058
2059void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid,
2060 uint16_t devno, SubchDev *sch)
2061{
2062 CssImage *css;
2063 SubchSet *s_set;
2064
2065 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid,
2066 devno);
562f5e0b 2067 if (!channel_subsys.css[cssid]) {
df1fe5bb
CH		 2068 fprintf(stderr,
2069 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n",
2070 __func__, cssid, ssid, schid);
2071 return;
2072 }
562f5e0b 2073 css = channel_subsys.css[cssid];
df1fe5bb
CH		 2074
2075 if (!css->sch_set[ssid]) {
2076 css->sch_set[ssid] = g_malloc0(sizeof(SubchSet));
2077 }
2078 s_set = css->sch_set[ssid];
2079
2080 s_set->sch[schid] = sch;
2081 if (sch) {
2082 set_bit(schid, s_set->schids_used);
2083 set_bit(devno, s_set->devnos_used);
2084 } else {
2085 clear_bit(schid, s_set->schids_used);
2086 clear_bit(devno, s_set->devnos_used);
2087 }
2088}
2089
5c8d6f00
DJS		 2090void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited,
2091 int chain, uint16_t rsid)
df1fe5bb
CH		 2092{
2093 CrwContainer *crw_cont;
2094
2095 trace_css_crw(rsc, erc, rsid, chain ? "(chained)" : "");
2096 /* TODO: Maybe use a static crw pool? */
2097 crw_cont = g_try_malloc0(sizeof(CrwContainer));
2098 if (!crw_cont) {
562f5e0b 2099 channel_subsys.crws_lost = true;
df1fe5bb
CH		 2100 return;
2101 }
2102 crw_cont->crw.flags = (rsc << 8) | erc;
5c8d6f00
DJS		 2103 if (solicited) {
2104 crw_cont->crw.flags |= CRW_FLAGS_MASK_S;
2105 }
df1fe5bb
CH		 2106 if (chain) {
2107 crw_cont->crw.flags |= CRW_FLAGS_MASK_C;
2108 }
2109 crw_cont->crw.rsid = rsid;
562f5e0b 2110 if (channel_subsys.crws_lost) {
df1fe5bb 2111 crw_cont->crw.flags |= CRW_FLAGS_MASK_R;
562f5e0b 2112 channel_subsys.crws_lost = false;
df1fe5bb
CH		 2113 }
2114
562f5e0b 2115 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb 2116
562f5e0b
EH		 2117 if (channel_subsys.do_crw_mchk) {
2118 channel_subsys.do_crw_mchk = false;
df1fe5bb 2119 /* Inject crw pending machine check. */
de13d216 2120 s390_crw_mchk();
df1fe5bb
CH		 2121 }
2122}
2123
2124void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid,
2125 int hotplugged, int add)
2126{
2127 uint8_t guest_cssid;
2128 bool chain_crw;
2129
2130 if (add && !hotplugged) {
2131 return;
2132 }
562f5e0b 2133 if (channel_subsys.max_cssid == 0) {
df1fe5bb 2134 /* Default cssid shows up as 0. */
562f5e0b 2135 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid;
df1fe5bb
CH		 2136 } else {
2137 /* Show real cssid to the guest. */
2138 guest_cssid = cssid;
2139 }
2140 /*
2141 * Only notify for higher subchannel sets/channel subsystems if the
2142 * guest has enabled it.
2143 */
562f5e0b
EH		 2144 if ((ssid > channel_subsys.max_ssid) ||
2145 (guest_cssid > channel_subsys.max_cssid) ||
2146 ((channel_subsys.max_cssid == 0) &&
2147 (cssid != channel_subsys.default_cssid))) {
df1fe5bb
CH		 2148 return;
2149 }
562f5e0b
EH		 2150 chain_crw = (channel_subsys.max_ssid > 0) ||
2151 (channel_subsys.max_cssid > 0);
5c8d6f00 2152 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid);
df1fe5bb 2153 if (chain_crw) {
5c8d6f00 2154 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0,
df1fe5bb
CH		 2155 (guest_cssid << 8) | (ssid << 4));
2156 }
c1755b14
HP		 2157 /* RW_ERC_IPI --> clear pending interrupts */
2158 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid);
df1fe5bb
CH		 2159}
2160
2161void css_generate_chp_crws(uint8_t cssid, uint8_t chpid)
2162{
2163 /* TODO */
2164}
2165
8cba80c3
FB		 2166void css_generate_css_crws(uint8_t cssid)
2167{
562f5e0b 2168 if (!channel_subsys.sei_pending) {
5c8d6f00 2169 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid);
c81b4f89 2170 }
562f5e0b 2171 channel_subsys.sei_pending = true;
c81b4f89
SSG		 2172}
2173
2174void css_clear_sei_pending(void)
2175{
562f5e0b 2176 channel_subsys.sei_pending = false;
8cba80c3
FB		 2177}
2178
df1fe5bb
CH		 2179int css_enable_mcsse(void)
2180{
2181 trace_css_enable_facility("mcsse");
562f5e0b 2182 channel_subsys.max_cssid = MAX_CSSID;
df1fe5bb
CH		 2183 return 0;
2184}
2185
2186int css_enable_mss(void)
2187{
2188 trace_css_enable_facility("mss");
562f5e0b 2189 channel_subsys.max_ssid = MAX_SSID;
df1fe5bb
CH		 2190 return 0;
2191}
2192
df1fe5bb
CH		 2193void css_reset_sch(SubchDev *sch)
2194{
2195 PMCW *p = &sch->curr_status.pmcw;
2196
62ac4a52
TH		 2197 if ((p->flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) {
2198 sch->disable_cb(sch);
2199 }
2200
df1fe5bb
CH		 2201 p->intparm = 0;
2202 p->flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA |
2203 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME |
2204 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF);
2205 p->flags |= PMCW_FLAGS_MASK_DNV;
2206 p->devno = sch->devno;
2207 p->pim = 0x80;
2208 p->lpm = p->pim;
2209 p->pnom = 0;
2210 p->lpum = 0;
2211 p->mbi = 0;
2212 p->pom = 0xff;
2213 p->pam = 0x80;
2214 p->chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME |
2215 PMCW_CHARS_MASK_CSENSE);
2216
2217 memset(&sch->curr_status.scsw, 0, sizeof(sch->curr_status.scsw));
2218 sch->curr_status.mba = 0;
2219
2220 sch->channel_prog = 0x0;
2221 sch->last_cmd_valid = false;
7e749462 2222 sch->thinint_active = false;
df1fe5bb
CH		 2223}
2224
2225void css_reset(void)
2226{
2227 CrwContainer *crw_cont;
2228
2229 /* Clean up monitoring. */
562f5e0b
EH		 2230 channel_subsys.chnmon_active = false;
2231 channel_subsys.chnmon_area = 0;
df1fe5bb
CH		 2232
2233 /* Clear pending CRWs. */
562f5e0b
EH		 2234 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) {
2235 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling);
df1fe5bb
CH		 2236 g_free(crw_cont);
2237 }
562f5e0b
EH		 2238 channel_subsys.sei_pending = false;
2239 channel_subsys.do_crw_mchk = true;
2240 channel_subsys.crws_lost = false;
df1fe5bb
CH		 2241
2242 /* Reset maximum ids. */
562f5e0b
EH		 2243 channel_subsys.max_cssid = 0;
2244 channel_subsys.max_ssid = 0;
df1fe5bb 2245}
06e686ea
CH		 2246
2247static void get_css_devid(Object *obj, Visitor *v, const char *name,
2248 void *opaque, Error **errp)
2249{
2250 DeviceState *dev = DEVICE(obj);
2251 Property *prop = opaque;
2252 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
2253 char buffer[] = "xx.x.xxxx";
2254 char *p = buffer;
2255 int r;
2256
2257 if (dev_id->valid) {
2258
2259 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid,
2260 dev_id->ssid, dev_id->devid);
2261 assert(r == sizeof(buffer) - 1);
2262
2263 /* drop leading zero */
2264 if (dev_id->cssid <= 0xf) {
2265 p++;
2266 }
2267 } else {
2268 snprintf(buffer, sizeof(buffer), "<unset>");
2269 }
2270
2271 visit_type_str(v, name, &p, errp);
2272}
2273
2274/*
2275 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid
2276 */
2277static void set_css_devid(Object *obj, Visitor *v, const char *name,
2278 void *opaque, Error **errp)
2279{
2280 DeviceState *dev = DEVICE(obj);
2281 Property *prop = opaque;
2282 CssDevId *dev_id = qdev_get_prop_ptr(dev, prop);
2283 Error *local_err = NULL;
2284 char *str;
2285 int num, n1, n2;
2286 unsigned int cssid, ssid, devid;
2287
2288 if (dev->realized) {
2289 qdev_prop_set_after_realize(dev, name, errp);
2290 return;
2291 }
2292
2293 visit_type_str(v, name, &str, &local_err);
2294 if (local_err) {
2295 error_propagate(errp, local_err);
2296 return;
2297 }
2298
2299 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2);
2300 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) {
2301 error_set_from_qdev_prop_error(errp, EINVAL, dev, prop, str);
2302 goto out;
2303 }
2304 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) {
2305 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x",
2306 cssid, ssid);
2307 goto out;
2308 }
2309
2310 dev_id->cssid = cssid;
2311 dev_id->ssid = ssid;
2312 dev_id->devid = devid;
2313 dev_id->valid = true;
2314
2315out:
2316 g_free(str);
2317}
2318
1b6b7d10 2319const PropertyInfo css_devid_propinfo = {
06e686ea
CH		 2320 .name = "str",
2321 .description = "Identifier of an I/O device in the channel "
2322 "subsystem, example: fe.1.23ab",
2323 .get = get_css_devid,
2324 .set = set_css_devid,
2325};
cf249935 2326
1b6b7d10 2327const PropertyInfo css_devid_ro_propinfo = {
c35fc6aa
DJS		 2328 .name = "str",
2329 .description = "Read-only identifier of an I/O device in the channel "
2330 "subsystem, example: fe.1.23ab",
2331 .get = get_css_devid,
2332};
2333
817d4a6b
DJS		 2334SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss,
2335 Error **errp)
cf249935
SS		 2336{
2337 uint16_t schid = 0;
2338 SubchDev *sch;
2339
2340 if (bus_id.valid) {
817d4a6b
DJS		 2341 if (is_virtual != (bus_id.cssid == VIRTUAL_CSSID)) {
2342 error_setg(errp, "cssid %hhx not valid for %s devices",
2343 bus_id.cssid,
2344 (is_virtual ? "virtual" : "non-virtual"));
cf249935
SS		 2345 return NULL;
2346 }
817d4a6b
DJS		 2347 }
2348
2349 if (bus_id.valid) {
2350 if (squash_mcss) {
2351 bus_id.cssid = channel_subsys.default_cssid;
2352 } else if (!channel_subsys.css[bus_id.cssid]) {
2353 css_create_css_image(bus_id.cssid, false);
2354 }
2355
cf249935
SS		 2356 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid,
2357 bus_id.devid, &schid, errp)) {
2358 return NULL;
2359 }
817d4a6b
DJS		 2360 } else if (squash_mcss || is_virtual) {
2361 bus_id.cssid = channel_subsys.default_cssid;
2362
cf249935
SS		 2363 if (!css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid,
2364 &bus_id.devid, &schid, errp)) {
2365 return NULL;
2366 }
817d4a6b
DJS		 2367 } else {
2368 for (bus_id.cssid = 0; bus_id.cssid < MAX_CSSID; ++bus_id.cssid) {
2369 if (bus_id.cssid == VIRTUAL_CSSID) {
2370 continue;
2371 }
2372
2373 if (!channel_subsys.css[bus_id.cssid]) {
2374 css_create_css_image(bus_id.cssid, false);
2375 }
2376
2377 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid,
2378 &bus_id.devid, &schid,
2379 NULL)) {
2380 break;
2381 }
2382 if (bus_id.cssid == MAX_CSSID) {
2383 error_setg(errp, "Virtual channel subsystem is full!");
2384 return NULL;
2385 }
2386 }
cf249935
SS		 2387 }
2388
2389 sch = g_malloc0(sizeof(*sch));
2390 sch->cssid = bus_id.cssid;
2391 sch->ssid = bus_id.ssid;
2392 sch->devno = bus_id.devid;
2393 sch->schid = schid;
2394 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch);
2395 return sch;
2396}
8f3cf012
XFR		 2397
2398static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id)
2399{
2400 char *fid_path;
2401 FILE *fd;
2402 uint32_t chpid[8];
2403 int i;
2404 PMCW *p = &sch->curr_status.pmcw;
2405
2406 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids",
2407 dev_id->cssid, dev_id->ssid, dev_id->devid);
2408 fd = fopen(fid_path, "r");
2409 if (fd == NULL) {
2410 error_report("%s: open %s failed", __func__, fid_path);
2411 g_free(fid_path);
2412 return -EINVAL;
2413 }
2414
2415 if (fscanf(fd, "%x %x %x %x %x %x %x %x",
2416 &chpid[0], &chpid[1], &chpid[2], &chpid[3],
2417 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) {
2418 fclose(fd);
2419 g_free(fid_path);
2420 return -EINVAL;
2421 }
2422
2423 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) {
2424 p->chpid[i] = chpid[i];
2425 }
2426
2427 fclose(fd);
2428 g_free(fid_path);
2429
2430 return 0;
2431}
2432
2433static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id)
2434{
2435 char *fid_path;
2436 FILE *fd;
2437 uint32_t pim, pam, pom;
2438 PMCW *p = &sch->curr_status.pmcw;
2439
2440 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom",
2441 dev_id->cssid, dev_id->ssid, dev_id->devid);
2442 fd = fopen(fid_path, "r");
2443 if (fd == NULL) {
2444 error_report("%s: open %s failed", __func__, fid_path);
2445 g_free(fid_path);
2446 return -EINVAL;
2447 }
2448
2449 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) {
2450 fclose(fd);
2451 g_free(fid_path);
2452 return -EINVAL;
2453 }
2454
2455 p->pim = pim;
2456 p->pam = pam;
2457 p->pom = pom;
2458 fclose(fd);
2459 g_free(fid_path);
2460
2461 return 0;
2462}
2463
2464static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type,
2465 CssDevId *dev_id)
2466{
2467 char *fid_path;
2468 FILE *fd;
2469
2470 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type",
2471 dev_id->cssid, chpid);
2472 fd = fopen(fid_path, "r");
2473 if (fd == NULL) {
2474 error_report("%s: open %s failed", __func__, fid_path);
2475 g_free(fid_path);
2476 return -EINVAL;
2477 }
2478
2479 if (fscanf(fd, "%x", type) != 1) {
2480 fclose(fd);
2481 g_free(fid_path);
2482 return -EINVAL;
2483 }
2484
2485 fclose(fd);
2486 g_free(fid_path);
2487
2488 return 0;
2489}
2490
2491/*
2492 * We currently retrieve the real device information from sysfs to build the
2493 * guest subchannel information block without considering the migration feature.
2494 * We need to revisit this problem when we want to add migration support.
2495 */
2496int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id)
2497{
2498 CssImage *css = channel_subsys.css[sch->cssid];
2499 PMCW *p = &sch->curr_status.pmcw;
2500 SCSW *s = &sch->curr_status.scsw;
2501 uint32_t type;
2502 int i, ret;
2503
2504 assert(css != NULL);
2505 memset(p, 0, sizeof(PMCW));
2506 p->flags |= PMCW_FLAGS_MASK_DNV;
2507 /* We are dealing with I/O subchannels only. */
2508 p->devno = sch->devno;
2509
2510 /* Grab path mask from sysfs. */
2511 ret = css_sch_get_path_masks(sch, dev_id);
2512 if (ret) {
2513 return ret;
2514 }
2515
2516 /* Grab chpids from sysfs. */
2517 ret = css_sch_get_chpids(sch, dev_id);
2518 if (ret) {
2519 return ret;
2520 }
2521
2522 /* Build chpid type. */
2523 for (i = 0; i < ARRAY_SIZE(p->chpid); i++) {
2524 if (p->chpid[i] && !css->chpids[p->chpid[i]].in_use) {
2525 ret = css_sch_get_chpid_type(p->chpid[i], &type, dev_id);
2526 if (ret) {
2527 return ret;
2528 }
2529 css_add_chpid(sch->cssid, p->chpid[i], type, false);
2530 }
2531 }
2532
2533 memset(s, 0, sizeof(SCSW));
2534 sch->curr_status.mba = 0;
2535 for (i = 0; i < ARRAY_SIZE(sch->curr_status.mda); i++) {
2536 sch->curr_status.mda[i] = 0;
2537 }
2538
2539 return 0;
2540}
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