[mirror_qemu.git] / hw / s390x / s390-pci-bus.h

/*
 * s390 PCI BUS definitions
 *
 * Copyright 2014 IBM Corp.
 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
 *            Hong Bo Li <lihbbj@cn.ibm.com>
 *            Yi Min Zhao <zyimin@cn.ibm.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or (at
 * your option) any later version. See the COPYING file in the top-level
 * directory.
 */

#ifndef HW_S390_PCI_BUS_H
#define HW_S390_PCI_BUS_H

#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/s390x/sclp.h"
#include "hw/s390x/s390_flic.h"
#include "hw/s390x/css.h"

#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
#define TYPE_S390_PCI_BUS "s390-pcibus"
#define TYPE_S390_PCI_DEVICE "zpci"
#define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
#define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region"
#define FH_MASK_ENABLE   0x80000000
#define FH_MASK_INSTANCE 0x7f000000
#define FH_MASK_SHM      0x00ff0000
#define FH_MASK_INDEX    0x0000ffff
#define FH_SHM_VFIO      0x00010000
#define FH_SHM_EMUL      0x00020000
#define ZPCI_MAX_FID 0xffffffff
#define ZPCI_MAX_UID 0xffff
#define UID_UNDEFINED 0
#define UID_CHECKING_ENABLED 0x01
#define HOT_UNPLUG_TIMEOUT (NANOSECONDS_PER_SECOND * 60 * 5)

#define S390_PCI_HOST_BRIDGE(obj) \
    OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
#define S390_PCI_BUS(obj) \
    OBJECT_CHECK(S390PCIBus, (obj), TYPE_S390_PCI_BUS)
#define S390_PCI_DEVICE(obj) \
    OBJECT_CHECK(S390PCIBusDevice, (obj), TYPE_S390_PCI_DEVICE)
#define S390_PCI_IOMMU(obj) \
    OBJECT_CHECK(S390PCIIOMMU, (obj), TYPE_S390_PCI_IOMMU)

#define HP_EVENT_TO_CONFIGURED        0x0301
#define HP_EVENT_RESERVED_TO_STANDBY  0x0302
#define HP_EVENT_DECONFIGURE_REQUEST  0x0303
#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
#define HP_EVENT_STANDBY_TO_RESERVED  0x0308

#define ERR_EVENT_INVALAS 0x1
#define ERR_EVENT_OORANGE 0x2
#define ERR_EVENT_INVALTF 0x3
#define ERR_EVENT_TPROTE  0x4
#define ERR_EVENT_APROTE  0x5
#define ERR_EVENT_KEYE    0x6
#define ERR_EVENT_INVALTE 0x7
#define ERR_EVENT_INVALTL 0x8
#define ERR_EVENT_TT      0x9
#define ERR_EVENT_INVALMS 0xa
#define ERR_EVENT_SERR    0xb
#define ERR_EVENT_NOMSI   0x10
#define ERR_EVENT_INVALBV 0x11
#define ERR_EVENT_AIBV    0x12
#define ERR_EVENT_AIRERR  0x13
#define ERR_EVENT_FMBA    0x2a
#define ERR_EVENT_FMBUP   0x2b
#define ERR_EVENT_FMBPRO  0x2c
#define ERR_EVENT_CCONF   0x30
#define ERR_EVENT_SERVAC  0x3a
#define ERR_EVENT_PERMERR 0x3b

#define ERR_EVENT_Q_BIT 0x2
#define ERR_EVENT_MVN_OFFSET 16

#define ZPCI_MSI_VEC_BITS 11
#define ZPCI_MSI_VEC_MASK 0x7ff

#define ZPCI_MSI_ADDR  0xfe00000000000000ULL
#define ZPCI_SDMA_ADDR 0x100000000ULL
#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL

#define PAGE_SHIFT      12
#define PAGE_SIZE       (1 << PAGE_SHIFT)
#define PAGE_MASK       (~(PAGE_SIZE-1))
#define PAGE_DEFAULT_ACC        0
#define PAGE_DEFAULT_KEY        (PAGE_DEFAULT_ACC << 4)

/* I/O Translation Anchor (IOTA) */
enum ZpciIoatDtype {
    ZPCI_IOTA_STO = 0,
    ZPCI_IOTA_RTTO = 1,
    ZPCI_IOTA_RSTO = 2,
    ZPCI_IOTA_RFTO = 3,
    ZPCI_IOTA_PFAA = 4,
    ZPCI_IOTA_IOPFAA = 5,
    ZPCI_IOTA_IOPTO = 7
};

#define ZPCI_IOTA_IOT_ENABLED           0x800ULL
#define ZPCI_IOTA_DT_ST                 (ZPCI_IOTA_STO  << 2)
#define ZPCI_IOTA_DT_RT                 (ZPCI_IOTA_RTTO << 2)
#define ZPCI_IOTA_DT_RS                 (ZPCI_IOTA_RSTO << 2)
#define ZPCI_IOTA_DT_RF                 (ZPCI_IOTA_RFTO << 2)
#define ZPCI_IOTA_DT_PF                 (ZPCI_IOTA_PFAA << 2)
#define ZPCI_IOTA_FS_4K                 0
#define ZPCI_IOTA_FS_1M                 1
#define ZPCI_IOTA_FS_2G                 2
#define ZPCI_KEY                        (PAGE_DEFAULT_KEY << 5)

#define ZPCI_IOTA_STO_FLAG  (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
                             ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)

/* I/O Region and segment tables */
#define ZPCI_INDEX_MASK         0x7ffULL

#define ZPCI_TABLE_TYPE_MASK    0xc
#define ZPCI_TABLE_TYPE_RFX     0xc
#define ZPCI_TABLE_TYPE_RSX     0x8
#define ZPCI_TABLE_TYPE_RTX     0x4
#define ZPCI_TABLE_TYPE_SX      0x0

#define ZPCI_TABLE_LEN_RFX      0x3
#define ZPCI_TABLE_LEN_RSX      0x3
#define ZPCI_TABLE_LEN_RTX      0x3

#define ZPCI_TABLE_OFFSET_MASK  0xc0
#define ZPCI_TABLE_SIZE         0x4000
#define ZPCI_TABLE_ALIGN        ZPCI_TABLE_SIZE
#define ZPCI_TABLE_ENTRY_SIZE   (sizeof(unsigned long))
#define ZPCI_TABLE_ENTRIES      (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)

#define ZPCI_TABLE_BITS         11
#define ZPCI_PT_BITS            8
#define ZPCI_ST_SHIFT           (ZPCI_PT_BITS + PAGE_SHIFT)
#define ZPCI_RT_SHIFT           (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)

#define ZPCI_RTE_FLAG_MASK      0x3fffULL
#define ZPCI_RTE_ADDR_MASK      (~ZPCI_RTE_FLAG_MASK)
#define ZPCI_STE_FLAG_MASK      0x7ffULL
#define ZPCI_STE_ADDR_MASK      (~ZPCI_STE_FLAG_MASK)

#define ZPCI_SFAA_MASK          (~((1ULL << 20) - 1))

/* I/O Page tables */
#define ZPCI_PTE_VALID_MASK             0x400
#define ZPCI_PTE_INVALID                0x400
#define ZPCI_PTE_VALID                  0x000
#define ZPCI_PT_SIZE                    0x800
#define ZPCI_PT_ALIGN                   ZPCI_PT_SIZE
#define ZPCI_PT_ENTRIES                 (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
#define ZPCI_PT_MASK                    (ZPCI_PT_ENTRIES - 1)

#define ZPCI_PTE_FLAG_MASK              0xfffULL
#define ZPCI_PTE_ADDR_MASK              (~ZPCI_PTE_FLAG_MASK)

/* Shared bits */
#define ZPCI_TABLE_VALID                0x00
#define ZPCI_TABLE_INVALID              0x20
#define ZPCI_TABLE_PROTECTED            0x200
#define ZPCI_TABLE_UNPROTECTED          0x000
#define ZPCI_TABLE_FC                   0x400

#define ZPCI_TABLE_VALID_MASK           0x20
#define ZPCI_TABLE_PROT_MASK            0x200

#define ZPCI_ETT_RT 1
#define ZPCI_ETT_ST 0
#define ZPCI_ETT_PT -1

/* PCI Function States
 *
 * reserved: default; device has just been plugged or is in progress of being
 *           unplugged
 * standby: device is present but not configured; transition from any
 *          configured state/to this state via sclp configure/deconfigure
 *
 * The following states make up the "configured" meta-state:
 * disabled: device is configured but not enabled; transition between this
 *           state and enabled via clp enable/disable
 * enbaled: device is ready for use; transition to disabled via clp disable;
 *          may enter an error state
 * blocked: ignore all DMA and interrupts; transition back to enabled or from
 *          error state via mpcifc
 * error: an error occurred; transition back to enabled via mpcifc
 * permanent error: an unrecoverable error occurred; transition to standby via
 *                  sclp deconfigure
 */
typedef enum {
    ZPCI_FS_RESERVED,
    ZPCI_FS_STANDBY,
    ZPCI_FS_DISABLED,
    ZPCI_FS_ENABLED,
    ZPCI_FS_BLOCKED,
    ZPCI_FS_ERROR,
    ZPCI_FS_PERMANENT_ERROR,
} ZpciState;

typedef struct SeiContainer {
    QTAILQ_ENTRY(SeiContainer) link;
    uint32_t fid;
    uint32_t fh;
    uint8_t cc;
    uint16_t pec;
    uint64_t faddr;
    uint32_t e;
} SeiContainer;

typedef struct PciCcdfErr {
    uint32_t reserved1;
    uint32_t fh;
    uint32_t fid;
    uint32_t e;
    uint64_t faddr;
    uint32_t reserved3;
    uint16_t reserved4;
    uint16_t pec;
} QEMU_PACKED PciCcdfErr;

typedef struct PciCcdfAvail {
    uint32_t reserved1;
    uint32_t fh;
    uint32_t fid;
    uint32_t reserved2;
    uint32_t reserved3;
    uint32_t reserved4;
    uint32_t reserved5;
    uint16_t reserved6;
    uint16_t pec;
} QEMU_PACKED PciCcdfAvail;

typedef struct ChscSeiNt2Res {
    uint16_t length;
    uint16_t code;
    uint16_t reserved1;
    uint8_t reserved2;
    uint8_t nt;
    uint8_t flags;
    uint8_t reserved3;
    uint8_t reserved4;
    uint8_t cc;
    uint32_t reserved5[13];
    uint8_t ccdf[4016];
} QEMU_PACKED ChscSeiNt2Res;

typedef struct S390MsixInfo {
    uint8_t table_bar;
    uint8_t pba_bar;
    uint16_t entries;
    uint32_t table_offset;
    uint32_t pba_offset;
} S390MsixInfo;

typedef struct S390IOTLBEntry {
    uint64_t iova;
    uint64_t translated_addr;
    uint64_t len;
    uint64_t perm;
} S390IOTLBEntry;

typedef struct S390PCIBusDevice S390PCIBusDevice;
typedef struct S390PCIIOMMU {
    Object parent_obj;
    S390PCIBusDevice *pbdev;
    AddressSpace as;
    MemoryRegion mr;
    IOMMUMemoryRegion iommu_mr;
    bool enabled;
    uint64_t g_iota;
    uint64_t pba;
    uint64_t pal;
    GHashTable *iotlb;
} S390PCIIOMMU;

typedef struct S390PCIIOMMUTable {
    uint64_t key;
    S390PCIIOMMU *iommu[PCI_SLOT_MAX];
} S390PCIIOMMUTable;

/* Function Measurement Block */
#define DEFAULT_MUI 4000
#define UPDATE_U_BIT 0x1ULL
#define FMBK_MASK 0xfULL

typedef struct ZpciFmbFmt0 {
    uint64_t dma_rbytes;
    uint64_t dma_wbytes;
} ZpciFmbFmt0;

#define ZPCI_FMB_CNT_LD    0
#define ZPCI_FMB_CNT_ST    1
#define ZPCI_FMB_CNT_STB   2
#define ZPCI_FMB_CNT_RPCIT 3
#define ZPCI_FMB_CNT_MAX   4

#define ZPCI_FMB_FORMAT    0

typedef struct ZpciFmb {
    uint32_t format;
    uint32_t sample;
    uint64_t last_update;
    uint64_t counter[ZPCI_FMB_CNT_MAX];
    ZpciFmbFmt0 fmt0;
} ZpciFmb;
QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb");

struct S390PCIBusDevice {
    DeviceState qdev;
    PCIDevice *pdev;
    ZpciState state;
    char *target;
    uint16_t uid;
    uint32_t idx;
    uint32_t fh;
    uint32_t fid;
    bool fid_defined;
    uint64_t fmb_addr;
    ZpciFmb fmb;
    QEMUTimer *fmb_timer;
    uint8_t isc;
    uint16_t noi;
    uint16_t maxstbl;
    uint8_t sum;
    S390MsixInfo msix;
    AdapterRoutes routes;
    S390PCIIOMMU *iommu;
    MemoryRegion msix_notify_mr;
    IndAddr *summary_ind;
    IndAddr *indicator;
    QEMUTimer *release_timer;
    QTAILQ_ENTRY(S390PCIBusDevice) link;
};

typedef struct S390PCIBus {
    BusState qbus;
} S390PCIBus;

typedef struct S390pciState {
    PCIHostState parent_obj;
    uint32_t next_idx;
    int bus_no;
    S390PCIBus *bus;
    GHashTable *iommu_table;
    GHashTable *zpci_table;
    QTAILQ_HEAD(, SeiContainer) pending_sei;
    QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
} S390pciState;

S390pciState *s390_get_phb(void);
int pci_chsc_sei_nt2_get_event(void *res);
int pci_chsc_sei_nt2_have_event(void);
void s390_pci_sclp_configure(SCCB *sccb);
void s390_pci_sclp_deconfigure(SCCB *sccb);
void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
                                   uint64_t faddr, uint32_t e);
uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
                                  S390IOTLBEntry *entry);
S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx);
S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh);
S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid);
S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s,
                                              const char *target);
S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
                                               S390PCIBusDevice *pbdev);

#endif
Commit	Line	Data
8cba80c3 FB	1	/*
	2	* s390 PCI BUS definitions
	3	*
	4	* Copyright 2014 IBM Corp.
	5	* Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
	6	* Hong Bo Li <lihbbj@cn.ibm.com>
	7	* Yi Min Zhao <zyimin@cn.ibm.com>
	8	*
	9	* This work is licensed under the terms of the GNU GPL, version 2 or (at
	10	* your option) any later version. See the COPYING file in the top-level
	11	* directory.
	12	*/
	13
	14	#ifndef HW_S390_PCI_BUS_H
	15	#define HW_S390_PCI_BUS_H
	16
a9c94277 MA	17	#include "hw/pci/pci.h"
a9c94277 MA	18	#include "hw/pci/pci_host.h"
8cba80c3 FB	19	#include "hw/s390x/sclp.h"
	20	#include "hw/s390x/s390_flic.h"
	21	#include "hw/s390x/css.h"
	22
	23	#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
90a0f9af	24	#define TYPE_S390_PCI_BUS "s390-pcibus"
3e5cfba3	25	#define TYPE_S390_PCI_DEVICE "zpci"
de91ea92	26	#define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
1221a474	27	#define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region"
c188e303 YMZ	28	#define FH_MASK_ENABLE 0x80000000
	29	#define FH_MASK_INSTANCE 0x7f000000
	30	#define FH_MASK_SHM 0x00ff0000
e70377df	31	#define FH_MASK_INDEX 0x0000ffff
c188e303 YMZ	32	#define FH_SHM_VFIO 0x00010000
c188e303 YMZ	33	#define FH_SHM_EMUL 0x00020000
3e5cfba3 YMZ	34	#define ZPCI_MAX_FID 0xffffffff
	35	#define ZPCI_MAX_UID 0xffff
	36	#define UID_UNDEFINED 0
bf328399	37	#define UID_CHECKING_ENABLED 0x01
93d16d81	38	#define HOT_UNPLUG_TIMEOUT (NANOSECONDS_PER_SECOND * 60 * 5)
8cba80c3 FB	39
	40	#define S390_PCI_HOST_BRIDGE(obj) \
	41	OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
90a0f9af YMZ	42	#define S390_PCI_BUS(obj) \
90a0f9af YMZ	43	OBJECT_CHECK(S390PCIBus, (obj), TYPE_S390_PCI_BUS)
3e5cfba3 YMZ	44	#define S390_PCI_DEVICE(obj) \
3e5cfba3 YMZ	45	OBJECT_CHECK(S390PCIBusDevice, (obj), TYPE_S390_PCI_DEVICE)
de91ea92 YMZ	46	#define S390_PCI_IOMMU(obj) \
de91ea92 YMZ	47	OBJECT_CHECK(S390PCIIOMMU, (obj), TYPE_S390_PCI_IOMMU)
8cba80c3 FB	48
	49	#define HP_EVENT_TO_CONFIGURED 0x0301
	50	#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
93d16d81	51	#define HP_EVENT_DECONFIGURE_REQUEST 0x0303
8cba80c3 FB	52	#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
	53	#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
	54
	55	#define ERR_EVENT_INVALAS 0x1
	56	#define ERR_EVENT_OORANGE 0x2
	57	#define ERR_EVENT_INVALTF 0x3
	58	#define ERR_EVENT_TPROTE 0x4
	59	#define ERR_EVENT_APROTE 0x5
	60	#define ERR_EVENT_KEYE 0x6
	61	#define ERR_EVENT_INVALTE 0x7
	62	#define ERR_EVENT_INVALTL 0x8
	63	#define ERR_EVENT_TT 0x9
	64	#define ERR_EVENT_INVALMS 0xa
	65	#define ERR_EVENT_SERR 0xb
	66	#define ERR_EVENT_NOMSI 0x10
	67	#define ERR_EVENT_INVALBV 0x11
	68	#define ERR_EVENT_AIBV 0x12
	69	#define ERR_EVENT_AIRERR 0x13
	70	#define ERR_EVENT_FMBA 0x2a
	71	#define ERR_EVENT_FMBUP 0x2b
	72	#define ERR_EVENT_FMBPRO 0x2c
	73	#define ERR_EVENT_CCONF 0x30
	74	#define ERR_EVENT_SERVAC 0x3a
	75	#define ERR_EVENT_PERMERR 0x3b
	76
	77	#define ERR_EVENT_Q_BIT 0x2
	78	#define ERR_EVENT_MVN_OFFSET 16
	79
	80	#define ZPCI_MSI_VEC_BITS 11
	81	#define ZPCI_MSI_VEC_MASK 0x7ff
	82
	83	#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
	84	#define ZPCI_SDMA_ADDR 0x100000000ULL
	85	#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
	86
	87	#define PAGE_SHIFT 12
8f955950	88	#define PAGE_SIZE (1 << PAGE_SHIFT)
8cba80c3 FB	89	#define PAGE_MASK (~(PAGE_SIZE-1))
	90	#define PAGE_DEFAULT_ACC 0
	91	#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
	92
	93	/* I/O Translation Anchor (IOTA) */
	94	enum ZpciIoatDtype {
	95	ZPCI_IOTA_STO = 0,
	96	ZPCI_IOTA_RTTO = 1,
	97	ZPCI_IOTA_RSTO = 2,
	98	ZPCI_IOTA_RFTO = 3,
	99	ZPCI_IOTA_PFAA = 4,
	100	ZPCI_IOTA_IOPFAA = 5,
	101	ZPCI_IOTA_IOPTO = 7
	102	};
	103
	104	#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
	105	#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
	106	#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
	107	#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
	108	#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
	109	#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
	110	#define ZPCI_IOTA_FS_4K 0
	111	#define ZPCI_IOTA_FS_1M 1
	112	#define ZPCI_IOTA_FS_2G 2
	113	#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
	114
	115	#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \| ZPCI_IOTA_DT_ST)
	116	#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \| ZPCI_IOTA_DT_RT)
	117	#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \| ZPCI_IOTA_DT_RS)
	118	#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \| ZPCI_IOTA_DT_RF)
	119	#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED \| ZPCI_KEY \|\
	120	ZPCI_IOTA_DT_PF \| ZPCI_IOTA_FS_2G)
	121
	122	/* I/O Region and segment tables */
	123	#define ZPCI_INDEX_MASK 0x7ffULL
	124
	125	#define ZPCI_TABLE_TYPE_MASK 0xc
	126	#define ZPCI_TABLE_TYPE_RFX 0xc
	127	#define ZPCI_TABLE_TYPE_RSX 0x8
	128	#define ZPCI_TABLE_TYPE_RTX 0x4
	129	#define ZPCI_TABLE_TYPE_SX 0x0
	130
	131	#define ZPCI_TABLE_LEN_RFX 0x3
	132	#define ZPCI_TABLE_LEN_RSX 0x3
	133	#define ZPCI_TABLE_LEN_RTX 0x3
	134
	135	#define ZPCI_TABLE_OFFSET_MASK 0xc0
	136	#define ZPCI_TABLE_SIZE 0x4000
	137	#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
	138	#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
	139	#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
	140
	141	#define ZPCI_TABLE_BITS 11
	142	#define ZPCI_PT_BITS 8
	143	#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
	144	#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
	145
	146	#define ZPCI_RTE_FLAG_MASK 0x3fffULL
	147	#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
	148	#define ZPCI_STE_FLAG_MASK 0x7ffULL
	149	#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
	150
0125861e YMZ	151	#define ZPCI_SFAA_MASK (~((1ULL << 20) - 1))
0125861e YMZ	152
8cba80c3 FB	153	/* I/O Page tables */
	154	#define ZPCI_PTE_VALID_MASK 0x400
	155	#define ZPCI_PTE_INVALID 0x400
	156	#define ZPCI_PTE_VALID 0x000
	157	#define ZPCI_PT_SIZE 0x800
	158	#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
	159	#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
	160	#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
	161
	162	#define ZPCI_PTE_FLAG_MASK 0xfffULL
	163	#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
	164
	165	/* Shared bits */
	166	#define ZPCI_TABLE_VALID 0x00
	167	#define ZPCI_TABLE_INVALID 0x20
	168	#define ZPCI_TABLE_PROTECTED 0x200
	169	#define ZPCI_TABLE_UNPROTECTED 0x000
0125861e	170	#define ZPCI_TABLE_FC 0x400
8cba80c3 FB	171
	172	#define ZPCI_TABLE_VALID_MASK 0x20
	173	#define ZPCI_TABLE_PROT_MASK 0x200
	174
0125861e YMZ	175	#define ZPCI_ETT_RT 1
	176	#define ZPCI_ETT_ST 0
	177	#define ZPCI_ETT_PT -1
	178
5d1abf23 YMZ	179	/* PCI Function States
	180	*
	181	* reserved: default; device has just been plugged or is in progress of being
	182	* unplugged
	183	* standby: device is present but not configured; transition from any
	184	* configured state/to this state via sclp configure/deconfigure
	185	*
	186	* The following states make up the "configured" meta-state:
	187	* disabled: device is configured but not enabled; transition between this
	188	* state and enabled via clp enable/disable
	189	* enbaled: device is ready for use; transition to disabled via clp disable;
	190	* may enter an error state
	191	* blocked: ignore all DMA and interrupts; transition back to enabled or from
	192	* error state via mpcifc
b12227af SW	193	* error: an error occurred; transition back to enabled via mpcifc
b12227af SW	194	* permanent error: an unrecoverable error occurred; transition to standby via
5d1abf23 YMZ	195	* sclp deconfigure
	196	*/
	197	typedef enum {
	198	ZPCI_FS_RESERVED,
	199	ZPCI_FS_STANDBY,
	200	ZPCI_FS_DISABLED,
	201	ZPCI_FS_ENABLED,
	202	ZPCI_FS_BLOCKED,
	203	ZPCI_FS_ERROR,
	204	ZPCI_FS_PERMANENT_ERROR,
	205	} ZpciState;
	206
8cba80c3 FB	207	typedef struct SeiContainer {
	208	QTAILQ_ENTRY(SeiContainer) link;
	209	uint32_t fid;
	210	uint32_t fh;
	211	uint8_t cc;
	212	uint16_t pec;
	213	uint64_t faddr;
	214	uint32_t e;
	215	} SeiContainer;
	216
	217	typedef struct PciCcdfErr {
	218	uint32_t reserved1;
	219	uint32_t fh;
	220	uint32_t fid;
	221	uint32_t e;
	222	uint64_t faddr;
	223	uint32_t reserved3;
	224	uint16_t reserved4;
	225	uint16_t pec;
	226	} QEMU_PACKED PciCcdfErr;
	227
	228	typedef struct PciCcdfAvail {
	229	uint32_t reserved1;
	230	uint32_t fh;
	231	uint32_t fid;
	232	uint32_t reserved2;
	233	uint32_t reserved3;
	234	uint32_t reserved4;
	235	uint32_t reserved5;
	236	uint16_t reserved6;
	237	uint16_t pec;
	238	} QEMU_PACKED PciCcdfAvail;
	239
	240	typedef struct ChscSeiNt2Res {
	241	uint16_t length;
	242	uint16_t code;
	243	uint16_t reserved1;
	244	uint8_t reserved2;
	245	uint8_t nt;
	246	uint8_t flags;
	247	uint8_t reserved3;
	248	uint8_t reserved4;
	249	uint8_t cc;
	250	uint32_t reserved5[13];
	251	uint8_t ccdf[4016];
	252	} QEMU_PACKED ChscSeiNt2Res;
	253
8cba80c3	254	typedef struct S390MsixInfo {
8cba80c3 FB	255	uint8_t table_bar;
	256	uint8_t pba_bar;
	257	uint16_t entries;
	258	uint32_t table_offset;
	259	uint32_t pba_offset;
	260	} S390MsixInfo;
	261
0125861e YMZ	262	typedef struct S390IOTLBEntry {
	263	uint64_t iova;
	264	uint64_t translated_addr;
	265	uint64_t len;
	266	uint64_t perm;
	267	} S390IOTLBEntry;
	268
de91ea92	269	typedef struct S390PCIBusDevice S390PCIBusDevice;
67d5cd97	270	typedef struct S390PCIIOMMU {
de91ea92 YMZ	271	Object parent_obj;
de91ea92 YMZ	272	S390PCIBusDevice *pbdev;
67d5cd97 YMZ	273	AddressSpace as;
67d5cd97 YMZ	274	MemoryRegion mr;
3df9d748	275	IOMMUMemoryRegion iommu_mr;
de91ea92 YMZ	276	bool enabled;
	277	uint64_t g_iota;
	278	uint64_t pba;
	279	uint64_t pal;
b3f05d8c	280	GHashTable *iotlb;
67d5cd97 YMZ	281	} S390PCIIOMMU;
67d5cd97 YMZ	282
03805be0 YMZ	283	typedef struct S390PCIIOMMUTable {
	284	uint64_t key;
	285	S390PCIIOMMU *iommu[PCI_SLOT_MAX];
	286	} S390PCIIOMMUTable;
	287
6e92c70c YMZ	288	/* Function Measurement Block */
	289	#define DEFAULT_MUI 4000
	290	#define UPDATE_U_BIT 0x1ULL
	291	#define FMBK_MASK 0xfULL
	292
	293	typedef struct ZpciFmbFmt0 {
	294	uint64_t dma_rbytes;
	295	uint64_t dma_wbytes;
	296	} ZpciFmbFmt0;
	297
	298	#define ZPCI_FMB_CNT_LD 0
	299	#define ZPCI_FMB_CNT_ST 1
	300	#define ZPCI_FMB_CNT_STB 2
	301	#define ZPCI_FMB_CNT_RPCIT 3
	302	#define ZPCI_FMB_CNT_MAX 4
	303
	304	#define ZPCI_FMB_FORMAT 0
	305
	306	typedef struct ZpciFmb {
	307	uint32_t format;
	308	uint32_t sample;
	309	uint64_t last_update;
	310	uint64_t counter[ZPCI_FMB_CNT_MAX];
	311	ZpciFmbFmt0 fmt0;
	312	} ZpciFmb;
	313	QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb");
	314
2034ee51	315	struct S390PCIBusDevice {
3e5cfba3	316	DeviceState qdev;
8cba80c3	317	PCIDevice *pdev;
5d1abf23	318	ZpciState state;
3e5cfba3 YMZ	319	char *target;
3e5cfba3 YMZ	320	uint16_t uid;
e70377df	321	uint32_t idx;
8cba80c3 FB	322	uint32_t fh;
8cba80c3 FB	323	uint32_t fid;
3e5cfba3	324	bool fid_defined;
8cba80c3	325	uint64_t fmb_addr;
6e92c70c YMZ	326	ZpciFmb fmb;
6e92c70c YMZ	327	QEMUTimer *fmb_timer;
8cba80c3 FB	328	uint8_t isc;
8cba80c3 FB	329	uint16_t noi;
0e7c259a	330	uint16_t maxstbl;
8cba80c3 FB	331	uint8_t sum;
	332	S390MsixInfo msix;
	333	AdapterRoutes routes;
67d5cd97	334	S390PCIIOMMU *iommu;
8f955950	335	MemoryRegion msix_notify_mr;
8581c115 YMZ	336	IndAddr *summary_ind;
8581c115 YMZ	337	IndAddr *indicator;
93d16d81	338	QEMUTimer *release_timer;
e70377df	339	QTAILQ_ENTRY(S390PCIBusDevice) link;
2034ee51	340	};
8cba80c3	341
90a0f9af YMZ	342	typedef struct S390PCIBus {
	343	BusState qbus;
	344	} S390PCIBus;
	345
8cba80c3 FB	346	typedef struct S390pciState {
8cba80c3 FB	347	PCIHostState parent_obj;
e70377df	348	uint32_t next_idx;
d2f07120	349	int bus_no;
90a0f9af	350	S390PCIBus *bus;
03805be0	351	GHashTable *iommu_table;
df8dd91b	352	GHashTable *zpci_table;
8cba80c3	353	QTAILQ_HEAD(, SeiContainer) pending_sei;
e70377df	354	QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
8cba80c3 FB	355	} S390pciState;
8cba80c3 FB	356
a975a24a	357	S390pciState *s390_get_phb(void);
1c5deaec CH	358	int pci_chsc_sei_nt2_get_event(void *res);
1c5deaec CH	359	int pci_chsc_sei_nt2_have_event(void);
8f5cb693 YMZ	360	void s390_pci_sclp_configure(SCCB *sccb);
8f5cb693 YMZ	361	void s390_pci_sclp_deconfigure(SCCB *sccb);
de91ea92 YMZ	362	void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
de91ea92 YMZ	363	void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
5d1abf23 YMZ	364	void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
5d1abf23 YMZ	365	uint64_t faddr, uint32_t e);
0125861e YMZ	366	uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
0125861e YMZ	367	S390IOTLBEntry *entry);
a975a24a YMZ	368	S390PCIBusDevice s390_pci_find_dev_by_idx(S390pciState s, uint32_t idx);
	369	S390PCIBusDevice s390_pci_find_dev_by_fh(S390pciState s, uint32_t fh);
	370	S390PCIBusDevice s390_pci_find_dev_by_fid(S390pciState s, uint32_t fid);
ceb7054f YMZ	371	S390PCIBusDevice s390_pci_find_dev_by_target(S390pciState s,
ceb7054f YMZ	372	const char *target);
a975a24a YMZ	373	S390PCIBusDevice s390_pci_find_next_avail_dev(S390pciState s,
a975a24a YMZ	374	S390PCIBusDevice *pbdev);
8cba80c3 FB	375
8cba80c3 FB	376	#endif