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Commit | Line | Data |
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863f6f52 FB |
1 | /* |
2 | * s390 PCI instructions | |
3 | * | |
4 | * Copyright 2014 IBM Corp. | |
5 | * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> | |
6 | * Hong Bo Li <lihbbj@cn.ibm.com> | |
7 | * Yi Min Zhao <zyimin@cn.ibm.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2 or (at | |
10 | * your option) any later version. See the COPYING file in the top-level | |
11 | * directory. | |
12 | */ | |
13 | ||
9615495a | 14 | #include "qemu/osdep.h" |
4771d756 | 15 | #include "cpu.h" |
863f6f52 FB |
16 | #include "s390-pci-inst.h" |
17 | #include "s390-pci-bus.h" | |
a9c94277 MA |
18 | #include "exec/memory-internal.h" |
19 | #include "qemu/error-report.h" | |
b3946626 | 20 | #include "sysemu/hw_accel.h" |
6e92c70c | 21 | #include "hw/s390x/tod.h" |
863f6f52 | 22 | |
229913f0 DA |
23 | #ifndef DEBUG_S390PCI_INST |
24 | #define DEBUG_S390PCI_INST 0 | |
863f6f52 FB |
25 | #endif |
26 | ||
229913f0 DA |
27 | #define DPRINTF(fmt, ...) \ |
28 | do { \ | |
29 | if (DEBUG_S390PCI_INST) { \ | |
30 | fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \ | |
31 | } \ | |
32 | } while (0) | |
33 | ||
863f6f52 FB |
34 | static void s390_set_status_code(CPUS390XState *env, |
35 | uint8_t r, uint64_t status_code) | |
36 | { | |
37 | env->regs[r] &= ~0xff000000ULL; | |
38 | env->regs[r] |= (status_code & 0xff) << 24; | |
39 | } | |
40 | ||
41 | static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) | |
42 | { | |
4e3bfc16 | 43 | S390PCIBusDevice *pbdev = NULL; |
a975a24a | 44 | S390pciState *s = s390_get_phb(); |
4e3bfc16 YMZ |
45 | uint32_t res_code, initial_l2, g_l2; |
46 | int rc, i; | |
863f6f52 FB |
47 | uint64_t resume_token; |
48 | ||
49 | rc = 0; | |
50 | if (lduw_p(&rrb->request.hdr.len) != 32) { | |
51 | res_code = CLP_RC_LEN; | |
52 | rc = -EINVAL; | |
53 | goto out; | |
54 | } | |
55 | ||
56 | if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { | |
57 | res_code = CLP_RC_FMT; | |
58 | rc = -EINVAL; | |
59 | goto out; | |
60 | } | |
61 | ||
62 | if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || | |
bf328399 | 63 | ldq_p(&rrb->request.reserved1) != 0) { |
863f6f52 FB |
64 | res_code = CLP_RC_RESNOT0; |
65 | rc = -EINVAL; | |
66 | goto out; | |
67 | } | |
68 | ||
69 | resume_token = ldq_p(&rrb->request.resume_token); | |
70 | ||
71 | if (resume_token) { | |
a975a24a | 72 | pbdev = s390_pci_find_dev_by_idx(s, resume_token); |
863f6f52 FB |
73 | if (!pbdev) { |
74 | res_code = CLP_RC_LISTPCI_BADRT; | |
75 | rc = -EINVAL; | |
76 | goto out; | |
77 | } | |
4e3bfc16 | 78 | } else { |
a975a24a | 79 | pbdev = s390_pci_find_next_avail_dev(s, NULL); |
863f6f52 FB |
80 | } |
81 | ||
82 | if (lduw_p(&rrb->response.hdr.len) < 48) { | |
83 | res_code = CLP_RC_8K; | |
84 | rc = -EINVAL; | |
85 | goto out; | |
86 | } | |
87 | ||
88 | initial_l2 = lduw_p(&rrb->response.hdr.len); | |
89 | if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) | |
90 | != 0) { | |
91 | res_code = CLP_RC_LEN; | |
92 | rc = -EINVAL; | |
93 | *cc = 3; | |
94 | goto out; | |
95 | } | |
96 | ||
97 | stl_p(&rrb->response.fmt, 0); | |
98 | stq_p(&rrb->response.reserved1, 0); | |
c188e303 | 99 | stl_p(&rrb->response.mdd, FH_MASK_SHM); |
863f6f52 | 100 | stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); |
bf328399 | 101 | rrb->response.flags = UID_CHECKING_ENABLED; |
863f6f52 | 102 | rrb->response.entry_size = sizeof(ClpFhListEntry); |
4e3bfc16 YMZ |
103 | |
104 | i = 0; | |
863f6f52 | 105 | g_l2 = LIST_PCI_HDR_LEN; |
4e3bfc16 YMZ |
106 | while (g_l2 < initial_l2 && pbdev) { |
107 | stw_p(&rrb->response.fh_list[i].device_id, | |
863f6f52 | 108 | pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); |
4e3bfc16 | 109 | stw_p(&rrb->response.fh_list[i].vendor_id, |
863f6f52 | 110 | pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); |
5d1abf23 | 111 | /* Ignore RESERVED devices. */ |
4e3bfc16 | 112 | stl_p(&rrb->response.fh_list[i].config, |
5d1abf23 | 113 | pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); |
4e3bfc16 YMZ |
114 | stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); |
115 | stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); | |
863f6f52 FB |
116 | |
117 | g_l2 += sizeof(ClpFhListEntry); | |
118 | /* Add endian check for DPRINTF? */ | |
119 | DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n", | |
4e3bfc16 YMZ |
120 | g_l2, |
121 | lduw_p(&rrb->response.fh_list[i].vendor_id), | |
122 | lduw_p(&rrb->response.fh_list[i].device_id), | |
123 | ldl_p(&rrb->response.fh_list[i].fid), | |
124 | ldl_p(&rrb->response.fh_list[i].fh)); | |
a975a24a | 125 | pbdev = s390_pci_find_next_avail_dev(s, pbdev); |
4e3bfc16 YMZ |
126 | i++; |
127 | } | |
128 | ||
129 | if (!pbdev) { | |
863f6f52 FB |
130 | resume_token = 0; |
131 | } else { | |
4e3bfc16 | 132 | resume_token = pbdev->fh & FH_MASK_INDEX; |
863f6f52 FB |
133 | } |
134 | stq_p(&rrb->response.resume_token, resume_token); | |
135 | stw_p(&rrb->response.hdr.len, g_l2); | |
136 | stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); | |
137 | out: | |
138 | if (rc) { | |
139 | DPRINTF("list pci failed rc 0x%x\n", rc); | |
140 | stw_p(&rrb->response.hdr.rsp, res_code); | |
141 | } | |
142 | return rc; | |
143 | } | |
144 | ||
468a9389 | 145 | int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) |
863f6f52 FB |
146 | { |
147 | ClpReqHdr *reqh; | |
148 | ClpRspHdr *resh; | |
149 | S390PCIBusDevice *pbdev; | |
150 | uint32_t req_len; | |
151 | uint32_t res_len; | |
152 | uint8_t buffer[4096 * 2]; | |
153 | uint8_t cc = 0; | |
154 | CPUS390XState *env = &cpu->env; | |
a975a24a | 155 | S390pciState *s = s390_get_phb(); |
863f6f52 FB |
156 | int i; |
157 | ||
863f6f52 | 158 | if (env->psw.mask & PSW_MASK_PSTATE) { |
468a9389 | 159 | s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); |
863f6f52 FB |
160 | return 0; |
161 | } | |
162 | ||
6cb1e49d | 163 | if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) { |
98ee9bed | 164 | s390_cpu_virt_mem_handle_exc(cpu, ra); |
63ceef61 FB |
165 | return 0; |
166 | } | |
863f6f52 FB |
167 | reqh = (ClpReqHdr *)buffer; |
168 | req_len = lduw_p(&reqh->len); | |
169 | if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { | |
468a9389 | 170 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
863f6f52 FB |
171 | return 0; |
172 | } | |
173 | ||
6cb1e49d | 174 | if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, |
63ceef61 | 175 | req_len + sizeof(*resh))) { |
98ee9bed | 176 | s390_cpu_virt_mem_handle_exc(cpu, ra); |
63ceef61 FB |
177 | return 0; |
178 | } | |
863f6f52 FB |
179 | resh = (ClpRspHdr *)(buffer + req_len); |
180 | res_len = lduw_p(&resh->len); | |
181 | if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { | |
468a9389 | 182 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
863f6f52 FB |
183 | return 0; |
184 | } | |
185 | if ((req_len + res_len) > 8192) { | |
468a9389 | 186 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
863f6f52 FB |
187 | return 0; |
188 | } | |
189 | ||
6cb1e49d | 190 | if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, |
63ceef61 | 191 | req_len + res_len)) { |
98ee9bed | 192 | s390_cpu_virt_mem_handle_exc(cpu, ra); |
63ceef61 FB |
193 | return 0; |
194 | } | |
863f6f52 FB |
195 | |
196 | if (req_len != 32) { | |
197 | stw_p(&resh->rsp, CLP_RC_LEN); | |
198 | goto out; | |
199 | } | |
200 | ||
201 | switch (lduw_p(&reqh->cmd)) { | |
202 | case CLP_LIST_PCI: { | |
203 | ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; | |
204 | list_pci(rrb, &cc); | |
205 | break; | |
206 | } | |
207 | case CLP_SET_PCI_FN: { | |
208 | ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; | |
209 | ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; | |
210 | ||
a975a24a | 211 | pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); |
863f6f52 FB |
212 | if (!pbdev) { |
213 | stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); | |
214 | goto out; | |
215 | } | |
216 | ||
217 | switch (reqsetpci->oc) { | |
218 | case CLP_SET_ENABLE_PCI_FN: | |
bd497683 YMZ |
219 | switch (reqsetpci->ndas) { |
220 | case 0: | |
221 | stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); | |
222 | goto out; | |
223 | case 1: | |
224 | break; | |
225 | default: | |
226 | stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); | |
227 | goto out; | |
228 | } | |
229 | ||
230 | if (pbdev->fh & FH_MASK_ENABLE) { | |
231 | stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); | |
232 | goto out; | |
233 | } | |
234 | ||
c188e303 | 235 | pbdev->fh |= FH_MASK_ENABLE; |
5d1abf23 | 236 | pbdev->state = ZPCI_FS_ENABLED; |
863f6f52 FB |
237 | stl_p(&ressetpci->fh, pbdev->fh); |
238 | stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); | |
239 | break; | |
240 | case CLP_SET_DISABLE_PCI_FN: | |
bd497683 YMZ |
241 | if (!(pbdev->fh & FH_MASK_ENABLE)) { |
242 | stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); | |
243 | goto out; | |
244 | } | |
245 | device_reset(DEVICE(pbdev)); | |
c188e303 | 246 | pbdev->fh &= ~FH_MASK_ENABLE; |
5d1abf23 | 247 | pbdev->state = ZPCI_FS_DISABLED; |
863f6f52 FB |
248 | stl_p(&ressetpci->fh, pbdev->fh); |
249 | stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); | |
250 | break; | |
251 | default: | |
252 | DPRINTF("unknown set pci command\n"); | |
253 | stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); | |
254 | break; | |
255 | } | |
256 | break; | |
257 | } | |
258 | case CLP_QUERY_PCI_FN: { | |
259 | ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; | |
260 | ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; | |
261 | ||
a975a24a | 262 | pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); |
863f6f52 FB |
263 | if (!pbdev) { |
264 | DPRINTF("query pci no pci dev\n"); | |
265 | stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); | |
266 | goto out; | |
267 | } | |
268 | ||
269 | for (i = 0; i < PCI_BAR_COUNT; i++) { | |
270 | uint32_t data = pci_get_long(pbdev->pdev->config + | |
271 | PCI_BASE_ADDRESS_0 + (i * 4)); | |
272 | ||
273 | stl_p(&resquery->bar[i], data); | |
274 | resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? | |
275 | ctz64(pbdev->pdev->io_regions[i].size) : 0; | |
276 | DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i, | |
277 | ldl_p(&resquery->bar[i]), | |
278 | pbdev->pdev->io_regions[i].size, | |
279 | resquery->bar_size[i]); | |
280 | } | |
281 | ||
282 | stq_p(&resquery->sdma, ZPCI_SDMA_ADDR); | |
283 | stq_p(&resquery->edma, ZPCI_EDMA_ADDR); | |
67aad508 | 284 | stl_p(&resquery->fid, pbdev->fid); |
863f6f52 FB |
285 | stw_p(&resquery->pchid, 0); |
286 | stw_p(&resquery->ug, 1); | |
bf328399 | 287 | stl_p(&resquery->uid, pbdev->uid); |
863f6f52 FB |
288 | stw_p(&resquery->hdr.rsp, CLP_RC_OK); |
289 | break; | |
290 | } | |
291 | case CLP_QUERY_PCI_FNGRP: { | |
292 | ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh; | |
293 | resgrp->fr = 1; | |
294 | stq_p(&resgrp->dasm, 0); | |
295 | stq_p(&resgrp->msia, ZPCI_MSI_ADDR); | |
6e92c70c | 296 | stw_p(&resgrp->mui, DEFAULT_MUI); |
863f6f52 | 297 | stw_p(&resgrp->i, 128); |
0e7c259a | 298 | stw_p(&resgrp->maxstbl, 128); |
863f6f52 FB |
299 | resgrp->version = 0; |
300 | ||
301 | stw_p(&resgrp->hdr.rsp, CLP_RC_OK); | |
302 | break; | |
303 | } | |
304 | default: | |
305 | DPRINTF("unknown clp command\n"); | |
306 | stw_p(&resh->rsp, CLP_RC_CMD); | |
307 | break; | |
308 | } | |
309 | ||
310 | out: | |
6cb1e49d | 311 | if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer, |
63ceef61 | 312 | req_len + res_len)) { |
98ee9bed | 313 | s390_cpu_virt_mem_handle_exc(cpu, ra); |
63ceef61 FB |
314 | return 0; |
315 | } | |
863f6f52 FB |
316 | setcc(cpu, cc); |
317 | return 0; | |
318 | } | |
319 | ||
c748814b PM |
320 | /** |
321 | * Swap data contained in s390x big endian registers to little endian | |
322 | * PCI bars. | |
323 | * | |
324 | * @ptr: a pointer to a uint64_t data field | |
325 | * @len: the length of the valid data, must be 1,2,4 or 8 | |
326 | */ | |
327 | static int zpci_endian_swap(uint64_t *ptr, uint8_t len) | |
328 | { | |
329 | uint64_t data = *ptr; | |
330 | ||
331 | switch (len) { | |
332 | case 1: | |
333 | break; | |
334 | case 2: | |
335 | data = bswap16(data); | |
336 | break; | |
337 | case 4: | |
338 | data = bswap32(data); | |
339 | break; | |
340 | case 8: | |
341 | data = bswap64(data); | |
342 | break; | |
343 | default: | |
344 | return -EINVAL; | |
345 | } | |
346 | *ptr = data; | |
347 | return 0; | |
348 | } | |
349 | ||
4f6482bf PM |
350 | static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset, |
351 | uint8_t len) | |
352 | { | |
353 | MemoryRegion *subregion; | |
354 | uint64_t subregion_size; | |
355 | ||
356 | QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { | |
357 | subregion_size = int128_get64(subregion->size); | |
358 | if ((offset >= subregion->addr) && | |
359 | (offset + len) <= (subregion->addr + subregion_size)) { | |
360 | mr = subregion; | |
361 | break; | |
362 | } | |
363 | } | |
364 | return mr; | |
365 | } | |
366 | ||
ab0380ca PM |
367 | static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias, |
368 | uint64_t offset, uint64_t *data, uint8_t len) | |
369 | { | |
370 | MemoryRegion *mr; | |
371 | ||
372 | mr = pbdev->pdev->io_regions[pcias].memory; | |
4f6482bf PM |
373 | mr = s390_get_subregion(mr, offset, len); |
374 | offset -= mr->addr; | |
ab0380ca PM |
375 | return memory_region_dispatch_read(mr, offset, data, len, |
376 | MEMTXATTRS_UNSPECIFIED); | |
377 | } | |
378 | ||
468a9389 | 379 | int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) |
863f6f52 FB |
380 | { |
381 | CPUS390XState *env = &cpu->env; | |
382 | S390PCIBusDevice *pbdev; | |
383 | uint64_t offset; | |
384 | uint64_t data; | |
88ee13c7 | 385 | MemTxResult result; |
863f6f52 FB |
386 | uint8_t len; |
387 | uint32_t fh; | |
388 | uint8_t pcias; | |
389 | ||
863f6f52 | 390 | if (env->psw.mask & PSW_MASK_PSTATE) { |
468a9389 | 391 | s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); |
863f6f52 FB |
392 | return 0; |
393 | } | |
394 | ||
395 | if (r2 & 0x1) { | |
468a9389 | 396 | s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); |
863f6f52 FB |
397 | return 0; |
398 | } | |
399 | ||
400 | fh = env->regs[r2] >> 32; | |
401 | pcias = (env->regs[r2] >> 16) & 0xf; | |
402 | len = env->regs[r2] & 0xf; | |
403 | offset = env->regs[r2 + 1]; | |
404 | ||
8cbd6aab PM |
405 | if (!(fh & FH_MASK_ENABLE)) { |
406 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
407 | return 0; | |
408 | } | |
409 | ||
a975a24a | 410 | pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); |
5d1abf23 | 411 | if (!pbdev) { |
863f6f52 FB |
412 | DPRINTF("pcilg no pci dev\n"); |
413 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
414 | return 0; | |
415 | } | |
416 | ||
5d1abf23 | 417 | switch (pbdev->state) { |
5d1abf23 | 418 | case ZPCI_FS_PERMANENT_ERROR: |
5d1abf23 | 419 | case ZPCI_FS_ERROR: |
863f6f52 FB |
420 | setcc(cpu, ZPCI_PCI_LS_ERR); |
421 | s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); | |
422 | return 0; | |
5d1abf23 YMZ |
423 | default: |
424 | break; | |
863f6f52 FB |
425 | } |
426 | ||
8cbd6aab PM |
427 | switch (pcias) { |
428 | case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: | |
429 | if (!len || (len > (8 - (offset & 0x7)))) { | |
468a9389 | 430 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
863f6f52 FB |
431 | return 0; |
432 | } | |
ab0380ca | 433 | result = zpci_read_bar(pbdev, pcias, offset, &data, len); |
88ee13c7 | 434 | if (result != MEMTX_OK) { |
468a9389 | 435 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
88ee13c7 PM |
436 | return 0; |
437 | } | |
8cbd6aab PM |
438 | break; |
439 | case ZPCI_CONFIG_BAR: | |
440 | if (!len || (len > (4 - (offset & 0x3))) || len == 3) { | |
468a9389 | 441 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
863f6f52 FB |
442 | return 0; |
443 | } | |
444 | data = pci_host_config_read_common( | |
445 | pbdev->pdev, offset, pci_config_size(pbdev->pdev), len); | |
446 | ||
c748814b | 447 | if (zpci_endian_swap(&data, len)) { |
468a9389 | 448 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
863f6f52 FB |
449 | return 0; |
450 | } | |
8cbd6aab PM |
451 | break; |
452 | default: | |
453 | DPRINTF("pcilg invalid space\n"); | |
863f6f52 FB |
454 | setcc(cpu, ZPCI_PCI_LS_ERR); |
455 | s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); | |
456 | return 0; | |
457 | } | |
458 | ||
6e92c70c YMZ |
459 | pbdev->fmb.counter[ZPCI_FMB_CNT_LD]++; |
460 | ||
863f6f52 FB |
461 | env->regs[r1] = data; |
462 | setcc(cpu, ZPCI_PCI_LS_OK); | |
463 | return 0; | |
464 | } | |
465 | ||
8af27a9e PM |
466 | static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias, |
467 | uint64_t offset, uint64_t data, uint8_t len) | |
468 | { | |
469 | MemoryRegion *mr; | |
470 | ||
4f6482bf PM |
471 | mr = pbdev->pdev->io_regions[pcias].memory; |
472 | mr = s390_get_subregion(mr, offset, len); | |
473 | offset -= mr->addr; | |
8af27a9e PM |
474 | return memory_region_dispatch_write(mr, offset, data, len, |
475 | MEMTXATTRS_UNSPECIFIED); | |
476 | } | |
477 | ||
468a9389 | 478 | int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) |
863f6f52 FB |
479 | { |
480 | CPUS390XState *env = &cpu->env; | |
481 | uint64_t offset, data; | |
482 | S390PCIBusDevice *pbdev; | |
88ee13c7 | 483 | MemTxResult result; |
863f6f52 FB |
484 | uint8_t len; |
485 | uint32_t fh; | |
486 | uint8_t pcias; | |
487 | ||
863f6f52 | 488 | if (env->psw.mask & PSW_MASK_PSTATE) { |
468a9389 | 489 | s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); |
863f6f52 FB |
490 | return 0; |
491 | } | |
492 | ||
493 | if (r2 & 0x1) { | |
468a9389 | 494 | s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); |
863f6f52 FB |
495 | return 0; |
496 | } | |
497 | ||
498 | fh = env->regs[r2] >> 32; | |
499 | pcias = (env->regs[r2] >> 16) & 0xf; | |
500 | len = env->regs[r2] & 0xf; | |
501 | offset = env->regs[r2 + 1]; | |
7645b9a7 PM |
502 | data = env->regs[r1]; |
503 | ||
504 | if (!(fh & FH_MASK_ENABLE)) { | |
505 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
506 | return 0; | |
507 | } | |
863f6f52 | 508 | |
a975a24a | 509 | pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); |
5d1abf23 | 510 | if (!pbdev) { |
863f6f52 FB |
511 | DPRINTF("pcistg no pci dev\n"); |
512 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
513 | return 0; | |
514 | } | |
515 | ||
5d1abf23 | 516 | switch (pbdev->state) { |
7645b9a7 PM |
517 | /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED |
518 | * are already covered by the FH_MASK_ENABLE check above | |
519 | */ | |
5d1abf23 | 520 | case ZPCI_FS_PERMANENT_ERROR: |
5d1abf23 | 521 | case ZPCI_FS_ERROR: |
863f6f52 FB |
522 | setcc(cpu, ZPCI_PCI_LS_ERR); |
523 | s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); | |
524 | return 0; | |
5d1abf23 YMZ |
525 | default: |
526 | break; | |
863f6f52 FB |
527 | } |
528 | ||
7645b9a7 PM |
529 | switch (pcias) { |
530 | /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */ | |
531 | case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: | |
532 | /* Check length: | |
533 | * A length of 0 is invalid and length should not cross a double word | |
534 | */ | |
535 | if (!len || (len > (8 - (offset & 0x7)))) { | |
468a9389 | 536 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
863f6f52 FB |
537 | return 0; |
538 | } | |
205e5de4 | 539 | |
8af27a9e | 540 | result = zpci_write_bar(pbdev, pcias, offset, data, len); |
88ee13c7 | 541 | if (result != MEMTX_OK) { |
468a9389 | 542 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
88ee13c7 PM |
543 | return 0; |
544 | } | |
7645b9a7 PM |
545 | break; |
546 | case ZPCI_CONFIG_BAR: | |
547 | /* ZPCI uses the pseudo BAR number 15 as configuration space */ | |
548 | /* possible access lengths are 1,2,4 and must not cross a word */ | |
549 | if (!len || (len > (4 - (offset & 0x3))) || len == 3) { | |
468a9389 | 550 | s390_program_interrupt(env, PGM_OPERAND, 4, ra); |
863f6f52 FB |
551 | return 0; |
552 | } | |
7645b9a7 PM |
553 | /* len = 1,2,4 so we do not need to test */ |
554 | zpci_endian_swap(&data, len); | |
863f6f52 FB |
555 | pci_host_config_write_common(pbdev->pdev, offset, |
556 | pci_config_size(pbdev->pdev), | |
557 | data, len); | |
7645b9a7 PM |
558 | break; |
559 | default: | |
863f6f52 FB |
560 | DPRINTF("pcistg invalid space\n"); |
561 | setcc(cpu, ZPCI_PCI_LS_ERR); | |
562 | s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); | |
563 | return 0; | |
564 | } | |
565 | ||
6e92c70c YMZ |
566 | pbdev->fmb.counter[ZPCI_FMB_CNT_ST]++; |
567 | ||
863f6f52 FB |
568 | setcc(cpu, ZPCI_PCI_LS_OK); |
569 | return 0; | |
570 | } | |
571 | ||
b3f05d8c YMZ |
572 | static void s390_pci_update_iotlb(S390PCIIOMMU *iommu, S390IOTLBEntry *entry) |
573 | { | |
574 | S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova); | |
575 | IOMMUTLBEntry notify = { | |
576 | .target_as = &address_space_memory, | |
577 | .iova = entry->iova, | |
578 | .translated_addr = entry->translated_addr, | |
579 | .perm = entry->perm, | |
580 | .addr_mask = ~PAGE_MASK, | |
581 | }; | |
582 | ||
583 | if (entry->perm == IOMMU_NONE) { | |
584 | if (!cache) { | |
585 | return; | |
586 | } | |
587 | g_hash_table_remove(iommu->iotlb, &entry->iova); | |
588 | } else { | |
589 | if (cache) { | |
590 | if (cache->perm == entry->perm && | |
591 | cache->translated_addr == entry->translated_addr) { | |
592 | return; | |
593 | } | |
594 | ||
595 | notify.perm = IOMMU_NONE; | |
cb1efcf4 | 596 | memory_region_notify_iommu(&iommu->iommu_mr, 0, notify); |
b3f05d8c YMZ |
597 | notify.perm = entry->perm; |
598 | } | |
599 | ||
600 | cache = g_new(S390IOTLBEntry, 1); | |
601 | cache->iova = entry->iova; | |
602 | cache->translated_addr = entry->translated_addr; | |
603 | cache->len = PAGE_SIZE; | |
604 | cache->perm = entry->perm; | |
605 | g_hash_table_replace(iommu->iotlb, &cache->iova, cache); | |
606 | } | |
607 | ||
cb1efcf4 | 608 | memory_region_notify_iommu(&iommu->iommu_mr, 0, notify); |
b3f05d8c YMZ |
609 | } |
610 | ||
468a9389 | 611 | int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) |
863f6f52 FB |
612 | { |
613 | CPUS390XState *env = &cpu->env; | |
614 | uint32_t fh; | |
0125861e | 615 | uint16_t error = 0; |
863f6f52 | 616 | S390PCIBusDevice *pbdev; |
de91ea92 | 617 | S390PCIIOMMU *iommu; |
0125861e | 618 | S390IOTLBEntry entry; |
4e99a0f7 | 619 | hwaddr start, end; |
863f6f52 | 620 | |
863f6f52 | 621 | if (env->psw.mask & PSW_MASK_PSTATE) { |
468a9389 | 622 | s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); |
0125861e | 623 | return 0; |
863f6f52 FB |
624 | } |
625 | ||
626 | if (r2 & 0x1) { | |
468a9389 | 627 | s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); |
0125861e | 628 | return 0; |
863f6f52 FB |
629 | } |
630 | ||
631 | fh = env->regs[r1] >> 32; | |
4e99a0f7 YMZ |
632 | start = env->regs[r2]; |
633 | end = start + env->regs[r2 + 1]; | |
863f6f52 | 634 | |
a975a24a | 635 | pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); |
5d1abf23 | 636 | if (!pbdev) { |
863f6f52 FB |
637 | DPRINTF("rpcit no pci dev\n"); |
638 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
0125861e | 639 | return 0; |
863f6f52 FB |
640 | } |
641 | ||
5d1abf23 YMZ |
642 | switch (pbdev->state) { |
643 | case ZPCI_FS_RESERVED: | |
644 | case ZPCI_FS_STANDBY: | |
645 | case ZPCI_FS_DISABLED: | |
646 | case ZPCI_FS_PERMANENT_ERROR: | |
647 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
648 | return 0; | |
649 | case ZPCI_FS_ERROR: | |
650 | setcc(cpu, ZPCI_PCI_LS_ERR); | |
651 | s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER); | |
652 | return 0; | |
653 | default: | |
654 | break; | |
655 | } | |
656 | ||
de91ea92 YMZ |
657 | iommu = pbdev->iommu; |
658 | if (!iommu->g_iota) { | |
0125861e YMZ |
659 | error = ERR_EVENT_INVALAS; |
660 | goto err; | |
5d1abf23 YMZ |
661 | } |
662 | ||
de91ea92 | 663 | if (end < iommu->pba || start > iommu->pal) { |
0125861e YMZ |
664 | error = ERR_EVENT_OORANGE; |
665 | goto err; | |
5d1abf23 YMZ |
666 | } |
667 | ||
4e99a0f7 | 668 | while (start < end) { |
0125861e YMZ |
669 | error = s390_guest_io_table_walk(iommu->g_iota, start, &entry); |
670 | if (error) { | |
671 | break; | |
4e99a0f7 | 672 | } |
b3f05d8c | 673 | |
0125861e | 674 | start += entry.len; |
b3f05d8c YMZ |
675 | while (entry.iova < start && entry.iova < end) { |
676 | s390_pci_update_iotlb(iommu, &entry); | |
677 | entry.iova += PAGE_SIZE; | |
678 | entry.translated_addr += PAGE_SIZE; | |
679 | } | |
863f6f52 | 680 | } |
0125861e YMZ |
681 | err: |
682 | if (error) { | |
683 | pbdev->state = ZPCI_FS_ERROR; | |
684 | setcc(cpu, ZPCI_PCI_LS_ERR); | |
685 | s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR); | |
686 | s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0); | |
687 | } else { | |
6e92c70c | 688 | pbdev->fmb.counter[ZPCI_FMB_CNT_RPCIT]++; |
0125861e YMZ |
689 | setcc(cpu, ZPCI_PCI_LS_OK); |
690 | } | |
863f6f52 FB |
691 | return 0; |
692 | } | |
693 | ||
6cb1e49d | 694 | int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, |
468a9389 | 695 | uint8_t ar, uintptr_t ra) |
863f6f52 FB |
696 | { |
697 | CPUS390XState *env = &cpu->env; | |
698 | S390PCIBusDevice *pbdev; | |
699 | MemoryRegion *mr; | |
88ee13c7 | 700 | MemTxResult result; |
0e7c259a | 701 | uint64_t offset; |
863f6f52 | 702 | int i; |
863f6f52 FB |
703 | uint32_t fh; |
704 | uint8_t pcias; | |
705 | uint8_t len; | |
63ceef61 | 706 | uint8_t buffer[128]; |
863f6f52 FB |
707 | |
708 | if (env->psw.mask & PSW_MASK_PSTATE) { | |
468a9389 | 709 | s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); |
863f6f52 FB |
710 | return 0; |
711 | } | |
712 | ||
713 | fh = env->regs[r1] >> 32; | |
714 | pcias = (env->regs[r1] >> 16) & 0xf; | |
715 | len = env->regs[r1] & 0xff; | |
0e7c259a | 716 | offset = env->regs[r3]; |
863f6f52 | 717 | |
0e7c259a PM |
718 | if (!(fh & FH_MASK_ENABLE)) { |
719 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
863f6f52 FB |
720 | return 0; |
721 | } | |
722 | ||
a975a24a | 723 | pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); |
5d1abf23 | 724 | if (!pbdev) { |
863f6f52 FB |
725 | DPRINTF("pcistb no pci dev fh 0x%x\n", fh); |
726 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
727 | return 0; | |
728 | } | |
729 | ||
5d1abf23 | 730 | switch (pbdev->state) { |
5d1abf23 | 731 | case ZPCI_FS_PERMANENT_ERROR: |
5d1abf23 | 732 | case ZPCI_FS_ERROR: |
863f6f52 FB |
733 | setcc(cpu, ZPCI_PCI_LS_ERR); |
734 | s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED); | |
735 | return 0; | |
5d1abf23 YMZ |
736 | default: |
737 | break; | |
863f6f52 FB |
738 | } |
739 | ||
0e7c259a PM |
740 | if (pcias > ZPCI_IO_BAR_MAX) { |
741 | DPRINTF("pcistb invalid space\n"); | |
742 | setcc(cpu, ZPCI_PCI_LS_ERR); | |
743 | s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS); | |
744 | return 0; | |
745 | } | |
746 | ||
747 | /* Verify the address, offset and length */ | |
748 | /* offset must be a multiple of 8 */ | |
749 | if (offset % 8) { | |
750 | goto specification_error; | |
751 | } | |
752 | /* Length must be greater than 8, a multiple of 8 */ | |
753 | /* and not greater than maxstbl */ | |
754 | if ((len <= 8) || (len % 8) || (len > pbdev->maxstbl)) { | |
755 | goto specification_error; | |
756 | } | |
757 | /* Do not cross a 4K-byte boundary */ | |
758 | if (((offset & 0xfff) + len) > 0x1000) { | |
759 | goto specification_error; | |
760 | } | |
761 | /* Guest address must be double word aligned */ | |
762 | if (gaddr & 0x07UL) { | |
763 | goto specification_error; | |
764 | } | |
765 | ||
863f6f52 | 766 | mr = pbdev->pdev->io_regions[pcias].memory; |
4f6482bf PM |
767 | mr = s390_get_subregion(mr, offset, len); |
768 | offset -= mr->addr; | |
769 | ||
6d7b9a6c PM |
770 | if (!memory_region_access_valid(mr, offset, len, true, |
771 | MEMTXATTRS_UNSPECIFIED)) { | |
468a9389 | 772 | s390_program_interrupt(env, PGM_OPERAND, 6, ra); |
863f6f52 FB |
773 | return 0; |
774 | } | |
775 | ||
6cb1e49d | 776 | if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) { |
98ee9bed | 777 | s390_cpu_virt_mem_handle_exc(cpu, ra); |
63ceef61 FB |
778 | return 0; |
779 | } | |
780 | ||
863f6f52 | 781 | for (i = 0; i < len / 8; i++) { |
0e7c259a PM |
782 | result = memory_region_dispatch_write(mr, offset + i * 8, |
783 | ldq_p(buffer + i * 8), 8, | |
784 | MEMTXATTRS_UNSPECIFIED); | |
88ee13c7 | 785 | if (result != MEMTX_OK) { |
468a9389 | 786 | s390_program_interrupt(env, PGM_OPERAND, 6, ra); |
88ee13c7 PM |
787 | return 0; |
788 | } | |
863f6f52 FB |
789 | } |
790 | ||
6e92c70c YMZ |
791 | pbdev->fmb.counter[ZPCI_FMB_CNT_STB]++; |
792 | ||
863f6f52 FB |
793 | setcc(cpu, ZPCI_PCI_LS_OK); |
794 | return 0; | |
0e7c259a PM |
795 | |
796 | specification_error: | |
797 | s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); | |
798 | return 0; | |
863f6f52 FB |
799 | } |
800 | ||
801 | static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) | |
802 | { | |
8581c115 | 803 | int ret, len; |
dde522bb | 804 | uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); |
863f6f52 | 805 | |
dde522bb FL |
806 | pbdev->routes.adapter.adapter_id = css_get_adapter_id( |
807 | CSS_IO_ADAPTER_PCI, isc); | |
8581c115 YMZ |
808 | pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); |
809 | len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); | |
810 | pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); | |
811 | ||
bac45d51 YMZ |
812 | ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); |
813 | if (ret) { | |
814 | goto out; | |
815 | } | |
816 | ||
817 | ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator); | |
818 | if (ret) { | |
819 | goto out; | |
820 | } | |
863f6f52 FB |
821 | |
822 | pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); | |
823 | pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); | |
824 | pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); | |
825 | pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); | |
dde522bb | 826 | pbdev->isc = isc; |
863f6f52 FB |
827 | pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); |
828 | pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); | |
829 | ||
830 | DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); | |
831 | return 0; | |
bac45d51 YMZ |
832 | out: |
833 | release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); | |
834 | release_indicator(&pbdev->routes.adapter, pbdev->indicator); | |
835 | pbdev->summary_ind = NULL; | |
836 | pbdev->indicator = NULL; | |
837 | return ret; | |
863f6f52 FB |
838 | } |
839 | ||
e141dbad | 840 | int pci_dereg_irqs(S390PCIBusDevice *pbdev) |
863f6f52 | 841 | { |
8581c115 YMZ |
842 | release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); |
843 | release_indicator(&pbdev->routes.adapter, pbdev->indicator); | |
863f6f52 | 844 | |
8581c115 YMZ |
845 | pbdev->summary_ind = NULL; |
846 | pbdev->indicator = NULL; | |
863f6f52 FB |
847 | pbdev->routes.adapter.summary_addr = 0; |
848 | pbdev->routes.adapter.summary_offset = 0; | |
849 | pbdev->routes.adapter.ind_addr = 0; | |
850 | pbdev->routes.adapter.ind_offset = 0; | |
851 | pbdev->isc = 0; | |
852 | pbdev->noi = 0; | |
853 | pbdev->sum = 0; | |
854 | ||
855 | DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); | |
856 | return 0; | |
857 | } | |
858 | ||
468a9389 DH |
859 | static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, |
860 | uintptr_t ra) | |
863f6f52 FB |
861 | { |
862 | uint64_t pba = ldq_p(&fib.pba); | |
863 | uint64_t pal = ldq_p(&fib.pal); | |
864 | uint64_t g_iota = ldq_p(&fib.iota); | |
865 | uint8_t dt = (g_iota >> 2) & 0x7; | |
866 | uint8_t t = (g_iota >> 11) & 0x1; | |
867 | ||
f9125e3a YMZ |
868 | pba &= ~0xfff; |
869 | pal |= 0xfff; | |
863f6f52 | 870 | if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { |
468a9389 | 871 | s390_program_interrupt(env, PGM_OPERAND, 6, ra); |
863f6f52 FB |
872 | return -EINVAL; |
873 | } | |
874 | ||
875 | /* currently we only support designation type 1 with translation */ | |
876 | if (!(dt == ZPCI_IOTA_RTTO && t)) { | |
877 | error_report("unsupported ioat dt %d t %d", dt, t); | |
468a9389 | 878 | s390_program_interrupt(env, PGM_OPERAND, 6, ra); |
863f6f52 FB |
879 | return -EINVAL; |
880 | } | |
881 | ||
de91ea92 YMZ |
882 | iommu->pba = pba; |
883 | iommu->pal = pal; | |
884 | iommu->g_iota = g_iota; | |
f0a399db | 885 | |
de91ea92 | 886 | s390_pci_iommu_enable(iommu); |
f0a399db | 887 | |
863f6f52 FB |
888 | return 0; |
889 | } | |
890 | ||
de91ea92 | 891 | void pci_dereg_ioat(S390PCIIOMMU *iommu) |
863f6f52 | 892 | { |
de91ea92 YMZ |
893 | s390_pci_iommu_disable(iommu); |
894 | iommu->pba = 0; | |
895 | iommu->pal = 0; | |
896 | iommu->g_iota = 0; | |
863f6f52 FB |
897 | } |
898 | ||
6e92c70c YMZ |
899 | void fmb_timer_free(S390PCIBusDevice *pbdev) |
900 | { | |
901 | if (pbdev->fmb_timer) { | |
902 | timer_del(pbdev->fmb_timer); | |
903 | timer_free(pbdev->fmb_timer); | |
904 | pbdev->fmb_timer = NULL; | |
905 | } | |
906 | pbdev->fmb_addr = 0; | |
907 | memset(&pbdev->fmb, 0, sizeof(ZpciFmb)); | |
908 | } | |
909 | ||
910 | static int fmb_do_update(S390PCIBusDevice *pbdev, int offset, uint64_t val, | |
911 | int len) | |
912 | { | |
913 | MemTxResult ret; | |
914 | uint64_t dst = pbdev->fmb_addr + offset; | |
915 | ||
916 | switch (len) { | |
917 | case 8: | |
918 | address_space_stq_be(&address_space_memory, dst, val, | |
919 | MEMTXATTRS_UNSPECIFIED, | |
920 | &ret); | |
921 | break; | |
922 | case 4: | |
923 | address_space_stl_be(&address_space_memory, dst, val, | |
924 | MEMTXATTRS_UNSPECIFIED, | |
925 | &ret); | |
926 | break; | |
927 | case 2: | |
928 | address_space_stw_be(&address_space_memory, dst, val, | |
929 | MEMTXATTRS_UNSPECIFIED, | |
930 | &ret); | |
931 | break; | |
932 | case 1: | |
933 | address_space_stb(&address_space_memory, dst, val, | |
934 | MEMTXATTRS_UNSPECIFIED, | |
935 | &ret); | |
936 | break; | |
937 | default: | |
938 | ret = MEMTX_ERROR; | |
939 | break; | |
940 | } | |
941 | if (ret != MEMTX_OK) { | |
942 | s390_pci_generate_error_event(ERR_EVENT_FMBA, pbdev->fh, pbdev->fid, | |
943 | pbdev->fmb_addr, 0); | |
944 | fmb_timer_free(pbdev); | |
945 | } | |
946 | ||
947 | return ret; | |
948 | } | |
949 | ||
950 | static void fmb_update(void *opaque) | |
951 | { | |
952 | S390PCIBusDevice *pbdev = opaque; | |
953 | int64_t t = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); | |
954 | int i; | |
955 | ||
956 | /* Update U bit */ | |
957 | pbdev->fmb.last_update *= 2; | |
958 | pbdev->fmb.last_update |= UPDATE_U_BIT; | |
959 | if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update), | |
960 | pbdev->fmb.last_update, | |
961 | sizeof(pbdev->fmb.last_update))) { | |
962 | return; | |
963 | } | |
964 | ||
965 | /* Update FMB sample count */ | |
966 | if (fmb_do_update(pbdev, offsetof(ZpciFmb, sample), | |
967 | pbdev->fmb.sample++, | |
968 | sizeof(pbdev->fmb.sample))) { | |
969 | return; | |
970 | } | |
971 | ||
972 | /* Update FMB counters */ | |
973 | for (i = 0; i < ZPCI_FMB_CNT_MAX; i++) { | |
974 | if (fmb_do_update(pbdev, offsetof(ZpciFmb, counter[i]), | |
975 | pbdev->fmb.counter[i], | |
976 | sizeof(pbdev->fmb.counter[0]))) { | |
977 | return; | |
978 | } | |
979 | } | |
980 | ||
981 | /* Clear U bit and update the time */ | |
982 | pbdev->fmb.last_update = time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); | |
983 | pbdev->fmb.last_update *= 2; | |
984 | if (fmb_do_update(pbdev, offsetof(ZpciFmb, last_update), | |
985 | pbdev->fmb.last_update, | |
986 | sizeof(pbdev->fmb.last_update))) { | |
987 | return; | |
988 | } | |
989 | timer_mod(pbdev->fmb_timer, t + DEFAULT_MUI); | |
990 | } | |
991 | ||
468a9389 DH |
992 | int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, |
993 | uintptr_t ra) | |
863f6f52 FB |
994 | { |
995 | CPUS390XState *env = &cpu->env; | |
a6d9d4f2 | 996 | uint8_t oc, dmaas; |
863f6f52 FB |
997 | uint32_t fh; |
998 | ZpciFib fib; | |
999 | S390PCIBusDevice *pbdev; | |
1000 | uint64_t cc = ZPCI_PCI_LS_OK; | |
1001 | ||
1002 | if (env->psw.mask & PSW_MASK_PSTATE) { | |
468a9389 | 1003 | s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); |
863f6f52 FB |
1004 | return 0; |
1005 | } | |
1006 | ||
1007 | oc = env->regs[r1] & 0xff; | |
a6d9d4f2 | 1008 | dmaas = (env->regs[r1] >> 16) & 0xff; |
863f6f52 FB |
1009 | fh = env->regs[r1] >> 32; |
1010 | ||
1011 | if (fiba & 0x7) { | |
468a9389 | 1012 | s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); |
863f6f52 FB |
1013 | return 0; |
1014 | } | |
1015 | ||
a975a24a | 1016 | pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); |
5d1abf23 | 1017 | if (!pbdev) { |
863f6f52 FB |
1018 | DPRINTF("mpcifc no pci dev fh 0x%x\n", fh); |
1019 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
1020 | return 0; | |
1021 | } | |
1022 | ||
5d1abf23 YMZ |
1023 | switch (pbdev->state) { |
1024 | case ZPCI_FS_RESERVED: | |
1025 | case ZPCI_FS_STANDBY: | |
1026 | case ZPCI_FS_DISABLED: | |
1027 | case ZPCI_FS_PERMANENT_ERROR: | |
1028 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
1029 | return 0; | |
1030 | default: | |
1031 | break; | |
1032 | } | |
1033 | ||
6cb1e49d | 1034 | if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { |
98ee9bed | 1035 | s390_cpu_virt_mem_handle_exc(cpu, ra); |
63ceef61 FB |
1036 | return 0; |
1037 | } | |
863f6f52 | 1038 | |
a6d9d4f2 | 1039 | if (fib.fmt != 0) { |
468a9389 | 1040 | s390_program_interrupt(env, PGM_OPERAND, 6, ra); |
a6d9d4f2 YMZ |
1041 | return 0; |
1042 | } | |
1043 | ||
863f6f52 FB |
1044 | switch (oc) { |
1045 | case ZPCI_MOD_FC_REG_INT: | |
a6d9d4f2 | 1046 | if (pbdev->summary_ind) { |
863f6f52 | 1047 | cc = ZPCI_PCI_LS_ERR; |
a6d9d4f2 YMZ |
1048 | s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); |
1049 | } else if (reg_irqs(env, pbdev, fib)) { | |
1050 | cc = ZPCI_PCI_LS_ERR; | |
1051 | s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL); | |
863f6f52 FB |
1052 | } |
1053 | break; | |
1054 | case ZPCI_MOD_FC_DEREG_INT: | |
a6d9d4f2 YMZ |
1055 | if (!pbdev->summary_ind) { |
1056 | cc = ZPCI_PCI_LS_ERR; | |
1057 | s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); | |
1058 | } else { | |
1059 | pci_dereg_irqs(pbdev); | |
1060 | } | |
863f6f52 FB |
1061 | break; |
1062 | case ZPCI_MOD_FC_REG_IOAT: | |
a6d9d4f2 | 1063 | if (dmaas != 0) { |
863f6f52 | 1064 | cc = ZPCI_PCI_LS_ERR; |
a6d9d4f2 | 1065 | s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); |
de91ea92 | 1066 | } else if (pbdev->iommu->enabled) { |
a6d9d4f2 YMZ |
1067 | cc = ZPCI_PCI_LS_ERR; |
1068 | s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); | |
468a9389 | 1069 | } else if (reg_ioat(env, pbdev->iommu, fib, ra)) { |
a6d9d4f2 YMZ |
1070 | cc = ZPCI_PCI_LS_ERR; |
1071 | s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); | |
863f6f52 FB |
1072 | } |
1073 | break; | |
1074 | case ZPCI_MOD_FC_DEREG_IOAT: | |
a6d9d4f2 YMZ |
1075 | if (dmaas != 0) { |
1076 | cc = ZPCI_PCI_LS_ERR; | |
1077 | s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); | |
de91ea92 | 1078 | } else if (!pbdev->iommu->enabled) { |
a6d9d4f2 YMZ |
1079 | cc = ZPCI_PCI_LS_ERR; |
1080 | s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); | |
1081 | } else { | |
de91ea92 | 1082 | pci_dereg_ioat(pbdev->iommu); |
a6d9d4f2 | 1083 | } |
863f6f52 FB |
1084 | break; |
1085 | case ZPCI_MOD_FC_REREG_IOAT: | |
a6d9d4f2 | 1086 | if (dmaas != 0) { |
863f6f52 | 1087 | cc = ZPCI_PCI_LS_ERR; |
a6d9d4f2 | 1088 | s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); |
de91ea92 | 1089 | } else if (!pbdev->iommu->enabled) { |
a6d9d4f2 YMZ |
1090 | cc = ZPCI_PCI_LS_ERR; |
1091 | s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); | |
1092 | } else { | |
de91ea92 | 1093 | pci_dereg_ioat(pbdev->iommu); |
468a9389 | 1094 | if (reg_ioat(env, pbdev->iommu, fib, ra)) { |
a6d9d4f2 YMZ |
1095 | cc = ZPCI_PCI_LS_ERR; |
1096 | s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); | |
1097 | } | |
863f6f52 FB |
1098 | } |
1099 | break; | |
1100 | case ZPCI_MOD_FC_RESET_ERROR: | |
5d1abf23 YMZ |
1101 | switch (pbdev->state) { |
1102 | case ZPCI_FS_BLOCKED: | |
1103 | case ZPCI_FS_ERROR: | |
1104 | pbdev->state = ZPCI_FS_ENABLED; | |
1105 | break; | |
1106 | default: | |
1107 | cc = ZPCI_PCI_LS_ERR; | |
1108 | s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); | |
1109 | } | |
863f6f52 FB |
1110 | break; |
1111 | case ZPCI_MOD_FC_RESET_BLOCK: | |
5d1abf23 YMZ |
1112 | switch (pbdev->state) { |
1113 | case ZPCI_FS_ERROR: | |
1114 | pbdev->state = ZPCI_FS_BLOCKED; | |
1115 | break; | |
1116 | default: | |
1117 | cc = ZPCI_PCI_LS_ERR; | |
1118 | s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); | |
1119 | } | |
863f6f52 | 1120 | break; |
6e92c70c YMZ |
1121 | case ZPCI_MOD_FC_SET_MEASURE: { |
1122 | uint64_t fmb_addr = ldq_p(&fib.fmb_addr); | |
1123 | ||
1124 | if (fmb_addr & FMBK_MASK) { | |
1125 | cc = ZPCI_PCI_LS_ERR; | |
1126 | s390_pci_generate_error_event(ERR_EVENT_FMBPRO, pbdev->fh, | |
1127 | pbdev->fid, fmb_addr, 0); | |
1128 | fmb_timer_free(pbdev); | |
1129 | break; | |
1130 | } | |
1131 | ||
1132 | if (!fmb_addr) { | |
1133 | /* Stop updating FMB. */ | |
1134 | fmb_timer_free(pbdev); | |
1135 | break; | |
1136 | } | |
1137 | ||
1138 | if (!pbdev->fmb_timer) { | |
1139 | pbdev->fmb_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, | |
1140 | fmb_update, pbdev); | |
1141 | } else if (timer_pending(pbdev->fmb_timer)) { | |
1142 | /* Remove pending timer to update FMB address. */ | |
1143 | timer_del(pbdev->fmb_timer); | |
1144 | } | |
1145 | pbdev->fmb_addr = fmb_addr; | |
1146 | timer_mod(pbdev->fmb_timer, | |
1147 | qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + DEFAULT_MUI); | |
863f6f52 | 1148 | break; |
6e92c70c | 1149 | } |
863f6f52 | 1150 | default: |
468a9389 | 1151 | s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra); |
863f6f52 FB |
1152 | cc = ZPCI_PCI_LS_ERR; |
1153 | } | |
1154 | ||
1155 | setcc(cpu, cc); | |
1156 | return 0; | |
1157 | } | |
1158 | ||
468a9389 DH |
1159 | int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, |
1160 | uintptr_t ra) | |
863f6f52 FB |
1161 | { |
1162 | CPUS390XState *env = &cpu->env; | |
0a608a6e | 1163 | uint8_t dmaas; |
863f6f52 FB |
1164 | uint32_t fh; |
1165 | ZpciFib fib; | |
1166 | S390PCIBusDevice *pbdev; | |
1167 | uint32_t data; | |
1168 | uint64_t cc = ZPCI_PCI_LS_OK; | |
1169 | ||
1170 | if (env->psw.mask & PSW_MASK_PSTATE) { | |
468a9389 | 1171 | s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); |
863f6f52 FB |
1172 | return 0; |
1173 | } | |
1174 | ||
1175 | fh = env->regs[r1] >> 32; | |
0a608a6e YMZ |
1176 | dmaas = (env->regs[r1] >> 16) & 0xff; |
1177 | ||
1178 | if (dmaas) { | |
1179 | setcc(cpu, ZPCI_PCI_LS_ERR); | |
1180 | s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS); | |
1181 | return 0; | |
1182 | } | |
863f6f52 FB |
1183 | |
1184 | if (fiba & 0x7) { | |
468a9389 | 1185 | s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); |
863f6f52 FB |
1186 | return 0; |
1187 | } | |
1188 | ||
a975a24a | 1189 | pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX); |
863f6f52 FB |
1190 | if (!pbdev) { |
1191 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | memset(&fib, 0, sizeof(fib)); | |
5d1abf23 YMZ |
1196 | |
1197 | switch (pbdev->state) { | |
1198 | case ZPCI_FS_RESERVED: | |
1199 | case ZPCI_FS_STANDBY: | |
1200 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
1201 | return 0; | |
1202 | case ZPCI_FS_DISABLED: | |
1203 | if (fh & FH_MASK_ENABLE) { | |
1204 | setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); | |
1205 | return 0; | |
1206 | } | |
1207 | goto out; | |
1208 | /* BLOCKED bit is set to one coincident with the setting of ERROR bit. | |
1209 | * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */ | |
1210 | case ZPCI_FS_ERROR: | |
1211 | fib.fc |= 0x20; | |
1212 | case ZPCI_FS_BLOCKED: | |
1213 | fib.fc |= 0x40; | |
1214 | case ZPCI_FS_ENABLED: | |
1215 | fib.fc |= 0x80; | |
de91ea92 | 1216 | if (pbdev->iommu->enabled) { |
5d1abf23 YMZ |
1217 | fib.fc |= 0x10; |
1218 | } | |
1219 | if (!(fh & FH_MASK_ENABLE)) { | |
1220 | env->regs[r1] |= 1ULL << 63; | |
1221 | } | |
1222 | break; | |
1223 | case ZPCI_FS_PERMANENT_ERROR: | |
1224 | setcc(cpu, ZPCI_PCI_LS_ERR); | |
1225 | s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR); | |
1226 | return 0; | |
1227 | } | |
1228 | ||
de91ea92 YMZ |
1229 | stq_p(&fib.pba, pbdev->iommu->pba); |
1230 | stq_p(&fib.pal, pbdev->iommu->pal); | |
1231 | stq_p(&fib.iota, pbdev->iommu->g_iota); | |
863f6f52 FB |
1232 | stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); |
1233 | stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); | |
1234 | stq_p(&fib.fmb_addr, pbdev->fmb_addr); | |
1235 | ||
c0eb33ab FB |
1236 | data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | |
1237 | ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | | |
1238 | ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; | |
1239 | stl_p(&fib.data, data); | |
863f6f52 | 1240 | |
5d1abf23 | 1241 | out: |
6cb1e49d | 1242 | if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { |
98ee9bed | 1243 | s390_cpu_virt_mem_handle_exc(cpu, ra); |
63ceef61 FB |
1244 | return 0; |
1245 | } | |
1246 | ||
863f6f52 FB |
1247 | setcc(cpu, cc); |
1248 | return 0; | |
1249 | } |