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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
fabaaf1d | 5 | * Copyright (c) 2012 Herve Poussineau |
5fafdf24 | 6 | * |
6f7e9aec FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
5d20fa6b | 25 | |
a4ab4792 | 26 | #include "qemu/osdep.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
64552b6b | 29 | #include "hw/irq.h" |
0d09e41a | 30 | #include "hw/scsi/esp.h" |
bf4b9889 | 31 | #include "trace.h" |
1de7afc9 | 32 | #include "qemu/log.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
6f7e9aec | 34 | |
67e999be | 35 | /* |
5ad6bb97 BS |
36 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
37 | * also produced as NCR89C100. See | |
67e999be FB |
38 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
39 | * and | |
40 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
74d71ea1 LV |
41 | * |
42 | * On Macintosh Quadra it is a NCR53C96. | |
67e999be FB |
43 | */ |
44 | ||
c73f96fd BS |
45 | static void esp_raise_irq(ESPState *s) |
46 | { | |
47 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
48 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
49 | qemu_irq_raise(s->irq); | |
bf4b9889 | 50 | trace_esp_raise_irq(); |
c73f96fd BS |
51 | } |
52 | } | |
53 | ||
54 | static void esp_lower_irq(ESPState *s) | |
55 | { | |
56 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
57 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
58 | qemu_irq_lower(s->irq); | |
bf4b9889 | 59 | trace_esp_lower_irq(); |
c73f96fd BS |
60 | } |
61 | } | |
62 | ||
74d71ea1 LV |
63 | static void esp_raise_drq(ESPState *s) |
64 | { | |
65 | qemu_irq_raise(s->irq_data); | |
960ebfd9 | 66 | trace_esp_raise_drq(); |
74d71ea1 LV |
67 | } |
68 | ||
69 | static void esp_lower_drq(ESPState *s) | |
70 | { | |
71 | qemu_irq_lower(s->irq_data); | |
960ebfd9 | 72 | trace_esp_lower_drq(); |
74d71ea1 LV |
73 | } |
74 | ||
9c7e23fc | 75 | void esp_dma_enable(ESPState *s, int irq, int level) |
73d74342 | 76 | { |
73d74342 BS |
77 | if (level) { |
78 | s->dma_enabled = 1; | |
bf4b9889 | 79 | trace_esp_dma_enable(); |
73d74342 BS |
80 | if (s->dma_cb) { |
81 | s->dma_cb(s); | |
82 | s->dma_cb = NULL; | |
83 | } | |
84 | } else { | |
bf4b9889 | 85 | trace_esp_dma_disable(); |
73d74342 BS |
86 | s->dma_enabled = 0; |
87 | } | |
88 | } | |
89 | ||
9c7e23fc | 90 | void esp_request_cancelled(SCSIRequest *req) |
94d3f98a | 91 | { |
e6810db8 | 92 | ESPState *s = req->hba_private; |
94d3f98a PB |
93 | |
94 | if (req == s->current_req) { | |
95 | scsi_req_unref(s->current_req); | |
96 | s->current_req = NULL; | |
97 | s->current_dev = NULL; | |
324c8809 | 98 | s->async_len = 0; |
94d3f98a PB |
99 | } |
100 | } | |
101 | ||
e5455b8c | 102 | static void esp_fifo_push(Fifo8 *fifo, uint8_t val) |
042879fc | 103 | { |
e5455b8c | 104 | if (fifo8_num_used(fifo) == fifo->capacity) { |
042879fc MCA |
105 | trace_esp_error_fifo_overrun(); |
106 | return; | |
107 | } | |
108 | ||
e5455b8c | 109 | fifo8_push(fifo, val); |
042879fc | 110 | } |
042879fc | 111 | |
c5fef911 | 112 | static uint8_t esp_fifo_pop(Fifo8 *fifo) |
023666da | 113 | { |
c5fef911 | 114 | if (fifo8_is_empty(fifo)) { |
023666da MCA |
115 | return 0; |
116 | } | |
117 | ||
c5fef911 | 118 | return fifo8_pop(fifo); |
023666da MCA |
119 | } |
120 | ||
7b320a8e MCA |
121 | static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) |
122 | { | |
123 | const uint8_t *buf; | |
124 | uint32_t n; | |
125 | ||
126 | if (maxlen == 0) { | |
127 | return 0; | |
128 | } | |
129 | ||
130 | buf = fifo8_pop_buf(fifo, maxlen, &n); | |
131 | if (dest) { | |
132 | memcpy(dest, buf, n); | |
133 | } | |
134 | ||
135 | return n; | |
136 | } | |
137 | ||
c47b5835 MCA |
138 | static uint32_t esp_get_tc(ESPState *s) |
139 | { | |
140 | uint32_t dmalen; | |
141 | ||
142 | dmalen = s->rregs[ESP_TCLO]; | |
143 | dmalen |= s->rregs[ESP_TCMID] << 8; | |
144 | dmalen |= s->rregs[ESP_TCHI] << 16; | |
145 | ||
146 | return dmalen; | |
147 | } | |
148 | ||
149 | static void esp_set_tc(ESPState *s, uint32_t dmalen) | |
150 | { | |
151 | s->rregs[ESP_TCLO] = dmalen; | |
152 | s->rregs[ESP_TCMID] = dmalen >> 8; | |
153 | s->rregs[ESP_TCHI] = dmalen >> 16; | |
154 | } | |
155 | ||
c04ed569 MCA |
156 | static uint32_t esp_get_stc(ESPState *s) |
157 | { | |
158 | uint32_t dmalen; | |
159 | ||
160 | dmalen = s->wregs[ESP_TCLO]; | |
161 | dmalen |= s->wregs[ESP_TCMID] << 8; | |
162 | dmalen |= s->wregs[ESP_TCHI] << 16; | |
163 | ||
164 | return dmalen; | |
165 | } | |
166 | ||
761bef75 MCA |
167 | static uint8_t esp_pdma_read(ESPState *s) |
168 | { | |
8da90e81 MCA |
169 | uint8_t val; |
170 | ||
43d02df3 | 171 | if (s->do_cmd) { |
c5fef911 | 172 | val = esp_fifo_pop(&s->cmdfifo); |
43d02df3 | 173 | } else { |
c5fef911 | 174 | val = esp_fifo_pop(&s->fifo); |
6e3fafa8 | 175 | } |
8da90e81 | 176 | |
8da90e81 | 177 | return val; |
761bef75 MCA |
178 | } |
179 | ||
180 | static void esp_pdma_write(ESPState *s, uint8_t val) | |
181 | { | |
8da90e81 MCA |
182 | uint32_t dmalen = esp_get_tc(s); |
183 | ||
3c421400 | 184 | if (dmalen == 0) { |
8da90e81 MCA |
185 | return; |
186 | } | |
187 | ||
43d02df3 | 188 | if (s->do_cmd) { |
e5455b8c | 189 | esp_fifo_push(&s->cmdfifo, val); |
43d02df3 | 190 | } else { |
e5455b8c | 191 | esp_fifo_push(&s->fifo, val); |
6e3fafa8 | 192 | } |
8da90e81 | 193 | |
8da90e81 MCA |
194 | dmalen--; |
195 | esp_set_tc(s, dmalen); | |
761bef75 MCA |
196 | } |
197 | ||
c7bce09c | 198 | static int esp_select(ESPState *s) |
6130b188 LV |
199 | { |
200 | int target; | |
201 | ||
202 | target = s->wregs[ESP_WBUSID] & BUSID_DID; | |
203 | ||
204 | s->ti_size = 0; | |
042879fc | 205 | fifo8_reset(&s->fifo); |
6130b188 LV |
206 | |
207 | if (s->current_req) { | |
208 | /* Started a new command before the old one finished. Cancel it. */ | |
209 | scsi_req_cancel(s->current_req); | |
6130b188 LV |
210 | } |
211 | ||
212 | s->current_dev = scsi_device_find(&s->bus, 0, target, 0); | |
213 | if (!s->current_dev) { | |
214 | /* No such drive */ | |
215 | s->rregs[ESP_RSTAT] = 0; | |
cf1a7a9b | 216 | s->rregs[ESP_RINTR] = INTR_DC; |
6130b188 LV |
217 | s->rregs[ESP_RSEQ] = SEQ_0; |
218 | esp_raise_irq(s); | |
219 | return -1; | |
220 | } | |
4e78f3bf MCA |
221 | |
222 | /* | |
223 | * Note that we deliberately don't raise the IRQ here: this will be done | |
4eb86065 | 224 | * either in do_command_phase() for DATA OUT transfers or by the deferred |
4e78f3bf MCA |
225 | * IRQ mechanism in esp_transfer_data() for DATA IN transfers |
226 | */ | |
227 | s->rregs[ESP_RINTR] |= INTR_FC; | |
228 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
6130b188 LV |
229 | return 0; |
230 | } | |
231 | ||
20c8d2ed | 232 | static uint32_t get_cmd(ESPState *s, uint32_t maxlen) |
2f275b8f | 233 | { |
023666da | 234 | uint8_t buf[ESP_CMDFIFO_SZ]; |
042879fc | 235 | uint32_t dmalen, n; |
2f275b8f FB |
236 | int target; |
237 | ||
8dea1dd4 | 238 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 239 | if (s->dma) { |
20c8d2ed MCA |
240 | dmalen = MIN(esp_get_tc(s), maxlen); |
241 | if (dmalen == 0) { | |
6c1fef6b PP |
242 | return 0; |
243 | } | |
74d71ea1 LV |
244 | if (s->dma_memory_read) { |
245 | s->dma_memory_read(s->dma_opaque, buf, dmalen); | |
fbc6510e | 246 | dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); |
023666da | 247 | fifo8_push_all(&s->cmdfifo, buf, dmalen); |
74d71ea1 | 248 | } else { |
49691315 | 249 | if (esp_select(s) < 0) { |
023666da | 250 | fifo8_reset(&s->cmdfifo); |
49691315 MCA |
251 | return -1; |
252 | } | |
74d71ea1 | 253 | esp_raise_drq(s); |
023666da | 254 | fifo8_reset(&s->cmdfifo); |
74d71ea1 LV |
255 | return 0; |
256 | } | |
4f6200f0 | 257 | } else { |
023666da | 258 | dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); |
20c8d2ed | 259 | if (dmalen == 0) { |
d3cdc491 PP |
260 | return 0; |
261 | } | |
7b320a8e | 262 | n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); |
fbc6510e | 263 | n = MIN(fifo8_num_free(&s->cmdfifo), n); |
7b320a8e | 264 | fifo8_push_all(&s->cmdfifo, buf, n); |
4f6200f0 | 265 | } |
bf4b9889 | 266 | trace_esp_get_cmd(dmalen, target); |
2e5d83bb | 267 | |
c7bce09c | 268 | if (esp_select(s) < 0) { |
023666da | 269 | fifo8_reset(&s->cmdfifo); |
49691315 | 270 | return -1; |
2f275b8f | 271 | } |
9f149aa9 PB |
272 | return dmalen; |
273 | } | |
274 | ||
4eb86065 | 275 | static void do_command_phase(ESPState *s) |
9f149aa9 | 276 | { |
7b320a8e | 277 | uint32_t cmdlen; |
9f149aa9 | 278 | int32_t datalen; |
f48a7a6e | 279 | SCSIDevice *current_lun; |
7b320a8e | 280 | uint8_t buf[ESP_CMDFIFO_SZ]; |
9f149aa9 | 281 | |
4eb86065 | 282 | trace_esp_do_command_phase(s->lun); |
023666da | 283 | cmdlen = fifo8_num_used(&s->cmdfifo); |
99545751 MCA |
284 | if (!cmdlen || !s->current_dev) { |
285 | return; | |
286 | } | |
7b320a8e | 287 | esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); |
023666da | 288 | |
4eb86065 PB |
289 | current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); |
290 | s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, s); | |
c39ce112 | 291 | datalen = scsi_req_enqueue(s->current_req); |
67e999be | 292 | s->ti_size = datalen; |
023666da | 293 | fifo8_reset(&s->cmdfifo); |
67e999be | 294 | if (datalen != 0) { |
c73f96fd | 295 | s->rregs[ESP_RSTAT] = STAT_TC; |
4e78f3bf | 296 | s->rregs[ESP_RSEQ] = SEQ_CD; |
1b9e48a5 | 297 | s->ti_cmd = 0; |
6cc88d6b | 298 | esp_set_tc(s, 0); |
2e5d83bb | 299 | if (datalen > 0) { |
4e78f3bf MCA |
300 | /* |
301 | * Switch to DATA IN phase but wait until initial data xfer is | |
302 | * complete before raising the command completion interrupt | |
303 | */ | |
304 | s->data_in_ready = false; | |
5ad6bb97 | 305 | s->rregs[ESP_RSTAT] |= STAT_DI; |
2e5d83bb | 306 | } else { |
5ad6bb97 | 307 | s->rregs[ESP_RSTAT] |= STAT_DO; |
4e78f3bf MCA |
308 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
309 | esp_raise_irq(s); | |
310 | esp_lower_drq(s); | |
b9788fc4 | 311 | } |
ad3376cc | 312 | scsi_req_continue(s->current_req); |
4e78f3bf | 313 | return; |
2f275b8f | 314 | } |
2f275b8f FB |
315 | } |
316 | ||
4eb86065 | 317 | static void do_message_phase(ESPState *s) |
f2818f22 | 318 | { |
4eb86065 PB |
319 | if (s->cmdfifo_cdb_offset) { |
320 | uint8_t message = esp_fifo_pop(&s->cmdfifo); | |
023666da | 321 | |
4eb86065 PB |
322 | trace_esp_do_identify(message); |
323 | s->lun = message & 7; | |
324 | s->cmdfifo_cdb_offset--; | |
325 | } | |
f2818f22 | 326 | |
799d90d8 | 327 | /* Ignore extended messages for now */ |
023666da | 328 | if (s->cmdfifo_cdb_offset) { |
4eb86065 | 329 | int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); |
fa7505c1 | 330 | esp_fifo_pop_buf(&s->cmdfifo, NULL, len); |
023666da MCA |
331 | s->cmdfifo_cdb_offset = 0; |
332 | } | |
4eb86065 | 333 | } |
023666da | 334 | |
4eb86065 PB |
335 | static void do_cmd(ESPState *s) |
336 | { | |
337 | do_message_phase(s); | |
338 | assert(s->cmdfifo_cdb_offset == 0); | |
339 | do_command_phase(s); | |
f2818f22 AT |
340 | } |
341 | ||
74d71ea1 LV |
342 | static void satn_pdma_cb(ESPState *s) |
343 | { | |
e62a959a | 344 | if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { |
023666da | 345 | s->cmdfifo_cdb_offset = 1; |
e62a959a | 346 | s->do_cmd = 0; |
c959f218 | 347 | do_cmd(s); |
74d71ea1 LV |
348 | } |
349 | } | |
350 | ||
9f149aa9 PB |
351 | static void handle_satn(ESPState *s) |
352 | { | |
49691315 MCA |
353 | int32_t cmdlen; |
354 | ||
1b26eaa1 | 355 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
356 | s->dma_cb = handle_satn; |
357 | return; | |
358 | } | |
74d71ea1 | 359 | s->pdma_cb = satn_pdma_cb; |
023666da | 360 | cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); |
49691315 | 361 | if (cmdlen > 0) { |
023666da | 362 | s->cmdfifo_cdb_offset = 1; |
60720694 | 363 | s->do_cmd = 0; |
c959f218 | 364 | do_cmd(s); |
49691315 | 365 | } else if (cmdlen == 0) { |
bb0bc7bb | 366 | s->do_cmd = 1; |
49691315 MCA |
367 | /* Target present, but no cmd yet - switch to command phase */ |
368 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
369 | s->rregs[ESP_RSTAT] = STAT_CD; | |
94d5c79d | 370 | } |
9f149aa9 PB |
371 | } |
372 | ||
74d71ea1 LV |
373 | static void s_without_satn_pdma_cb(ESPState *s) |
374 | { | |
e62a959a | 375 | if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { |
023666da | 376 | s->cmdfifo_cdb_offset = 0; |
e62a959a | 377 | s->do_cmd = 0; |
4eb86065 | 378 | do_cmd(s); |
74d71ea1 LV |
379 | } |
380 | } | |
381 | ||
f2818f22 AT |
382 | static void handle_s_without_atn(ESPState *s) |
383 | { | |
49691315 MCA |
384 | int32_t cmdlen; |
385 | ||
1b26eaa1 | 386 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
387 | s->dma_cb = handle_s_without_atn; |
388 | return; | |
389 | } | |
74d71ea1 | 390 | s->pdma_cb = s_without_satn_pdma_cb; |
023666da | 391 | cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); |
49691315 | 392 | if (cmdlen > 0) { |
023666da | 393 | s->cmdfifo_cdb_offset = 0; |
60720694 | 394 | s->do_cmd = 0; |
4eb86065 | 395 | do_cmd(s); |
49691315 | 396 | } else if (cmdlen == 0) { |
bb0bc7bb | 397 | s->do_cmd = 1; |
49691315 MCA |
398 | /* Target present, but no cmd yet - switch to command phase */ |
399 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
400 | s->rregs[ESP_RSTAT] = STAT_CD; | |
f2818f22 AT |
401 | } |
402 | } | |
403 | ||
74d71ea1 LV |
404 | static void satn_stop_pdma_cb(ESPState *s) |
405 | { | |
e62a959a | 406 | if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { |
023666da | 407 | trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); |
74d71ea1 | 408 | s->do_cmd = 1; |
023666da | 409 | s->cmdfifo_cdb_offset = 1; |
74d71ea1 | 410 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
cf47a41e | 411 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
412 | s->rregs[ESP_RSEQ] = SEQ_CD; |
413 | esp_raise_irq(s); | |
414 | } | |
415 | } | |
416 | ||
9f149aa9 PB |
417 | static void handle_satn_stop(ESPState *s) |
418 | { | |
49691315 MCA |
419 | int32_t cmdlen; |
420 | ||
1b26eaa1 | 421 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
422 | s->dma_cb = handle_satn_stop; |
423 | return; | |
424 | } | |
c62c1fa0 | 425 | s->pdma_cb = satn_stop_pdma_cb; |
799d90d8 | 426 | cmdlen = get_cmd(s, 1); |
49691315 | 427 | if (cmdlen > 0) { |
023666da | 428 | trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); |
9f149aa9 | 429 | s->do_cmd = 1; |
023666da | 430 | s->cmdfifo_cdb_offset = 1; |
799d90d8 | 431 | s->rregs[ESP_RSTAT] = STAT_MO; |
cf47a41e | 432 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
799d90d8 | 433 | s->rregs[ESP_RSEQ] = SEQ_MO; |
c73f96fd | 434 | esp_raise_irq(s); |
49691315 | 435 | } else if (cmdlen == 0) { |
bb0bc7bb | 436 | s->do_cmd = 1; |
799d90d8 MCA |
437 | /* Target present, switch to message out phase */ |
438 | s->rregs[ESP_RSEQ] = SEQ_MO; | |
439 | s->rregs[ESP_RSTAT] = STAT_MO; | |
9f149aa9 PB |
440 | } |
441 | } | |
442 | ||
74d71ea1 LV |
443 | static void write_response_pdma_cb(ESPState *s) |
444 | { | |
445 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
cf47a41e | 446 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
447 | s->rregs[ESP_RSEQ] = SEQ_CD; |
448 | esp_raise_irq(s); | |
449 | } | |
450 | ||
0fc5c15a | 451 | static void write_response(ESPState *s) |
2f275b8f | 452 | { |
e3922557 | 453 | uint8_t buf[2]; |
042879fc | 454 | |
bf4b9889 | 455 | trace_esp_write_response(s->status); |
042879fc | 456 | |
e3922557 MCA |
457 | buf[0] = s->status; |
458 | buf[1] = 0; | |
042879fc | 459 | |
4f6200f0 | 460 | if (s->dma) { |
74d71ea1 | 461 | if (s->dma_memory_write) { |
e3922557 | 462 | s->dma_memory_write(s->dma_opaque, buf, 2); |
74d71ea1 | 463 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
cf47a41e | 464 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
465 | s->rregs[ESP_RSEQ] = SEQ_CD; |
466 | } else { | |
74d71ea1 LV |
467 | s->pdma_cb = write_response_pdma_cb; |
468 | esp_raise_drq(s); | |
469 | return; | |
470 | } | |
4f6200f0 | 471 | } else { |
e3922557 MCA |
472 | fifo8_reset(&s->fifo); |
473 | fifo8_push_all(&s->fifo, buf, 2); | |
5ad6bb97 | 474 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 475 | } |
c73f96fd | 476 | esp_raise_irq(s); |
2f275b8f | 477 | } |
4f6200f0 | 478 | |
a917d384 PB |
479 | static void esp_dma_done(ESPState *s) |
480 | { | |
c73f96fd | 481 | s->rregs[ESP_RSTAT] |= STAT_TC; |
cf47a41e | 482 | s->rregs[ESP_RINTR] |= INTR_BS; |
5ad6bb97 | 483 | s->rregs[ESP_RFLAGS] = 0; |
c47b5835 | 484 | esp_set_tc(s, 0); |
c73f96fd | 485 | esp_raise_irq(s); |
a917d384 PB |
486 | } |
487 | ||
74d71ea1 LV |
488 | static void do_dma_pdma_cb(ESPState *s) |
489 | { | |
4ca2ba6f | 490 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
82141c8b | 491 | int len; |
042879fc | 492 | uint32_t n; |
6cc88d6b | 493 | |
74d71ea1 | 494 | if (s->do_cmd) { |
e62a959a MCA |
495 | /* Ensure we have received complete command after SATN and stop */ |
496 | if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { | |
497 | return; | |
498 | } | |
499 | ||
74d71ea1 | 500 | s->ti_size = 0; |
c348458f MCA |
501 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { |
502 | /* No command received */ | |
503 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { | |
504 | return; | |
505 | } | |
506 | ||
507 | /* Command has been received */ | |
508 | s->do_cmd = 0; | |
509 | do_cmd(s); | |
510 | } else { | |
511 | /* | |
512 | * Extra message out bytes received: update cmdfifo_cdb_offset | |
513 | * and then switch to commmand phase | |
514 | */ | |
515 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); | |
516 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; | |
517 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
518 | s->rregs[ESP_RINTR] |= INTR_BS; | |
519 | esp_raise_irq(s); | |
520 | } | |
74d71ea1 LV |
521 | return; |
522 | } | |
82141c8b | 523 | |
0db89536 MCA |
524 | if (!s->current_req) { |
525 | return; | |
526 | } | |
527 | ||
82141c8b MCA |
528 | if (to_device) { |
529 | /* Copy FIFO data to device */ | |
7aa6baee MCA |
530 | len = MIN(s->async_len, ESP_FIFO_SZ); |
531 | len = MIN(len, fifo8_num_used(&s->fifo)); | |
7b320a8e | 532 | n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
7aa6baee MCA |
533 | s->async_buf += n; |
534 | s->async_len -= n; | |
535 | s->ti_size += n; | |
536 | ||
537 | if (n < len) { | |
538 | /* Unaligned accesses can cause FIFO wraparound */ | |
539 | len = len - n; | |
7b320a8e | 540 | n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
7aa6baee MCA |
541 | s->async_buf += n; |
542 | s->async_len -= n; | |
543 | s->ti_size += n; | |
544 | } | |
545 | ||
82141c8b MCA |
546 | if (s->async_len == 0) { |
547 | scsi_req_continue(s->current_req); | |
74d71ea1 LV |
548 | return; |
549 | } | |
74d71ea1 | 550 | |
82141c8b MCA |
551 | if (esp_get_tc(s) == 0) { |
552 | esp_lower_drq(s); | |
553 | esp_dma_done(s); | |
554 | } | |
555 | ||
556 | return; | |
557 | } else { | |
558 | if (s->async_len == 0) { | |
0db89536 MCA |
559 | /* Defer until the scsi layer has completed */ |
560 | scsi_req_continue(s->current_req); | |
561 | s->data_in_ready = false; | |
4e78f3bf | 562 | return; |
82141c8b MCA |
563 | } |
564 | ||
565 | if (esp_get_tc(s) != 0) { | |
566 | /* Copy device data to FIFO */ | |
7aa6baee MCA |
567 | len = MIN(s->async_len, esp_get_tc(s)); |
568 | len = MIN(len, fifo8_num_free(&s->fifo)); | |
042879fc | 569 | fifo8_push_all(&s->fifo, s->async_buf, len); |
82141c8b MCA |
570 | s->async_buf += len; |
571 | s->async_len -= len; | |
572 | s->ti_size -= len; | |
573 | esp_set_tc(s, esp_get_tc(s) - len); | |
7aa6baee MCA |
574 | |
575 | if (esp_get_tc(s) == 0) { | |
576 | /* Indicate transfer to FIFO is complete */ | |
577 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
578 | } | |
82141c8b MCA |
579 | return; |
580 | } | |
581 | ||
582 | /* Partially filled a scsi buffer. Complete immediately. */ | |
583 | esp_lower_drq(s); | |
584 | esp_dma_done(s); | |
585 | } | |
74d71ea1 LV |
586 | } |
587 | ||
4d611c9a PB |
588 | static void esp_do_dma(ESPState *s) |
589 | { | |
023666da | 590 | uint32_t len, cmdlen; |
4ca2ba6f | 591 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
023666da | 592 | uint8_t buf[ESP_CMDFIFO_SZ]; |
a917d384 | 593 | |
6cc88d6b | 594 | len = esp_get_tc(s); |
4d611c9a | 595 | if (s->do_cmd) { |
15407433 LV |
596 | /* |
597 | * handle_ti_cmd() case: esp_do_dma() is called only from | |
598 | * handle_ti_cmd() with do_cmd != NULL (see the assert()) | |
599 | */ | |
023666da MCA |
600 | cmdlen = fifo8_num_used(&s->cmdfifo); |
601 | trace_esp_do_dma(cmdlen, len); | |
74d71ea1 | 602 | if (s->dma_memory_read) { |
0ebb5fd8 | 603 | len = MIN(len, fifo8_num_free(&s->cmdfifo)); |
023666da MCA |
604 | s->dma_memory_read(s->dma_opaque, buf, len); |
605 | fifo8_push_all(&s->cmdfifo, buf, len); | |
74d71ea1 | 606 | } else { |
74d71ea1 LV |
607 | s->pdma_cb = do_dma_pdma_cb; |
608 | esp_raise_drq(s); | |
609 | return; | |
610 | } | |
023666da | 611 | trace_esp_handle_ti_cmd(cmdlen); |
15407433 | 612 | s->ti_size = 0; |
799d90d8 MCA |
613 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { |
614 | /* No command received */ | |
023666da | 615 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { |
799d90d8 MCA |
616 | return; |
617 | } | |
618 | ||
619 | /* Command has been received */ | |
799d90d8 MCA |
620 | s->do_cmd = 0; |
621 | do_cmd(s); | |
622 | } else { | |
623 | /* | |
023666da | 624 | * Extra message out bytes received: update cmdfifo_cdb_offset |
799d90d8 MCA |
625 | * and then switch to commmand phase |
626 | */ | |
023666da | 627 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); |
799d90d8 MCA |
628 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
629 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
630 | s->rregs[ESP_RINTR] |= INTR_BS; | |
631 | esp_raise_irq(s); | |
632 | } | |
4d611c9a | 633 | return; |
a917d384 | 634 | } |
0db89536 MCA |
635 | if (!s->current_req) { |
636 | return; | |
637 | } | |
a917d384 PB |
638 | if (s->async_len == 0) { |
639 | /* Defer until data is available. */ | |
640 | return; | |
641 | } | |
642 | if (len > s->async_len) { | |
643 | len = s->async_len; | |
644 | } | |
645 | if (to_device) { | |
74d71ea1 LV |
646 | if (s->dma_memory_read) { |
647 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); | |
648 | } else { | |
74d71ea1 LV |
649 | s->pdma_cb = do_dma_pdma_cb; |
650 | esp_raise_drq(s); | |
651 | return; | |
652 | } | |
4d611c9a | 653 | } else { |
74d71ea1 LV |
654 | if (s->dma_memory_write) { |
655 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); | |
656 | } else { | |
7aa6baee MCA |
657 | /* Adjust TC for any leftover data in the FIFO */ |
658 | if (!fifo8_is_empty(&s->fifo)) { | |
659 | esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); | |
660 | } | |
661 | ||
82141c8b | 662 | /* Copy device data to FIFO */ |
042879fc MCA |
663 | len = MIN(len, fifo8_num_free(&s->fifo)); |
664 | fifo8_push_all(&s->fifo, s->async_buf, len); | |
82141c8b MCA |
665 | s->async_buf += len; |
666 | s->async_len -= len; | |
667 | s->ti_size -= len; | |
7aa6baee MCA |
668 | |
669 | /* | |
670 | * MacOS toolbox uses a TI length of 16 bytes for all commands, so | |
671 | * commands shorter than this must be padded accordingly | |
672 | */ | |
673 | if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) { | |
674 | while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) { | |
e5455b8c | 675 | esp_fifo_push(&s->fifo, 0); |
7aa6baee MCA |
676 | len++; |
677 | } | |
678 | } | |
679 | ||
82141c8b | 680 | esp_set_tc(s, esp_get_tc(s) - len); |
74d71ea1 LV |
681 | s->pdma_cb = do_dma_pdma_cb; |
682 | esp_raise_drq(s); | |
82141c8b MCA |
683 | |
684 | /* Indicate transfer to FIFO is complete */ | |
685 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
74d71ea1 LV |
686 | return; |
687 | } | |
a917d384 | 688 | } |
6cc88d6b | 689 | esp_set_tc(s, esp_get_tc(s) - len); |
a917d384 PB |
690 | s->async_buf += len; |
691 | s->async_len -= len; | |
94d5c79d | 692 | if (to_device) { |
6787f5fa | 693 | s->ti_size += len; |
94d5c79d | 694 | } else { |
6787f5fa | 695 | s->ti_size -= len; |
94d5c79d | 696 | } |
a917d384 | 697 | if (s->async_len == 0) { |
ad3376cc | 698 | scsi_req_continue(s->current_req); |
94d5c79d MCA |
699 | /* |
700 | * If there is still data to be read from the device then | |
701 | * complete the DMA operation immediately. Otherwise defer | |
702 | * until the scsi layer has completed. | |
703 | */ | |
6cc88d6b | 704 | if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) { |
ad3376cc | 705 | return; |
4d611c9a | 706 | } |
a917d384 | 707 | } |
ad3376cc PB |
708 | |
709 | /* Partially filled a scsi buffer. Complete immediately. */ | |
710 | esp_dma_done(s); | |
82141c8b | 711 | esp_lower_drq(s); |
4d611c9a PB |
712 | } |
713 | ||
1b9e48a5 MCA |
714 | static void esp_do_nodma(ESPState *s) |
715 | { | |
716 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); | |
7b320a8e | 717 | uint32_t cmdlen; |
1b9e48a5 MCA |
718 | int len; |
719 | ||
720 | if (s->do_cmd) { | |
721 | cmdlen = fifo8_num_used(&s->cmdfifo); | |
722 | trace_esp_handle_ti_cmd(cmdlen); | |
723 | s->ti_size = 0; | |
724 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { | |
725 | /* No command received */ | |
726 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { | |
727 | return; | |
728 | } | |
729 | ||
730 | /* Command has been received */ | |
731 | s->do_cmd = 0; | |
732 | do_cmd(s); | |
733 | } else { | |
734 | /* | |
735 | * Extra message out bytes received: update cmdfifo_cdb_offset | |
736 | * and then switch to commmand phase | |
737 | */ | |
738 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); | |
739 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; | |
740 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
741 | s->rregs[ESP_RINTR] |= INTR_BS; | |
742 | esp_raise_irq(s); | |
743 | } | |
744 | return; | |
745 | } | |
746 | ||
0db89536 MCA |
747 | if (!s->current_req) { |
748 | return; | |
749 | } | |
750 | ||
1b9e48a5 MCA |
751 | if (s->async_len == 0) { |
752 | /* Defer until data is available. */ | |
753 | return; | |
754 | } | |
755 | ||
756 | if (to_device) { | |
757 | len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ); | |
7b320a8e | 758 | esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
1b9e48a5 MCA |
759 | s->async_buf += len; |
760 | s->async_len -= len; | |
761 | s->ti_size += len; | |
762 | } else { | |
6ef2cabc MCA |
763 | if (fifo8_is_empty(&s->fifo)) { |
764 | fifo8_push(&s->fifo, s->async_buf[0]); | |
765 | s->async_buf++; | |
766 | s->async_len--; | |
767 | s->ti_size--; | |
768 | } | |
1b9e48a5 MCA |
769 | } |
770 | ||
771 | if (s->async_len == 0) { | |
772 | scsi_req_continue(s->current_req); | |
6ef2cabc | 773 | return; |
1b9e48a5 MCA |
774 | } |
775 | ||
776 | s->rregs[ESP_RINTR] |= INTR_BS; | |
777 | esp_raise_irq(s); | |
778 | } | |
779 | ||
4aaa6ac3 | 780 | void esp_command_complete(SCSIRequest *req, size_t resid) |
2e5d83bb | 781 | { |
4aaa6ac3 | 782 | ESPState *s = req->hba_private; |
6ef2cabc | 783 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
4aaa6ac3 | 784 | |
bf4b9889 | 785 | trace_esp_command_complete(); |
6ef2cabc MCA |
786 | |
787 | /* | |
788 | * Non-DMA transfers from the target will leave the last byte in | |
789 | * the FIFO so don't reset ti_size in this case | |
790 | */ | |
791 | if (s->dma || to_device) { | |
792 | if (s->ti_size != 0) { | |
793 | trace_esp_command_complete_unexpected(); | |
794 | } | |
795 | s->ti_size = 0; | |
c6df7102 | 796 | } |
6ef2cabc | 797 | |
c6df7102 | 798 | s->async_len = 0; |
4aaa6ac3 | 799 | if (req->status) { |
bf4b9889 | 800 | trace_esp_command_complete_fail(); |
c6df7102 | 801 | } |
4aaa6ac3 | 802 | s->status = req->status; |
6ef2cabc MCA |
803 | |
804 | /* | |
805 | * If the transfer is finished, switch to status phase. For non-DMA | |
806 | * transfers from the target the last byte is still in the FIFO | |
807 | */ | |
808 | if (s->ti_size == 0) { | |
809 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
810 | esp_dma_done(s); | |
811 | esp_lower_drq(s); | |
812 | } | |
813 | ||
c6df7102 PB |
814 | if (s->current_req) { |
815 | scsi_req_unref(s->current_req); | |
816 | s->current_req = NULL; | |
817 | s->current_dev = NULL; | |
818 | } | |
819 | } | |
820 | ||
9c7e23fc | 821 | void esp_transfer_data(SCSIRequest *req, uint32_t len) |
c6df7102 | 822 | { |
e6810db8 | 823 | ESPState *s = req->hba_private; |
4e78f3bf | 824 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
6cc88d6b | 825 | uint32_t dmalen = esp_get_tc(s); |
c6df7102 | 826 | |
7f0b6e11 | 827 | assert(!s->do_cmd); |
6cc88d6b | 828 | trace_esp_transfer_data(dmalen, s->ti_size); |
aba1f023 | 829 | s->async_len = len; |
c6df7102 | 830 | s->async_buf = scsi_req_get_buf(req); |
4e78f3bf MCA |
831 | |
832 | if (!to_device && !s->data_in_ready) { | |
833 | /* | |
834 | * Initial incoming data xfer is complete so raise command | |
835 | * completion interrupt | |
836 | */ | |
837 | s->data_in_ready = true; | |
838 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
839 | s->rregs[ESP_RINTR] |= INTR_BS; | |
840 | esp_raise_irq(s); | |
4e78f3bf MCA |
841 | } |
842 | ||
1b9e48a5 | 843 | if (s->ti_cmd == 0) { |
94d5c79d | 844 | /* |
1b9e48a5 MCA |
845 | * Always perform the initial transfer upon reception of the next TI |
846 | * command to ensure the DMA/non-DMA status of the command is correct. | |
847 | * It is not possible to use s->dma directly in the section below as | |
848 | * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the | |
849 | * async data transfer is delayed then s->dma is set incorrectly. | |
94d5c79d | 850 | */ |
1b9e48a5 MCA |
851 | return; |
852 | } | |
853 | ||
880d3089 | 854 | if (s->ti_cmd == (CMD_TI | CMD_DMA)) { |
1b9e48a5 MCA |
855 | if (dmalen) { |
856 | esp_do_dma(s); | |
857 | } else if (s->ti_size <= 0) { | |
858 | /* | |
859 | * If this was the last part of a DMA transfer then the | |
860 | * completion interrupt is deferred to here. | |
861 | */ | |
862 | esp_dma_done(s); | |
863 | esp_lower_drq(s); | |
864 | } | |
880d3089 | 865 | } else if (s->ti_cmd == CMD_TI) { |
1b9e48a5 | 866 | esp_do_nodma(s); |
4d611c9a | 867 | } |
2e5d83bb PB |
868 | } |
869 | ||
2f275b8f FB |
870 | static void handle_ti(ESPState *s) |
871 | { | |
1b9e48a5 | 872 | uint32_t dmalen; |
2f275b8f | 873 | |
7246e160 HP |
874 | if (s->dma && !s->dma_enabled) { |
875 | s->dma_cb = handle_ti; | |
876 | return; | |
877 | } | |
878 | ||
1b9e48a5 | 879 | s->ti_cmd = s->rregs[ESP_CMD]; |
4f6200f0 | 880 | if (s->dma) { |
1b9e48a5 | 881 | dmalen = esp_get_tc(s); |
b76624de | 882 | trace_esp_handle_ti(dmalen); |
5ad6bb97 | 883 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 884 | esp_do_dma(s); |
1b9e48a5 MCA |
885 | } else { |
886 | trace_esp_handle_ti(s->ti_size); | |
887 | esp_do_nodma(s); | |
9f149aa9 | 888 | } |
2f275b8f FB |
889 | } |
890 | ||
9c7e23fc | 891 | void esp_hard_reset(ESPState *s) |
6f7e9aec | 892 | { |
5aca8c3b BS |
893 | memset(s->rregs, 0, ESP_REGS); |
894 | memset(s->wregs, 0, ESP_REGS); | |
c9cf45c1 | 895 | s->tchi_written = 0; |
4e9aec74 | 896 | s->ti_size = 0; |
042879fc | 897 | fifo8_reset(&s->fifo); |
023666da | 898 | fifo8_reset(&s->cmdfifo); |
4e9aec74 | 899 | s->dma = 0; |
9f149aa9 | 900 | s->do_cmd = 0; |
73d74342 | 901 | s->dma_cb = NULL; |
8dea1dd4 BS |
902 | |
903 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
904 | } |
905 | ||
a391fdbc | 906 | static void esp_soft_reset(ESPState *s) |
85948643 | 907 | { |
85948643 | 908 | qemu_irq_lower(s->irq); |
74d71ea1 | 909 | qemu_irq_lower(s->irq_data); |
a391fdbc | 910 | esp_hard_reset(s); |
85948643 BS |
911 | } |
912 | ||
a391fdbc | 913 | static void parent_esp_reset(ESPState *s, int irq, int level) |
2d069bab | 914 | { |
85948643 | 915 | if (level) { |
a391fdbc | 916 | esp_soft_reset(s); |
85948643 | 917 | } |
2d069bab BS |
918 | } |
919 | ||
9c7e23fc | 920 | uint64_t esp_reg_read(ESPState *s, uint32_t saddr) |
73d74342 | 921 | { |
b630c075 | 922 | uint32_t val; |
73d74342 | 923 | |
6f7e9aec | 924 | switch (saddr) { |
5ad6bb97 | 925 | case ESP_FIFO: |
1b9e48a5 MCA |
926 | if (s->dma_memory_read && s->dma_memory_write && |
927 | (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { | |
ff589551 PP |
928 | /* Data out. */ |
929 | qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); | |
930 | s->rregs[ESP_FIFO] = 0; | |
042879fc | 931 | } else { |
6ef2cabc MCA |
932 | if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { |
933 | if (s->ti_size) { | |
934 | esp_do_nodma(s); | |
935 | } else { | |
936 | /* | |
937 | * The last byte of a non-DMA transfer has been read out | |
938 | * of the FIFO so switch to status phase | |
939 | */ | |
940 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
941 | } | |
942 | } | |
c5fef911 | 943 | s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); |
4f6200f0 | 944 | } |
b630c075 | 945 | val = s->rregs[ESP_FIFO]; |
f930d07e | 946 | break; |
5ad6bb97 | 947 | case ESP_RINTR: |
94d5c79d MCA |
948 | /* |
949 | * Clear sequence step, interrupt register and all status bits | |
950 | * except TC | |
951 | */ | |
b630c075 | 952 | val = s->rregs[ESP_RINTR]; |
2814df28 BS |
953 | s->rregs[ESP_RINTR] = 0; |
954 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
af947a3d MCA |
955 | /* |
956 | * According to the datasheet ESP_RSEQ should be cleared, but as the | |
957 | * emulation currently defers information transfers to the next TI | |
958 | * command leave it for now so that pedantic guests such as the old | |
959 | * Linux 2.6 driver see the correct flags before the next SCSI phase | |
960 | * transition. | |
961 | * | |
962 | * s->rregs[ESP_RSEQ] = SEQ_0; | |
963 | */ | |
c73f96fd | 964 | esp_lower_irq(s); |
b630c075 | 965 | break; |
c9cf45c1 HR |
966 | case ESP_TCHI: |
967 | /* Return the unique id if the value has never been written */ | |
968 | if (!s->tchi_written) { | |
b630c075 MCA |
969 | val = s->chip_id; |
970 | } else { | |
971 | val = s->rregs[saddr]; | |
c9cf45c1 | 972 | } |
b630c075 | 973 | break; |
238ec4d7 MCA |
974 | case ESP_RFLAGS: |
975 | /* Bottom 5 bits indicate number of bytes in FIFO */ | |
976 | val = fifo8_num_used(&s->fifo); | |
977 | break; | |
6f7e9aec | 978 | default: |
b630c075 | 979 | val = s->rregs[saddr]; |
f930d07e | 980 | break; |
6f7e9aec | 981 | } |
b630c075 MCA |
982 | |
983 | trace_esp_mem_readb(saddr, val); | |
984 | return val; | |
6f7e9aec FB |
985 | } |
986 | ||
9c7e23fc | 987 | void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) |
6f7e9aec | 988 | { |
bf4b9889 | 989 | trace_esp_mem_writeb(saddr, s->wregs[saddr], val); |
6f7e9aec | 990 | switch (saddr) { |
c9cf45c1 HR |
991 | case ESP_TCHI: |
992 | s->tchi_written = true; | |
993 | /* fall through */ | |
5ad6bb97 BS |
994 | case ESP_TCLO: |
995 | case ESP_TCMID: | |
996 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 997 | break; |
5ad6bb97 | 998 | case ESP_FIFO: |
9f149aa9 | 999 | if (s->do_cmd) { |
e5455b8c | 1000 | esp_fifo_push(&s->cmdfifo, val); |
6ef2cabc MCA |
1001 | |
1002 | /* | |
1003 | * If any unexpected message out/command phase data is | |
1004 | * transferred using non-DMA, raise the interrupt | |
1005 | */ | |
1006 | if (s->rregs[ESP_CMD] == CMD_TI) { | |
1007 | s->rregs[ESP_RINTR] |= INTR_BS; | |
1008 | esp_raise_irq(s); | |
1009 | } | |
2e5d83bb | 1010 | } else { |
e5455b8c | 1011 | esp_fifo_push(&s->fifo, val); |
2e5d83bb | 1012 | } |
f930d07e | 1013 | break; |
5ad6bb97 | 1014 | case ESP_CMD: |
4f6200f0 | 1015 | s->rregs[saddr] = val; |
5ad6bb97 | 1016 | if (val & CMD_DMA) { |
f930d07e | 1017 | s->dma = 1; |
6787f5fa | 1018 | /* Reload DMA counter. */ |
96676c2f MCA |
1019 | if (esp_get_stc(s) == 0) { |
1020 | esp_set_tc(s, 0x10000); | |
1021 | } else { | |
1022 | esp_set_tc(s, esp_get_stc(s)); | |
1023 | } | |
f930d07e BS |
1024 | } else { |
1025 | s->dma = 0; | |
1026 | } | |
94d5c79d | 1027 | switch (val & CMD_CMD) { |
5ad6bb97 | 1028 | case CMD_NOP: |
bf4b9889 | 1029 | trace_esp_mem_writeb_cmd_nop(val); |
f930d07e | 1030 | break; |
5ad6bb97 | 1031 | case CMD_FLUSH: |
bf4b9889 | 1032 | trace_esp_mem_writeb_cmd_flush(val); |
042879fc | 1033 | fifo8_reset(&s->fifo); |
f930d07e | 1034 | break; |
5ad6bb97 | 1035 | case CMD_RESET: |
bf4b9889 | 1036 | trace_esp_mem_writeb_cmd_reset(val); |
a391fdbc | 1037 | esp_soft_reset(s); |
f930d07e | 1038 | break; |
5ad6bb97 | 1039 | case CMD_BUSRESET: |
bf4b9889 | 1040 | trace_esp_mem_writeb_cmd_bus_reset(val); |
5ad6bb97 | 1041 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { |
cf47a41e | 1042 | s->rregs[ESP_RINTR] |= INTR_RST; |
c73f96fd | 1043 | esp_raise_irq(s); |
9e61bde5 | 1044 | } |
f930d07e | 1045 | break; |
5ad6bb97 | 1046 | case CMD_TI: |
0097d3ec | 1047 | trace_esp_mem_writeb_cmd_ti(val); |
f930d07e BS |
1048 | handle_ti(s); |
1049 | break; | |
5ad6bb97 | 1050 | case CMD_ICCS: |
bf4b9889 | 1051 | trace_esp_mem_writeb_cmd_iccs(val); |
f930d07e | 1052 | write_response(s); |
cf47a41e | 1053 | s->rregs[ESP_RINTR] |= INTR_FC; |
4bf5801d | 1054 | s->rregs[ESP_RSTAT] |= STAT_MI; |
f930d07e | 1055 | break; |
5ad6bb97 | 1056 | case CMD_MSGACC: |
bf4b9889 | 1057 | trace_esp_mem_writeb_cmd_msgacc(val); |
cf47a41e | 1058 | s->rregs[ESP_RINTR] |= INTR_DC; |
5ad6bb97 | 1059 | s->rregs[ESP_RSEQ] = 0; |
4e2a68c1 AT |
1060 | s->rregs[ESP_RFLAGS] = 0; |
1061 | esp_raise_irq(s); | |
f930d07e | 1062 | break; |
0fd0eb21 | 1063 | case CMD_PAD: |
bf4b9889 | 1064 | trace_esp_mem_writeb_cmd_pad(val); |
0fd0eb21 | 1065 | s->rregs[ESP_RSTAT] = STAT_TC; |
cf47a41e | 1066 | s->rregs[ESP_RINTR] |= INTR_FC; |
0fd0eb21 BS |
1067 | s->rregs[ESP_RSEQ] = 0; |
1068 | break; | |
5ad6bb97 | 1069 | case CMD_SATN: |
bf4b9889 | 1070 | trace_esp_mem_writeb_cmd_satn(val); |
f930d07e | 1071 | break; |
6915bff1 HP |
1072 | case CMD_RSTATN: |
1073 | trace_esp_mem_writeb_cmd_rstatn(val); | |
1074 | break; | |
5e1e0a3b | 1075 | case CMD_SEL: |
bf4b9889 | 1076 | trace_esp_mem_writeb_cmd_sel(val); |
f2818f22 | 1077 | handle_s_without_atn(s); |
5e1e0a3b | 1078 | break; |
5ad6bb97 | 1079 | case CMD_SELATN: |
bf4b9889 | 1080 | trace_esp_mem_writeb_cmd_selatn(val); |
f930d07e BS |
1081 | handle_satn(s); |
1082 | break; | |
5ad6bb97 | 1083 | case CMD_SELATNS: |
bf4b9889 | 1084 | trace_esp_mem_writeb_cmd_selatns(val); |
f930d07e BS |
1085 | handle_satn_stop(s); |
1086 | break; | |
5ad6bb97 | 1087 | case CMD_ENSEL: |
bf4b9889 | 1088 | trace_esp_mem_writeb_cmd_ensel(val); |
e3926838 | 1089 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 1090 | break; |
6fe84c18 HP |
1091 | case CMD_DISSEL: |
1092 | trace_esp_mem_writeb_cmd_dissel(val); | |
1093 | s->rregs[ESP_RINTR] = 0; | |
1094 | esp_raise_irq(s); | |
1095 | break; | |
f930d07e | 1096 | default: |
3af4e9aa | 1097 | trace_esp_error_unhandled_command(val); |
f930d07e BS |
1098 | break; |
1099 | } | |
1100 | break; | |
5ad6bb97 | 1101 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 1102 | break; |
5ad6bb97 | 1103 | case ESP_CFG1: |
9ea73f8b PB |
1104 | case ESP_CFG2: case ESP_CFG3: |
1105 | case ESP_RES3: case ESP_RES4: | |
4f6200f0 FB |
1106 | s->rregs[saddr] = val; |
1107 | break; | |
5ad6bb97 | 1108 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 1109 | break; |
6f7e9aec | 1110 | default: |
3af4e9aa | 1111 | trace_esp_error_invalid_write(val, saddr); |
8dea1dd4 | 1112 | return; |
6f7e9aec | 1113 | } |
2f275b8f | 1114 | s->wregs[saddr] = val; |
6f7e9aec FB |
1115 | } |
1116 | ||
a8170e5e | 1117 | static bool esp_mem_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
1118 | unsigned size, bool is_write, |
1119 | MemTxAttrs attrs) | |
67bb5314 AK |
1120 | { |
1121 | return (size == 1) || (is_write && size == 4); | |
1122 | } | |
6f7e9aec | 1123 | |
6cc88d6b MCA |
1124 | static bool esp_is_before_version_5(void *opaque, int version_id) |
1125 | { | |
1126 | ESPState *s = ESP(opaque); | |
1127 | ||
1128 | version_id = MIN(version_id, s->mig_version_id); | |
1129 | return version_id < 5; | |
1130 | } | |
1131 | ||
4e78f3bf MCA |
1132 | static bool esp_is_version_5(void *opaque, int version_id) |
1133 | { | |
1134 | ESPState *s = ESP(opaque); | |
1135 | ||
1136 | version_id = MIN(version_id, s->mig_version_id); | |
0bcd5a18 | 1137 | return version_id >= 5; |
4e78f3bf MCA |
1138 | } |
1139 | ||
4eb86065 PB |
1140 | static bool esp_is_version_6(void *opaque, int version_id) |
1141 | { | |
1142 | ESPState *s = ESP(opaque); | |
1143 | ||
1144 | version_id = MIN(version_id, s->mig_version_id); | |
1145 | return version_id >= 6; | |
1146 | } | |
1147 | ||
ff4a1dab | 1148 | int esp_pre_save(void *opaque) |
0bd005be | 1149 | { |
ff4a1dab MCA |
1150 | ESPState *s = ESP(object_resolve_path_component( |
1151 | OBJECT(opaque), "esp")); | |
0bd005be MCA |
1152 | |
1153 | s->mig_version_id = vmstate_esp.version_id; | |
1154 | return 0; | |
1155 | } | |
1156 | ||
1157 | static int esp_post_load(void *opaque, int version_id) | |
1158 | { | |
1159 | ESPState *s = ESP(opaque); | |
042879fc | 1160 | int len, i; |
0bd005be | 1161 | |
6cc88d6b MCA |
1162 | version_id = MIN(version_id, s->mig_version_id); |
1163 | ||
1164 | if (version_id < 5) { | |
1165 | esp_set_tc(s, s->mig_dma_left); | |
042879fc MCA |
1166 | |
1167 | /* Migrate ti_buf to fifo */ | |
1168 | len = s->mig_ti_wptr - s->mig_ti_rptr; | |
1169 | for (i = 0; i < len; i++) { | |
1170 | fifo8_push(&s->fifo, s->mig_ti_buf[i]); | |
1171 | } | |
023666da MCA |
1172 | |
1173 | /* Migrate cmdbuf to cmdfifo */ | |
1174 | for (i = 0; i < s->mig_cmdlen; i++) { | |
1175 | fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); | |
1176 | } | |
6cc88d6b MCA |
1177 | } |
1178 | ||
0bd005be MCA |
1179 | s->mig_version_id = vmstate_esp.version_id; |
1180 | return 0; | |
1181 | } | |
1182 | ||
9c7e23fc | 1183 | const VMStateDescription vmstate_esp = { |
94d5c79d | 1184 | .name = "esp", |
4eb86065 | 1185 | .version_id = 6, |
cc9952f3 | 1186 | .minimum_version_id = 3, |
0bd005be | 1187 | .post_load = esp_post_load, |
35d08458 | 1188 | .fields = (VMStateField[]) { |
cc9952f3 BS |
1189 | VMSTATE_BUFFER(rregs, ESPState), |
1190 | VMSTATE_BUFFER(wregs, ESPState), | |
1191 | VMSTATE_INT32(ti_size, ESPState), | |
042879fc MCA |
1192 | VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), |
1193 | VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), | |
1194 | VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), | |
3944966d | 1195 | VMSTATE_UINT32(status, ESPState), |
4aaa6ac3 MCA |
1196 | VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, |
1197 | esp_is_before_version_5), | |
1198 | VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, | |
1199 | esp_is_before_version_5), | |
cc9952f3 | 1200 | VMSTATE_UINT32(dma, ESPState), |
023666da MCA |
1201 | VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, |
1202 | esp_is_before_version_5, 0, 16), | |
1203 | VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, | |
1204 | esp_is_before_version_5, 16, | |
1205 | sizeof(typeof_field(ESPState, mig_cmdbuf))), | |
1206 | VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), | |
cc9952f3 | 1207 | VMSTATE_UINT32(do_cmd, ESPState), |
6cc88d6b | 1208 | VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), |
4e78f3bf | 1209 | VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), |
023666da | 1210 | VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), |
042879fc | 1211 | VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), |
023666da | 1212 | VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), |
1b9e48a5 | 1213 | VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), |
4eb86065 | 1214 | VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), |
cc9952f3 | 1215 | VMSTATE_END_OF_LIST() |
74d71ea1 | 1216 | }, |
cc9952f3 | 1217 | }; |
6f7e9aec | 1218 | |
a8170e5e | 1219 | static void sysbus_esp_mem_write(void *opaque, hwaddr addr, |
a391fdbc HP |
1220 | uint64_t val, unsigned int size) |
1221 | { | |
1222 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1223 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1224 | uint32_t saddr; |
1225 | ||
1226 | saddr = addr >> sysbus->it_shift; | |
eb169c76 | 1227 | esp_reg_write(s, saddr, val); |
a391fdbc HP |
1228 | } |
1229 | ||
a8170e5e | 1230 | static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, |
a391fdbc HP |
1231 | unsigned int size) |
1232 | { | |
1233 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1234 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1235 | uint32_t saddr; |
1236 | ||
1237 | saddr = addr >> sysbus->it_shift; | |
eb169c76 | 1238 | return esp_reg_read(s, saddr); |
a391fdbc HP |
1239 | } |
1240 | ||
1241 | static const MemoryRegionOps sysbus_esp_mem_ops = { | |
1242 | .read = sysbus_esp_mem_read, | |
1243 | .write = sysbus_esp_mem_write, | |
1244 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1245 | .valid.accepts = esp_mem_accepts, | |
1246 | }; | |
1247 | ||
74d71ea1 LV |
1248 | static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, |
1249 | uint64_t val, unsigned int size) | |
1250 | { | |
1251 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1252 | ESPState *s = ESP(&sysbus->esp); |
74d71ea1 | 1253 | |
960ebfd9 MCA |
1254 | trace_esp_pdma_write(size); |
1255 | ||
74d71ea1 LV |
1256 | switch (size) { |
1257 | case 1: | |
761bef75 | 1258 | esp_pdma_write(s, val); |
74d71ea1 LV |
1259 | break; |
1260 | case 2: | |
761bef75 MCA |
1261 | esp_pdma_write(s, val >> 8); |
1262 | esp_pdma_write(s, val); | |
74d71ea1 LV |
1263 | break; |
1264 | } | |
e62a959a | 1265 | s->pdma_cb(s); |
74d71ea1 LV |
1266 | } |
1267 | ||
1268 | static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, | |
1269 | unsigned int size) | |
1270 | { | |
1271 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1272 | ESPState *s = ESP(&sysbus->esp); |
74d71ea1 LV |
1273 | uint64_t val = 0; |
1274 | ||
960ebfd9 MCA |
1275 | trace_esp_pdma_read(size); |
1276 | ||
74d71ea1 LV |
1277 | switch (size) { |
1278 | case 1: | |
761bef75 | 1279 | val = esp_pdma_read(s); |
74d71ea1 LV |
1280 | break; |
1281 | case 2: | |
761bef75 MCA |
1282 | val = esp_pdma_read(s); |
1283 | val = (val << 8) | esp_pdma_read(s); | |
74d71ea1 LV |
1284 | break; |
1285 | } | |
7aa6baee | 1286 | if (fifo8_num_used(&s->fifo) < 2) { |
74d71ea1 | 1287 | s->pdma_cb(s); |
74d71ea1 LV |
1288 | } |
1289 | return val; | |
1290 | } | |
1291 | ||
1292 | static const MemoryRegionOps sysbus_esp_pdma_ops = { | |
1293 | .read = sysbus_esp_pdma_read, | |
1294 | .write = sysbus_esp_pdma_write, | |
1295 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1296 | .valid.min_access_size = 1, | |
cf1b8286 MCA |
1297 | .valid.max_access_size = 4, |
1298 | .impl.min_access_size = 1, | |
1299 | .impl.max_access_size = 2, | |
74d71ea1 LV |
1300 | }; |
1301 | ||
afd4030c PB |
1302 | static const struct SCSIBusInfo esp_scsi_info = { |
1303 | .tcq = false, | |
7e0380b9 PB |
1304 | .max_target = ESP_MAX_DEVS, |
1305 | .max_lun = 7, | |
afd4030c | 1306 | |
c6df7102 | 1307 | .transfer_data = esp_transfer_data, |
94d3f98a PB |
1308 | .complete = esp_command_complete, |
1309 | .cancel = esp_request_cancelled | |
cfdc1bb0 PB |
1310 | }; |
1311 | ||
a391fdbc | 1312 | static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) |
cfb9de9c | 1313 | { |
84fbefed | 1314 | SysBusESPState *sysbus = SYSBUS_ESP(opaque); |
eb169c76 | 1315 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1316 | |
1317 | switch (irq) { | |
1318 | case 0: | |
1319 | parent_esp_reset(s, irq, level); | |
1320 | break; | |
1321 | case 1: | |
1322 | esp_dma_enable(opaque, irq, level); | |
1323 | break; | |
1324 | } | |
1325 | } | |
1326 | ||
b09318ca | 1327 | static void sysbus_esp_realize(DeviceState *dev, Error **errp) |
a391fdbc | 1328 | { |
b09318ca | 1329 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
84fbefed | 1330 | SysBusESPState *sysbus = SYSBUS_ESP(dev); |
eb169c76 MCA |
1331 | ESPState *s = ESP(&sysbus->esp); |
1332 | ||
1333 | if (!qdev_realize(DEVICE(s), NULL, errp)) { | |
1334 | return; | |
1335 | } | |
6f7e9aec | 1336 | |
b09318ca | 1337 | sysbus_init_irq(sbd, &s->irq); |
74d71ea1 | 1338 | sysbus_init_irq(sbd, &s->irq_data); |
a391fdbc | 1339 | assert(sysbus->it_shift != -1); |
6f7e9aec | 1340 | |
d32e4b3d | 1341 | s->chip_id = TCHI_FAS100A; |
29776739 | 1342 | memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, |
74d71ea1 | 1343 | sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); |
b09318ca | 1344 | sysbus_init_mmio(sbd, &sysbus->iomem); |
74d71ea1 | 1345 | memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, |
cf1b8286 | 1346 | sysbus, "esp-pdma", 4); |
74d71ea1 | 1347 | sysbus_init_mmio(sbd, &sysbus->pdma); |
6f7e9aec | 1348 | |
b09318ca | 1349 | qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); |
2d069bab | 1350 | |
b1187b51 | 1351 | scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); |
67e999be | 1352 | } |
cfb9de9c | 1353 | |
a391fdbc HP |
1354 | static void sysbus_esp_hard_reset(DeviceState *dev) |
1355 | { | |
84fbefed | 1356 | SysBusESPState *sysbus = SYSBUS_ESP(dev); |
eb169c76 MCA |
1357 | ESPState *s = ESP(&sysbus->esp); |
1358 | ||
1359 | esp_hard_reset(s); | |
1360 | } | |
1361 | ||
1362 | static void sysbus_esp_init(Object *obj) | |
1363 | { | |
1364 | SysBusESPState *sysbus = SYSBUS_ESP(obj); | |
1365 | ||
1366 | object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); | |
a391fdbc HP |
1367 | } |
1368 | ||
1369 | static const VMStateDescription vmstate_sysbus_esp_scsi = { | |
1370 | .name = "sysbusespscsi", | |
0bd005be | 1371 | .version_id = 2, |
ea84a442 | 1372 | .minimum_version_id = 1, |
ff4a1dab | 1373 | .pre_save = esp_pre_save, |
a391fdbc | 1374 | .fields = (VMStateField[]) { |
0bd005be | 1375 | VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), |
a391fdbc HP |
1376 | VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), |
1377 | VMSTATE_END_OF_LIST() | |
1378 | } | |
999e12bb AL |
1379 | }; |
1380 | ||
a391fdbc | 1381 | static void sysbus_esp_class_init(ObjectClass *klass, void *data) |
999e12bb | 1382 | { |
39bffca2 | 1383 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1384 | |
b09318ca | 1385 | dc->realize = sysbus_esp_realize; |
a391fdbc HP |
1386 | dc->reset = sysbus_esp_hard_reset; |
1387 | dc->vmsd = &vmstate_sysbus_esp_scsi; | |
125ee0ed | 1388 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
999e12bb AL |
1389 | } |
1390 | ||
1f077308 | 1391 | static const TypeInfo sysbus_esp_info = { |
84fbefed | 1392 | .name = TYPE_SYSBUS_ESP, |
39bffca2 | 1393 | .parent = TYPE_SYS_BUS_DEVICE, |
eb169c76 | 1394 | .instance_init = sysbus_esp_init, |
a391fdbc HP |
1395 | .instance_size = sizeof(SysBusESPState), |
1396 | .class_init = sysbus_esp_class_init, | |
63235df8 BS |
1397 | }; |
1398 | ||
042879fc MCA |
1399 | static void esp_finalize(Object *obj) |
1400 | { | |
1401 | ESPState *s = ESP(obj); | |
1402 | ||
1403 | fifo8_destroy(&s->fifo); | |
023666da | 1404 | fifo8_destroy(&s->cmdfifo); |
042879fc MCA |
1405 | } |
1406 | ||
1407 | static void esp_init(Object *obj) | |
1408 | { | |
1409 | ESPState *s = ESP(obj); | |
1410 | ||
1411 | fifo8_create(&s->fifo, ESP_FIFO_SZ); | |
023666da | 1412 | fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); |
042879fc MCA |
1413 | } |
1414 | ||
eb169c76 MCA |
1415 | static void esp_class_init(ObjectClass *klass, void *data) |
1416 | { | |
1417 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1418 | ||
1419 | /* internal device for sysbusesp/pciespscsi, not user-creatable */ | |
1420 | dc->user_creatable = false; | |
1421 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | |
1422 | } | |
1423 | ||
1424 | static const TypeInfo esp_info = { | |
1425 | .name = TYPE_ESP, | |
1426 | .parent = TYPE_DEVICE, | |
042879fc MCA |
1427 | .instance_init = esp_init, |
1428 | .instance_finalize = esp_finalize, | |
eb169c76 MCA |
1429 | .instance_size = sizeof(ESPState), |
1430 | .class_init = esp_class_init, | |
1431 | }; | |
1432 | ||
83f7d43a | 1433 | static void esp_register_types(void) |
cfb9de9c | 1434 | { |
a391fdbc | 1435 | type_register_static(&sysbus_esp_info); |
eb169c76 | 1436 | type_register_static(&esp_info); |
cfb9de9c PB |
1437 | } |
1438 | ||
83f7d43a | 1439 | type_init(esp_register_types) |