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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
fabaaf1d | 5 | * Copyright (c) 2012 Herve Poussineau |
5fafdf24 | 6 | * |
6f7e9aec FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
5d20fa6b | 25 | |
a4ab4792 | 26 | #include "qemu/osdep.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
64552b6b | 29 | #include "hw/irq.h" |
0d09e41a | 30 | #include "hw/scsi/esp.h" |
bf4b9889 | 31 | #include "trace.h" |
1de7afc9 | 32 | #include "qemu/log.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
6f7e9aec | 34 | |
67e999be | 35 | /* |
5ad6bb97 BS |
36 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
37 | * also produced as NCR89C100. See | |
67e999be FB |
38 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
39 | * and | |
40 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
74d71ea1 LV |
41 | * |
42 | * On Macintosh Quadra it is a NCR53C96. | |
67e999be FB |
43 | */ |
44 | ||
c73f96fd BS |
45 | static void esp_raise_irq(ESPState *s) |
46 | { | |
47 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
48 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
49 | qemu_irq_raise(s->irq); | |
bf4b9889 | 50 | trace_esp_raise_irq(); |
c73f96fd BS |
51 | } |
52 | } | |
53 | ||
54 | static void esp_lower_irq(ESPState *s) | |
55 | { | |
56 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
57 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
58 | qemu_irq_lower(s->irq); | |
bf4b9889 | 59 | trace_esp_lower_irq(); |
c73f96fd BS |
60 | } |
61 | } | |
62 | ||
74d71ea1 LV |
63 | static void esp_raise_drq(ESPState *s) |
64 | { | |
65 | qemu_irq_raise(s->irq_data); | |
960ebfd9 | 66 | trace_esp_raise_drq(); |
74d71ea1 LV |
67 | } |
68 | ||
69 | static void esp_lower_drq(ESPState *s) | |
70 | { | |
71 | qemu_irq_lower(s->irq_data); | |
960ebfd9 | 72 | trace_esp_lower_drq(); |
74d71ea1 LV |
73 | } |
74 | ||
9c7e23fc | 75 | void esp_dma_enable(ESPState *s, int irq, int level) |
73d74342 | 76 | { |
73d74342 BS |
77 | if (level) { |
78 | s->dma_enabled = 1; | |
bf4b9889 | 79 | trace_esp_dma_enable(); |
73d74342 BS |
80 | if (s->dma_cb) { |
81 | s->dma_cb(s); | |
82 | s->dma_cb = NULL; | |
83 | } | |
84 | } else { | |
bf4b9889 | 85 | trace_esp_dma_disable(); |
73d74342 BS |
86 | s->dma_enabled = 0; |
87 | } | |
88 | } | |
89 | ||
9c7e23fc | 90 | void esp_request_cancelled(SCSIRequest *req) |
94d3f98a | 91 | { |
e6810db8 | 92 | ESPState *s = req->hba_private; |
94d3f98a PB |
93 | |
94 | if (req == s->current_req) { | |
95 | scsi_req_unref(s->current_req); | |
96 | s->current_req = NULL; | |
97 | s->current_dev = NULL; | |
324c8809 | 98 | s->async_len = 0; |
94d3f98a PB |
99 | } |
100 | } | |
101 | ||
e5455b8c | 102 | static void esp_fifo_push(Fifo8 *fifo, uint8_t val) |
042879fc | 103 | { |
e5455b8c | 104 | if (fifo8_num_used(fifo) == fifo->capacity) { |
042879fc MCA |
105 | trace_esp_error_fifo_overrun(); |
106 | return; | |
107 | } | |
108 | ||
e5455b8c | 109 | fifo8_push(fifo, val); |
042879fc | 110 | } |
042879fc | 111 | |
c5fef911 | 112 | static uint8_t esp_fifo_pop(Fifo8 *fifo) |
023666da | 113 | { |
c5fef911 | 114 | if (fifo8_is_empty(fifo)) { |
023666da MCA |
115 | return 0; |
116 | } | |
117 | ||
c5fef911 | 118 | return fifo8_pop(fifo); |
023666da MCA |
119 | } |
120 | ||
7b320a8e MCA |
121 | static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) |
122 | { | |
123 | const uint8_t *buf; | |
124 | uint32_t n; | |
125 | ||
126 | if (maxlen == 0) { | |
127 | return 0; | |
128 | } | |
129 | ||
130 | buf = fifo8_pop_buf(fifo, maxlen, &n); | |
131 | if (dest) { | |
132 | memcpy(dest, buf, n); | |
133 | } | |
134 | ||
135 | return n; | |
136 | } | |
137 | ||
c47b5835 MCA |
138 | static uint32_t esp_get_tc(ESPState *s) |
139 | { | |
140 | uint32_t dmalen; | |
141 | ||
142 | dmalen = s->rregs[ESP_TCLO]; | |
143 | dmalen |= s->rregs[ESP_TCMID] << 8; | |
144 | dmalen |= s->rregs[ESP_TCHI] << 16; | |
145 | ||
146 | return dmalen; | |
147 | } | |
148 | ||
149 | static void esp_set_tc(ESPState *s, uint32_t dmalen) | |
150 | { | |
151 | s->rregs[ESP_TCLO] = dmalen; | |
152 | s->rregs[ESP_TCMID] = dmalen >> 8; | |
153 | s->rregs[ESP_TCHI] = dmalen >> 16; | |
154 | } | |
155 | ||
c04ed569 MCA |
156 | static uint32_t esp_get_stc(ESPState *s) |
157 | { | |
158 | uint32_t dmalen; | |
159 | ||
160 | dmalen = s->wregs[ESP_TCLO]; | |
161 | dmalen |= s->wregs[ESP_TCMID] << 8; | |
162 | dmalen |= s->wregs[ESP_TCHI] << 16; | |
163 | ||
164 | return dmalen; | |
165 | } | |
166 | ||
761bef75 MCA |
167 | static uint8_t esp_pdma_read(ESPState *s) |
168 | { | |
8da90e81 MCA |
169 | uint8_t val; |
170 | ||
43d02df3 | 171 | if (s->do_cmd) { |
c5fef911 | 172 | val = esp_fifo_pop(&s->cmdfifo); |
43d02df3 | 173 | } else { |
c5fef911 | 174 | val = esp_fifo_pop(&s->fifo); |
6e3fafa8 | 175 | } |
8da90e81 | 176 | |
8da90e81 | 177 | return val; |
761bef75 MCA |
178 | } |
179 | ||
180 | static void esp_pdma_write(ESPState *s, uint8_t val) | |
181 | { | |
8da90e81 MCA |
182 | uint32_t dmalen = esp_get_tc(s); |
183 | ||
3c421400 | 184 | if (dmalen == 0) { |
8da90e81 MCA |
185 | return; |
186 | } | |
187 | ||
43d02df3 | 188 | if (s->do_cmd) { |
e5455b8c | 189 | esp_fifo_push(&s->cmdfifo, val); |
43d02df3 | 190 | } else { |
e5455b8c | 191 | esp_fifo_push(&s->fifo, val); |
6e3fafa8 | 192 | } |
8da90e81 | 193 | |
8da90e81 MCA |
194 | dmalen--; |
195 | esp_set_tc(s, dmalen); | |
761bef75 MCA |
196 | } |
197 | ||
77987ef5 | 198 | static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) |
1e794c51 MCA |
199 | { |
200 | s->pdma_cb = cb; | |
201 | } | |
202 | ||
c7bce09c | 203 | static int esp_select(ESPState *s) |
6130b188 LV |
204 | { |
205 | int target; | |
206 | ||
207 | target = s->wregs[ESP_WBUSID] & BUSID_DID; | |
208 | ||
209 | s->ti_size = 0; | |
042879fc | 210 | fifo8_reset(&s->fifo); |
6130b188 | 211 | |
6130b188 LV |
212 | s->current_dev = scsi_device_find(&s->bus, 0, target, 0); |
213 | if (!s->current_dev) { | |
214 | /* No such drive */ | |
215 | s->rregs[ESP_RSTAT] = 0; | |
cf1a7a9b | 216 | s->rregs[ESP_RINTR] = INTR_DC; |
6130b188 LV |
217 | s->rregs[ESP_RSEQ] = SEQ_0; |
218 | esp_raise_irq(s); | |
219 | return -1; | |
220 | } | |
4e78f3bf MCA |
221 | |
222 | /* | |
223 | * Note that we deliberately don't raise the IRQ here: this will be done | |
4eb86065 | 224 | * either in do_command_phase() for DATA OUT transfers or by the deferred |
4e78f3bf MCA |
225 | * IRQ mechanism in esp_transfer_data() for DATA IN transfers |
226 | */ | |
227 | s->rregs[ESP_RINTR] |= INTR_FC; | |
228 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
6130b188 LV |
229 | return 0; |
230 | } | |
231 | ||
20c8d2ed | 232 | static uint32_t get_cmd(ESPState *s, uint32_t maxlen) |
2f275b8f | 233 | { |
023666da | 234 | uint8_t buf[ESP_CMDFIFO_SZ]; |
042879fc | 235 | uint32_t dmalen, n; |
2f275b8f FB |
236 | int target; |
237 | ||
de7e2cb1 MCA |
238 | if (s->current_req) { |
239 | /* Started a new command before the old one finished. Cancel it. */ | |
240 | scsi_req_cancel(s->current_req); | |
241 | } | |
242 | ||
8dea1dd4 | 243 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 244 | if (s->dma) { |
20c8d2ed MCA |
245 | dmalen = MIN(esp_get_tc(s), maxlen); |
246 | if (dmalen == 0) { | |
6c1fef6b PP |
247 | return 0; |
248 | } | |
74d71ea1 LV |
249 | if (s->dma_memory_read) { |
250 | s->dma_memory_read(s->dma_opaque, buf, dmalen); | |
fbc6510e | 251 | dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); |
023666da | 252 | fifo8_push_all(&s->cmdfifo, buf, dmalen); |
74d71ea1 | 253 | } else { |
49691315 | 254 | if (esp_select(s) < 0) { |
023666da | 255 | fifo8_reset(&s->cmdfifo); |
49691315 MCA |
256 | return -1; |
257 | } | |
74d71ea1 | 258 | esp_raise_drq(s); |
023666da | 259 | fifo8_reset(&s->cmdfifo); |
74d71ea1 LV |
260 | return 0; |
261 | } | |
4f6200f0 | 262 | } else { |
023666da | 263 | dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); |
20c8d2ed | 264 | if (dmalen == 0) { |
d3cdc491 PP |
265 | return 0; |
266 | } | |
7b320a8e | 267 | n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); |
fbc6510e | 268 | n = MIN(fifo8_num_free(&s->cmdfifo), n); |
7b320a8e | 269 | fifo8_push_all(&s->cmdfifo, buf, n); |
4f6200f0 | 270 | } |
bf4b9889 | 271 | trace_esp_get_cmd(dmalen, target); |
2e5d83bb | 272 | |
c7bce09c | 273 | if (esp_select(s) < 0) { |
023666da | 274 | fifo8_reset(&s->cmdfifo); |
49691315 | 275 | return -1; |
2f275b8f | 276 | } |
9f149aa9 PB |
277 | return dmalen; |
278 | } | |
279 | ||
4eb86065 | 280 | static void do_command_phase(ESPState *s) |
9f149aa9 | 281 | { |
7b320a8e | 282 | uint32_t cmdlen; |
9f149aa9 | 283 | int32_t datalen; |
f48a7a6e | 284 | SCSIDevice *current_lun; |
7b320a8e | 285 | uint8_t buf[ESP_CMDFIFO_SZ]; |
9f149aa9 | 286 | |
4eb86065 | 287 | trace_esp_do_command_phase(s->lun); |
023666da | 288 | cmdlen = fifo8_num_used(&s->cmdfifo); |
99545751 MCA |
289 | if (!cmdlen || !s->current_dev) { |
290 | return; | |
291 | } | |
7b320a8e | 292 | esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); |
023666da | 293 | |
4eb86065 | 294 | current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); |
fe9d8927 | 295 | s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); |
c39ce112 | 296 | datalen = scsi_req_enqueue(s->current_req); |
67e999be | 297 | s->ti_size = datalen; |
023666da | 298 | fifo8_reset(&s->cmdfifo); |
67e999be | 299 | if (datalen != 0) { |
c73f96fd | 300 | s->rregs[ESP_RSTAT] = STAT_TC; |
4e78f3bf | 301 | s->rregs[ESP_RSEQ] = SEQ_CD; |
1b9e48a5 | 302 | s->ti_cmd = 0; |
6cc88d6b | 303 | esp_set_tc(s, 0); |
2e5d83bb | 304 | if (datalen > 0) { |
4e78f3bf MCA |
305 | /* |
306 | * Switch to DATA IN phase but wait until initial data xfer is | |
307 | * complete before raising the command completion interrupt | |
308 | */ | |
309 | s->data_in_ready = false; | |
5ad6bb97 | 310 | s->rregs[ESP_RSTAT] |= STAT_DI; |
2e5d83bb | 311 | } else { |
5ad6bb97 | 312 | s->rregs[ESP_RSTAT] |= STAT_DO; |
4e78f3bf MCA |
313 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
314 | esp_raise_irq(s); | |
315 | esp_lower_drq(s); | |
b9788fc4 | 316 | } |
ad3376cc | 317 | scsi_req_continue(s->current_req); |
4e78f3bf | 318 | return; |
2f275b8f | 319 | } |
2f275b8f FB |
320 | } |
321 | ||
4eb86065 | 322 | static void do_message_phase(ESPState *s) |
f2818f22 | 323 | { |
4eb86065 PB |
324 | if (s->cmdfifo_cdb_offset) { |
325 | uint8_t message = esp_fifo_pop(&s->cmdfifo); | |
023666da | 326 | |
4eb86065 PB |
327 | trace_esp_do_identify(message); |
328 | s->lun = message & 7; | |
329 | s->cmdfifo_cdb_offset--; | |
330 | } | |
f2818f22 | 331 | |
799d90d8 | 332 | /* Ignore extended messages for now */ |
023666da | 333 | if (s->cmdfifo_cdb_offset) { |
4eb86065 | 334 | int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); |
fa7505c1 | 335 | esp_fifo_pop_buf(&s->cmdfifo, NULL, len); |
023666da MCA |
336 | s->cmdfifo_cdb_offset = 0; |
337 | } | |
4eb86065 | 338 | } |
023666da | 339 | |
4eb86065 PB |
340 | static void do_cmd(ESPState *s) |
341 | { | |
342 | do_message_phase(s); | |
343 | assert(s->cmdfifo_cdb_offset == 0); | |
344 | do_command_phase(s); | |
f2818f22 AT |
345 | } |
346 | ||
74d71ea1 LV |
347 | static void satn_pdma_cb(ESPState *s) |
348 | { | |
e62a959a | 349 | if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { |
023666da | 350 | s->cmdfifo_cdb_offset = 1; |
e62a959a | 351 | s->do_cmd = 0; |
c959f218 | 352 | do_cmd(s); |
74d71ea1 LV |
353 | } |
354 | } | |
355 | ||
9f149aa9 PB |
356 | static void handle_satn(ESPState *s) |
357 | { | |
49691315 MCA |
358 | int32_t cmdlen; |
359 | ||
1b26eaa1 | 360 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
361 | s->dma_cb = handle_satn; |
362 | return; | |
363 | } | |
77987ef5 | 364 | esp_set_pdma_cb(s, SATN_PDMA_CB); |
023666da | 365 | cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); |
49691315 | 366 | if (cmdlen > 0) { |
023666da | 367 | s->cmdfifo_cdb_offset = 1; |
60720694 | 368 | s->do_cmd = 0; |
c959f218 | 369 | do_cmd(s); |
49691315 | 370 | } else if (cmdlen == 0) { |
bb0bc7bb | 371 | s->do_cmd = 1; |
49691315 MCA |
372 | /* Target present, but no cmd yet - switch to command phase */ |
373 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
374 | s->rregs[ESP_RSTAT] = STAT_CD; | |
94d5c79d | 375 | } |
9f149aa9 PB |
376 | } |
377 | ||
74d71ea1 LV |
378 | static void s_without_satn_pdma_cb(ESPState *s) |
379 | { | |
e62a959a | 380 | if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { |
023666da | 381 | s->cmdfifo_cdb_offset = 0; |
e62a959a | 382 | s->do_cmd = 0; |
4eb86065 | 383 | do_cmd(s); |
74d71ea1 LV |
384 | } |
385 | } | |
386 | ||
f2818f22 AT |
387 | static void handle_s_without_atn(ESPState *s) |
388 | { | |
49691315 MCA |
389 | int32_t cmdlen; |
390 | ||
1b26eaa1 | 391 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
392 | s->dma_cb = handle_s_without_atn; |
393 | return; | |
394 | } | |
77987ef5 | 395 | esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); |
023666da | 396 | cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); |
49691315 | 397 | if (cmdlen > 0) { |
023666da | 398 | s->cmdfifo_cdb_offset = 0; |
60720694 | 399 | s->do_cmd = 0; |
4eb86065 | 400 | do_cmd(s); |
49691315 | 401 | } else if (cmdlen == 0) { |
bb0bc7bb | 402 | s->do_cmd = 1; |
49691315 MCA |
403 | /* Target present, but no cmd yet - switch to command phase */ |
404 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
405 | s->rregs[ESP_RSTAT] = STAT_CD; | |
f2818f22 AT |
406 | } |
407 | } | |
408 | ||
74d71ea1 LV |
409 | static void satn_stop_pdma_cb(ESPState *s) |
410 | { | |
e62a959a | 411 | if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { |
023666da | 412 | trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); |
74d71ea1 | 413 | s->do_cmd = 1; |
023666da | 414 | s->cmdfifo_cdb_offset = 1; |
74d71ea1 | 415 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
cf47a41e | 416 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
417 | s->rregs[ESP_RSEQ] = SEQ_CD; |
418 | esp_raise_irq(s); | |
419 | } | |
420 | } | |
421 | ||
9f149aa9 PB |
422 | static void handle_satn_stop(ESPState *s) |
423 | { | |
49691315 MCA |
424 | int32_t cmdlen; |
425 | ||
1b26eaa1 | 426 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
427 | s->dma_cb = handle_satn_stop; |
428 | return; | |
429 | } | |
77987ef5 | 430 | esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); |
799d90d8 | 431 | cmdlen = get_cmd(s, 1); |
49691315 | 432 | if (cmdlen > 0) { |
023666da | 433 | trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); |
9f149aa9 | 434 | s->do_cmd = 1; |
023666da | 435 | s->cmdfifo_cdb_offset = 1; |
799d90d8 | 436 | s->rregs[ESP_RSTAT] = STAT_MO; |
cf47a41e | 437 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
799d90d8 | 438 | s->rregs[ESP_RSEQ] = SEQ_MO; |
c73f96fd | 439 | esp_raise_irq(s); |
49691315 | 440 | } else if (cmdlen == 0) { |
bb0bc7bb | 441 | s->do_cmd = 1; |
799d90d8 MCA |
442 | /* Target present, switch to message out phase */ |
443 | s->rregs[ESP_RSEQ] = SEQ_MO; | |
444 | s->rregs[ESP_RSTAT] = STAT_MO; | |
9f149aa9 PB |
445 | } |
446 | } | |
447 | ||
74d71ea1 LV |
448 | static void write_response_pdma_cb(ESPState *s) |
449 | { | |
450 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
cf47a41e | 451 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
452 | s->rregs[ESP_RSEQ] = SEQ_CD; |
453 | esp_raise_irq(s); | |
454 | } | |
455 | ||
0fc5c15a | 456 | static void write_response(ESPState *s) |
2f275b8f | 457 | { |
e3922557 | 458 | uint8_t buf[2]; |
042879fc | 459 | |
bf4b9889 | 460 | trace_esp_write_response(s->status); |
042879fc | 461 | |
e3922557 MCA |
462 | buf[0] = s->status; |
463 | buf[1] = 0; | |
042879fc | 464 | |
4f6200f0 | 465 | if (s->dma) { |
74d71ea1 | 466 | if (s->dma_memory_write) { |
e3922557 | 467 | s->dma_memory_write(s->dma_opaque, buf, 2); |
74d71ea1 | 468 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
cf47a41e | 469 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
470 | s->rregs[ESP_RSEQ] = SEQ_CD; |
471 | } else { | |
77987ef5 | 472 | esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); |
74d71ea1 LV |
473 | esp_raise_drq(s); |
474 | return; | |
475 | } | |
4f6200f0 | 476 | } else { |
e3922557 MCA |
477 | fifo8_reset(&s->fifo); |
478 | fifo8_push_all(&s->fifo, buf, 2); | |
5ad6bb97 | 479 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 480 | } |
c73f96fd | 481 | esp_raise_irq(s); |
2f275b8f | 482 | } |
4f6200f0 | 483 | |
a917d384 PB |
484 | static void esp_dma_done(ESPState *s) |
485 | { | |
c73f96fd | 486 | s->rregs[ESP_RSTAT] |= STAT_TC; |
cf47a41e | 487 | s->rregs[ESP_RINTR] |= INTR_BS; |
5ad6bb97 | 488 | s->rregs[ESP_RFLAGS] = 0; |
c47b5835 | 489 | esp_set_tc(s, 0); |
c73f96fd | 490 | esp_raise_irq(s); |
a917d384 PB |
491 | } |
492 | ||
74d71ea1 LV |
493 | static void do_dma_pdma_cb(ESPState *s) |
494 | { | |
4ca2ba6f | 495 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
82141c8b | 496 | int len; |
042879fc | 497 | uint32_t n; |
6cc88d6b | 498 | |
74d71ea1 | 499 | if (s->do_cmd) { |
e62a959a MCA |
500 | /* Ensure we have received complete command after SATN and stop */ |
501 | if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { | |
502 | return; | |
503 | } | |
504 | ||
74d71ea1 | 505 | s->ti_size = 0; |
c348458f MCA |
506 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { |
507 | /* No command received */ | |
508 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { | |
509 | return; | |
510 | } | |
511 | ||
512 | /* Command has been received */ | |
513 | s->do_cmd = 0; | |
514 | do_cmd(s); | |
515 | } else { | |
516 | /* | |
517 | * Extra message out bytes received: update cmdfifo_cdb_offset | |
2cb40d44 | 518 | * and then switch to command phase |
c348458f MCA |
519 | */ |
520 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); | |
521 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; | |
522 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
523 | s->rregs[ESP_RINTR] |= INTR_BS; | |
524 | esp_raise_irq(s); | |
525 | } | |
74d71ea1 LV |
526 | return; |
527 | } | |
82141c8b | 528 | |
0db89536 MCA |
529 | if (!s->current_req) { |
530 | return; | |
531 | } | |
532 | ||
82141c8b MCA |
533 | if (to_device) { |
534 | /* Copy FIFO data to device */ | |
7aa6baee MCA |
535 | len = MIN(s->async_len, ESP_FIFO_SZ); |
536 | len = MIN(len, fifo8_num_used(&s->fifo)); | |
7b320a8e | 537 | n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
7aa6baee MCA |
538 | s->async_buf += n; |
539 | s->async_len -= n; | |
540 | s->ti_size += n; | |
541 | ||
542 | if (n < len) { | |
543 | /* Unaligned accesses can cause FIFO wraparound */ | |
544 | len = len - n; | |
7b320a8e | 545 | n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
7aa6baee MCA |
546 | s->async_buf += n; |
547 | s->async_len -= n; | |
548 | s->ti_size += n; | |
549 | } | |
550 | ||
82141c8b MCA |
551 | if (s->async_len == 0) { |
552 | scsi_req_continue(s->current_req); | |
74d71ea1 LV |
553 | return; |
554 | } | |
74d71ea1 | 555 | |
82141c8b MCA |
556 | if (esp_get_tc(s) == 0) { |
557 | esp_lower_drq(s); | |
558 | esp_dma_done(s); | |
559 | } | |
560 | ||
561 | return; | |
562 | } else { | |
563 | if (s->async_len == 0) { | |
0db89536 MCA |
564 | /* Defer until the scsi layer has completed */ |
565 | scsi_req_continue(s->current_req); | |
566 | s->data_in_ready = false; | |
4e78f3bf | 567 | return; |
82141c8b MCA |
568 | } |
569 | ||
570 | if (esp_get_tc(s) != 0) { | |
571 | /* Copy device data to FIFO */ | |
7aa6baee MCA |
572 | len = MIN(s->async_len, esp_get_tc(s)); |
573 | len = MIN(len, fifo8_num_free(&s->fifo)); | |
042879fc | 574 | fifo8_push_all(&s->fifo, s->async_buf, len); |
82141c8b MCA |
575 | s->async_buf += len; |
576 | s->async_len -= len; | |
577 | s->ti_size -= len; | |
578 | esp_set_tc(s, esp_get_tc(s) - len); | |
7aa6baee MCA |
579 | |
580 | if (esp_get_tc(s) == 0) { | |
581 | /* Indicate transfer to FIFO is complete */ | |
582 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
583 | } | |
82141c8b MCA |
584 | return; |
585 | } | |
586 | ||
587 | /* Partially filled a scsi buffer. Complete immediately. */ | |
588 | esp_lower_drq(s); | |
589 | esp_dma_done(s); | |
590 | } | |
74d71ea1 LV |
591 | } |
592 | ||
4d611c9a PB |
593 | static void esp_do_dma(ESPState *s) |
594 | { | |
023666da | 595 | uint32_t len, cmdlen; |
4ca2ba6f | 596 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
023666da | 597 | uint8_t buf[ESP_CMDFIFO_SZ]; |
a917d384 | 598 | |
6cc88d6b | 599 | len = esp_get_tc(s); |
4d611c9a | 600 | if (s->do_cmd) { |
15407433 LV |
601 | /* |
602 | * handle_ti_cmd() case: esp_do_dma() is called only from | |
603 | * handle_ti_cmd() with do_cmd != NULL (see the assert()) | |
604 | */ | |
023666da MCA |
605 | cmdlen = fifo8_num_used(&s->cmdfifo); |
606 | trace_esp_do_dma(cmdlen, len); | |
74d71ea1 | 607 | if (s->dma_memory_read) { |
0ebb5fd8 | 608 | len = MIN(len, fifo8_num_free(&s->cmdfifo)); |
023666da MCA |
609 | s->dma_memory_read(s->dma_opaque, buf, len); |
610 | fifo8_push_all(&s->cmdfifo, buf, len); | |
74d71ea1 | 611 | } else { |
77987ef5 | 612 | esp_set_pdma_cb(s, DO_DMA_PDMA_CB); |
74d71ea1 LV |
613 | esp_raise_drq(s); |
614 | return; | |
615 | } | |
023666da | 616 | trace_esp_handle_ti_cmd(cmdlen); |
15407433 | 617 | s->ti_size = 0; |
799d90d8 MCA |
618 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { |
619 | /* No command received */ | |
023666da | 620 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { |
799d90d8 MCA |
621 | return; |
622 | } | |
623 | ||
624 | /* Command has been received */ | |
799d90d8 MCA |
625 | s->do_cmd = 0; |
626 | do_cmd(s); | |
627 | } else { | |
628 | /* | |
023666da | 629 | * Extra message out bytes received: update cmdfifo_cdb_offset |
2cb40d44 | 630 | * and then switch to command phase |
799d90d8 | 631 | */ |
023666da | 632 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); |
799d90d8 MCA |
633 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
634 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
635 | s->rregs[ESP_RINTR] |= INTR_BS; | |
636 | esp_raise_irq(s); | |
637 | } | |
4d611c9a | 638 | return; |
a917d384 | 639 | } |
0db89536 MCA |
640 | if (!s->current_req) { |
641 | return; | |
642 | } | |
a917d384 PB |
643 | if (s->async_len == 0) { |
644 | /* Defer until data is available. */ | |
645 | return; | |
646 | } | |
647 | if (len > s->async_len) { | |
648 | len = s->async_len; | |
649 | } | |
650 | if (to_device) { | |
74d71ea1 LV |
651 | if (s->dma_memory_read) { |
652 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); | |
653 | } else { | |
77987ef5 | 654 | esp_set_pdma_cb(s, DO_DMA_PDMA_CB); |
74d71ea1 LV |
655 | esp_raise_drq(s); |
656 | return; | |
657 | } | |
4d611c9a | 658 | } else { |
74d71ea1 LV |
659 | if (s->dma_memory_write) { |
660 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); | |
661 | } else { | |
7aa6baee MCA |
662 | /* Adjust TC for any leftover data in the FIFO */ |
663 | if (!fifo8_is_empty(&s->fifo)) { | |
664 | esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); | |
665 | } | |
666 | ||
82141c8b | 667 | /* Copy device data to FIFO */ |
042879fc MCA |
668 | len = MIN(len, fifo8_num_free(&s->fifo)); |
669 | fifo8_push_all(&s->fifo, s->async_buf, len); | |
82141c8b MCA |
670 | s->async_buf += len; |
671 | s->async_len -= len; | |
672 | s->ti_size -= len; | |
7aa6baee MCA |
673 | |
674 | /* | |
675 | * MacOS toolbox uses a TI length of 16 bytes for all commands, so | |
676 | * commands shorter than this must be padded accordingly | |
677 | */ | |
678 | if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) { | |
679 | while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) { | |
e5455b8c | 680 | esp_fifo_push(&s->fifo, 0); |
7aa6baee MCA |
681 | len++; |
682 | } | |
683 | } | |
684 | ||
82141c8b | 685 | esp_set_tc(s, esp_get_tc(s) - len); |
77987ef5 | 686 | esp_set_pdma_cb(s, DO_DMA_PDMA_CB); |
74d71ea1 | 687 | esp_raise_drq(s); |
82141c8b MCA |
688 | |
689 | /* Indicate transfer to FIFO is complete */ | |
690 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
74d71ea1 LV |
691 | return; |
692 | } | |
a917d384 | 693 | } |
6cc88d6b | 694 | esp_set_tc(s, esp_get_tc(s) - len); |
a917d384 PB |
695 | s->async_buf += len; |
696 | s->async_len -= len; | |
94d5c79d | 697 | if (to_device) { |
6787f5fa | 698 | s->ti_size += len; |
94d5c79d | 699 | } else { |
6787f5fa | 700 | s->ti_size -= len; |
94d5c79d | 701 | } |
a917d384 | 702 | if (s->async_len == 0) { |
ad3376cc | 703 | scsi_req_continue(s->current_req); |
94d5c79d MCA |
704 | /* |
705 | * If there is still data to be read from the device then | |
706 | * complete the DMA operation immediately. Otherwise defer | |
707 | * until the scsi layer has completed. | |
708 | */ | |
6cc88d6b | 709 | if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) { |
ad3376cc | 710 | return; |
4d611c9a | 711 | } |
a917d384 | 712 | } |
ad3376cc PB |
713 | |
714 | /* Partially filled a scsi buffer. Complete immediately. */ | |
715 | esp_dma_done(s); | |
82141c8b | 716 | esp_lower_drq(s); |
4d611c9a PB |
717 | } |
718 | ||
1b9e48a5 MCA |
719 | static void esp_do_nodma(ESPState *s) |
720 | { | |
721 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); | |
7b320a8e | 722 | uint32_t cmdlen; |
1b9e48a5 MCA |
723 | int len; |
724 | ||
725 | if (s->do_cmd) { | |
726 | cmdlen = fifo8_num_used(&s->cmdfifo); | |
727 | trace_esp_handle_ti_cmd(cmdlen); | |
728 | s->ti_size = 0; | |
729 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { | |
730 | /* No command received */ | |
731 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { | |
732 | return; | |
733 | } | |
734 | ||
735 | /* Command has been received */ | |
736 | s->do_cmd = 0; | |
737 | do_cmd(s); | |
738 | } else { | |
739 | /* | |
740 | * Extra message out bytes received: update cmdfifo_cdb_offset | |
2cb40d44 | 741 | * and then switch to command phase |
1b9e48a5 MCA |
742 | */ |
743 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); | |
744 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; | |
745 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
746 | s->rregs[ESP_RINTR] |= INTR_BS; | |
747 | esp_raise_irq(s); | |
748 | } | |
749 | return; | |
750 | } | |
751 | ||
0db89536 MCA |
752 | if (!s->current_req) { |
753 | return; | |
754 | } | |
755 | ||
1b9e48a5 MCA |
756 | if (s->async_len == 0) { |
757 | /* Defer until data is available. */ | |
758 | return; | |
759 | } | |
760 | ||
761 | if (to_device) { | |
762 | len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ); | |
7b320a8e | 763 | esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
1b9e48a5 MCA |
764 | s->async_buf += len; |
765 | s->async_len -= len; | |
766 | s->ti_size += len; | |
767 | } else { | |
6ef2cabc MCA |
768 | if (fifo8_is_empty(&s->fifo)) { |
769 | fifo8_push(&s->fifo, s->async_buf[0]); | |
770 | s->async_buf++; | |
771 | s->async_len--; | |
772 | s->ti_size--; | |
773 | } | |
1b9e48a5 MCA |
774 | } |
775 | ||
776 | if (s->async_len == 0) { | |
777 | scsi_req_continue(s->current_req); | |
6ef2cabc | 778 | return; |
1b9e48a5 MCA |
779 | } |
780 | ||
781 | s->rregs[ESP_RINTR] |= INTR_BS; | |
782 | esp_raise_irq(s); | |
783 | } | |
784 | ||
77987ef5 MCA |
785 | static void esp_pdma_cb(ESPState *s) |
786 | { | |
787 | switch (s->pdma_cb) { | |
788 | case SATN_PDMA_CB: | |
789 | satn_pdma_cb(s); | |
790 | break; | |
791 | case S_WITHOUT_SATN_PDMA_CB: | |
792 | s_without_satn_pdma_cb(s); | |
793 | break; | |
794 | case SATN_STOP_PDMA_CB: | |
795 | satn_stop_pdma_cb(s); | |
796 | break; | |
797 | case WRITE_RESPONSE_PDMA_CB: | |
798 | write_response_pdma_cb(s); | |
799 | break; | |
800 | case DO_DMA_PDMA_CB: | |
801 | do_dma_pdma_cb(s); | |
802 | break; | |
803 | default: | |
804 | g_assert_not_reached(); | |
805 | } | |
806 | } | |
807 | ||
4aaa6ac3 | 808 | void esp_command_complete(SCSIRequest *req, size_t resid) |
2e5d83bb | 809 | { |
4aaa6ac3 | 810 | ESPState *s = req->hba_private; |
6ef2cabc | 811 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
4aaa6ac3 | 812 | |
bf4b9889 | 813 | trace_esp_command_complete(); |
6ef2cabc MCA |
814 | |
815 | /* | |
816 | * Non-DMA transfers from the target will leave the last byte in | |
817 | * the FIFO so don't reset ti_size in this case | |
818 | */ | |
819 | if (s->dma || to_device) { | |
820 | if (s->ti_size != 0) { | |
821 | trace_esp_command_complete_unexpected(); | |
822 | } | |
823 | s->ti_size = 0; | |
c6df7102 | 824 | } |
6ef2cabc | 825 | |
c6df7102 | 826 | s->async_len = 0; |
4aaa6ac3 | 827 | if (req->status) { |
bf4b9889 | 828 | trace_esp_command_complete_fail(); |
c6df7102 | 829 | } |
4aaa6ac3 | 830 | s->status = req->status; |
6ef2cabc MCA |
831 | |
832 | /* | |
833 | * If the transfer is finished, switch to status phase. For non-DMA | |
834 | * transfers from the target the last byte is still in the FIFO | |
835 | */ | |
836 | if (s->ti_size == 0) { | |
837 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
838 | esp_dma_done(s); | |
839 | esp_lower_drq(s); | |
840 | } | |
841 | ||
c6df7102 PB |
842 | if (s->current_req) { |
843 | scsi_req_unref(s->current_req); | |
844 | s->current_req = NULL; | |
845 | s->current_dev = NULL; | |
846 | } | |
847 | } | |
848 | ||
9c7e23fc | 849 | void esp_transfer_data(SCSIRequest *req, uint32_t len) |
c6df7102 | 850 | { |
e6810db8 | 851 | ESPState *s = req->hba_private; |
4e78f3bf | 852 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
6cc88d6b | 853 | uint32_t dmalen = esp_get_tc(s); |
c6df7102 | 854 | |
7f0b6e11 | 855 | assert(!s->do_cmd); |
6cc88d6b | 856 | trace_esp_transfer_data(dmalen, s->ti_size); |
aba1f023 | 857 | s->async_len = len; |
c6df7102 | 858 | s->async_buf = scsi_req_get_buf(req); |
4e78f3bf MCA |
859 | |
860 | if (!to_device && !s->data_in_ready) { | |
861 | /* | |
862 | * Initial incoming data xfer is complete so raise command | |
863 | * completion interrupt | |
864 | */ | |
865 | s->data_in_ready = true; | |
866 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
867 | s->rregs[ESP_RINTR] |= INTR_BS; | |
868 | esp_raise_irq(s); | |
4e78f3bf MCA |
869 | } |
870 | ||
1b9e48a5 | 871 | if (s->ti_cmd == 0) { |
94d5c79d | 872 | /* |
1b9e48a5 MCA |
873 | * Always perform the initial transfer upon reception of the next TI |
874 | * command to ensure the DMA/non-DMA status of the command is correct. | |
875 | * It is not possible to use s->dma directly in the section below as | |
876 | * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the | |
877 | * async data transfer is delayed then s->dma is set incorrectly. | |
94d5c79d | 878 | */ |
1b9e48a5 MCA |
879 | return; |
880 | } | |
881 | ||
880d3089 | 882 | if (s->ti_cmd == (CMD_TI | CMD_DMA)) { |
1b9e48a5 MCA |
883 | if (dmalen) { |
884 | esp_do_dma(s); | |
885 | } else if (s->ti_size <= 0) { | |
886 | /* | |
887 | * If this was the last part of a DMA transfer then the | |
888 | * completion interrupt is deferred to here. | |
889 | */ | |
890 | esp_dma_done(s); | |
891 | esp_lower_drq(s); | |
892 | } | |
880d3089 | 893 | } else if (s->ti_cmd == CMD_TI) { |
1b9e48a5 | 894 | esp_do_nodma(s); |
4d611c9a | 895 | } |
2e5d83bb PB |
896 | } |
897 | ||
2f275b8f FB |
898 | static void handle_ti(ESPState *s) |
899 | { | |
1b9e48a5 | 900 | uint32_t dmalen; |
2f275b8f | 901 | |
7246e160 HP |
902 | if (s->dma && !s->dma_enabled) { |
903 | s->dma_cb = handle_ti; | |
904 | return; | |
905 | } | |
906 | ||
1b9e48a5 | 907 | s->ti_cmd = s->rregs[ESP_CMD]; |
4f6200f0 | 908 | if (s->dma) { |
1b9e48a5 | 909 | dmalen = esp_get_tc(s); |
b76624de | 910 | trace_esp_handle_ti(dmalen); |
5ad6bb97 | 911 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 912 | esp_do_dma(s); |
1b9e48a5 MCA |
913 | } else { |
914 | trace_esp_handle_ti(s->ti_size); | |
915 | esp_do_nodma(s); | |
9f149aa9 | 916 | } |
2f275b8f FB |
917 | } |
918 | ||
9c7e23fc | 919 | void esp_hard_reset(ESPState *s) |
6f7e9aec | 920 | { |
5aca8c3b BS |
921 | memset(s->rregs, 0, ESP_REGS); |
922 | memset(s->wregs, 0, ESP_REGS); | |
c9cf45c1 | 923 | s->tchi_written = 0; |
4e9aec74 | 924 | s->ti_size = 0; |
3f26c975 | 925 | s->async_len = 0; |
042879fc | 926 | fifo8_reset(&s->fifo); |
023666da | 927 | fifo8_reset(&s->cmdfifo); |
4e9aec74 | 928 | s->dma = 0; |
9f149aa9 | 929 | s->do_cmd = 0; |
73d74342 | 930 | s->dma_cb = NULL; |
8dea1dd4 BS |
931 | |
932 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
933 | } |
934 | ||
a391fdbc | 935 | static void esp_soft_reset(ESPState *s) |
85948643 | 936 | { |
85948643 | 937 | qemu_irq_lower(s->irq); |
74d71ea1 | 938 | qemu_irq_lower(s->irq_data); |
a391fdbc | 939 | esp_hard_reset(s); |
85948643 BS |
940 | } |
941 | ||
c6e51f1b JM |
942 | static void esp_bus_reset(ESPState *s) |
943 | { | |
4a5fc890 | 944 | bus_cold_reset(BUS(&s->bus)); |
c6e51f1b JM |
945 | } |
946 | ||
a391fdbc | 947 | static void parent_esp_reset(ESPState *s, int irq, int level) |
2d069bab | 948 | { |
85948643 | 949 | if (level) { |
a391fdbc | 950 | esp_soft_reset(s); |
85948643 | 951 | } |
2d069bab BS |
952 | } |
953 | ||
9c7e23fc | 954 | uint64_t esp_reg_read(ESPState *s, uint32_t saddr) |
73d74342 | 955 | { |
b630c075 | 956 | uint32_t val; |
73d74342 | 957 | |
6f7e9aec | 958 | switch (saddr) { |
5ad6bb97 | 959 | case ESP_FIFO: |
1b9e48a5 MCA |
960 | if (s->dma_memory_read && s->dma_memory_write && |
961 | (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { | |
ff589551 PP |
962 | /* Data out. */ |
963 | qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); | |
964 | s->rregs[ESP_FIFO] = 0; | |
042879fc | 965 | } else { |
6ef2cabc MCA |
966 | if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { |
967 | if (s->ti_size) { | |
968 | esp_do_nodma(s); | |
969 | } else { | |
970 | /* | |
971 | * The last byte of a non-DMA transfer has been read out | |
972 | * of the FIFO so switch to status phase | |
973 | */ | |
974 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
975 | } | |
976 | } | |
c5fef911 | 977 | s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); |
4f6200f0 | 978 | } |
b630c075 | 979 | val = s->rregs[ESP_FIFO]; |
f930d07e | 980 | break; |
5ad6bb97 | 981 | case ESP_RINTR: |
94d5c79d MCA |
982 | /* |
983 | * Clear sequence step, interrupt register and all status bits | |
984 | * except TC | |
985 | */ | |
b630c075 | 986 | val = s->rregs[ESP_RINTR]; |
2814df28 BS |
987 | s->rregs[ESP_RINTR] = 0; |
988 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
af947a3d MCA |
989 | /* |
990 | * According to the datasheet ESP_RSEQ should be cleared, but as the | |
991 | * emulation currently defers information transfers to the next TI | |
992 | * command leave it for now so that pedantic guests such as the old | |
993 | * Linux 2.6 driver see the correct flags before the next SCSI phase | |
994 | * transition. | |
995 | * | |
996 | * s->rregs[ESP_RSEQ] = SEQ_0; | |
997 | */ | |
c73f96fd | 998 | esp_lower_irq(s); |
b630c075 | 999 | break; |
c9cf45c1 HR |
1000 | case ESP_TCHI: |
1001 | /* Return the unique id if the value has never been written */ | |
1002 | if (!s->tchi_written) { | |
b630c075 MCA |
1003 | val = s->chip_id; |
1004 | } else { | |
1005 | val = s->rregs[saddr]; | |
c9cf45c1 | 1006 | } |
b630c075 | 1007 | break; |
238ec4d7 MCA |
1008 | case ESP_RFLAGS: |
1009 | /* Bottom 5 bits indicate number of bytes in FIFO */ | |
1010 | val = fifo8_num_used(&s->fifo); | |
1011 | break; | |
6f7e9aec | 1012 | default: |
b630c075 | 1013 | val = s->rregs[saddr]; |
f930d07e | 1014 | break; |
6f7e9aec | 1015 | } |
b630c075 MCA |
1016 | |
1017 | trace_esp_mem_readb(saddr, val); | |
1018 | return val; | |
6f7e9aec FB |
1019 | } |
1020 | ||
9c7e23fc | 1021 | void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) |
6f7e9aec | 1022 | { |
bf4b9889 | 1023 | trace_esp_mem_writeb(saddr, s->wregs[saddr], val); |
6f7e9aec | 1024 | switch (saddr) { |
c9cf45c1 HR |
1025 | case ESP_TCHI: |
1026 | s->tchi_written = true; | |
1027 | /* fall through */ | |
5ad6bb97 BS |
1028 | case ESP_TCLO: |
1029 | case ESP_TCMID: | |
1030 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 1031 | break; |
5ad6bb97 | 1032 | case ESP_FIFO: |
9f149aa9 | 1033 | if (s->do_cmd) { |
e5455b8c | 1034 | esp_fifo_push(&s->cmdfifo, val); |
6ef2cabc MCA |
1035 | |
1036 | /* | |
1037 | * If any unexpected message out/command phase data is | |
1038 | * transferred using non-DMA, raise the interrupt | |
1039 | */ | |
1040 | if (s->rregs[ESP_CMD] == CMD_TI) { | |
1041 | s->rregs[ESP_RINTR] |= INTR_BS; | |
1042 | esp_raise_irq(s); | |
1043 | } | |
2e5d83bb | 1044 | } else { |
e5455b8c | 1045 | esp_fifo_push(&s->fifo, val); |
2e5d83bb | 1046 | } |
f930d07e | 1047 | break; |
5ad6bb97 | 1048 | case ESP_CMD: |
4f6200f0 | 1049 | s->rregs[saddr] = val; |
5ad6bb97 | 1050 | if (val & CMD_DMA) { |
f930d07e | 1051 | s->dma = 1; |
6787f5fa | 1052 | /* Reload DMA counter. */ |
96676c2f MCA |
1053 | if (esp_get_stc(s) == 0) { |
1054 | esp_set_tc(s, 0x10000); | |
1055 | } else { | |
1056 | esp_set_tc(s, esp_get_stc(s)); | |
1057 | } | |
f930d07e BS |
1058 | } else { |
1059 | s->dma = 0; | |
1060 | } | |
94d5c79d | 1061 | switch (val & CMD_CMD) { |
5ad6bb97 | 1062 | case CMD_NOP: |
bf4b9889 | 1063 | trace_esp_mem_writeb_cmd_nop(val); |
f930d07e | 1064 | break; |
5ad6bb97 | 1065 | case CMD_FLUSH: |
bf4b9889 | 1066 | trace_esp_mem_writeb_cmd_flush(val); |
042879fc | 1067 | fifo8_reset(&s->fifo); |
f930d07e | 1068 | break; |
5ad6bb97 | 1069 | case CMD_RESET: |
bf4b9889 | 1070 | trace_esp_mem_writeb_cmd_reset(val); |
a391fdbc | 1071 | esp_soft_reset(s); |
f930d07e | 1072 | break; |
5ad6bb97 | 1073 | case CMD_BUSRESET: |
bf4b9889 | 1074 | trace_esp_mem_writeb_cmd_bus_reset(val); |
c6e51f1b | 1075 | esp_bus_reset(s); |
5ad6bb97 | 1076 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { |
cf47a41e | 1077 | s->rregs[ESP_RINTR] |= INTR_RST; |
c73f96fd | 1078 | esp_raise_irq(s); |
9e61bde5 | 1079 | } |
f930d07e | 1080 | break; |
5ad6bb97 | 1081 | case CMD_TI: |
0097d3ec | 1082 | trace_esp_mem_writeb_cmd_ti(val); |
f930d07e BS |
1083 | handle_ti(s); |
1084 | break; | |
5ad6bb97 | 1085 | case CMD_ICCS: |
bf4b9889 | 1086 | trace_esp_mem_writeb_cmd_iccs(val); |
f930d07e | 1087 | write_response(s); |
cf47a41e | 1088 | s->rregs[ESP_RINTR] |= INTR_FC; |
4bf5801d | 1089 | s->rregs[ESP_RSTAT] |= STAT_MI; |
f930d07e | 1090 | break; |
5ad6bb97 | 1091 | case CMD_MSGACC: |
bf4b9889 | 1092 | trace_esp_mem_writeb_cmd_msgacc(val); |
cf47a41e | 1093 | s->rregs[ESP_RINTR] |= INTR_DC; |
5ad6bb97 | 1094 | s->rregs[ESP_RSEQ] = 0; |
4e2a68c1 AT |
1095 | s->rregs[ESP_RFLAGS] = 0; |
1096 | esp_raise_irq(s); | |
f930d07e | 1097 | break; |
0fd0eb21 | 1098 | case CMD_PAD: |
bf4b9889 | 1099 | trace_esp_mem_writeb_cmd_pad(val); |
0fd0eb21 | 1100 | s->rregs[ESP_RSTAT] = STAT_TC; |
cf47a41e | 1101 | s->rregs[ESP_RINTR] |= INTR_FC; |
0fd0eb21 BS |
1102 | s->rregs[ESP_RSEQ] = 0; |
1103 | break; | |
5ad6bb97 | 1104 | case CMD_SATN: |
bf4b9889 | 1105 | trace_esp_mem_writeb_cmd_satn(val); |
f930d07e | 1106 | break; |
6915bff1 HP |
1107 | case CMD_RSTATN: |
1108 | trace_esp_mem_writeb_cmd_rstatn(val); | |
1109 | break; | |
5e1e0a3b | 1110 | case CMD_SEL: |
bf4b9889 | 1111 | trace_esp_mem_writeb_cmd_sel(val); |
f2818f22 | 1112 | handle_s_without_atn(s); |
5e1e0a3b | 1113 | break; |
5ad6bb97 | 1114 | case CMD_SELATN: |
bf4b9889 | 1115 | trace_esp_mem_writeb_cmd_selatn(val); |
f930d07e BS |
1116 | handle_satn(s); |
1117 | break; | |
5ad6bb97 | 1118 | case CMD_SELATNS: |
bf4b9889 | 1119 | trace_esp_mem_writeb_cmd_selatns(val); |
f930d07e BS |
1120 | handle_satn_stop(s); |
1121 | break; | |
5ad6bb97 | 1122 | case CMD_ENSEL: |
bf4b9889 | 1123 | trace_esp_mem_writeb_cmd_ensel(val); |
e3926838 | 1124 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 1125 | break; |
6fe84c18 HP |
1126 | case CMD_DISSEL: |
1127 | trace_esp_mem_writeb_cmd_dissel(val); | |
1128 | s->rregs[ESP_RINTR] = 0; | |
1129 | esp_raise_irq(s); | |
1130 | break; | |
f930d07e | 1131 | default: |
3af4e9aa | 1132 | trace_esp_error_unhandled_command(val); |
f930d07e BS |
1133 | break; |
1134 | } | |
1135 | break; | |
5ad6bb97 | 1136 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 1137 | break; |
5ad6bb97 | 1138 | case ESP_CFG1: |
9ea73f8b PB |
1139 | case ESP_CFG2: case ESP_CFG3: |
1140 | case ESP_RES3: case ESP_RES4: | |
4f6200f0 FB |
1141 | s->rregs[saddr] = val; |
1142 | break; | |
5ad6bb97 | 1143 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 1144 | break; |
6f7e9aec | 1145 | default: |
3af4e9aa | 1146 | trace_esp_error_invalid_write(val, saddr); |
8dea1dd4 | 1147 | return; |
6f7e9aec | 1148 | } |
2f275b8f | 1149 | s->wregs[saddr] = val; |
6f7e9aec FB |
1150 | } |
1151 | ||
a8170e5e | 1152 | static bool esp_mem_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
1153 | unsigned size, bool is_write, |
1154 | MemTxAttrs attrs) | |
67bb5314 AK |
1155 | { |
1156 | return (size == 1) || (is_write && size == 4); | |
1157 | } | |
6f7e9aec | 1158 | |
6cc88d6b MCA |
1159 | static bool esp_is_before_version_5(void *opaque, int version_id) |
1160 | { | |
1161 | ESPState *s = ESP(opaque); | |
1162 | ||
1163 | version_id = MIN(version_id, s->mig_version_id); | |
1164 | return version_id < 5; | |
1165 | } | |
1166 | ||
4e78f3bf MCA |
1167 | static bool esp_is_version_5(void *opaque, int version_id) |
1168 | { | |
1169 | ESPState *s = ESP(opaque); | |
1170 | ||
1171 | version_id = MIN(version_id, s->mig_version_id); | |
0bcd5a18 | 1172 | return version_id >= 5; |
4e78f3bf MCA |
1173 | } |
1174 | ||
4eb86065 PB |
1175 | static bool esp_is_version_6(void *opaque, int version_id) |
1176 | { | |
1177 | ESPState *s = ESP(opaque); | |
1178 | ||
1179 | version_id = MIN(version_id, s->mig_version_id); | |
1180 | return version_id >= 6; | |
1181 | } | |
1182 | ||
ff4a1dab | 1183 | int esp_pre_save(void *opaque) |
0bd005be | 1184 | { |
ff4a1dab MCA |
1185 | ESPState *s = ESP(object_resolve_path_component( |
1186 | OBJECT(opaque), "esp")); | |
0bd005be MCA |
1187 | |
1188 | s->mig_version_id = vmstate_esp.version_id; | |
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | static int esp_post_load(void *opaque, int version_id) | |
1193 | { | |
1194 | ESPState *s = ESP(opaque); | |
042879fc | 1195 | int len, i; |
0bd005be | 1196 | |
6cc88d6b MCA |
1197 | version_id = MIN(version_id, s->mig_version_id); |
1198 | ||
1199 | if (version_id < 5) { | |
1200 | esp_set_tc(s, s->mig_dma_left); | |
042879fc MCA |
1201 | |
1202 | /* Migrate ti_buf to fifo */ | |
1203 | len = s->mig_ti_wptr - s->mig_ti_rptr; | |
1204 | for (i = 0; i < len; i++) { | |
1205 | fifo8_push(&s->fifo, s->mig_ti_buf[i]); | |
1206 | } | |
023666da MCA |
1207 | |
1208 | /* Migrate cmdbuf to cmdfifo */ | |
1209 | for (i = 0; i < s->mig_cmdlen; i++) { | |
1210 | fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); | |
1211 | } | |
6cc88d6b MCA |
1212 | } |
1213 | ||
0bd005be MCA |
1214 | s->mig_version_id = vmstate_esp.version_id; |
1215 | return 0; | |
1216 | } | |
1217 | ||
eda59b39 MCA |
1218 | /* |
1219 | * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the | |
1220 | * guest CPU to perform the transfers between the SCSI bus and memory | |
1221 | * itself. This is indicated by the dma_memory_read and dma_memory_write | |
1222 | * functions being NULL (in contrast to the ESP PCI device) whilst | |
1223 | * dma_enabled is still set. | |
1224 | */ | |
1225 | ||
1226 | static bool esp_pdma_needed(void *opaque) | |
1227 | { | |
1228 | ESPState *s = ESP(opaque); | |
1229 | ||
1230 | return s->dma_memory_read == NULL && s->dma_memory_write == NULL && | |
1231 | s->dma_enabled; | |
1232 | } | |
1233 | ||
1234 | static const VMStateDescription vmstate_esp_pdma = { | |
1235 | .name = "esp/pdma", | |
1236 | .version_id = 0, | |
1237 | .minimum_version_id = 0, | |
1238 | .needed = esp_pdma_needed, | |
1239 | .fields = (VMStateField[]) { | |
1240 | VMSTATE_UINT8(pdma_cb, ESPState), | |
1241 | VMSTATE_END_OF_LIST() | |
1242 | } | |
1243 | }; | |
1244 | ||
9c7e23fc | 1245 | const VMStateDescription vmstate_esp = { |
94d5c79d | 1246 | .name = "esp", |
4eb86065 | 1247 | .version_id = 6, |
cc9952f3 | 1248 | .minimum_version_id = 3, |
0bd005be | 1249 | .post_load = esp_post_load, |
35d08458 | 1250 | .fields = (VMStateField[]) { |
cc9952f3 BS |
1251 | VMSTATE_BUFFER(rregs, ESPState), |
1252 | VMSTATE_BUFFER(wregs, ESPState), | |
1253 | VMSTATE_INT32(ti_size, ESPState), | |
042879fc MCA |
1254 | VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), |
1255 | VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), | |
1256 | VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), | |
3944966d | 1257 | VMSTATE_UINT32(status, ESPState), |
4aaa6ac3 MCA |
1258 | VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, |
1259 | esp_is_before_version_5), | |
1260 | VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, | |
1261 | esp_is_before_version_5), | |
cc9952f3 | 1262 | VMSTATE_UINT32(dma, ESPState), |
023666da MCA |
1263 | VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, |
1264 | esp_is_before_version_5, 0, 16), | |
1265 | VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, | |
1266 | esp_is_before_version_5, 16, | |
1267 | sizeof(typeof_field(ESPState, mig_cmdbuf))), | |
1268 | VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), | |
cc9952f3 | 1269 | VMSTATE_UINT32(do_cmd, ESPState), |
6cc88d6b | 1270 | VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), |
4e78f3bf | 1271 | VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), |
023666da | 1272 | VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), |
042879fc | 1273 | VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), |
023666da | 1274 | VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), |
1b9e48a5 | 1275 | VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), |
4eb86065 | 1276 | VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), |
cc9952f3 | 1277 | VMSTATE_END_OF_LIST() |
74d71ea1 | 1278 | }, |
eda59b39 MCA |
1279 | .subsections = (const VMStateDescription * []) { |
1280 | &vmstate_esp_pdma, | |
1281 | NULL | |
1282 | } | |
cc9952f3 | 1283 | }; |
6f7e9aec | 1284 | |
a8170e5e | 1285 | static void sysbus_esp_mem_write(void *opaque, hwaddr addr, |
a391fdbc HP |
1286 | uint64_t val, unsigned int size) |
1287 | { | |
1288 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1289 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1290 | uint32_t saddr; |
1291 | ||
1292 | saddr = addr >> sysbus->it_shift; | |
eb169c76 | 1293 | esp_reg_write(s, saddr, val); |
a391fdbc HP |
1294 | } |
1295 | ||
a8170e5e | 1296 | static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, |
a391fdbc HP |
1297 | unsigned int size) |
1298 | { | |
1299 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1300 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1301 | uint32_t saddr; |
1302 | ||
1303 | saddr = addr >> sysbus->it_shift; | |
eb169c76 | 1304 | return esp_reg_read(s, saddr); |
a391fdbc HP |
1305 | } |
1306 | ||
1307 | static const MemoryRegionOps sysbus_esp_mem_ops = { | |
1308 | .read = sysbus_esp_mem_read, | |
1309 | .write = sysbus_esp_mem_write, | |
1310 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1311 | .valid.accepts = esp_mem_accepts, | |
1312 | }; | |
1313 | ||
74d71ea1 LV |
1314 | static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, |
1315 | uint64_t val, unsigned int size) | |
1316 | { | |
1317 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1318 | ESPState *s = ESP(&sysbus->esp); |
74d71ea1 | 1319 | |
960ebfd9 MCA |
1320 | trace_esp_pdma_write(size); |
1321 | ||
74d71ea1 LV |
1322 | switch (size) { |
1323 | case 1: | |
761bef75 | 1324 | esp_pdma_write(s, val); |
74d71ea1 LV |
1325 | break; |
1326 | case 2: | |
761bef75 MCA |
1327 | esp_pdma_write(s, val >> 8); |
1328 | esp_pdma_write(s, val); | |
74d71ea1 LV |
1329 | break; |
1330 | } | |
d0243b09 | 1331 | esp_pdma_cb(s); |
74d71ea1 LV |
1332 | } |
1333 | ||
1334 | static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, | |
1335 | unsigned int size) | |
1336 | { | |
1337 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1338 | ESPState *s = ESP(&sysbus->esp); |
74d71ea1 LV |
1339 | uint64_t val = 0; |
1340 | ||
960ebfd9 MCA |
1341 | trace_esp_pdma_read(size); |
1342 | ||
74d71ea1 LV |
1343 | switch (size) { |
1344 | case 1: | |
761bef75 | 1345 | val = esp_pdma_read(s); |
74d71ea1 LV |
1346 | break; |
1347 | case 2: | |
761bef75 MCA |
1348 | val = esp_pdma_read(s); |
1349 | val = (val << 8) | esp_pdma_read(s); | |
74d71ea1 LV |
1350 | break; |
1351 | } | |
7aa6baee | 1352 | if (fifo8_num_used(&s->fifo) < 2) { |
d0243b09 | 1353 | esp_pdma_cb(s); |
74d71ea1 LV |
1354 | } |
1355 | return val; | |
1356 | } | |
1357 | ||
a7a22088 MCA |
1358 | static void *esp_load_request(QEMUFile *f, SCSIRequest *req) |
1359 | { | |
1360 | ESPState *s = container_of(req->bus, ESPState, bus); | |
1361 | ||
1362 | scsi_req_ref(req); | |
1363 | s->current_req = req; | |
1364 | return s; | |
1365 | } | |
1366 | ||
74d71ea1 LV |
1367 | static const MemoryRegionOps sysbus_esp_pdma_ops = { |
1368 | .read = sysbus_esp_pdma_read, | |
1369 | .write = sysbus_esp_pdma_write, | |
1370 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1371 | .valid.min_access_size = 1, | |
cf1b8286 MCA |
1372 | .valid.max_access_size = 4, |
1373 | .impl.min_access_size = 1, | |
1374 | .impl.max_access_size = 2, | |
74d71ea1 LV |
1375 | }; |
1376 | ||
afd4030c PB |
1377 | static const struct SCSIBusInfo esp_scsi_info = { |
1378 | .tcq = false, | |
7e0380b9 PB |
1379 | .max_target = ESP_MAX_DEVS, |
1380 | .max_lun = 7, | |
afd4030c | 1381 | |
a7a22088 | 1382 | .load_request = esp_load_request, |
c6df7102 | 1383 | .transfer_data = esp_transfer_data, |
94d3f98a PB |
1384 | .complete = esp_command_complete, |
1385 | .cancel = esp_request_cancelled | |
cfdc1bb0 PB |
1386 | }; |
1387 | ||
a391fdbc | 1388 | static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) |
cfb9de9c | 1389 | { |
84fbefed | 1390 | SysBusESPState *sysbus = SYSBUS_ESP(opaque); |
eb169c76 | 1391 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1392 | |
1393 | switch (irq) { | |
1394 | case 0: | |
1395 | parent_esp_reset(s, irq, level); | |
1396 | break; | |
1397 | case 1: | |
1398 | esp_dma_enable(opaque, irq, level); | |
1399 | break; | |
1400 | } | |
1401 | } | |
1402 | ||
b09318ca | 1403 | static void sysbus_esp_realize(DeviceState *dev, Error **errp) |
a391fdbc | 1404 | { |
b09318ca | 1405 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
84fbefed | 1406 | SysBusESPState *sysbus = SYSBUS_ESP(dev); |
eb169c76 MCA |
1407 | ESPState *s = ESP(&sysbus->esp); |
1408 | ||
1409 | if (!qdev_realize(DEVICE(s), NULL, errp)) { | |
1410 | return; | |
1411 | } | |
6f7e9aec | 1412 | |
b09318ca | 1413 | sysbus_init_irq(sbd, &s->irq); |
74d71ea1 | 1414 | sysbus_init_irq(sbd, &s->irq_data); |
a391fdbc | 1415 | assert(sysbus->it_shift != -1); |
6f7e9aec | 1416 | |
d32e4b3d | 1417 | s->chip_id = TCHI_FAS100A; |
29776739 | 1418 | memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, |
74d71ea1 | 1419 | sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); |
b09318ca | 1420 | sysbus_init_mmio(sbd, &sysbus->iomem); |
74d71ea1 | 1421 | memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, |
cf1b8286 | 1422 | sysbus, "esp-pdma", 4); |
74d71ea1 | 1423 | sysbus_init_mmio(sbd, &sysbus->pdma); |
6f7e9aec | 1424 | |
b09318ca | 1425 | qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); |
2d069bab | 1426 | |
739e95f5 | 1427 | scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); |
67e999be | 1428 | } |
cfb9de9c | 1429 | |
a391fdbc HP |
1430 | static void sysbus_esp_hard_reset(DeviceState *dev) |
1431 | { | |
84fbefed | 1432 | SysBusESPState *sysbus = SYSBUS_ESP(dev); |
eb169c76 MCA |
1433 | ESPState *s = ESP(&sysbus->esp); |
1434 | ||
1435 | esp_hard_reset(s); | |
1436 | } | |
1437 | ||
1438 | static void sysbus_esp_init(Object *obj) | |
1439 | { | |
1440 | SysBusESPState *sysbus = SYSBUS_ESP(obj); | |
1441 | ||
1442 | object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); | |
a391fdbc HP |
1443 | } |
1444 | ||
1445 | static const VMStateDescription vmstate_sysbus_esp_scsi = { | |
1446 | .name = "sysbusespscsi", | |
0bd005be | 1447 | .version_id = 2, |
ea84a442 | 1448 | .minimum_version_id = 1, |
ff4a1dab | 1449 | .pre_save = esp_pre_save, |
a391fdbc | 1450 | .fields = (VMStateField[]) { |
0bd005be | 1451 | VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), |
a391fdbc HP |
1452 | VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), |
1453 | VMSTATE_END_OF_LIST() | |
1454 | } | |
999e12bb AL |
1455 | }; |
1456 | ||
a391fdbc | 1457 | static void sysbus_esp_class_init(ObjectClass *klass, void *data) |
999e12bb | 1458 | { |
39bffca2 | 1459 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1460 | |
b09318ca | 1461 | dc->realize = sysbus_esp_realize; |
a391fdbc HP |
1462 | dc->reset = sysbus_esp_hard_reset; |
1463 | dc->vmsd = &vmstate_sysbus_esp_scsi; | |
125ee0ed | 1464 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
999e12bb AL |
1465 | } |
1466 | ||
1f077308 | 1467 | static const TypeInfo sysbus_esp_info = { |
84fbefed | 1468 | .name = TYPE_SYSBUS_ESP, |
39bffca2 | 1469 | .parent = TYPE_SYS_BUS_DEVICE, |
eb169c76 | 1470 | .instance_init = sysbus_esp_init, |
a391fdbc HP |
1471 | .instance_size = sizeof(SysBusESPState), |
1472 | .class_init = sysbus_esp_class_init, | |
63235df8 BS |
1473 | }; |
1474 | ||
042879fc MCA |
1475 | static void esp_finalize(Object *obj) |
1476 | { | |
1477 | ESPState *s = ESP(obj); | |
1478 | ||
1479 | fifo8_destroy(&s->fifo); | |
023666da | 1480 | fifo8_destroy(&s->cmdfifo); |
042879fc MCA |
1481 | } |
1482 | ||
1483 | static void esp_init(Object *obj) | |
1484 | { | |
1485 | ESPState *s = ESP(obj); | |
1486 | ||
1487 | fifo8_create(&s->fifo, ESP_FIFO_SZ); | |
023666da | 1488 | fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); |
042879fc MCA |
1489 | } |
1490 | ||
eb169c76 MCA |
1491 | static void esp_class_init(ObjectClass *klass, void *data) |
1492 | { | |
1493 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1494 | ||
1495 | /* internal device for sysbusesp/pciespscsi, not user-creatable */ | |
1496 | dc->user_creatable = false; | |
1497 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | |
1498 | } | |
1499 | ||
1500 | static const TypeInfo esp_info = { | |
1501 | .name = TYPE_ESP, | |
1502 | .parent = TYPE_DEVICE, | |
042879fc MCA |
1503 | .instance_init = esp_init, |
1504 | .instance_finalize = esp_finalize, | |
eb169c76 MCA |
1505 | .instance_size = sizeof(ESPState), |
1506 | .class_init = esp_class_init, | |
1507 | }; | |
1508 | ||
83f7d43a | 1509 | static void esp_register_types(void) |
cfb9de9c | 1510 | { |
a391fdbc | 1511 | type_register_static(&sysbus_esp_info); |
eb169c76 | 1512 | type_register_static(&esp_info); |
cfb9de9c PB |
1513 | } |
1514 | ||
83f7d43a | 1515 | type_init(esp_register_types) |