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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
fabaaf1d | 5 | * Copyright (c) 2012 Herve Poussineau |
5fafdf24 | 6 | * |
6f7e9aec FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
5d20fa6b | 25 | |
a4ab4792 | 26 | #include "qemu/osdep.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
0d09e41a | 28 | #include "hw/scsi/esp.h" |
bf4b9889 | 29 | #include "trace.h" |
da34e65c | 30 | #include "qapi/error.h" |
1de7afc9 | 31 | #include "qemu/log.h" |
6f7e9aec | 32 | |
67e999be | 33 | /* |
5ad6bb97 BS |
34 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
35 | * also produced as NCR89C100. See | |
67e999be FB |
36 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
37 | * and | |
38 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
39 | */ | |
40 | ||
c73f96fd BS |
41 | static void esp_raise_irq(ESPState *s) |
42 | { | |
43 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
44 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
45 | qemu_irq_raise(s->irq); | |
bf4b9889 | 46 | trace_esp_raise_irq(); |
c73f96fd BS |
47 | } |
48 | } | |
49 | ||
50 | static void esp_lower_irq(ESPState *s) | |
51 | { | |
52 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
53 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
54 | qemu_irq_lower(s->irq); | |
bf4b9889 | 55 | trace_esp_lower_irq(); |
c73f96fd BS |
56 | } |
57 | } | |
58 | ||
9c7e23fc | 59 | void esp_dma_enable(ESPState *s, int irq, int level) |
73d74342 | 60 | { |
73d74342 BS |
61 | if (level) { |
62 | s->dma_enabled = 1; | |
bf4b9889 | 63 | trace_esp_dma_enable(); |
73d74342 BS |
64 | if (s->dma_cb) { |
65 | s->dma_cb(s); | |
66 | s->dma_cb = NULL; | |
67 | } | |
68 | } else { | |
bf4b9889 | 69 | trace_esp_dma_disable(); |
73d74342 BS |
70 | s->dma_enabled = 0; |
71 | } | |
72 | } | |
73 | ||
9c7e23fc | 74 | void esp_request_cancelled(SCSIRequest *req) |
94d3f98a | 75 | { |
e6810db8 | 76 | ESPState *s = req->hba_private; |
94d3f98a PB |
77 | |
78 | if (req == s->current_req) { | |
79 | scsi_req_unref(s->current_req); | |
80 | s->current_req = NULL; | |
81 | s->current_dev = NULL; | |
82 | } | |
83 | } | |
84 | ||
6c1fef6b | 85 | static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) |
2f275b8f | 86 | { |
a917d384 | 87 | uint32_t dmalen; |
2f275b8f FB |
88 | int target; |
89 | ||
8dea1dd4 | 90 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 91 | if (s->dma) { |
9ea73f8b PB |
92 | dmalen = s->rregs[ESP_TCLO]; |
93 | dmalen |= s->rregs[ESP_TCMID] << 8; | |
94 | dmalen |= s->rregs[ESP_TCHI] << 16; | |
6c1fef6b PP |
95 | if (dmalen > buflen) { |
96 | return 0; | |
97 | } | |
8b17de88 | 98 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
4f6200f0 | 99 | } else { |
fc4d65da | 100 | dmalen = s->ti_size; |
d3cdc491 PP |
101 | if (dmalen > TI_BUFSZ) { |
102 | return 0; | |
103 | } | |
fc4d65da | 104 | memcpy(buf, s->ti_buf, dmalen); |
75ef8496 | 105 | buf[0] = buf[2] >> 5; |
4f6200f0 | 106 | } |
bf4b9889 | 107 | trace_esp_get_cmd(dmalen, target); |
2e5d83bb | 108 | |
2f275b8f | 109 | s->ti_size = 0; |
4f6200f0 FB |
110 | s->ti_rptr = 0; |
111 | s->ti_wptr = 0; | |
2f275b8f | 112 | |
429bef69 | 113 | if (s->current_req) { |
a917d384 | 114 | /* Started a new command before the old one finished. Cancel it. */ |
94d3f98a | 115 | scsi_req_cancel(s->current_req); |
a917d384 PB |
116 | s->async_len = 0; |
117 | } | |
118 | ||
0d3545e7 | 119 | s->current_dev = scsi_device_find(&s->bus, 0, target, 0); |
f48a7a6e | 120 | if (!s->current_dev) { |
2e5d83bb | 121 | // No such drive |
c73f96fd | 122 | s->rregs[ESP_RSTAT] = 0; |
5ad6bb97 BS |
123 | s->rregs[ESP_RINTR] = INTR_DC; |
124 | s->rregs[ESP_RSEQ] = SEQ_0; | |
c73f96fd | 125 | esp_raise_irq(s); |
f930d07e | 126 | return 0; |
2f275b8f | 127 | } |
9f149aa9 PB |
128 | return dmalen; |
129 | } | |
130 | ||
f2818f22 | 131 | static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) |
9f149aa9 PB |
132 | { |
133 | int32_t datalen; | |
134 | int lun; | |
f48a7a6e | 135 | SCSIDevice *current_lun; |
9f149aa9 | 136 | |
bf4b9889 | 137 | trace_esp_do_busid_cmd(busid); |
f2818f22 | 138 | lun = busid & 7; |
0d3545e7 | 139 | current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); |
e6810db8 | 140 | s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); |
c39ce112 | 141 | datalen = scsi_req_enqueue(s->current_req); |
67e999be FB |
142 | s->ti_size = datalen; |
143 | if (datalen != 0) { | |
c73f96fd | 144 | s->rregs[ESP_RSTAT] = STAT_TC; |
a917d384 | 145 | s->dma_left = 0; |
6787f5fa | 146 | s->dma_counter = 0; |
2e5d83bb | 147 | if (datalen > 0) { |
5ad6bb97 | 148 | s->rregs[ESP_RSTAT] |= STAT_DI; |
2e5d83bb | 149 | } else { |
5ad6bb97 | 150 | s->rregs[ESP_RSTAT] |= STAT_DO; |
b9788fc4 | 151 | } |
ad3376cc | 152 | scsi_req_continue(s->current_req); |
2f275b8f | 153 | } |
5ad6bb97 BS |
154 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
155 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 156 | esp_raise_irq(s); |
2f275b8f FB |
157 | } |
158 | ||
f2818f22 AT |
159 | static void do_cmd(ESPState *s, uint8_t *buf) |
160 | { | |
161 | uint8_t busid = buf[0]; | |
162 | ||
163 | do_busid_cmd(s, &buf[1], busid); | |
164 | } | |
165 | ||
9f149aa9 PB |
166 | static void handle_satn(ESPState *s) |
167 | { | |
168 | uint8_t buf[32]; | |
169 | int len; | |
170 | ||
1b26eaa1 | 171 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
172 | s->dma_cb = handle_satn; |
173 | return; | |
174 | } | |
6c1fef6b | 175 | len = get_cmd(s, buf, sizeof(buf)); |
9f149aa9 PB |
176 | if (len) |
177 | do_cmd(s, buf); | |
178 | } | |
179 | ||
f2818f22 AT |
180 | static void handle_s_without_atn(ESPState *s) |
181 | { | |
182 | uint8_t buf[32]; | |
183 | int len; | |
184 | ||
1b26eaa1 | 185 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
186 | s->dma_cb = handle_s_without_atn; |
187 | return; | |
188 | } | |
6c1fef6b | 189 | len = get_cmd(s, buf, sizeof(buf)); |
f2818f22 AT |
190 | if (len) { |
191 | do_busid_cmd(s, buf, 0); | |
192 | } | |
193 | } | |
194 | ||
9f149aa9 PB |
195 | static void handle_satn_stop(ESPState *s) |
196 | { | |
1b26eaa1 | 197 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
198 | s->dma_cb = handle_satn_stop; |
199 | return; | |
200 | } | |
6c1fef6b | 201 | s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); |
9f149aa9 | 202 | if (s->cmdlen) { |
bf4b9889 | 203 | trace_esp_handle_satn_stop(s->cmdlen); |
9f149aa9 | 204 | s->do_cmd = 1; |
c73f96fd | 205 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
5ad6bb97 BS |
206 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
207 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 208 | esp_raise_irq(s); |
9f149aa9 PB |
209 | } |
210 | } | |
211 | ||
0fc5c15a | 212 | static void write_response(ESPState *s) |
2f275b8f | 213 | { |
bf4b9889 | 214 | trace_esp_write_response(s->status); |
3944966d | 215 | s->ti_buf[0] = s->status; |
0fc5c15a | 216 | s->ti_buf[1] = 0; |
4f6200f0 | 217 | if (s->dma) { |
8b17de88 | 218 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); |
c73f96fd | 219 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
5ad6bb97 BS |
220 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
221 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
4f6200f0 | 222 | } else { |
f930d07e BS |
223 | s->ti_size = 2; |
224 | s->ti_rptr = 0; | |
d020aa50 | 225 | s->ti_wptr = 2; |
5ad6bb97 | 226 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 227 | } |
c73f96fd | 228 | esp_raise_irq(s); |
2f275b8f | 229 | } |
4f6200f0 | 230 | |
a917d384 PB |
231 | static void esp_dma_done(ESPState *s) |
232 | { | |
c73f96fd | 233 | s->rregs[ESP_RSTAT] |= STAT_TC; |
5ad6bb97 BS |
234 | s->rregs[ESP_RINTR] = INTR_BS; |
235 | s->rregs[ESP_RSEQ] = 0; | |
236 | s->rregs[ESP_RFLAGS] = 0; | |
237 | s->rregs[ESP_TCLO] = 0; | |
238 | s->rregs[ESP_TCMID] = 0; | |
9ea73f8b | 239 | s->rregs[ESP_TCHI] = 0; |
c73f96fd | 240 | esp_raise_irq(s); |
a917d384 PB |
241 | } |
242 | ||
4d611c9a PB |
243 | static void esp_do_dma(ESPState *s) |
244 | { | |
67e999be | 245 | uint32_t len; |
4d611c9a | 246 | int to_device; |
a917d384 | 247 | |
a917d384 | 248 | len = s->dma_left; |
4d611c9a | 249 | if (s->do_cmd) { |
bf4b9889 | 250 | trace_esp_do_dma(s->cmdlen, len); |
926cde5f PP |
251 | assert (s->cmdlen <= sizeof(s->cmdbuf) && |
252 | len <= sizeof(s->cmdbuf) - s->cmdlen); | |
8b17de88 | 253 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
4d611c9a | 254 | return; |
a917d384 PB |
255 | } |
256 | if (s->async_len == 0) { | |
257 | /* Defer until data is available. */ | |
258 | return; | |
259 | } | |
260 | if (len > s->async_len) { | |
261 | len = s->async_len; | |
262 | } | |
7f0b6e11 | 263 | to_device = (s->ti_size < 0); |
a917d384 | 264 | if (to_device) { |
8b17de88 | 265 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
4d611c9a | 266 | } else { |
8b17de88 | 267 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
a917d384 | 268 | } |
a917d384 PB |
269 | s->dma_left -= len; |
270 | s->async_buf += len; | |
271 | s->async_len -= len; | |
6787f5fa PB |
272 | if (to_device) |
273 | s->ti_size += len; | |
274 | else | |
275 | s->ti_size -= len; | |
a917d384 | 276 | if (s->async_len == 0) { |
ad3376cc PB |
277 | scsi_req_continue(s->current_req); |
278 | /* If there is still data to be read from the device then | |
279 | complete the DMA operation immediately. Otherwise defer | |
280 | until the scsi layer has completed. */ | |
281 | if (to_device || s->dma_left != 0 || s->ti_size == 0) { | |
282 | return; | |
4d611c9a | 283 | } |
a917d384 | 284 | } |
ad3376cc PB |
285 | |
286 | /* Partially filled a scsi buffer. Complete immediately. */ | |
287 | esp_dma_done(s); | |
4d611c9a PB |
288 | } |
289 | ||
9c7e23fc | 290 | void esp_command_complete(SCSIRequest *req, uint32_t status, |
01e95455 | 291 | size_t resid) |
2e5d83bb | 292 | { |
e6810db8 | 293 | ESPState *s = req->hba_private; |
2e5d83bb | 294 | |
bf4b9889 | 295 | trace_esp_command_complete(); |
c6df7102 | 296 | if (s->ti_size != 0) { |
bf4b9889 | 297 | trace_esp_command_complete_unexpected(); |
c6df7102 PB |
298 | } |
299 | s->ti_size = 0; | |
300 | s->dma_left = 0; | |
301 | s->async_len = 0; | |
aba1f023 | 302 | if (status) { |
bf4b9889 | 303 | trace_esp_command_complete_fail(); |
c6df7102 | 304 | } |
aba1f023 | 305 | s->status = status; |
c6df7102 PB |
306 | s->rregs[ESP_RSTAT] = STAT_ST; |
307 | esp_dma_done(s); | |
308 | if (s->current_req) { | |
309 | scsi_req_unref(s->current_req); | |
310 | s->current_req = NULL; | |
311 | s->current_dev = NULL; | |
312 | } | |
313 | } | |
314 | ||
9c7e23fc | 315 | void esp_transfer_data(SCSIRequest *req, uint32_t len) |
c6df7102 | 316 | { |
e6810db8 | 317 | ESPState *s = req->hba_private; |
c6df7102 | 318 | |
7f0b6e11 | 319 | assert(!s->do_cmd); |
bf4b9889 | 320 | trace_esp_transfer_data(s->dma_left, s->ti_size); |
aba1f023 | 321 | s->async_len = len; |
c6df7102 PB |
322 | s->async_buf = scsi_req_get_buf(req); |
323 | if (s->dma_left) { | |
324 | esp_do_dma(s); | |
325 | } else if (s->dma_counter != 0 && s->ti_size <= 0) { | |
326 | /* If this was the last part of a DMA transfer then the | |
327 | completion interrupt is deferred to here. */ | |
a917d384 | 328 | esp_dma_done(s); |
4d611c9a | 329 | } |
2e5d83bb PB |
330 | } |
331 | ||
2f275b8f FB |
332 | static void handle_ti(ESPState *s) |
333 | { | |
4d611c9a | 334 | uint32_t dmalen, minlen; |
2f275b8f | 335 | |
7246e160 HP |
336 | if (s->dma && !s->dma_enabled) { |
337 | s->dma_cb = handle_ti; | |
338 | return; | |
339 | } | |
340 | ||
9ea73f8b PB |
341 | dmalen = s->rregs[ESP_TCLO]; |
342 | dmalen |= s->rregs[ESP_TCMID] << 8; | |
343 | dmalen |= s->rregs[ESP_TCHI] << 16; | |
db59203d PB |
344 | if (dmalen==0) { |
345 | dmalen=0x10000; | |
346 | } | |
6787f5fa | 347 | s->dma_counter = dmalen; |
db59203d | 348 | |
9f149aa9 | 349 | if (s->do_cmd) |
926cde5f | 350 | minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ; |
67e999be FB |
351 | else if (s->ti_size < 0) |
352 | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; | |
9f149aa9 PB |
353 | else |
354 | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; | |
bf4b9889 | 355 | trace_esp_handle_ti(minlen); |
4f6200f0 | 356 | if (s->dma) { |
4d611c9a | 357 | s->dma_left = minlen; |
5ad6bb97 | 358 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 359 | esp_do_dma(s); |
7f0b6e11 PB |
360 | } |
361 | if (s->do_cmd) { | |
bf4b9889 | 362 | trace_esp_handle_ti_cmd(s->cmdlen); |
9f149aa9 PB |
363 | s->ti_size = 0; |
364 | s->cmdlen = 0; | |
365 | s->do_cmd = 0; | |
366 | do_cmd(s, s->cmdbuf); | |
9f149aa9 | 367 | } |
2f275b8f FB |
368 | } |
369 | ||
9c7e23fc | 370 | void esp_hard_reset(ESPState *s) |
6f7e9aec | 371 | { |
5aca8c3b BS |
372 | memset(s->rregs, 0, ESP_REGS); |
373 | memset(s->wregs, 0, ESP_REGS); | |
c9cf45c1 | 374 | s->tchi_written = 0; |
4e9aec74 PB |
375 | s->ti_size = 0; |
376 | s->ti_rptr = 0; | |
377 | s->ti_wptr = 0; | |
4e9aec74 | 378 | s->dma = 0; |
9f149aa9 | 379 | s->do_cmd = 0; |
73d74342 | 380 | s->dma_cb = NULL; |
8dea1dd4 BS |
381 | |
382 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
383 | } |
384 | ||
a391fdbc | 385 | static void esp_soft_reset(ESPState *s) |
85948643 | 386 | { |
85948643 | 387 | qemu_irq_lower(s->irq); |
a391fdbc | 388 | esp_hard_reset(s); |
85948643 BS |
389 | } |
390 | ||
a391fdbc | 391 | static void parent_esp_reset(ESPState *s, int irq, int level) |
2d069bab | 392 | { |
85948643 | 393 | if (level) { |
a391fdbc | 394 | esp_soft_reset(s); |
85948643 | 395 | } |
2d069bab BS |
396 | } |
397 | ||
9c7e23fc | 398 | uint64_t esp_reg_read(ESPState *s, uint32_t saddr) |
73d74342 | 399 | { |
a391fdbc | 400 | uint32_t old_val; |
73d74342 | 401 | |
bf4b9889 | 402 | trace_esp_mem_readb(saddr, s->rregs[saddr]); |
6f7e9aec | 403 | switch (saddr) { |
5ad6bb97 | 404 | case ESP_FIFO: |
ff589551 PP |
405 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
406 | /* Data out. */ | |
407 | qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); | |
408 | s->rregs[ESP_FIFO] = 0; | |
ff589551 | 409 | } else if (s->ti_rptr < s->ti_wptr) { |
f930d07e | 410 | s->ti_size--; |
ff589551 | 411 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
f930d07e | 412 | } |
ff589551 | 413 | if (s->ti_rptr == s->ti_wptr) { |
4f6200f0 FB |
414 | s->ti_rptr = 0; |
415 | s->ti_wptr = 0; | |
416 | } | |
f930d07e | 417 | break; |
5ad6bb97 | 418 | case ESP_RINTR: |
2814df28 BS |
419 | /* Clear sequence step, interrupt register and all status bits |
420 | except TC */ | |
421 | old_val = s->rregs[ESP_RINTR]; | |
422 | s->rregs[ESP_RINTR] = 0; | |
423 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
424 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 425 | esp_lower_irq(s); |
2814df28 BS |
426 | |
427 | return old_val; | |
c9cf45c1 HR |
428 | case ESP_TCHI: |
429 | /* Return the unique id if the value has never been written */ | |
430 | if (!s->tchi_written) { | |
431 | return s->chip_id; | |
432 | } | |
6f7e9aec | 433 | default: |
f930d07e | 434 | break; |
6f7e9aec | 435 | } |
2f275b8f | 436 | return s->rregs[saddr]; |
6f7e9aec FB |
437 | } |
438 | ||
9c7e23fc | 439 | void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) |
6f7e9aec | 440 | { |
bf4b9889 | 441 | trace_esp_mem_writeb(saddr, s->wregs[saddr], val); |
6f7e9aec | 442 | switch (saddr) { |
c9cf45c1 HR |
443 | case ESP_TCHI: |
444 | s->tchi_written = true; | |
445 | /* fall through */ | |
5ad6bb97 BS |
446 | case ESP_TCLO: |
447 | case ESP_TCMID: | |
448 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 449 | break; |
5ad6bb97 | 450 | case ESP_FIFO: |
9f149aa9 | 451 | if (s->do_cmd) { |
926cde5f | 452 | if (s->cmdlen < ESP_CMDBUF_SZ) { |
c98c6c10 PP |
453 | s->cmdbuf[s->cmdlen++] = val & 0xff; |
454 | } else { | |
455 | trace_esp_error_fifo_overrun(); | |
456 | } | |
ff589551 | 457 | } else if (s->ti_wptr == TI_BUFSZ - 1) { |
3af4e9aa | 458 | trace_esp_error_fifo_overrun(); |
2e5d83bb PB |
459 | } else { |
460 | s->ti_size++; | |
461 | s->ti_buf[s->ti_wptr++] = val & 0xff; | |
462 | } | |
f930d07e | 463 | break; |
5ad6bb97 | 464 | case ESP_CMD: |
4f6200f0 | 465 | s->rregs[saddr] = val; |
5ad6bb97 | 466 | if (val & CMD_DMA) { |
f930d07e | 467 | s->dma = 1; |
6787f5fa | 468 | /* Reload DMA counter. */ |
5ad6bb97 BS |
469 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
470 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; | |
9ea73f8b | 471 | s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI]; |
f930d07e BS |
472 | } else { |
473 | s->dma = 0; | |
474 | } | |
5ad6bb97 BS |
475 | switch(val & CMD_CMD) { |
476 | case CMD_NOP: | |
bf4b9889 | 477 | trace_esp_mem_writeb_cmd_nop(val); |
f930d07e | 478 | break; |
5ad6bb97 | 479 | case CMD_FLUSH: |
bf4b9889 | 480 | trace_esp_mem_writeb_cmd_flush(val); |
9e61bde5 | 481 | //s->ti_size = 0; |
5ad6bb97 BS |
482 | s->rregs[ESP_RINTR] = INTR_FC; |
483 | s->rregs[ESP_RSEQ] = 0; | |
a214c598 | 484 | s->rregs[ESP_RFLAGS] = 0; |
f930d07e | 485 | break; |
5ad6bb97 | 486 | case CMD_RESET: |
bf4b9889 | 487 | trace_esp_mem_writeb_cmd_reset(val); |
a391fdbc | 488 | esp_soft_reset(s); |
f930d07e | 489 | break; |
5ad6bb97 | 490 | case CMD_BUSRESET: |
bf4b9889 | 491 | trace_esp_mem_writeb_cmd_bus_reset(val); |
5ad6bb97 BS |
492 | s->rregs[ESP_RINTR] = INTR_RST; |
493 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { | |
c73f96fd | 494 | esp_raise_irq(s); |
9e61bde5 | 495 | } |
f930d07e | 496 | break; |
5ad6bb97 | 497 | case CMD_TI: |
f930d07e BS |
498 | handle_ti(s); |
499 | break; | |
5ad6bb97 | 500 | case CMD_ICCS: |
bf4b9889 | 501 | trace_esp_mem_writeb_cmd_iccs(val); |
f930d07e | 502 | write_response(s); |
4bf5801d BS |
503 | s->rregs[ESP_RINTR] = INTR_FC; |
504 | s->rregs[ESP_RSTAT] |= STAT_MI; | |
f930d07e | 505 | break; |
5ad6bb97 | 506 | case CMD_MSGACC: |
bf4b9889 | 507 | trace_esp_mem_writeb_cmd_msgacc(val); |
5ad6bb97 BS |
508 | s->rregs[ESP_RINTR] = INTR_DC; |
509 | s->rregs[ESP_RSEQ] = 0; | |
4e2a68c1 AT |
510 | s->rregs[ESP_RFLAGS] = 0; |
511 | esp_raise_irq(s); | |
f930d07e | 512 | break; |
0fd0eb21 | 513 | case CMD_PAD: |
bf4b9889 | 514 | trace_esp_mem_writeb_cmd_pad(val); |
0fd0eb21 BS |
515 | s->rregs[ESP_RSTAT] = STAT_TC; |
516 | s->rregs[ESP_RINTR] = INTR_FC; | |
517 | s->rregs[ESP_RSEQ] = 0; | |
518 | break; | |
5ad6bb97 | 519 | case CMD_SATN: |
bf4b9889 | 520 | trace_esp_mem_writeb_cmd_satn(val); |
f930d07e | 521 | break; |
6915bff1 HP |
522 | case CMD_RSTATN: |
523 | trace_esp_mem_writeb_cmd_rstatn(val); | |
524 | break; | |
5e1e0a3b | 525 | case CMD_SEL: |
bf4b9889 | 526 | trace_esp_mem_writeb_cmd_sel(val); |
f2818f22 | 527 | handle_s_without_atn(s); |
5e1e0a3b | 528 | break; |
5ad6bb97 | 529 | case CMD_SELATN: |
bf4b9889 | 530 | trace_esp_mem_writeb_cmd_selatn(val); |
f930d07e BS |
531 | handle_satn(s); |
532 | break; | |
5ad6bb97 | 533 | case CMD_SELATNS: |
bf4b9889 | 534 | trace_esp_mem_writeb_cmd_selatns(val); |
f930d07e BS |
535 | handle_satn_stop(s); |
536 | break; | |
5ad6bb97 | 537 | case CMD_ENSEL: |
bf4b9889 | 538 | trace_esp_mem_writeb_cmd_ensel(val); |
e3926838 | 539 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 540 | break; |
6fe84c18 HP |
541 | case CMD_DISSEL: |
542 | trace_esp_mem_writeb_cmd_dissel(val); | |
543 | s->rregs[ESP_RINTR] = 0; | |
544 | esp_raise_irq(s); | |
545 | break; | |
f930d07e | 546 | default: |
3af4e9aa | 547 | trace_esp_error_unhandled_command(val); |
f930d07e BS |
548 | break; |
549 | } | |
550 | break; | |
5ad6bb97 | 551 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 552 | break; |
5ad6bb97 | 553 | case ESP_CFG1: |
9ea73f8b PB |
554 | case ESP_CFG2: case ESP_CFG3: |
555 | case ESP_RES3: case ESP_RES4: | |
4f6200f0 FB |
556 | s->rregs[saddr] = val; |
557 | break; | |
5ad6bb97 | 558 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 559 | break; |
6f7e9aec | 560 | default: |
3af4e9aa | 561 | trace_esp_error_invalid_write(val, saddr); |
8dea1dd4 | 562 | return; |
6f7e9aec | 563 | } |
2f275b8f | 564 | s->wregs[saddr] = val; |
6f7e9aec FB |
565 | } |
566 | ||
a8170e5e | 567 | static bool esp_mem_accepts(void *opaque, hwaddr addr, |
67bb5314 AK |
568 | unsigned size, bool is_write) |
569 | { | |
570 | return (size == 1) || (is_write && size == 4); | |
571 | } | |
6f7e9aec | 572 | |
9c7e23fc | 573 | const VMStateDescription vmstate_esp = { |
cc9952f3 | 574 | .name ="esp", |
cc966774 | 575 | .version_id = 4, |
cc9952f3 | 576 | .minimum_version_id = 3, |
35d08458 | 577 | .fields = (VMStateField[]) { |
cc9952f3 BS |
578 | VMSTATE_BUFFER(rregs, ESPState), |
579 | VMSTATE_BUFFER(wregs, ESPState), | |
580 | VMSTATE_INT32(ti_size, ESPState), | |
581 | VMSTATE_UINT32(ti_rptr, ESPState), | |
582 | VMSTATE_UINT32(ti_wptr, ESPState), | |
583 | VMSTATE_BUFFER(ti_buf, ESPState), | |
3944966d | 584 | VMSTATE_UINT32(status, ESPState), |
cc9952f3 | 585 | VMSTATE_UINT32(dma, ESPState), |
cc966774 PB |
586 | VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16), |
587 | VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4), | |
cc9952f3 BS |
588 | VMSTATE_UINT32(cmdlen, ESPState), |
589 | VMSTATE_UINT32(do_cmd, ESPState), | |
590 | VMSTATE_UINT32(dma_left, ESPState), | |
591 | VMSTATE_END_OF_LIST() | |
592 | } | |
593 | }; | |
6f7e9aec | 594 | |
a71c7ec5 | 595 | #define TYPE_ESP "esp" |
80cac47e | 596 | #define ESP_STATE(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP) |
a71c7ec5 | 597 | |
a391fdbc | 598 | typedef struct { |
a71c7ec5 HT |
599 | /*< private >*/ |
600 | SysBusDevice parent_obj; | |
601 | /*< public >*/ | |
602 | ||
a391fdbc HP |
603 | MemoryRegion iomem; |
604 | uint32_t it_shift; | |
605 | ESPState esp; | |
606 | } SysBusESPState; | |
607 | ||
a8170e5e | 608 | static void sysbus_esp_mem_write(void *opaque, hwaddr addr, |
a391fdbc HP |
609 | uint64_t val, unsigned int size) |
610 | { | |
611 | SysBusESPState *sysbus = opaque; | |
612 | uint32_t saddr; | |
613 | ||
614 | saddr = addr >> sysbus->it_shift; | |
615 | esp_reg_write(&sysbus->esp, saddr, val); | |
616 | } | |
617 | ||
a8170e5e | 618 | static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, |
a391fdbc HP |
619 | unsigned int size) |
620 | { | |
621 | SysBusESPState *sysbus = opaque; | |
622 | uint32_t saddr; | |
623 | ||
624 | saddr = addr >> sysbus->it_shift; | |
625 | return esp_reg_read(&sysbus->esp, saddr); | |
626 | } | |
627 | ||
628 | static const MemoryRegionOps sysbus_esp_mem_ops = { | |
629 | .read = sysbus_esp_mem_read, | |
630 | .write = sysbus_esp_mem_write, | |
631 | .endianness = DEVICE_NATIVE_ENDIAN, | |
632 | .valid.accepts = esp_mem_accepts, | |
633 | }; | |
634 | ||
a8170e5e | 635 | void esp_init(hwaddr espaddr, int it_shift, |
ff9868ec BS |
636 | ESPDMAMemoryReadWriteFunc dma_memory_read, |
637 | ESPDMAMemoryReadWriteFunc dma_memory_write, | |
73d74342 BS |
638 | void *dma_opaque, qemu_irq irq, qemu_irq *reset, |
639 | qemu_irq *dma_enable) | |
6f7e9aec | 640 | { |
cfb9de9c PB |
641 | DeviceState *dev; |
642 | SysBusDevice *s; | |
a391fdbc | 643 | SysBusESPState *sysbus; |
ee6847d1 | 644 | ESPState *esp; |
cfb9de9c | 645 | |
a71c7ec5 | 646 | dev = qdev_create(NULL, TYPE_ESP); |
80cac47e | 647 | sysbus = ESP_STATE(dev); |
a391fdbc | 648 | esp = &sysbus->esp; |
ee6847d1 GH |
649 | esp->dma_memory_read = dma_memory_read; |
650 | esp->dma_memory_write = dma_memory_write; | |
651 | esp->dma_opaque = dma_opaque; | |
a391fdbc | 652 | sysbus->it_shift = it_shift; |
73d74342 BS |
653 | /* XXX for now until rc4030 has been changed to use DMA enable signal */ |
654 | esp->dma_enabled = 1; | |
e23a1b33 | 655 | qdev_init_nofail(dev); |
1356b98d | 656 | s = SYS_BUS_DEVICE(dev); |
cfb9de9c PB |
657 | sysbus_connect_irq(s, 0, irq); |
658 | sysbus_mmio_map(s, 0, espaddr); | |
74ff8d90 | 659 | *reset = qdev_get_gpio_in(dev, 0); |
73d74342 | 660 | *dma_enable = qdev_get_gpio_in(dev, 1); |
cfb9de9c | 661 | } |
6f7e9aec | 662 | |
afd4030c PB |
663 | static const struct SCSIBusInfo esp_scsi_info = { |
664 | .tcq = false, | |
7e0380b9 PB |
665 | .max_target = ESP_MAX_DEVS, |
666 | .max_lun = 7, | |
afd4030c | 667 | |
c6df7102 | 668 | .transfer_data = esp_transfer_data, |
94d3f98a PB |
669 | .complete = esp_command_complete, |
670 | .cancel = esp_request_cancelled | |
cfdc1bb0 PB |
671 | }; |
672 | ||
a391fdbc | 673 | static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) |
cfb9de9c | 674 | { |
80cac47e | 675 | SysBusESPState *sysbus = ESP_STATE(opaque); |
a391fdbc HP |
676 | ESPState *s = &sysbus->esp; |
677 | ||
678 | switch (irq) { | |
679 | case 0: | |
680 | parent_esp_reset(s, irq, level); | |
681 | break; | |
682 | case 1: | |
683 | esp_dma_enable(opaque, irq, level); | |
684 | break; | |
685 | } | |
686 | } | |
687 | ||
b09318ca | 688 | static void sysbus_esp_realize(DeviceState *dev, Error **errp) |
a391fdbc | 689 | { |
b09318ca | 690 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
80cac47e | 691 | SysBusESPState *sysbus = ESP_STATE(dev); |
a391fdbc | 692 | ESPState *s = &sysbus->esp; |
6f7e9aec | 693 | |
b09318ca | 694 | sysbus_init_irq(sbd, &s->irq); |
a391fdbc | 695 | assert(sysbus->it_shift != -1); |
6f7e9aec | 696 | |
d32e4b3d | 697 | s->chip_id = TCHI_FAS100A; |
29776739 PB |
698 | memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, |
699 | sysbus, "esp", ESP_REGS << sysbus->it_shift); | |
b09318ca | 700 | sysbus_init_mmio(sbd, &sysbus->iomem); |
6f7e9aec | 701 | |
b09318ca | 702 | qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); |
2d069bab | 703 | |
b1187b51 | 704 | scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); |
67e999be | 705 | } |
cfb9de9c | 706 | |
a391fdbc HP |
707 | static void sysbus_esp_hard_reset(DeviceState *dev) |
708 | { | |
80cac47e | 709 | SysBusESPState *sysbus = ESP_STATE(dev); |
a391fdbc HP |
710 | esp_hard_reset(&sysbus->esp); |
711 | } | |
712 | ||
713 | static const VMStateDescription vmstate_sysbus_esp_scsi = { | |
714 | .name = "sysbusespscsi", | |
715 | .version_id = 0, | |
716 | .minimum_version_id = 0, | |
a391fdbc HP |
717 | .fields = (VMStateField[]) { |
718 | VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), | |
719 | VMSTATE_END_OF_LIST() | |
720 | } | |
999e12bb AL |
721 | }; |
722 | ||
a391fdbc | 723 | static void sysbus_esp_class_init(ObjectClass *klass, void *data) |
999e12bb | 724 | { |
39bffca2 | 725 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 726 | |
b09318ca | 727 | dc->realize = sysbus_esp_realize; |
a391fdbc HP |
728 | dc->reset = sysbus_esp_hard_reset; |
729 | dc->vmsd = &vmstate_sysbus_esp_scsi; | |
125ee0ed | 730 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
999e12bb AL |
731 | } |
732 | ||
1f077308 | 733 | static const TypeInfo sysbus_esp_info = { |
a71c7ec5 | 734 | .name = TYPE_ESP, |
39bffca2 | 735 | .parent = TYPE_SYS_BUS_DEVICE, |
a391fdbc HP |
736 | .instance_size = sizeof(SysBusESPState), |
737 | .class_init = sysbus_esp_class_init, | |
63235df8 BS |
738 | }; |
739 | ||
83f7d43a | 740 | static void esp_register_types(void) |
cfb9de9c | 741 | { |
a391fdbc | 742 | type_register_static(&sysbus_esp_info); |
cfb9de9c PB |
743 | } |
744 | ||
83f7d43a | 745 | type_init(esp_register_types) |