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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
fabaaf1d | 5 | * Copyright (c) 2012 Herve Poussineau |
5fafdf24 | 6 | * |
6f7e9aec FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
5d20fa6b | 25 | |
a4ab4792 | 26 | #include "qemu/osdep.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
64552b6b | 29 | #include "hw/irq.h" |
0d09e41a | 30 | #include "hw/scsi/esp.h" |
bf4b9889 | 31 | #include "trace.h" |
1de7afc9 | 32 | #include "qemu/log.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
6f7e9aec | 34 | |
67e999be | 35 | /* |
5ad6bb97 BS |
36 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
37 | * also produced as NCR89C100. See | |
67e999be FB |
38 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
39 | * and | |
40 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
74d71ea1 LV |
41 | * |
42 | * On Macintosh Quadra it is a NCR53C96. | |
67e999be FB |
43 | */ |
44 | ||
c73f96fd BS |
45 | static void esp_raise_irq(ESPState *s) |
46 | { | |
47 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
48 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
49 | qemu_irq_raise(s->irq); | |
bf4b9889 | 50 | trace_esp_raise_irq(); |
c73f96fd BS |
51 | } |
52 | } | |
53 | ||
54 | static void esp_lower_irq(ESPState *s) | |
55 | { | |
56 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
57 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
58 | qemu_irq_lower(s->irq); | |
bf4b9889 | 59 | trace_esp_lower_irq(); |
c73f96fd BS |
60 | } |
61 | } | |
62 | ||
74d71ea1 LV |
63 | static void esp_raise_drq(ESPState *s) |
64 | { | |
65 | qemu_irq_raise(s->irq_data); | |
960ebfd9 | 66 | trace_esp_raise_drq(); |
74d71ea1 LV |
67 | } |
68 | ||
69 | static void esp_lower_drq(ESPState *s) | |
70 | { | |
71 | qemu_irq_lower(s->irq_data); | |
960ebfd9 | 72 | trace_esp_lower_drq(); |
74d71ea1 LV |
73 | } |
74 | ||
9c7e23fc | 75 | void esp_dma_enable(ESPState *s, int irq, int level) |
73d74342 | 76 | { |
73d74342 BS |
77 | if (level) { |
78 | s->dma_enabled = 1; | |
bf4b9889 | 79 | trace_esp_dma_enable(); |
73d74342 BS |
80 | if (s->dma_cb) { |
81 | s->dma_cb(s); | |
82 | s->dma_cb = NULL; | |
83 | } | |
84 | } else { | |
bf4b9889 | 85 | trace_esp_dma_disable(); |
73d74342 BS |
86 | s->dma_enabled = 0; |
87 | } | |
88 | } | |
89 | ||
9c7e23fc | 90 | void esp_request_cancelled(SCSIRequest *req) |
94d3f98a | 91 | { |
e6810db8 | 92 | ESPState *s = req->hba_private; |
94d3f98a PB |
93 | |
94 | if (req == s->current_req) { | |
95 | scsi_req_unref(s->current_req); | |
96 | s->current_req = NULL; | |
97 | s->current_dev = NULL; | |
324c8809 | 98 | s->async_len = 0; |
94d3f98a PB |
99 | } |
100 | } | |
101 | ||
e5455b8c | 102 | static void esp_fifo_push(Fifo8 *fifo, uint8_t val) |
042879fc | 103 | { |
e5455b8c | 104 | if (fifo8_num_used(fifo) == fifo->capacity) { |
042879fc MCA |
105 | trace_esp_error_fifo_overrun(); |
106 | return; | |
107 | } | |
108 | ||
e5455b8c | 109 | fifo8_push(fifo, val); |
042879fc | 110 | } |
042879fc | 111 | |
c5fef911 | 112 | static uint8_t esp_fifo_pop(Fifo8 *fifo) |
023666da | 113 | { |
c5fef911 | 114 | if (fifo8_is_empty(fifo)) { |
023666da MCA |
115 | return 0; |
116 | } | |
117 | ||
c5fef911 | 118 | return fifo8_pop(fifo); |
023666da MCA |
119 | } |
120 | ||
7b320a8e MCA |
121 | static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) |
122 | { | |
123 | const uint8_t *buf; | |
124 | uint32_t n; | |
125 | ||
126 | if (maxlen == 0) { | |
127 | return 0; | |
128 | } | |
129 | ||
130 | buf = fifo8_pop_buf(fifo, maxlen, &n); | |
131 | if (dest) { | |
132 | memcpy(dest, buf, n); | |
133 | } | |
134 | ||
135 | return n; | |
136 | } | |
137 | ||
c47b5835 MCA |
138 | static uint32_t esp_get_tc(ESPState *s) |
139 | { | |
140 | uint32_t dmalen; | |
141 | ||
142 | dmalen = s->rregs[ESP_TCLO]; | |
143 | dmalen |= s->rregs[ESP_TCMID] << 8; | |
144 | dmalen |= s->rregs[ESP_TCHI] << 16; | |
145 | ||
146 | return dmalen; | |
147 | } | |
148 | ||
149 | static void esp_set_tc(ESPState *s, uint32_t dmalen) | |
150 | { | |
151 | s->rregs[ESP_TCLO] = dmalen; | |
152 | s->rregs[ESP_TCMID] = dmalen >> 8; | |
153 | s->rregs[ESP_TCHI] = dmalen >> 16; | |
154 | } | |
155 | ||
c04ed569 MCA |
156 | static uint32_t esp_get_stc(ESPState *s) |
157 | { | |
158 | uint32_t dmalen; | |
159 | ||
160 | dmalen = s->wregs[ESP_TCLO]; | |
161 | dmalen |= s->wregs[ESP_TCMID] << 8; | |
162 | dmalen |= s->wregs[ESP_TCHI] << 16; | |
163 | ||
164 | return dmalen; | |
165 | } | |
166 | ||
761bef75 MCA |
167 | static uint8_t esp_pdma_read(ESPState *s) |
168 | { | |
8da90e81 MCA |
169 | uint8_t val; |
170 | ||
43d02df3 | 171 | if (s->do_cmd) { |
c5fef911 | 172 | val = esp_fifo_pop(&s->cmdfifo); |
43d02df3 | 173 | } else { |
c5fef911 | 174 | val = esp_fifo_pop(&s->fifo); |
6e3fafa8 | 175 | } |
8da90e81 | 176 | |
8da90e81 | 177 | return val; |
761bef75 MCA |
178 | } |
179 | ||
180 | static void esp_pdma_write(ESPState *s, uint8_t val) | |
181 | { | |
8da90e81 MCA |
182 | uint32_t dmalen = esp_get_tc(s); |
183 | ||
3c421400 | 184 | if (dmalen == 0) { |
8da90e81 MCA |
185 | return; |
186 | } | |
187 | ||
43d02df3 | 188 | if (s->do_cmd) { |
e5455b8c | 189 | esp_fifo_push(&s->cmdfifo, val); |
43d02df3 | 190 | } else { |
e5455b8c | 191 | esp_fifo_push(&s->fifo, val); |
6e3fafa8 | 192 | } |
8da90e81 | 193 | |
8da90e81 MCA |
194 | dmalen--; |
195 | esp_set_tc(s, dmalen); | |
761bef75 MCA |
196 | } |
197 | ||
1e794c51 MCA |
198 | static void esp_set_pdma_cb(ESPState *s, void (*cb)(ESPState *)) |
199 | { | |
200 | s->pdma_cb = cb; | |
201 | } | |
202 | ||
d0243b09 MCA |
203 | static void esp_pdma_cb(ESPState *s) |
204 | { | |
205 | s->pdma_cb(s); | |
206 | } | |
207 | ||
c7bce09c | 208 | static int esp_select(ESPState *s) |
6130b188 LV |
209 | { |
210 | int target; | |
211 | ||
212 | target = s->wregs[ESP_WBUSID] & BUSID_DID; | |
213 | ||
214 | s->ti_size = 0; | |
042879fc | 215 | fifo8_reset(&s->fifo); |
6130b188 | 216 | |
6130b188 LV |
217 | s->current_dev = scsi_device_find(&s->bus, 0, target, 0); |
218 | if (!s->current_dev) { | |
219 | /* No such drive */ | |
220 | s->rregs[ESP_RSTAT] = 0; | |
cf1a7a9b | 221 | s->rregs[ESP_RINTR] = INTR_DC; |
6130b188 LV |
222 | s->rregs[ESP_RSEQ] = SEQ_0; |
223 | esp_raise_irq(s); | |
224 | return -1; | |
225 | } | |
4e78f3bf MCA |
226 | |
227 | /* | |
228 | * Note that we deliberately don't raise the IRQ here: this will be done | |
4eb86065 | 229 | * either in do_command_phase() for DATA OUT transfers or by the deferred |
4e78f3bf MCA |
230 | * IRQ mechanism in esp_transfer_data() for DATA IN transfers |
231 | */ | |
232 | s->rregs[ESP_RINTR] |= INTR_FC; | |
233 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
6130b188 LV |
234 | return 0; |
235 | } | |
236 | ||
20c8d2ed | 237 | static uint32_t get_cmd(ESPState *s, uint32_t maxlen) |
2f275b8f | 238 | { |
023666da | 239 | uint8_t buf[ESP_CMDFIFO_SZ]; |
042879fc | 240 | uint32_t dmalen, n; |
2f275b8f FB |
241 | int target; |
242 | ||
de7e2cb1 MCA |
243 | if (s->current_req) { |
244 | /* Started a new command before the old one finished. Cancel it. */ | |
245 | scsi_req_cancel(s->current_req); | |
246 | } | |
247 | ||
8dea1dd4 | 248 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 249 | if (s->dma) { |
20c8d2ed MCA |
250 | dmalen = MIN(esp_get_tc(s), maxlen); |
251 | if (dmalen == 0) { | |
6c1fef6b PP |
252 | return 0; |
253 | } | |
74d71ea1 LV |
254 | if (s->dma_memory_read) { |
255 | s->dma_memory_read(s->dma_opaque, buf, dmalen); | |
fbc6510e | 256 | dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); |
023666da | 257 | fifo8_push_all(&s->cmdfifo, buf, dmalen); |
74d71ea1 | 258 | } else { |
49691315 | 259 | if (esp_select(s) < 0) { |
023666da | 260 | fifo8_reset(&s->cmdfifo); |
49691315 MCA |
261 | return -1; |
262 | } | |
74d71ea1 | 263 | esp_raise_drq(s); |
023666da | 264 | fifo8_reset(&s->cmdfifo); |
74d71ea1 LV |
265 | return 0; |
266 | } | |
4f6200f0 | 267 | } else { |
023666da | 268 | dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); |
20c8d2ed | 269 | if (dmalen == 0) { |
d3cdc491 PP |
270 | return 0; |
271 | } | |
7b320a8e | 272 | n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); |
fbc6510e | 273 | n = MIN(fifo8_num_free(&s->cmdfifo), n); |
7b320a8e | 274 | fifo8_push_all(&s->cmdfifo, buf, n); |
4f6200f0 | 275 | } |
bf4b9889 | 276 | trace_esp_get_cmd(dmalen, target); |
2e5d83bb | 277 | |
c7bce09c | 278 | if (esp_select(s) < 0) { |
023666da | 279 | fifo8_reset(&s->cmdfifo); |
49691315 | 280 | return -1; |
2f275b8f | 281 | } |
9f149aa9 PB |
282 | return dmalen; |
283 | } | |
284 | ||
4eb86065 | 285 | static void do_command_phase(ESPState *s) |
9f149aa9 | 286 | { |
7b320a8e | 287 | uint32_t cmdlen; |
9f149aa9 | 288 | int32_t datalen; |
f48a7a6e | 289 | SCSIDevice *current_lun; |
7b320a8e | 290 | uint8_t buf[ESP_CMDFIFO_SZ]; |
9f149aa9 | 291 | |
4eb86065 | 292 | trace_esp_do_command_phase(s->lun); |
023666da | 293 | cmdlen = fifo8_num_used(&s->cmdfifo); |
99545751 MCA |
294 | if (!cmdlen || !s->current_dev) { |
295 | return; | |
296 | } | |
7b320a8e | 297 | esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); |
023666da | 298 | |
4eb86065 PB |
299 | current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); |
300 | s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, s); | |
c39ce112 | 301 | datalen = scsi_req_enqueue(s->current_req); |
67e999be | 302 | s->ti_size = datalen; |
023666da | 303 | fifo8_reset(&s->cmdfifo); |
67e999be | 304 | if (datalen != 0) { |
c73f96fd | 305 | s->rregs[ESP_RSTAT] = STAT_TC; |
4e78f3bf | 306 | s->rregs[ESP_RSEQ] = SEQ_CD; |
1b9e48a5 | 307 | s->ti_cmd = 0; |
6cc88d6b | 308 | esp_set_tc(s, 0); |
2e5d83bb | 309 | if (datalen > 0) { |
4e78f3bf MCA |
310 | /* |
311 | * Switch to DATA IN phase but wait until initial data xfer is | |
312 | * complete before raising the command completion interrupt | |
313 | */ | |
314 | s->data_in_ready = false; | |
5ad6bb97 | 315 | s->rregs[ESP_RSTAT] |= STAT_DI; |
2e5d83bb | 316 | } else { |
5ad6bb97 | 317 | s->rregs[ESP_RSTAT] |= STAT_DO; |
4e78f3bf MCA |
318 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
319 | esp_raise_irq(s); | |
320 | esp_lower_drq(s); | |
b9788fc4 | 321 | } |
ad3376cc | 322 | scsi_req_continue(s->current_req); |
4e78f3bf | 323 | return; |
2f275b8f | 324 | } |
2f275b8f FB |
325 | } |
326 | ||
4eb86065 | 327 | static void do_message_phase(ESPState *s) |
f2818f22 | 328 | { |
4eb86065 PB |
329 | if (s->cmdfifo_cdb_offset) { |
330 | uint8_t message = esp_fifo_pop(&s->cmdfifo); | |
023666da | 331 | |
4eb86065 PB |
332 | trace_esp_do_identify(message); |
333 | s->lun = message & 7; | |
334 | s->cmdfifo_cdb_offset--; | |
335 | } | |
f2818f22 | 336 | |
799d90d8 | 337 | /* Ignore extended messages for now */ |
023666da | 338 | if (s->cmdfifo_cdb_offset) { |
4eb86065 | 339 | int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); |
fa7505c1 | 340 | esp_fifo_pop_buf(&s->cmdfifo, NULL, len); |
023666da MCA |
341 | s->cmdfifo_cdb_offset = 0; |
342 | } | |
4eb86065 | 343 | } |
023666da | 344 | |
4eb86065 PB |
345 | static void do_cmd(ESPState *s) |
346 | { | |
347 | do_message_phase(s); | |
348 | assert(s->cmdfifo_cdb_offset == 0); | |
349 | do_command_phase(s); | |
f2818f22 AT |
350 | } |
351 | ||
74d71ea1 LV |
352 | static void satn_pdma_cb(ESPState *s) |
353 | { | |
e62a959a | 354 | if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { |
023666da | 355 | s->cmdfifo_cdb_offset = 1; |
e62a959a | 356 | s->do_cmd = 0; |
c959f218 | 357 | do_cmd(s); |
74d71ea1 LV |
358 | } |
359 | } | |
360 | ||
9f149aa9 PB |
361 | static void handle_satn(ESPState *s) |
362 | { | |
49691315 MCA |
363 | int32_t cmdlen; |
364 | ||
1b26eaa1 | 365 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
366 | s->dma_cb = handle_satn; |
367 | return; | |
368 | } | |
1e794c51 | 369 | esp_set_pdma_cb(s, satn_pdma_cb); |
023666da | 370 | cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); |
49691315 | 371 | if (cmdlen > 0) { |
023666da | 372 | s->cmdfifo_cdb_offset = 1; |
60720694 | 373 | s->do_cmd = 0; |
c959f218 | 374 | do_cmd(s); |
49691315 | 375 | } else if (cmdlen == 0) { |
bb0bc7bb | 376 | s->do_cmd = 1; |
49691315 MCA |
377 | /* Target present, but no cmd yet - switch to command phase */ |
378 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
379 | s->rregs[ESP_RSTAT] = STAT_CD; | |
94d5c79d | 380 | } |
9f149aa9 PB |
381 | } |
382 | ||
74d71ea1 LV |
383 | static void s_without_satn_pdma_cb(ESPState *s) |
384 | { | |
e62a959a | 385 | if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { |
023666da | 386 | s->cmdfifo_cdb_offset = 0; |
e62a959a | 387 | s->do_cmd = 0; |
4eb86065 | 388 | do_cmd(s); |
74d71ea1 LV |
389 | } |
390 | } | |
391 | ||
f2818f22 AT |
392 | static void handle_s_without_atn(ESPState *s) |
393 | { | |
49691315 MCA |
394 | int32_t cmdlen; |
395 | ||
1b26eaa1 | 396 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
397 | s->dma_cb = handle_s_without_atn; |
398 | return; | |
399 | } | |
1e794c51 | 400 | esp_set_pdma_cb(s, s_without_satn_pdma_cb); |
023666da | 401 | cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); |
49691315 | 402 | if (cmdlen > 0) { |
023666da | 403 | s->cmdfifo_cdb_offset = 0; |
60720694 | 404 | s->do_cmd = 0; |
4eb86065 | 405 | do_cmd(s); |
49691315 | 406 | } else if (cmdlen == 0) { |
bb0bc7bb | 407 | s->do_cmd = 1; |
49691315 MCA |
408 | /* Target present, but no cmd yet - switch to command phase */ |
409 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
410 | s->rregs[ESP_RSTAT] = STAT_CD; | |
f2818f22 AT |
411 | } |
412 | } | |
413 | ||
74d71ea1 LV |
414 | static void satn_stop_pdma_cb(ESPState *s) |
415 | { | |
e62a959a | 416 | if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { |
023666da | 417 | trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); |
74d71ea1 | 418 | s->do_cmd = 1; |
023666da | 419 | s->cmdfifo_cdb_offset = 1; |
74d71ea1 | 420 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
cf47a41e | 421 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
422 | s->rregs[ESP_RSEQ] = SEQ_CD; |
423 | esp_raise_irq(s); | |
424 | } | |
425 | } | |
426 | ||
9f149aa9 PB |
427 | static void handle_satn_stop(ESPState *s) |
428 | { | |
49691315 MCA |
429 | int32_t cmdlen; |
430 | ||
1b26eaa1 | 431 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
432 | s->dma_cb = handle_satn_stop; |
433 | return; | |
434 | } | |
1e794c51 | 435 | esp_set_pdma_cb(s, satn_stop_pdma_cb); |
799d90d8 | 436 | cmdlen = get_cmd(s, 1); |
49691315 | 437 | if (cmdlen > 0) { |
023666da | 438 | trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); |
9f149aa9 | 439 | s->do_cmd = 1; |
023666da | 440 | s->cmdfifo_cdb_offset = 1; |
799d90d8 | 441 | s->rregs[ESP_RSTAT] = STAT_MO; |
cf47a41e | 442 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
799d90d8 | 443 | s->rregs[ESP_RSEQ] = SEQ_MO; |
c73f96fd | 444 | esp_raise_irq(s); |
49691315 | 445 | } else if (cmdlen == 0) { |
bb0bc7bb | 446 | s->do_cmd = 1; |
799d90d8 MCA |
447 | /* Target present, switch to message out phase */ |
448 | s->rregs[ESP_RSEQ] = SEQ_MO; | |
449 | s->rregs[ESP_RSTAT] = STAT_MO; | |
9f149aa9 PB |
450 | } |
451 | } | |
452 | ||
74d71ea1 LV |
453 | static void write_response_pdma_cb(ESPState *s) |
454 | { | |
455 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
cf47a41e | 456 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
457 | s->rregs[ESP_RSEQ] = SEQ_CD; |
458 | esp_raise_irq(s); | |
459 | } | |
460 | ||
0fc5c15a | 461 | static void write_response(ESPState *s) |
2f275b8f | 462 | { |
e3922557 | 463 | uint8_t buf[2]; |
042879fc | 464 | |
bf4b9889 | 465 | trace_esp_write_response(s->status); |
042879fc | 466 | |
e3922557 MCA |
467 | buf[0] = s->status; |
468 | buf[1] = 0; | |
042879fc | 469 | |
4f6200f0 | 470 | if (s->dma) { |
74d71ea1 | 471 | if (s->dma_memory_write) { |
e3922557 | 472 | s->dma_memory_write(s->dma_opaque, buf, 2); |
74d71ea1 | 473 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
cf47a41e | 474 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
475 | s->rregs[ESP_RSEQ] = SEQ_CD; |
476 | } else { | |
1e794c51 | 477 | esp_set_pdma_cb(s, write_response_pdma_cb); |
74d71ea1 LV |
478 | esp_raise_drq(s); |
479 | return; | |
480 | } | |
4f6200f0 | 481 | } else { |
e3922557 MCA |
482 | fifo8_reset(&s->fifo); |
483 | fifo8_push_all(&s->fifo, buf, 2); | |
5ad6bb97 | 484 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 485 | } |
c73f96fd | 486 | esp_raise_irq(s); |
2f275b8f | 487 | } |
4f6200f0 | 488 | |
a917d384 PB |
489 | static void esp_dma_done(ESPState *s) |
490 | { | |
c73f96fd | 491 | s->rregs[ESP_RSTAT] |= STAT_TC; |
cf47a41e | 492 | s->rregs[ESP_RINTR] |= INTR_BS; |
5ad6bb97 | 493 | s->rregs[ESP_RFLAGS] = 0; |
c47b5835 | 494 | esp_set_tc(s, 0); |
c73f96fd | 495 | esp_raise_irq(s); |
a917d384 PB |
496 | } |
497 | ||
74d71ea1 LV |
498 | static void do_dma_pdma_cb(ESPState *s) |
499 | { | |
4ca2ba6f | 500 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
82141c8b | 501 | int len; |
042879fc | 502 | uint32_t n; |
6cc88d6b | 503 | |
74d71ea1 | 504 | if (s->do_cmd) { |
e62a959a MCA |
505 | /* Ensure we have received complete command after SATN and stop */ |
506 | if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { | |
507 | return; | |
508 | } | |
509 | ||
74d71ea1 | 510 | s->ti_size = 0; |
c348458f MCA |
511 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { |
512 | /* No command received */ | |
513 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { | |
514 | return; | |
515 | } | |
516 | ||
517 | /* Command has been received */ | |
518 | s->do_cmd = 0; | |
519 | do_cmd(s); | |
520 | } else { | |
521 | /* | |
522 | * Extra message out bytes received: update cmdfifo_cdb_offset | |
523 | * and then switch to commmand phase | |
524 | */ | |
525 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); | |
526 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; | |
527 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
528 | s->rregs[ESP_RINTR] |= INTR_BS; | |
529 | esp_raise_irq(s); | |
530 | } | |
74d71ea1 LV |
531 | return; |
532 | } | |
82141c8b | 533 | |
0db89536 MCA |
534 | if (!s->current_req) { |
535 | return; | |
536 | } | |
537 | ||
82141c8b MCA |
538 | if (to_device) { |
539 | /* Copy FIFO data to device */ | |
7aa6baee MCA |
540 | len = MIN(s->async_len, ESP_FIFO_SZ); |
541 | len = MIN(len, fifo8_num_used(&s->fifo)); | |
7b320a8e | 542 | n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
7aa6baee MCA |
543 | s->async_buf += n; |
544 | s->async_len -= n; | |
545 | s->ti_size += n; | |
546 | ||
547 | if (n < len) { | |
548 | /* Unaligned accesses can cause FIFO wraparound */ | |
549 | len = len - n; | |
7b320a8e | 550 | n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
7aa6baee MCA |
551 | s->async_buf += n; |
552 | s->async_len -= n; | |
553 | s->ti_size += n; | |
554 | } | |
555 | ||
82141c8b MCA |
556 | if (s->async_len == 0) { |
557 | scsi_req_continue(s->current_req); | |
74d71ea1 LV |
558 | return; |
559 | } | |
74d71ea1 | 560 | |
82141c8b MCA |
561 | if (esp_get_tc(s) == 0) { |
562 | esp_lower_drq(s); | |
563 | esp_dma_done(s); | |
564 | } | |
565 | ||
566 | return; | |
567 | } else { | |
568 | if (s->async_len == 0) { | |
0db89536 MCA |
569 | /* Defer until the scsi layer has completed */ |
570 | scsi_req_continue(s->current_req); | |
571 | s->data_in_ready = false; | |
4e78f3bf | 572 | return; |
82141c8b MCA |
573 | } |
574 | ||
575 | if (esp_get_tc(s) != 0) { | |
576 | /* Copy device data to FIFO */ | |
7aa6baee MCA |
577 | len = MIN(s->async_len, esp_get_tc(s)); |
578 | len = MIN(len, fifo8_num_free(&s->fifo)); | |
042879fc | 579 | fifo8_push_all(&s->fifo, s->async_buf, len); |
82141c8b MCA |
580 | s->async_buf += len; |
581 | s->async_len -= len; | |
582 | s->ti_size -= len; | |
583 | esp_set_tc(s, esp_get_tc(s) - len); | |
7aa6baee MCA |
584 | |
585 | if (esp_get_tc(s) == 0) { | |
586 | /* Indicate transfer to FIFO is complete */ | |
587 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
588 | } | |
82141c8b MCA |
589 | return; |
590 | } | |
591 | ||
592 | /* Partially filled a scsi buffer. Complete immediately. */ | |
593 | esp_lower_drq(s); | |
594 | esp_dma_done(s); | |
595 | } | |
74d71ea1 LV |
596 | } |
597 | ||
4d611c9a PB |
598 | static void esp_do_dma(ESPState *s) |
599 | { | |
023666da | 600 | uint32_t len, cmdlen; |
4ca2ba6f | 601 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
023666da | 602 | uint8_t buf[ESP_CMDFIFO_SZ]; |
a917d384 | 603 | |
6cc88d6b | 604 | len = esp_get_tc(s); |
4d611c9a | 605 | if (s->do_cmd) { |
15407433 LV |
606 | /* |
607 | * handle_ti_cmd() case: esp_do_dma() is called only from | |
608 | * handle_ti_cmd() with do_cmd != NULL (see the assert()) | |
609 | */ | |
023666da MCA |
610 | cmdlen = fifo8_num_used(&s->cmdfifo); |
611 | trace_esp_do_dma(cmdlen, len); | |
74d71ea1 | 612 | if (s->dma_memory_read) { |
0ebb5fd8 | 613 | len = MIN(len, fifo8_num_free(&s->cmdfifo)); |
023666da MCA |
614 | s->dma_memory_read(s->dma_opaque, buf, len); |
615 | fifo8_push_all(&s->cmdfifo, buf, len); | |
74d71ea1 | 616 | } else { |
1e794c51 | 617 | esp_set_pdma_cb(s, do_dma_pdma_cb); |
74d71ea1 LV |
618 | esp_raise_drq(s); |
619 | return; | |
620 | } | |
023666da | 621 | trace_esp_handle_ti_cmd(cmdlen); |
15407433 | 622 | s->ti_size = 0; |
799d90d8 MCA |
623 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { |
624 | /* No command received */ | |
023666da | 625 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { |
799d90d8 MCA |
626 | return; |
627 | } | |
628 | ||
629 | /* Command has been received */ | |
799d90d8 MCA |
630 | s->do_cmd = 0; |
631 | do_cmd(s); | |
632 | } else { | |
633 | /* | |
023666da | 634 | * Extra message out bytes received: update cmdfifo_cdb_offset |
799d90d8 MCA |
635 | * and then switch to commmand phase |
636 | */ | |
023666da | 637 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); |
799d90d8 MCA |
638 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
639 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
640 | s->rregs[ESP_RINTR] |= INTR_BS; | |
641 | esp_raise_irq(s); | |
642 | } | |
4d611c9a | 643 | return; |
a917d384 | 644 | } |
0db89536 MCA |
645 | if (!s->current_req) { |
646 | return; | |
647 | } | |
a917d384 PB |
648 | if (s->async_len == 0) { |
649 | /* Defer until data is available. */ | |
650 | return; | |
651 | } | |
652 | if (len > s->async_len) { | |
653 | len = s->async_len; | |
654 | } | |
655 | if (to_device) { | |
74d71ea1 LV |
656 | if (s->dma_memory_read) { |
657 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); | |
658 | } else { | |
1e794c51 | 659 | esp_set_pdma_cb(s, do_dma_pdma_cb); |
74d71ea1 LV |
660 | esp_raise_drq(s); |
661 | return; | |
662 | } | |
4d611c9a | 663 | } else { |
74d71ea1 LV |
664 | if (s->dma_memory_write) { |
665 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); | |
666 | } else { | |
7aa6baee MCA |
667 | /* Adjust TC for any leftover data in the FIFO */ |
668 | if (!fifo8_is_empty(&s->fifo)) { | |
669 | esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); | |
670 | } | |
671 | ||
82141c8b | 672 | /* Copy device data to FIFO */ |
042879fc MCA |
673 | len = MIN(len, fifo8_num_free(&s->fifo)); |
674 | fifo8_push_all(&s->fifo, s->async_buf, len); | |
82141c8b MCA |
675 | s->async_buf += len; |
676 | s->async_len -= len; | |
677 | s->ti_size -= len; | |
7aa6baee MCA |
678 | |
679 | /* | |
680 | * MacOS toolbox uses a TI length of 16 bytes for all commands, so | |
681 | * commands shorter than this must be padded accordingly | |
682 | */ | |
683 | if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) { | |
684 | while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) { | |
e5455b8c | 685 | esp_fifo_push(&s->fifo, 0); |
7aa6baee MCA |
686 | len++; |
687 | } | |
688 | } | |
689 | ||
82141c8b | 690 | esp_set_tc(s, esp_get_tc(s) - len); |
1e794c51 | 691 | esp_set_pdma_cb(s, do_dma_pdma_cb); |
74d71ea1 | 692 | esp_raise_drq(s); |
82141c8b MCA |
693 | |
694 | /* Indicate transfer to FIFO is complete */ | |
695 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
74d71ea1 LV |
696 | return; |
697 | } | |
a917d384 | 698 | } |
6cc88d6b | 699 | esp_set_tc(s, esp_get_tc(s) - len); |
a917d384 PB |
700 | s->async_buf += len; |
701 | s->async_len -= len; | |
94d5c79d | 702 | if (to_device) { |
6787f5fa | 703 | s->ti_size += len; |
94d5c79d | 704 | } else { |
6787f5fa | 705 | s->ti_size -= len; |
94d5c79d | 706 | } |
a917d384 | 707 | if (s->async_len == 0) { |
ad3376cc | 708 | scsi_req_continue(s->current_req); |
94d5c79d MCA |
709 | /* |
710 | * If there is still data to be read from the device then | |
711 | * complete the DMA operation immediately. Otherwise defer | |
712 | * until the scsi layer has completed. | |
713 | */ | |
6cc88d6b | 714 | if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) { |
ad3376cc | 715 | return; |
4d611c9a | 716 | } |
a917d384 | 717 | } |
ad3376cc PB |
718 | |
719 | /* Partially filled a scsi buffer. Complete immediately. */ | |
720 | esp_dma_done(s); | |
82141c8b | 721 | esp_lower_drq(s); |
4d611c9a PB |
722 | } |
723 | ||
1b9e48a5 MCA |
724 | static void esp_do_nodma(ESPState *s) |
725 | { | |
726 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); | |
7b320a8e | 727 | uint32_t cmdlen; |
1b9e48a5 MCA |
728 | int len; |
729 | ||
730 | if (s->do_cmd) { | |
731 | cmdlen = fifo8_num_used(&s->cmdfifo); | |
732 | trace_esp_handle_ti_cmd(cmdlen); | |
733 | s->ti_size = 0; | |
734 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { | |
735 | /* No command received */ | |
736 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { | |
737 | return; | |
738 | } | |
739 | ||
740 | /* Command has been received */ | |
741 | s->do_cmd = 0; | |
742 | do_cmd(s); | |
743 | } else { | |
744 | /* | |
745 | * Extra message out bytes received: update cmdfifo_cdb_offset | |
746 | * and then switch to commmand phase | |
747 | */ | |
748 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); | |
749 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; | |
750 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
751 | s->rregs[ESP_RINTR] |= INTR_BS; | |
752 | esp_raise_irq(s); | |
753 | } | |
754 | return; | |
755 | } | |
756 | ||
0db89536 MCA |
757 | if (!s->current_req) { |
758 | return; | |
759 | } | |
760 | ||
1b9e48a5 MCA |
761 | if (s->async_len == 0) { |
762 | /* Defer until data is available. */ | |
763 | return; | |
764 | } | |
765 | ||
766 | if (to_device) { | |
767 | len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ); | |
7b320a8e | 768 | esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
1b9e48a5 MCA |
769 | s->async_buf += len; |
770 | s->async_len -= len; | |
771 | s->ti_size += len; | |
772 | } else { | |
6ef2cabc MCA |
773 | if (fifo8_is_empty(&s->fifo)) { |
774 | fifo8_push(&s->fifo, s->async_buf[0]); | |
775 | s->async_buf++; | |
776 | s->async_len--; | |
777 | s->ti_size--; | |
778 | } | |
1b9e48a5 MCA |
779 | } |
780 | ||
781 | if (s->async_len == 0) { | |
782 | scsi_req_continue(s->current_req); | |
6ef2cabc | 783 | return; |
1b9e48a5 MCA |
784 | } |
785 | ||
786 | s->rregs[ESP_RINTR] |= INTR_BS; | |
787 | esp_raise_irq(s); | |
788 | } | |
789 | ||
4aaa6ac3 | 790 | void esp_command_complete(SCSIRequest *req, size_t resid) |
2e5d83bb | 791 | { |
4aaa6ac3 | 792 | ESPState *s = req->hba_private; |
6ef2cabc | 793 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
4aaa6ac3 | 794 | |
bf4b9889 | 795 | trace_esp_command_complete(); |
6ef2cabc MCA |
796 | |
797 | /* | |
798 | * Non-DMA transfers from the target will leave the last byte in | |
799 | * the FIFO so don't reset ti_size in this case | |
800 | */ | |
801 | if (s->dma || to_device) { | |
802 | if (s->ti_size != 0) { | |
803 | trace_esp_command_complete_unexpected(); | |
804 | } | |
805 | s->ti_size = 0; | |
c6df7102 | 806 | } |
6ef2cabc | 807 | |
c6df7102 | 808 | s->async_len = 0; |
4aaa6ac3 | 809 | if (req->status) { |
bf4b9889 | 810 | trace_esp_command_complete_fail(); |
c6df7102 | 811 | } |
4aaa6ac3 | 812 | s->status = req->status; |
6ef2cabc MCA |
813 | |
814 | /* | |
815 | * If the transfer is finished, switch to status phase. For non-DMA | |
816 | * transfers from the target the last byte is still in the FIFO | |
817 | */ | |
818 | if (s->ti_size == 0) { | |
819 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
820 | esp_dma_done(s); | |
821 | esp_lower_drq(s); | |
822 | } | |
823 | ||
c6df7102 PB |
824 | if (s->current_req) { |
825 | scsi_req_unref(s->current_req); | |
826 | s->current_req = NULL; | |
827 | s->current_dev = NULL; | |
828 | } | |
829 | } | |
830 | ||
9c7e23fc | 831 | void esp_transfer_data(SCSIRequest *req, uint32_t len) |
c6df7102 | 832 | { |
e6810db8 | 833 | ESPState *s = req->hba_private; |
4e78f3bf | 834 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
6cc88d6b | 835 | uint32_t dmalen = esp_get_tc(s); |
c6df7102 | 836 | |
7f0b6e11 | 837 | assert(!s->do_cmd); |
6cc88d6b | 838 | trace_esp_transfer_data(dmalen, s->ti_size); |
aba1f023 | 839 | s->async_len = len; |
c6df7102 | 840 | s->async_buf = scsi_req_get_buf(req); |
4e78f3bf MCA |
841 | |
842 | if (!to_device && !s->data_in_ready) { | |
843 | /* | |
844 | * Initial incoming data xfer is complete so raise command | |
845 | * completion interrupt | |
846 | */ | |
847 | s->data_in_ready = true; | |
848 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
849 | s->rregs[ESP_RINTR] |= INTR_BS; | |
850 | esp_raise_irq(s); | |
4e78f3bf MCA |
851 | } |
852 | ||
1b9e48a5 | 853 | if (s->ti_cmd == 0) { |
94d5c79d | 854 | /* |
1b9e48a5 MCA |
855 | * Always perform the initial transfer upon reception of the next TI |
856 | * command to ensure the DMA/non-DMA status of the command is correct. | |
857 | * It is not possible to use s->dma directly in the section below as | |
858 | * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the | |
859 | * async data transfer is delayed then s->dma is set incorrectly. | |
94d5c79d | 860 | */ |
1b9e48a5 MCA |
861 | return; |
862 | } | |
863 | ||
880d3089 | 864 | if (s->ti_cmd == (CMD_TI | CMD_DMA)) { |
1b9e48a5 MCA |
865 | if (dmalen) { |
866 | esp_do_dma(s); | |
867 | } else if (s->ti_size <= 0) { | |
868 | /* | |
869 | * If this was the last part of a DMA transfer then the | |
870 | * completion interrupt is deferred to here. | |
871 | */ | |
872 | esp_dma_done(s); | |
873 | esp_lower_drq(s); | |
874 | } | |
880d3089 | 875 | } else if (s->ti_cmd == CMD_TI) { |
1b9e48a5 | 876 | esp_do_nodma(s); |
4d611c9a | 877 | } |
2e5d83bb PB |
878 | } |
879 | ||
2f275b8f FB |
880 | static void handle_ti(ESPState *s) |
881 | { | |
1b9e48a5 | 882 | uint32_t dmalen; |
2f275b8f | 883 | |
7246e160 HP |
884 | if (s->dma && !s->dma_enabled) { |
885 | s->dma_cb = handle_ti; | |
886 | return; | |
887 | } | |
888 | ||
1b9e48a5 | 889 | s->ti_cmd = s->rregs[ESP_CMD]; |
4f6200f0 | 890 | if (s->dma) { |
1b9e48a5 | 891 | dmalen = esp_get_tc(s); |
b76624de | 892 | trace_esp_handle_ti(dmalen); |
5ad6bb97 | 893 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 894 | esp_do_dma(s); |
1b9e48a5 MCA |
895 | } else { |
896 | trace_esp_handle_ti(s->ti_size); | |
897 | esp_do_nodma(s); | |
9f149aa9 | 898 | } |
2f275b8f FB |
899 | } |
900 | ||
9c7e23fc | 901 | void esp_hard_reset(ESPState *s) |
6f7e9aec | 902 | { |
5aca8c3b BS |
903 | memset(s->rregs, 0, ESP_REGS); |
904 | memset(s->wregs, 0, ESP_REGS); | |
c9cf45c1 | 905 | s->tchi_written = 0; |
4e9aec74 | 906 | s->ti_size = 0; |
3f26c975 | 907 | s->async_len = 0; |
042879fc | 908 | fifo8_reset(&s->fifo); |
023666da | 909 | fifo8_reset(&s->cmdfifo); |
4e9aec74 | 910 | s->dma = 0; |
9f149aa9 | 911 | s->do_cmd = 0; |
73d74342 | 912 | s->dma_cb = NULL; |
8dea1dd4 BS |
913 | |
914 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
915 | } |
916 | ||
a391fdbc | 917 | static void esp_soft_reset(ESPState *s) |
85948643 | 918 | { |
85948643 | 919 | qemu_irq_lower(s->irq); |
74d71ea1 | 920 | qemu_irq_lower(s->irq_data); |
a391fdbc | 921 | esp_hard_reset(s); |
85948643 BS |
922 | } |
923 | ||
a391fdbc | 924 | static void parent_esp_reset(ESPState *s, int irq, int level) |
2d069bab | 925 | { |
85948643 | 926 | if (level) { |
a391fdbc | 927 | esp_soft_reset(s); |
85948643 | 928 | } |
2d069bab BS |
929 | } |
930 | ||
9c7e23fc | 931 | uint64_t esp_reg_read(ESPState *s, uint32_t saddr) |
73d74342 | 932 | { |
b630c075 | 933 | uint32_t val; |
73d74342 | 934 | |
6f7e9aec | 935 | switch (saddr) { |
5ad6bb97 | 936 | case ESP_FIFO: |
1b9e48a5 MCA |
937 | if (s->dma_memory_read && s->dma_memory_write && |
938 | (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { | |
ff589551 PP |
939 | /* Data out. */ |
940 | qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); | |
941 | s->rregs[ESP_FIFO] = 0; | |
042879fc | 942 | } else { |
6ef2cabc MCA |
943 | if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { |
944 | if (s->ti_size) { | |
945 | esp_do_nodma(s); | |
946 | } else { | |
947 | /* | |
948 | * The last byte of a non-DMA transfer has been read out | |
949 | * of the FIFO so switch to status phase | |
950 | */ | |
951 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
952 | } | |
953 | } | |
c5fef911 | 954 | s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); |
4f6200f0 | 955 | } |
b630c075 | 956 | val = s->rregs[ESP_FIFO]; |
f930d07e | 957 | break; |
5ad6bb97 | 958 | case ESP_RINTR: |
94d5c79d MCA |
959 | /* |
960 | * Clear sequence step, interrupt register and all status bits | |
961 | * except TC | |
962 | */ | |
b630c075 | 963 | val = s->rregs[ESP_RINTR]; |
2814df28 BS |
964 | s->rregs[ESP_RINTR] = 0; |
965 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
af947a3d MCA |
966 | /* |
967 | * According to the datasheet ESP_RSEQ should be cleared, but as the | |
968 | * emulation currently defers information transfers to the next TI | |
969 | * command leave it for now so that pedantic guests such as the old | |
970 | * Linux 2.6 driver see the correct flags before the next SCSI phase | |
971 | * transition. | |
972 | * | |
973 | * s->rregs[ESP_RSEQ] = SEQ_0; | |
974 | */ | |
c73f96fd | 975 | esp_lower_irq(s); |
b630c075 | 976 | break; |
c9cf45c1 HR |
977 | case ESP_TCHI: |
978 | /* Return the unique id if the value has never been written */ | |
979 | if (!s->tchi_written) { | |
b630c075 MCA |
980 | val = s->chip_id; |
981 | } else { | |
982 | val = s->rregs[saddr]; | |
c9cf45c1 | 983 | } |
b630c075 | 984 | break; |
238ec4d7 MCA |
985 | case ESP_RFLAGS: |
986 | /* Bottom 5 bits indicate number of bytes in FIFO */ | |
987 | val = fifo8_num_used(&s->fifo); | |
988 | break; | |
6f7e9aec | 989 | default: |
b630c075 | 990 | val = s->rregs[saddr]; |
f930d07e | 991 | break; |
6f7e9aec | 992 | } |
b630c075 MCA |
993 | |
994 | trace_esp_mem_readb(saddr, val); | |
995 | return val; | |
6f7e9aec FB |
996 | } |
997 | ||
9c7e23fc | 998 | void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) |
6f7e9aec | 999 | { |
bf4b9889 | 1000 | trace_esp_mem_writeb(saddr, s->wregs[saddr], val); |
6f7e9aec | 1001 | switch (saddr) { |
c9cf45c1 HR |
1002 | case ESP_TCHI: |
1003 | s->tchi_written = true; | |
1004 | /* fall through */ | |
5ad6bb97 BS |
1005 | case ESP_TCLO: |
1006 | case ESP_TCMID: | |
1007 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 1008 | break; |
5ad6bb97 | 1009 | case ESP_FIFO: |
9f149aa9 | 1010 | if (s->do_cmd) { |
e5455b8c | 1011 | esp_fifo_push(&s->cmdfifo, val); |
6ef2cabc MCA |
1012 | |
1013 | /* | |
1014 | * If any unexpected message out/command phase data is | |
1015 | * transferred using non-DMA, raise the interrupt | |
1016 | */ | |
1017 | if (s->rregs[ESP_CMD] == CMD_TI) { | |
1018 | s->rregs[ESP_RINTR] |= INTR_BS; | |
1019 | esp_raise_irq(s); | |
1020 | } | |
2e5d83bb | 1021 | } else { |
e5455b8c | 1022 | esp_fifo_push(&s->fifo, val); |
2e5d83bb | 1023 | } |
f930d07e | 1024 | break; |
5ad6bb97 | 1025 | case ESP_CMD: |
4f6200f0 | 1026 | s->rregs[saddr] = val; |
5ad6bb97 | 1027 | if (val & CMD_DMA) { |
f930d07e | 1028 | s->dma = 1; |
6787f5fa | 1029 | /* Reload DMA counter. */ |
96676c2f MCA |
1030 | if (esp_get_stc(s) == 0) { |
1031 | esp_set_tc(s, 0x10000); | |
1032 | } else { | |
1033 | esp_set_tc(s, esp_get_stc(s)); | |
1034 | } | |
f930d07e BS |
1035 | } else { |
1036 | s->dma = 0; | |
1037 | } | |
94d5c79d | 1038 | switch (val & CMD_CMD) { |
5ad6bb97 | 1039 | case CMD_NOP: |
bf4b9889 | 1040 | trace_esp_mem_writeb_cmd_nop(val); |
f930d07e | 1041 | break; |
5ad6bb97 | 1042 | case CMD_FLUSH: |
bf4b9889 | 1043 | trace_esp_mem_writeb_cmd_flush(val); |
042879fc | 1044 | fifo8_reset(&s->fifo); |
f930d07e | 1045 | break; |
5ad6bb97 | 1046 | case CMD_RESET: |
bf4b9889 | 1047 | trace_esp_mem_writeb_cmd_reset(val); |
a391fdbc | 1048 | esp_soft_reset(s); |
f930d07e | 1049 | break; |
5ad6bb97 | 1050 | case CMD_BUSRESET: |
bf4b9889 | 1051 | trace_esp_mem_writeb_cmd_bus_reset(val); |
5ad6bb97 | 1052 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { |
cf47a41e | 1053 | s->rregs[ESP_RINTR] |= INTR_RST; |
c73f96fd | 1054 | esp_raise_irq(s); |
9e61bde5 | 1055 | } |
f930d07e | 1056 | break; |
5ad6bb97 | 1057 | case CMD_TI: |
0097d3ec | 1058 | trace_esp_mem_writeb_cmd_ti(val); |
f930d07e BS |
1059 | handle_ti(s); |
1060 | break; | |
5ad6bb97 | 1061 | case CMD_ICCS: |
bf4b9889 | 1062 | trace_esp_mem_writeb_cmd_iccs(val); |
f930d07e | 1063 | write_response(s); |
cf47a41e | 1064 | s->rregs[ESP_RINTR] |= INTR_FC; |
4bf5801d | 1065 | s->rregs[ESP_RSTAT] |= STAT_MI; |
f930d07e | 1066 | break; |
5ad6bb97 | 1067 | case CMD_MSGACC: |
bf4b9889 | 1068 | trace_esp_mem_writeb_cmd_msgacc(val); |
cf47a41e | 1069 | s->rregs[ESP_RINTR] |= INTR_DC; |
5ad6bb97 | 1070 | s->rregs[ESP_RSEQ] = 0; |
4e2a68c1 AT |
1071 | s->rregs[ESP_RFLAGS] = 0; |
1072 | esp_raise_irq(s); | |
f930d07e | 1073 | break; |
0fd0eb21 | 1074 | case CMD_PAD: |
bf4b9889 | 1075 | trace_esp_mem_writeb_cmd_pad(val); |
0fd0eb21 | 1076 | s->rregs[ESP_RSTAT] = STAT_TC; |
cf47a41e | 1077 | s->rregs[ESP_RINTR] |= INTR_FC; |
0fd0eb21 BS |
1078 | s->rregs[ESP_RSEQ] = 0; |
1079 | break; | |
5ad6bb97 | 1080 | case CMD_SATN: |
bf4b9889 | 1081 | trace_esp_mem_writeb_cmd_satn(val); |
f930d07e | 1082 | break; |
6915bff1 HP |
1083 | case CMD_RSTATN: |
1084 | trace_esp_mem_writeb_cmd_rstatn(val); | |
1085 | break; | |
5e1e0a3b | 1086 | case CMD_SEL: |
bf4b9889 | 1087 | trace_esp_mem_writeb_cmd_sel(val); |
f2818f22 | 1088 | handle_s_without_atn(s); |
5e1e0a3b | 1089 | break; |
5ad6bb97 | 1090 | case CMD_SELATN: |
bf4b9889 | 1091 | trace_esp_mem_writeb_cmd_selatn(val); |
f930d07e BS |
1092 | handle_satn(s); |
1093 | break; | |
5ad6bb97 | 1094 | case CMD_SELATNS: |
bf4b9889 | 1095 | trace_esp_mem_writeb_cmd_selatns(val); |
f930d07e BS |
1096 | handle_satn_stop(s); |
1097 | break; | |
5ad6bb97 | 1098 | case CMD_ENSEL: |
bf4b9889 | 1099 | trace_esp_mem_writeb_cmd_ensel(val); |
e3926838 | 1100 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 1101 | break; |
6fe84c18 HP |
1102 | case CMD_DISSEL: |
1103 | trace_esp_mem_writeb_cmd_dissel(val); | |
1104 | s->rregs[ESP_RINTR] = 0; | |
1105 | esp_raise_irq(s); | |
1106 | break; | |
f930d07e | 1107 | default: |
3af4e9aa | 1108 | trace_esp_error_unhandled_command(val); |
f930d07e BS |
1109 | break; |
1110 | } | |
1111 | break; | |
5ad6bb97 | 1112 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 1113 | break; |
5ad6bb97 | 1114 | case ESP_CFG1: |
9ea73f8b PB |
1115 | case ESP_CFG2: case ESP_CFG3: |
1116 | case ESP_RES3: case ESP_RES4: | |
4f6200f0 FB |
1117 | s->rregs[saddr] = val; |
1118 | break; | |
5ad6bb97 | 1119 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 1120 | break; |
6f7e9aec | 1121 | default: |
3af4e9aa | 1122 | trace_esp_error_invalid_write(val, saddr); |
8dea1dd4 | 1123 | return; |
6f7e9aec | 1124 | } |
2f275b8f | 1125 | s->wregs[saddr] = val; |
6f7e9aec FB |
1126 | } |
1127 | ||
a8170e5e | 1128 | static bool esp_mem_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
1129 | unsigned size, bool is_write, |
1130 | MemTxAttrs attrs) | |
67bb5314 AK |
1131 | { |
1132 | return (size == 1) || (is_write && size == 4); | |
1133 | } | |
6f7e9aec | 1134 | |
6cc88d6b MCA |
1135 | static bool esp_is_before_version_5(void *opaque, int version_id) |
1136 | { | |
1137 | ESPState *s = ESP(opaque); | |
1138 | ||
1139 | version_id = MIN(version_id, s->mig_version_id); | |
1140 | return version_id < 5; | |
1141 | } | |
1142 | ||
4e78f3bf MCA |
1143 | static bool esp_is_version_5(void *opaque, int version_id) |
1144 | { | |
1145 | ESPState *s = ESP(opaque); | |
1146 | ||
1147 | version_id = MIN(version_id, s->mig_version_id); | |
0bcd5a18 | 1148 | return version_id >= 5; |
4e78f3bf MCA |
1149 | } |
1150 | ||
4eb86065 PB |
1151 | static bool esp_is_version_6(void *opaque, int version_id) |
1152 | { | |
1153 | ESPState *s = ESP(opaque); | |
1154 | ||
1155 | version_id = MIN(version_id, s->mig_version_id); | |
1156 | return version_id >= 6; | |
1157 | } | |
1158 | ||
ff4a1dab | 1159 | int esp_pre_save(void *opaque) |
0bd005be | 1160 | { |
ff4a1dab MCA |
1161 | ESPState *s = ESP(object_resolve_path_component( |
1162 | OBJECT(opaque), "esp")); | |
0bd005be MCA |
1163 | |
1164 | s->mig_version_id = vmstate_esp.version_id; | |
1165 | return 0; | |
1166 | } | |
1167 | ||
1168 | static int esp_post_load(void *opaque, int version_id) | |
1169 | { | |
1170 | ESPState *s = ESP(opaque); | |
042879fc | 1171 | int len, i; |
0bd005be | 1172 | |
6cc88d6b MCA |
1173 | version_id = MIN(version_id, s->mig_version_id); |
1174 | ||
1175 | if (version_id < 5) { | |
1176 | esp_set_tc(s, s->mig_dma_left); | |
042879fc MCA |
1177 | |
1178 | /* Migrate ti_buf to fifo */ | |
1179 | len = s->mig_ti_wptr - s->mig_ti_rptr; | |
1180 | for (i = 0; i < len; i++) { | |
1181 | fifo8_push(&s->fifo, s->mig_ti_buf[i]); | |
1182 | } | |
023666da MCA |
1183 | |
1184 | /* Migrate cmdbuf to cmdfifo */ | |
1185 | for (i = 0; i < s->mig_cmdlen; i++) { | |
1186 | fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); | |
1187 | } | |
6cc88d6b MCA |
1188 | } |
1189 | ||
0bd005be MCA |
1190 | s->mig_version_id = vmstate_esp.version_id; |
1191 | return 0; | |
1192 | } | |
1193 | ||
9c7e23fc | 1194 | const VMStateDescription vmstate_esp = { |
94d5c79d | 1195 | .name = "esp", |
4eb86065 | 1196 | .version_id = 6, |
cc9952f3 | 1197 | .minimum_version_id = 3, |
0bd005be | 1198 | .post_load = esp_post_load, |
35d08458 | 1199 | .fields = (VMStateField[]) { |
cc9952f3 BS |
1200 | VMSTATE_BUFFER(rregs, ESPState), |
1201 | VMSTATE_BUFFER(wregs, ESPState), | |
1202 | VMSTATE_INT32(ti_size, ESPState), | |
042879fc MCA |
1203 | VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), |
1204 | VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), | |
1205 | VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), | |
3944966d | 1206 | VMSTATE_UINT32(status, ESPState), |
4aaa6ac3 MCA |
1207 | VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, |
1208 | esp_is_before_version_5), | |
1209 | VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, | |
1210 | esp_is_before_version_5), | |
cc9952f3 | 1211 | VMSTATE_UINT32(dma, ESPState), |
023666da MCA |
1212 | VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, |
1213 | esp_is_before_version_5, 0, 16), | |
1214 | VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, | |
1215 | esp_is_before_version_5, 16, | |
1216 | sizeof(typeof_field(ESPState, mig_cmdbuf))), | |
1217 | VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), | |
cc9952f3 | 1218 | VMSTATE_UINT32(do_cmd, ESPState), |
6cc88d6b | 1219 | VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), |
4e78f3bf | 1220 | VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), |
023666da | 1221 | VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), |
042879fc | 1222 | VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), |
023666da | 1223 | VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), |
1b9e48a5 | 1224 | VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), |
4eb86065 | 1225 | VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), |
cc9952f3 | 1226 | VMSTATE_END_OF_LIST() |
74d71ea1 | 1227 | }, |
cc9952f3 | 1228 | }; |
6f7e9aec | 1229 | |
a8170e5e | 1230 | static void sysbus_esp_mem_write(void *opaque, hwaddr addr, |
a391fdbc HP |
1231 | uint64_t val, unsigned int size) |
1232 | { | |
1233 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1234 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1235 | uint32_t saddr; |
1236 | ||
1237 | saddr = addr >> sysbus->it_shift; | |
eb169c76 | 1238 | esp_reg_write(s, saddr, val); |
a391fdbc HP |
1239 | } |
1240 | ||
a8170e5e | 1241 | static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, |
a391fdbc HP |
1242 | unsigned int size) |
1243 | { | |
1244 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1245 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1246 | uint32_t saddr; |
1247 | ||
1248 | saddr = addr >> sysbus->it_shift; | |
eb169c76 | 1249 | return esp_reg_read(s, saddr); |
a391fdbc HP |
1250 | } |
1251 | ||
1252 | static const MemoryRegionOps sysbus_esp_mem_ops = { | |
1253 | .read = sysbus_esp_mem_read, | |
1254 | .write = sysbus_esp_mem_write, | |
1255 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1256 | .valid.accepts = esp_mem_accepts, | |
1257 | }; | |
1258 | ||
74d71ea1 LV |
1259 | static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, |
1260 | uint64_t val, unsigned int size) | |
1261 | { | |
1262 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1263 | ESPState *s = ESP(&sysbus->esp); |
74d71ea1 | 1264 | |
960ebfd9 MCA |
1265 | trace_esp_pdma_write(size); |
1266 | ||
74d71ea1 LV |
1267 | switch (size) { |
1268 | case 1: | |
761bef75 | 1269 | esp_pdma_write(s, val); |
74d71ea1 LV |
1270 | break; |
1271 | case 2: | |
761bef75 MCA |
1272 | esp_pdma_write(s, val >> 8); |
1273 | esp_pdma_write(s, val); | |
74d71ea1 LV |
1274 | break; |
1275 | } | |
d0243b09 | 1276 | esp_pdma_cb(s); |
74d71ea1 LV |
1277 | } |
1278 | ||
1279 | static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, | |
1280 | unsigned int size) | |
1281 | { | |
1282 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1283 | ESPState *s = ESP(&sysbus->esp); |
74d71ea1 LV |
1284 | uint64_t val = 0; |
1285 | ||
960ebfd9 MCA |
1286 | trace_esp_pdma_read(size); |
1287 | ||
74d71ea1 LV |
1288 | switch (size) { |
1289 | case 1: | |
761bef75 | 1290 | val = esp_pdma_read(s); |
74d71ea1 LV |
1291 | break; |
1292 | case 2: | |
761bef75 MCA |
1293 | val = esp_pdma_read(s); |
1294 | val = (val << 8) | esp_pdma_read(s); | |
74d71ea1 LV |
1295 | break; |
1296 | } | |
7aa6baee | 1297 | if (fifo8_num_used(&s->fifo) < 2) { |
d0243b09 | 1298 | esp_pdma_cb(s); |
74d71ea1 LV |
1299 | } |
1300 | return val; | |
1301 | } | |
1302 | ||
1303 | static const MemoryRegionOps sysbus_esp_pdma_ops = { | |
1304 | .read = sysbus_esp_pdma_read, | |
1305 | .write = sysbus_esp_pdma_write, | |
1306 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1307 | .valid.min_access_size = 1, | |
cf1b8286 MCA |
1308 | .valid.max_access_size = 4, |
1309 | .impl.min_access_size = 1, | |
1310 | .impl.max_access_size = 2, | |
74d71ea1 LV |
1311 | }; |
1312 | ||
afd4030c PB |
1313 | static const struct SCSIBusInfo esp_scsi_info = { |
1314 | .tcq = false, | |
7e0380b9 PB |
1315 | .max_target = ESP_MAX_DEVS, |
1316 | .max_lun = 7, | |
afd4030c | 1317 | |
c6df7102 | 1318 | .transfer_data = esp_transfer_data, |
94d3f98a PB |
1319 | .complete = esp_command_complete, |
1320 | .cancel = esp_request_cancelled | |
cfdc1bb0 PB |
1321 | }; |
1322 | ||
a391fdbc | 1323 | static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) |
cfb9de9c | 1324 | { |
84fbefed | 1325 | SysBusESPState *sysbus = SYSBUS_ESP(opaque); |
eb169c76 | 1326 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1327 | |
1328 | switch (irq) { | |
1329 | case 0: | |
1330 | parent_esp_reset(s, irq, level); | |
1331 | break; | |
1332 | case 1: | |
1333 | esp_dma_enable(opaque, irq, level); | |
1334 | break; | |
1335 | } | |
1336 | } | |
1337 | ||
b09318ca | 1338 | static void sysbus_esp_realize(DeviceState *dev, Error **errp) |
a391fdbc | 1339 | { |
b09318ca | 1340 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
84fbefed | 1341 | SysBusESPState *sysbus = SYSBUS_ESP(dev); |
eb169c76 MCA |
1342 | ESPState *s = ESP(&sysbus->esp); |
1343 | ||
1344 | if (!qdev_realize(DEVICE(s), NULL, errp)) { | |
1345 | return; | |
1346 | } | |
6f7e9aec | 1347 | |
b09318ca | 1348 | sysbus_init_irq(sbd, &s->irq); |
74d71ea1 | 1349 | sysbus_init_irq(sbd, &s->irq_data); |
a391fdbc | 1350 | assert(sysbus->it_shift != -1); |
6f7e9aec | 1351 | |
d32e4b3d | 1352 | s->chip_id = TCHI_FAS100A; |
29776739 | 1353 | memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, |
74d71ea1 | 1354 | sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); |
b09318ca | 1355 | sysbus_init_mmio(sbd, &sysbus->iomem); |
74d71ea1 | 1356 | memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, |
cf1b8286 | 1357 | sysbus, "esp-pdma", 4); |
74d71ea1 | 1358 | sysbus_init_mmio(sbd, &sysbus->pdma); |
6f7e9aec | 1359 | |
b09318ca | 1360 | qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); |
2d069bab | 1361 | |
739e95f5 | 1362 | scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); |
67e999be | 1363 | } |
cfb9de9c | 1364 | |
a391fdbc HP |
1365 | static void sysbus_esp_hard_reset(DeviceState *dev) |
1366 | { | |
84fbefed | 1367 | SysBusESPState *sysbus = SYSBUS_ESP(dev); |
eb169c76 MCA |
1368 | ESPState *s = ESP(&sysbus->esp); |
1369 | ||
1370 | esp_hard_reset(s); | |
1371 | } | |
1372 | ||
1373 | static void sysbus_esp_init(Object *obj) | |
1374 | { | |
1375 | SysBusESPState *sysbus = SYSBUS_ESP(obj); | |
1376 | ||
1377 | object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); | |
a391fdbc HP |
1378 | } |
1379 | ||
1380 | static const VMStateDescription vmstate_sysbus_esp_scsi = { | |
1381 | .name = "sysbusespscsi", | |
0bd005be | 1382 | .version_id = 2, |
ea84a442 | 1383 | .minimum_version_id = 1, |
ff4a1dab | 1384 | .pre_save = esp_pre_save, |
a391fdbc | 1385 | .fields = (VMStateField[]) { |
0bd005be | 1386 | VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), |
a391fdbc HP |
1387 | VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), |
1388 | VMSTATE_END_OF_LIST() | |
1389 | } | |
999e12bb AL |
1390 | }; |
1391 | ||
a391fdbc | 1392 | static void sysbus_esp_class_init(ObjectClass *klass, void *data) |
999e12bb | 1393 | { |
39bffca2 | 1394 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1395 | |
b09318ca | 1396 | dc->realize = sysbus_esp_realize; |
a391fdbc HP |
1397 | dc->reset = sysbus_esp_hard_reset; |
1398 | dc->vmsd = &vmstate_sysbus_esp_scsi; | |
125ee0ed | 1399 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
999e12bb AL |
1400 | } |
1401 | ||
1f077308 | 1402 | static const TypeInfo sysbus_esp_info = { |
84fbefed | 1403 | .name = TYPE_SYSBUS_ESP, |
39bffca2 | 1404 | .parent = TYPE_SYS_BUS_DEVICE, |
eb169c76 | 1405 | .instance_init = sysbus_esp_init, |
a391fdbc HP |
1406 | .instance_size = sizeof(SysBusESPState), |
1407 | .class_init = sysbus_esp_class_init, | |
63235df8 BS |
1408 | }; |
1409 | ||
042879fc MCA |
1410 | static void esp_finalize(Object *obj) |
1411 | { | |
1412 | ESPState *s = ESP(obj); | |
1413 | ||
1414 | fifo8_destroy(&s->fifo); | |
023666da | 1415 | fifo8_destroy(&s->cmdfifo); |
042879fc MCA |
1416 | } |
1417 | ||
1418 | static void esp_init(Object *obj) | |
1419 | { | |
1420 | ESPState *s = ESP(obj); | |
1421 | ||
1422 | fifo8_create(&s->fifo, ESP_FIFO_SZ); | |
023666da | 1423 | fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); |
042879fc MCA |
1424 | } |
1425 | ||
eb169c76 MCA |
1426 | static void esp_class_init(ObjectClass *klass, void *data) |
1427 | { | |
1428 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1429 | ||
1430 | /* internal device for sysbusesp/pciespscsi, not user-creatable */ | |
1431 | dc->user_creatable = false; | |
1432 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | |
1433 | } | |
1434 | ||
1435 | static const TypeInfo esp_info = { | |
1436 | .name = TYPE_ESP, | |
1437 | .parent = TYPE_DEVICE, | |
042879fc MCA |
1438 | .instance_init = esp_init, |
1439 | .instance_finalize = esp_finalize, | |
eb169c76 MCA |
1440 | .instance_size = sizeof(ESPState), |
1441 | .class_init = esp_class_init, | |
1442 | }; | |
1443 | ||
83f7d43a | 1444 | static void esp_register_types(void) |
cfb9de9c | 1445 | { |
a391fdbc | 1446 | type_register_static(&sysbus_esp_info); |
eb169c76 | 1447 | type_register_static(&esp_info); |
cfb9de9c PB |
1448 | } |
1449 | ||
83f7d43a | 1450 | type_init(esp_register_types) |