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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
fabaaf1d | 5 | * Copyright (c) 2012 Herve Poussineau |
5fafdf24 | 6 | * |
6f7e9aec FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
5d20fa6b | 25 | |
a4ab4792 | 26 | #include "qemu/osdep.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
0d09e41a | 28 | #include "hw/scsi/esp.h" |
bf4b9889 | 29 | #include "trace.h" |
da34e65c | 30 | #include "qapi/error.h" |
1de7afc9 | 31 | #include "qemu/log.h" |
6f7e9aec | 32 | |
67e999be | 33 | /* |
5ad6bb97 BS |
34 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
35 | * also produced as NCR89C100. See | |
67e999be FB |
36 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
37 | * and | |
38 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
39 | */ | |
40 | ||
c73f96fd BS |
41 | static void esp_raise_irq(ESPState *s) |
42 | { | |
43 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
44 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
45 | qemu_irq_raise(s->irq); | |
bf4b9889 | 46 | trace_esp_raise_irq(); |
c73f96fd BS |
47 | } |
48 | } | |
49 | ||
50 | static void esp_lower_irq(ESPState *s) | |
51 | { | |
52 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
53 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
54 | qemu_irq_lower(s->irq); | |
bf4b9889 | 55 | trace_esp_lower_irq(); |
c73f96fd BS |
56 | } |
57 | } | |
58 | ||
9c7e23fc | 59 | void esp_dma_enable(ESPState *s, int irq, int level) |
73d74342 | 60 | { |
73d74342 BS |
61 | if (level) { |
62 | s->dma_enabled = 1; | |
bf4b9889 | 63 | trace_esp_dma_enable(); |
73d74342 BS |
64 | if (s->dma_cb) { |
65 | s->dma_cb(s); | |
66 | s->dma_cb = NULL; | |
67 | } | |
68 | } else { | |
bf4b9889 | 69 | trace_esp_dma_disable(); |
73d74342 BS |
70 | s->dma_enabled = 0; |
71 | } | |
72 | } | |
73 | ||
9c7e23fc | 74 | void esp_request_cancelled(SCSIRequest *req) |
94d3f98a | 75 | { |
e6810db8 | 76 | ESPState *s = req->hba_private; |
94d3f98a PB |
77 | |
78 | if (req == s->current_req) { | |
79 | scsi_req_unref(s->current_req); | |
80 | s->current_req = NULL; | |
81 | s->current_dev = NULL; | |
82 | } | |
83 | } | |
84 | ||
22548760 | 85 | static uint32_t get_cmd(ESPState *s, uint8_t *buf) |
2f275b8f | 86 | { |
a917d384 | 87 | uint32_t dmalen; |
2f275b8f FB |
88 | int target; |
89 | ||
8dea1dd4 | 90 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 91 | if (s->dma) { |
9ea73f8b PB |
92 | dmalen = s->rregs[ESP_TCLO]; |
93 | dmalen |= s->rregs[ESP_TCMID] << 8; | |
94 | dmalen |= s->rregs[ESP_TCHI] << 16; | |
8b17de88 | 95 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
4f6200f0 | 96 | } else { |
fc4d65da BS |
97 | dmalen = s->ti_size; |
98 | memcpy(buf, s->ti_buf, dmalen); | |
75ef8496 | 99 | buf[0] = buf[2] >> 5; |
4f6200f0 | 100 | } |
bf4b9889 | 101 | trace_esp_get_cmd(dmalen, target); |
2e5d83bb | 102 | |
2f275b8f | 103 | s->ti_size = 0; |
4f6200f0 FB |
104 | s->ti_rptr = 0; |
105 | s->ti_wptr = 0; | |
2f275b8f | 106 | |
429bef69 | 107 | if (s->current_req) { |
a917d384 | 108 | /* Started a new command before the old one finished. Cancel it. */ |
94d3f98a | 109 | scsi_req_cancel(s->current_req); |
a917d384 PB |
110 | s->async_len = 0; |
111 | } | |
112 | ||
0d3545e7 | 113 | s->current_dev = scsi_device_find(&s->bus, 0, target, 0); |
f48a7a6e | 114 | if (!s->current_dev) { |
2e5d83bb | 115 | // No such drive |
c73f96fd | 116 | s->rregs[ESP_RSTAT] = 0; |
5ad6bb97 BS |
117 | s->rregs[ESP_RINTR] = INTR_DC; |
118 | s->rregs[ESP_RSEQ] = SEQ_0; | |
c73f96fd | 119 | esp_raise_irq(s); |
f930d07e | 120 | return 0; |
2f275b8f | 121 | } |
9f149aa9 PB |
122 | return dmalen; |
123 | } | |
124 | ||
f2818f22 | 125 | static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) |
9f149aa9 PB |
126 | { |
127 | int32_t datalen; | |
128 | int lun; | |
f48a7a6e | 129 | SCSIDevice *current_lun; |
9f149aa9 | 130 | |
bf4b9889 | 131 | trace_esp_do_busid_cmd(busid); |
f2818f22 | 132 | lun = busid & 7; |
0d3545e7 | 133 | current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); |
e6810db8 | 134 | s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); |
c39ce112 | 135 | datalen = scsi_req_enqueue(s->current_req); |
67e999be FB |
136 | s->ti_size = datalen; |
137 | if (datalen != 0) { | |
c73f96fd | 138 | s->rregs[ESP_RSTAT] = STAT_TC; |
a917d384 | 139 | s->dma_left = 0; |
6787f5fa | 140 | s->dma_counter = 0; |
2e5d83bb | 141 | if (datalen > 0) { |
5ad6bb97 | 142 | s->rregs[ESP_RSTAT] |= STAT_DI; |
2e5d83bb | 143 | } else { |
5ad6bb97 | 144 | s->rregs[ESP_RSTAT] |= STAT_DO; |
b9788fc4 | 145 | } |
ad3376cc | 146 | scsi_req_continue(s->current_req); |
2f275b8f | 147 | } |
5ad6bb97 BS |
148 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
149 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 150 | esp_raise_irq(s); |
2f275b8f FB |
151 | } |
152 | ||
f2818f22 AT |
153 | static void do_cmd(ESPState *s, uint8_t *buf) |
154 | { | |
155 | uint8_t busid = buf[0]; | |
156 | ||
157 | do_busid_cmd(s, &buf[1], busid); | |
158 | } | |
159 | ||
9f149aa9 PB |
160 | static void handle_satn(ESPState *s) |
161 | { | |
162 | uint8_t buf[32]; | |
163 | int len; | |
164 | ||
1b26eaa1 | 165 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
166 | s->dma_cb = handle_satn; |
167 | return; | |
168 | } | |
9f149aa9 PB |
169 | len = get_cmd(s, buf); |
170 | if (len) | |
171 | do_cmd(s, buf); | |
172 | } | |
173 | ||
f2818f22 AT |
174 | static void handle_s_without_atn(ESPState *s) |
175 | { | |
176 | uint8_t buf[32]; | |
177 | int len; | |
178 | ||
1b26eaa1 | 179 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
180 | s->dma_cb = handle_s_without_atn; |
181 | return; | |
182 | } | |
f2818f22 AT |
183 | len = get_cmd(s, buf); |
184 | if (len) { | |
185 | do_busid_cmd(s, buf, 0); | |
186 | } | |
187 | } | |
188 | ||
9f149aa9 PB |
189 | static void handle_satn_stop(ESPState *s) |
190 | { | |
1b26eaa1 | 191 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
192 | s->dma_cb = handle_satn_stop; |
193 | return; | |
194 | } | |
9f149aa9 PB |
195 | s->cmdlen = get_cmd(s, s->cmdbuf); |
196 | if (s->cmdlen) { | |
bf4b9889 | 197 | trace_esp_handle_satn_stop(s->cmdlen); |
9f149aa9 | 198 | s->do_cmd = 1; |
c73f96fd | 199 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
5ad6bb97 BS |
200 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
201 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 202 | esp_raise_irq(s); |
9f149aa9 PB |
203 | } |
204 | } | |
205 | ||
0fc5c15a | 206 | static void write_response(ESPState *s) |
2f275b8f | 207 | { |
bf4b9889 | 208 | trace_esp_write_response(s->status); |
3944966d | 209 | s->ti_buf[0] = s->status; |
0fc5c15a | 210 | s->ti_buf[1] = 0; |
4f6200f0 | 211 | if (s->dma) { |
8b17de88 | 212 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); |
c73f96fd | 213 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
5ad6bb97 BS |
214 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
215 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
4f6200f0 | 216 | } else { |
f930d07e BS |
217 | s->ti_size = 2; |
218 | s->ti_rptr = 0; | |
219 | s->ti_wptr = 0; | |
5ad6bb97 | 220 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 221 | } |
c73f96fd | 222 | esp_raise_irq(s); |
2f275b8f | 223 | } |
4f6200f0 | 224 | |
a917d384 PB |
225 | static void esp_dma_done(ESPState *s) |
226 | { | |
c73f96fd | 227 | s->rregs[ESP_RSTAT] |= STAT_TC; |
5ad6bb97 BS |
228 | s->rregs[ESP_RINTR] = INTR_BS; |
229 | s->rregs[ESP_RSEQ] = 0; | |
230 | s->rregs[ESP_RFLAGS] = 0; | |
231 | s->rregs[ESP_TCLO] = 0; | |
232 | s->rregs[ESP_TCMID] = 0; | |
9ea73f8b | 233 | s->rregs[ESP_TCHI] = 0; |
c73f96fd | 234 | esp_raise_irq(s); |
a917d384 PB |
235 | } |
236 | ||
4d611c9a PB |
237 | static void esp_do_dma(ESPState *s) |
238 | { | |
67e999be | 239 | uint32_t len; |
4d611c9a | 240 | int to_device; |
a917d384 | 241 | |
67e999be | 242 | to_device = (s->ti_size < 0); |
a917d384 | 243 | len = s->dma_left; |
4d611c9a | 244 | if (s->do_cmd) { |
bf4b9889 | 245 | trace_esp_do_dma(s->cmdlen, len); |
8b17de88 | 246 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
4d611c9a PB |
247 | s->ti_size = 0; |
248 | s->cmdlen = 0; | |
249 | s->do_cmd = 0; | |
250 | do_cmd(s, s->cmdbuf); | |
251 | return; | |
a917d384 PB |
252 | } |
253 | if (s->async_len == 0) { | |
254 | /* Defer until data is available. */ | |
255 | return; | |
256 | } | |
257 | if (len > s->async_len) { | |
258 | len = s->async_len; | |
259 | } | |
260 | if (to_device) { | |
8b17de88 | 261 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
4d611c9a | 262 | } else { |
8b17de88 | 263 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
a917d384 | 264 | } |
a917d384 PB |
265 | s->dma_left -= len; |
266 | s->async_buf += len; | |
267 | s->async_len -= len; | |
6787f5fa PB |
268 | if (to_device) |
269 | s->ti_size += len; | |
270 | else | |
271 | s->ti_size -= len; | |
a917d384 | 272 | if (s->async_len == 0) { |
ad3376cc PB |
273 | scsi_req_continue(s->current_req); |
274 | /* If there is still data to be read from the device then | |
275 | complete the DMA operation immediately. Otherwise defer | |
276 | until the scsi layer has completed. */ | |
277 | if (to_device || s->dma_left != 0 || s->ti_size == 0) { | |
278 | return; | |
4d611c9a | 279 | } |
a917d384 | 280 | } |
ad3376cc PB |
281 | |
282 | /* Partially filled a scsi buffer. Complete immediately. */ | |
283 | esp_dma_done(s); | |
4d611c9a PB |
284 | } |
285 | ||
9c7e23fc | 286 | void esp_command_complete(SCSIRequest *req, uint32_t status, |
01e95455 | 287 | size_t resid) |
2e5d83bb | 288 | { |
e6810db8 | 289 | ESPState *s = req->hba_private; |
2e5d83bb | 290 | |
bf4b9889 | 291 | trace_esp_command_complete(); |
c6df7102 | 292 | if (s->ti_size != 0) { |
bf4b9889 | 293 | trace_esp_command_complete_unexpected(); |
c6df7102 PB |
294 | } |
295 | s->ti_size = 0; | |
296 | s->dma_left = 0; | |
297 | s->async_len = 0; | |
aba1f023 | 298 | if (status) { |
bf4b9889 | 299 | trace_esp_command_complete_fail(); |
c6df7102 | 300 | } |
aba1f023 | 301 | s->status = status; |
c6df7102 PB |
302 | s->rregs[ESP_RSTAT] = STAT_ST; |
303 | esp_dma_done(s); | |
304 | if (s->current_req) { | |
305 | scsi_req_unref(s->current_req); | |
306 | s->current_req = NULL; | |
307 | s->current_dev = NULL; | |
308 | } | |
309 | } | |
310 | ||
9c7e23fc | 311 | void esp_transfer_data(SCSIRequest *req, uint32_t len) |
c6df7102 | 312 | { |
e6810db8 | 313 | ESPState *s = req->hba_private; |
c6df7102 | 314 | |
bf4b9889 | 315 | trace_esp_transfer_data(s->dma_left, s->ti_size); |
aba1f023 | 316 | s->async_len = len; |
c6df7102 PB |
317 | s->async_buf = scsi_req_get_buf(req); |
318 | if (s->dma_left) { | |
319 | esp_do_dma(s); | |
320 | } else if (s->dma_counter != 0 && s->ti_size <= 0) { | |
321 | /* If this was the last part of a DMA transfer then the | |
322 | completion interrupt is deferred to here. */ | |
a917d384 | 323 | esp_dma_done(s); |
4d611c9a | 324 | } |
2e5d83bb PB |
325 | } |
326 | ||
2f275b8f FB |
327 | static void handle_ti(ESPState *s) |
328 | { | |
4d611c9a | 329 | uint32_t dmalen, minlen; |
2f275b8f | 330 | |
7246e160 HP |
331 | if (s->dma && !s->dma_enabled) { |
332 | s->dma_cb = handle_ti; | |
333 | return; | |
334 | } | |
335 | ||
9ea73f8b PB |
336 | dmalen = s->rregs[ESP_TCLO]; |
337 | dmalen |= s->rregs[ESP_TCMID] << 8; | |
338 | dmalen |= s->rregs[ESP_TCHI] << 16; | |
db59203d PB |
339 | if (dmalen==0) { |
340 | dmalen=0x10000; | |
341 | } | |
6787f5fa | 342 | s->dma_counter = dmalen; |
db59203d | 343 | |
9f149aa9 PB |
344 | if (s->do_cmd) |
345 | minlen = (dmalen < 32) ? dmalen : 32; | |
67e999be FB |
346 | else if (s->ti_size < 0) |
347 | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; | |
9f149aa9 PB |
348 | else |
349 | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; | |
bf4b9889 | 350 | trace_esp_handle_ti(minlen); |
4f6200f0 | 351 | if (s->dma) { |
4d611c9a | 352 | s->dma_left = minlen; |
5ad6bb97 | 353 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 354 | esp_do_dma(s); |
9f149aa9 | 355 | } else if (s->do_cmd) { |
bf4b9889 | 356 | trace_esp_handle_ti_cmd(s->cmdlen); |
9f149aa9 PB |
357 | s->ti_size = 0; |
358 | s->cmdlen = 0; | |
359 | s->do_cmd = 0; | |
360 | do_cmd(s, s->cmdbuf); | |
361 | return; | |
362 | } | |
2f275b8f FB |
363 | } |
364 | ||
9c7e23fc | 365 | void esp_hard_reset(ESPState *s) |
6f7e9aec | 366 | { |
5aca8c3b BS |
367 | memset(s->rregs, 0, ESP_REGS); |
368 | memset(s->wregs, 0, ESP_REGS); | |
c9cf45c1 | 369 | s->tchi_written = 0; |
4e9aec74 PB |
370 | s->ti_size = 0; |
371 | s->ti_rptr = 0; | |
372 | s->ti_wptr = 0; | |
4e9aec74 | 373 | s->dma = 0; |
9f149aa9 | 374 | s->do_cmd = 0; |
73d74342 | 375 | s->dma_cb = NULL; |
8dea1dd4 BS |
376 | |
377 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
378 | } |
379 | ||
a391fdbc | 380 | static void esp_soft_reset(ESPState *s) |
85948643 | 381 | { |
85948643 | 382 | qemu_irq_lower(s->irq); |
a391fdbc | 383 | esp_hard_reset(s); |
85948643 BS |
384 | } |
385 | ||
a391fdbc | 386 | static void parent_esp_reset(ESPState *s, int irq, int level) |
2d069bab | 387 | { |
85948643 | 388 | if (level) { |
a391fdbc | 389 | esp_soft_reset(s); |
85948643 | 390 | } |
2d069bab BS |
391 | } |
392 | ||
9c7e23fc | 393 | uint64_t esp_reg_read(ESPState *s, uint32_t saddr) |
73d74342 | 394 | { |
a391fdbc | 395 | uint32_t old_val; |
73d74342 | 396 | |
bf4b9889 | 397 | trace_esp_mem_readb(saddr, s->rregs[saddr]); |
6f7e9aec | 398 | switch (saddr) { |
5ad6bb97 | 399 | case ESP_FIFO: |
f930d07e BS |
400 | if (s->ti_size > 0) { |
401 | s->ti_size--; | |
5ad6bb97 | 402 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
8dea1dd4 | 403 | /* Data out. */ |
3af4e9aa HP |
404 | qemu_log_mask(LOG_UNIMP, |
405 | "esp: PIO data read not implemented\n"); | |
5ad6bb97 | 406 | s->rregs[ESP_FIFO] = 0; |
2e5d83bb | 407 | } else { |
5ad6bb97 | 408 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
2e5d83bb | 409 | } |
c73f96fd | 410 | esp_raise_irq(s); |
f930d07e BS |
411 | } |
412 | if (s->ti_size == 0) { | |
4f6200f0 FB |
413 | s->ti_rptr = 0; |
414 | s->ti_wptr = 0; | |
415 | } | |
f930d07e | 416 | break; |
5ad6bb97 | 417 | case ESP_RINTR: |
2814df28 BS |
418 | /* Clear sequence step, interrupt register and all status bits |
419 | except TC */ | |
420 | old_val = s->rregs[ESP_RINTR]; | |
421 | s->rregs[ESP_RINTR] = 0; | |
422 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
423 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
c73f96fd | 424 | esp_lower_irq(s); |
2814df28 BS |
425 | |
426 | return old_val; | |
c9cf45c1 HR |
427 | case ESP_TCHI: |
428 | /* Return the unique id if the value has never been written */ | |
429 | if (!s->tchi_written) { | |
430 | return s->chip_id; | |
431 | } | |
6f7e9aec | 432 | default: |
f930d07e | 433 | break; |
6f7e9aec | 434 | } |
2f275b8f | 435 | return s->rregs[saddr]; |
6f7e9aec FB |
436 | } |
437 | ||
9c7e23fc | 438 | void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) |
6f7e9aec | 439 | { |
bf4b9889 | 440 | trace_esp_mem_writeb(saddr, s->wregs[saddr], val); |
6f7e9aec | 441 | switch (saddr) { |
c9cf45c1 HR |
442 | case ESP_TCHI: |
443 | s->tchi_written = true; | |
444 | /* fall through */ | |
5ad6bb97 BS |
445 | case ESP_TCLO: |
446 | case ESP_TCMID: | |
447 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 448 | break; |
5ad6bb97 | 449 | case ESP_FIFO: |
9f149aa9 PB |
450 | if (s->do_cmd) { |
451 | s->cmdbuf[s->cmdlen++] = val & 0xff; | |
8dea1dd4 | 452 | } else if (s->ti_size == TI_BUFSZ - 1) { |
3af4e9aa | 453 | trace_esp_error_fifo_overrun(); |
2e5d83bb PB |
454 | } else { |
455 | s->ti_size++; | |
456 | s->ti_buf[s->ti_wptr++] = val & 0xff; | |
457 | } | |
f930d07e | 458 | break; |
5ad6bb97 | 459 | case ESP_CMD: |
4f6200f0 | 460 | s->rregs[saddr] = val; |
5ad6bb97 | 461 | if (val & CMD_DMA) { |
f930d07e | 462 | s->dma = 1; |
6787f5fa | 463 | /* Reload DMA counter. */ |
5ad6bb97 BS |
464 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
465 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; | |
9ea73f8b | 466 | s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI]; |
f930d07e BS |
467 | } else { |
468 | s->dma = 0; | |
469 | } | |
5ad6bb97 BS |
470 | switch(val & CMD_CMD) { |
471 | case CMD_NOP: | |
bf4b9889 | 472 | trace_esp_mem_writeb_cmd_nop(val); |
f930d07e | 473 | break; |
5ad6bb97 | 474 | case CMD_FLUSH: |
bf4b9889 | 475 | trace_esp_mem_writeb_cmd_flush(val); |
9e61bde5 | 476 | //s->ti_size = 0; |
5ad6bb97 BS |
477 | s->rregs[ESP_RINTR] = INTR_FC; |
478 | s->rregs[ESP_RSEQ] = 0; | |
a214c598 | 479 | s->rregs[ESP_RFLAGS] = 0; |
f930d07e | 480 | break; |
5ad6bb97 | 481 | case CMD_RESET: |
bf4b9889 | 482 | trace_esp_mem_writeb_cmd_reset(val); |
a391fdbc | 483 | esp_soft_reset(s); |
f930d07e | 484 | break; |
5ad6bb97 | 485 | case CMD_BUSRESET: |
bf4b9889 | 486 | trace_esp_mem_writeb_cmd_bus_reset(val); |
5ad6bb97 BS |
487 | s->rregs[ESP_RINTR] = INTR_RST; |
488 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { | |
c73f96fd | 489 | esp_raise_irq(s); |
9e61bde5 | 490 | } |
f930d07e | 491 | break; |
5ad6bb97 | 492 | case CMD_TI: |
f930d07e BS |
493 | handle_ti(s); |
494 | break; | |
5ad6bb97 | 495 | case CMD_ICCS: |
bf4b9889 | 496 | trace_esp_mem_writeb_cmd_iccs(val); |
f930d07e | 497 | write_response(s); |
4bf5801d BS |
498 | s->rregs[ESP_RINTR] = INTR_FC; |
499 | s->rregs[ESP_RSTAT] |= STAT_MI; | |
f930d07e | 500 | break; |
5ad6bb97 | 501 | case CMD_MSGACC: |
bf4b9889 | 502 | trace_esp_mem_writeb_cmd_msgacc(val); |
5ad6bb97 BS |
503 | s->rregs[ESP_RINTR] = INTR_DC; |
504 | s->rregs[ESP_RSEQ] = 0; | |
4e2a68c1 AT |
505 | s->rregs[ESP_RFLAGS] = 0; |
506 | esp_raise_irq(s); | |
f930d07e | 507 | break; |
0fd0eb21 | 508 | case CMD_PAD: |
bf4b9889 | 509 | trace_esp_mem_writeb_cmd_pad(val); |
0fd0eb21 BS |
510 | s->rregs[ESP_RSTAT] = STAT_TC; |
511 | s->rregs[ESP_RINTR] = INTR_FC; | |
512 | s->rregs[ESP_RSEQ] = 0; | |
513 | break; | |
5ad6bb97 | 514 | case CMD_SATN: |
bf4b9889 | 515 | trace_esp_mem_writeb_cmd_satn(val); |
f930d07e | 516 | break; |
6915bff1 HP |
517 | case CMD_RSTATN: |
518 | trace_esp_mem_writeb_cmd_rstatn(val); | |
519 | break; | |
5e1e0a3b | 520 | case CMD_SEL: |
bf4b9889 | 521 | trace_esp_mem_writeb_cmd_sel(val); |
f2818f22 | 522 | handle_s_without_atn(s); |
5e1e0a3b | 523 | break; |
5ad6bb97 | 524 | case CMD_SELATN: |
bf4b9889 | 525 | trace_esp_mem_writeb_cmd_selatn(val); |
f930d07e BS |
526 | handle_satn(s); |
527 | break; | |
5ad6bb97 | 528 | case CMD_SELATNS: |
bf4b9889 | 529 | trace_esp_mem_writeb_cmd_selatns(val); |
f930d07e BS |
530 | handle_satn_stop(s); |
531 | break; | |
5ad6bb97 | 532 | case CMD_ENSEL: |
bf4b9889 | 533 | trace_esp_mem_writeb_cmd_ensel(val); |
e3926838 | 534 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 535 | break; |
6fe84c18 HP |
536 | case CMD_DISSEL: |
537 | trace_esp_mem_writeb_cmd_dissel(val); | |
538 | s->rregs[ESP_RINTR] = 0; | |
539 | esp_raise_irq(s); | |
540 | break; | |
f930d07e | 541 | default: |
3af4e9aa | 542 | trace_esp_error_unhandled_command(val); |
f930d07e BS |
543 | break; |
544 | } | |
545 | break; | |
5ad6bb97 | 546 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 547 | break; |
5ad6bb97 | 548 | case ESP_CFG1: |
9ea73f8b PB |
549 | case ESP_CFG2: case ESP_CFG3: |
550 | case ESP_RES3: case ESP_RES4: | |
4f6200f0 FB |
551 | s->rregs[saddr] = val; |
552 | break; | |
5ad6bb97 | 553 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 554 | break; |
6f7e9aec | 555 | default: |
3af4e9aa | 556 | trace_esp_error_invalid_write(val, saddr); |
8dea1dd4 | 557 | return; |
6f7e9aec | 558 | } |
2f275b8f | 559 | s->wregs[saddr] = val; |
6f7e9aec FB |
560 | } |
561 | ||
a8170e5e | 562 | static bool esp_mem_accepts(void *opaque, hwaddr addr, |
67bb5314 AK |
563 | unsigned size, bool is_write) |
564 | { | |
565 | return (size == 1) || (is_write && size == 4); | |
566 | } | |
6f7e9aec | 567 | |
9c7e23fc | 568 | const VMStateDescription vmstate_esp = { |
cc9952f3 BS |
569 | .name ="esp", |
570 | .version_id = 3, | |
571 | .minimum_version_id = 3, | |
35d08458 | 572 | .fields = (VMStateField[]) { |
cc9952f3 BS |
573 | VMSTATE_BUFFER(rregs, ESPState), |
574 | VMSTATE_BUFFER(wregs, ESPState), | |
575 | VMSTATE_INT32(ti_size, ESPState), | |
576 | VMSTATE_UINT32(ti_rptr, ESPState), | |
577 | VMSTATE_UINT32(ti_wptr, ESPState), | |
578 | VMSTATE_BUFFER(ti_buf, ESPState), | |
3944966d | 579 | VMSTATE_UINT32(status, ESPState), |
cc9952f3 BS |
580 | VMSTATE_UINT32(dma, ESPState), |
581 | VMSTATE_BUFFER(cmdbuf, ESPState), | |
582 | VMSTATE_UINT32(cmdlen, ESPState), | |
583 | VMSTATE_UINT32(do_cmd, ESPState), | |
584 | VMSTATE_UINT32(dma_left, ESPState), | |
585 | VMSTATE_END_OF_LIST() | |
586 | } | |
587 | }; | |
6f7e9aec | 588 | |
a71c7ec5 HT |
589 | #define TYPE_ESP "esp" |
590 | #define ESP(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP) | |
591 | ||
a391fdbc | 592 | typedef struct { |
a71c7ec5 HT |
593 | /*< private >*/ |
594 | SysBusDevice parent_obj; | |
595 | /*< public >*/ | |
596 | ||
a391fdbc HP |
597 | MemoryRegion iomem; |
598 | uint32_t it_shift; | |
599 | ESPState esp; | |
600 | } SysBusESPState; | |
601 | ||
a8170e5e | 602 | static void sysbus_esp_mem_write(void *opaque, hwaddr addr, |
a391fdbc HP |
603 | uint64_t val, unsigned int size) |
604 | { | |
605 | SysBusESPState *sysbus = opaque; | |
606 | uint32_t saddr; | |
607 | ||
608 | saddr = addr >> sysbus->it_shift; | |
609 | esp_reg_write(&sysbus->esp, saddr, val); | |
610 | } | |
611 | ||
a8170e5e | 612 | static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, |
a391fdbc HP |
613 | unsigned int size) |
614 | { | |
615 | SysBusESPState *sysbus = opaque; | |
616 | uint32_t saddr; | |
617 | ||
618 | saddr = addr >> sysbus->it_shift; | |
619 | return esp_reg_read(&sysbus->esp, saddr); | |
620 | } | |
621 | ||
622 | static const MemoryRegionOps sysbus_esp_mem_ops = { | |
623 | .read = sysbus_esp_mem_read, | |
624 | .write = sysbus_esp_mem_write, | |
625 | .endianness = DEVICE_NATIVE_ENDIAN, | |
626 | .valid.accepts = esp_mem_accepts, | |
627 | }; | |
628 | ||
a8170e5e | 629 | void esp_init(hwaddr espaddr, int it_shift, |
ff9868ec BS |
630 | ESPDMAMemoryReadWriteFunc dma_memory_read, |
631 | ESPDMAMemoryReadWriteFunc dma_memory_write, | |
73d74342 BS |
632 | void *dma_opaque, qemu_irq irq, qemu_irq *reset, |
633 | qemu_irq *dma_enable) | |
6f7e9aec | 634 | { |
cfb9de9c PB |
635 | DeviceState *dev; |
636 | SysBusDevice *s; | |
a391fdbc | 637 | SysBusESPState *sysbus; |
ee6847d1 | 638 | ESPState *esp; |
cfb9de9c | 639 | |
a71c7ec5 HT |
640 | dev = qdev_create(NULL, TYPE_ESP); |
641 | sysbus = ESP(dev); | |
a391fdbc | 642 | esp = &sysbus->esp; |
ee6847d1 GH |
643 | esp->dma_memory_read = dma_memory_read; |
644 | esp->dma_memory_write = dma_memory_write; | |
645 | esp->dma_opaque = dma_opaque; | |
a391fdbc | 646 | sysbus->it_shift = it_shift; |
73d74342 BS |
647 | /* XXX for now until rc4030 has been changed to use DMA enable signal */ |
648 | esp->dma_enabled = 1; | |
e23a1b33 | 649 | qdev_init_nofail(dev); |
1356b98d | 650 | s = SYS_BUS_DEVICE(dev); |
cfb9de9c PB |
651 | sysbus_connect_irq(s, 0, irq); |
652 | sysbus_mmio_map(s, 0, espaddr); | |
74ff8d90 | 653 | *reset = qdev_get_gpio_in(dev, 0); |
73d74342 | 654 | *dma_enable = qdev_get_gpio_in(dev, 1); |
cfb9de9c | 655 | } |
6f7e9aec | 656 | |
afd4030c PB |
657 | static const struct SCSIBusInfo esp_scsi_info = { |
658 | .tcq = false, | |
7e0380b9 PB |
659 | .max_target = ESP_MAX_DEVS, |
660 | .max_lun = 7, | |
afd4030c | 661 | |
c6df7102 | 662 | .transfer_data = esp_transfer_data, |
94d3f98a PB |
663 | .complete = esp_command_complete, |
664 | .cancel = esp_request_cancelled | |
cfdc1bb0 PB |
665 | }; |
666 | ||
a391fdbc | 667 | static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) |
cfb9de9c | 668 | { |
a71c7ec5 | 669 | SysBusESPState *sysbus = ESP(opaque); |
a391fdbc HP |
670 | ESPState *s = &sysbus->esp; |
671 | ||
672 | switch (irq) { | |
673 | case 0: | |
674 | parent_esp_reset(s, irq, level); | |
675 | break; | |
676 | case 1: | |
677 | esp_dma_enable(opaque, irq, level); | |
678 | break; | |
679 | } | |
680 | } | |
681 | ||
b09318ca | 682 | static void sysbus_esp_realize(DeviceState *dev, Error **errp) |
a391fdbc | 683 | { |
b09318ca | 684 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
a71c7ec5 | 685 | SysBusESPState *sysbus = ESP(dev); |
a391fdbc | 686 | ESPState *s = &sysbus->esp; |
caad4eb3 | 687 | Error *err = NULL; |
6f7e9aec | 688 | |
b09318ca | 689 | sysbus_init_irq(sbd, &s->irq); |
a391fdbc | 690 | assert(sysbus->it_shift != -1); |
6f7e9aec | 691 | |
d32e4b3d | 692 | s->chip_id = TCHI_FAS100A; |
29776739 PB |
693 | memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, |
694 | sysbus, "esp", ESP_REGS << sysbus->it_shift); | |
b09318ca | 695 | sysbus_init_mmio(sbd, &sysbus->iomem); |
6f7e9aec | 696 | |
b09318ca | 697 | qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); |
2d069bab | 698 | |
b1187b51 | 699 | scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); |
caad4eb3 AF |
700 | scsi_bus_legacy_handle_cmdline(&s->bus, &err); |
701 | if (err != NULL) { | |
702 | error_propagate(errp, err); | |
b09318ca HT |
703 | return; |
704 | } | |
67e999be | 705 | } |
cfb9de9c | 706 | |
a391fdbc HP |
707 | static void sysbus_esp_hard_reset(DeviceState *dev) |
708 | { | |
a71c7ec5 | 709 | SysBusESPState *sysbus = ESP(dev); |
a391fdbc HP |
710 | esp_hard_reset(&sysbus->esp); |
711 | } | |
712 | ||
713 | static const VMStateDescription vmstate_sysbus_esp_scsi = { | |
714 | .name = "sysbusespscsi", | |
715 | .version_id = 0, | |
716 | .minimum_version_id = 0, | |
a391fdbc HP |
717 | .fields = (VMStateField[]) { |
718 | VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), | |
719 | VMSTATE_END_OF_LIST() | |
720 | } | |
999e12bb AL |
721 | }; |
722 | ||
a391fdbc | 723 | static void sysbus_esp_class_init(ObjectClass *klass, void *data) |
999e12bb | 724 | { |
39bffca2 | 725 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 726 | |
b09318ca | 727 | dc->realize = sysbus_esp_realize; |
a391fdbc HP |
728 | dc->reset = sysbus_esp_hard_reset; |
729 | dc->vmsd = &vmstate_sysbus_esp_scsi; | |
125ee0ed | 730 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
999e12bb AL |
731 | } |
732 | ||
1f077308 | 733 | static const TypeInfo sysbus_esp_info = { |
a71c7ec5 | 734 | .name = TYPE_ESP, |
39bffca2 | 735 | .parent = TYPE_SYS_BUS_DEVICE, |
a391fdbc HP |
736 | .instance_size = sizeof(SysBusESPState), |
737 | .class_init = sysbus_esp_class_init, | |
63235df8 BS |
738 | }; |
739 | ||
83f7d43a | 740 | static void esp_register_types(void) |
cfb9de9c | 741 | { |
a391fdbc | 742 | type_register_static(&sysbus_esp_info); |
cfb9de9c PB |
743 | } |
744 | ||
83f7d43a | 745 | type_init(esp_register_types) |