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Commit | Line | Data |
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6f7e9aec | 1 | /* |
67e999be | 2 | * QEMU ESP/NCR53C9x emulation |
5fafdf24 | 3 | * |
4e9aec74 | 4 | * Copyright (c) 2005-2006 Fabrice Bellard |
fabaaf1d | 5 | * Copyright (c) 2012 Herve Poussineau |
5fafdf24 | 6 | * |
6f7e9aec FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
5d20fa6b | 25 | |
a4ab4792 | 26 | #include "qemu/osdep.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
64552b6b | 29 | #include "hw/irq.h" |
0d09e41a | 30 | #include "hw/scsi/esp.h" |
bf4b9889 | 31 | #include "trace.h" |
1de7afc9 | 32 | #include "qemu/log.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
6f7e9aec | 34 | |
67e999be | 35 | /* |
5ad6bb97 BS |
36 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), |
37 | * also produced as NCR89C100. See | |
67e999be FB |
38 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt |
39 | * and | |
40 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt | |
74d71ea1 LV |
41 | * |
42 | * On Macintosh Quadra it is a NCR53C96. | |
67e999be FB |
43 | */ |
44 | ||
c73f96fd BS |
45 | static void esp_raise_irq(ESPState *s) |
46 | { | |
47 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { | |
48 | s->rregs[ESP_RSTAT] |= STAT_INT; | |
49 | qemu_irq_raise(s->irq); | |
bf4b9889 | 50 | trace_esp_raise_irq(); |
c73f96fd BS |
51 | } |
52 | } | |
53 | ||
54 | static void esp_lower_irq(ESPState *s) | |
55 | { | |
56 | if (s->rregs[ESP_RSTAT] & STAT_INT) { | |
57 | s->rregs[ESP_RSTAT] &= ~STAT_INT; | |
58 | qemu_irq_lower(s->irq); | |
bf4b9889 | 59 | trace_esp_lower_irq(); |
c73f96fd BS |
60 | } |
61 | } | |
62 | ||
74d71ea1 LV |
63 | static void esp_raise_drq(ESPState *s) |
64 | { | |
65 | qemu_irq_raise(s->irq_data); | |
960ebfd9 | 66 | trace_esp_raise_drq(); |
74d71ea1 LV |
67 | } |
68 | ||
69 | static void esp_lower_drq(ESPState *s) | |
70 | { | |
71 | qemu_irq_lower(s->irq_data); | |
960ebfd9 | 72 | trace_esp_lower_drq(); |
74d71ea1 LV |
73 | } |
74 | ||
9c7e23fc | 75 | void esp_dma_enable(ESPState *s, int irq, int level) |
73d74342 | 76 | { |
73d74342 BS |
77 | if (level) { |
78 | s->dma_enabled = 1; | |
bf4b9889 | 79 | trace_esp_dma_enable(); |
73d74342 BS |
80 | if (s->dma_cb) { |
81 | s->dma_cb(s); | |
82 | s->dma_cb = NULL; | |
83 | } | |
84 | } else { | |
bf4b9889 | 85 | trace_esp_dma_disable(); |
73d74342 BS |
86 | s->dma_enabled = 0; |
87 | } | |
88 | } | |
89 | ||
9c7e23fc | 90 | void esp_request_cancelled(SCSIRequest *req) |
94d3f98a | 91 | { |
e6810db8 | 92 | ESPState *s = req->hba_private; |
94d3f98a PB |
93 | |
94 | if (req == s->current_req) { | |
95 | scsi_req_unref(s->current_req); | |
96 | s->current_req = NULL; | |
97 | s->current_dev = NULL; | |
98 | } | |
99 | } | |
100 | ||
e5455b8c | 101 | static void esp_fifo_push(Fifo8 *fifo, uint8_t val) |
042879fc | 102 | { |
e5455b8c | 103 | if (fifo8_num_used(fifo) == fifo->capacity) { |
042879fc MCA |
104 | trace_esp_error_fifo_overrun(); |
105 | return; | |
106 | } | |
107 | ||
e5455b8c | 108 | fifo8_push(fifo, val); |
042879fc | 109 | } |
042879fc | 110 | |
c5fef911 | 111 | static uint8_t esp_fifo_pop(Fifo8 *fifo) |
023666da | 112 | { |
c5fef911 | 113 | if (fifo8_is_empty(fifo)) { |
023666da MCA |
114 | return 0; |
115 | } | |
116 | ||
c5fef911 | 117 | return fifo8_pop(fifo); |
023666da MCA |
118 | } |
119 | ||
7b320a8e MCA |
120 | static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) |
121 | { | |
122 | const uint8_t *buf; | |
123 | uint32_t n; | |
124 | ||
125 | if (maxlen == 0) { | |
126 | return 0; | |
127 | } | |
128 | ||
129 | buf = fifo8_pop_buf(fifo, maxlen, &n); | |
130 | if (dest) { | |
131 | memcpy(dest, buf, n); | |
132 | } | |
133 | ||
134 | return n; | |
135 | } | |
136 | ||
c47b5835 MCA |
137 | static uint32_t esp_get_tc(ESPState *s) |
138 | { | |
139 | uint32_t dmalen; | |
140 | ||
141 | dmalen = s->rregs[ESP_TCLO]; | |
142 | dmalen |= s->rregs[ESP_TCMID] << 8; | |
143 | dmalen |= s->rregs[ESP_TCHI] << 16; | |
144 | ||
145 | return dmalen; | |
146 | } | |
147 | ||
148 | static void esp_set_tc(ESPState *s, uint32_t dmalen) | |
149 | { | |
150 | s->rregs[ESP_TCLO] = dmalen; | |
151 | s->rregs[ESP_TCMID] = dmalen >> 8; | |
152 | s->rregs[ESP_TCHI] = dmalen >> 16; | |
153 | } | |
154 | ||
c04ed569 MCA |
155 | static uint32_t esp_get_stc(ESPState *s) |
156 | { | |
157 | uint32_t dmalen; | |
158 | ||
159 | dmalen = s->wregs[ESP_TCLO]; | |
160 | dmalen |= s->wregs[ESP_TCMID] << 8; | |
161 | dmalen |= s->wregs[ESP_TCHI] << 16; | |
162 | ||
163 | return dmalen; | |
164 | } | |
165 | ||
761bef75 MCA |
166 | static uint8_t esp_pdma_read(ESPState *s) |
167 | { | |
8da90e81 MCA |
168 | uint8_t val; |
169 | ||
43d02df3 | 170 | if (s->do_cmd) { |
c5fef911 | 171 | val = esp_fifo_pop(&s->cmdfifo); |
43d02df3 | 172 | } else { |
c5fef911 | 173 | val = esp_fifo_pop(&s->fifo); |
6e3fafa8 | 174 | } |
8da90e81 | 175 | |
8da90e81 | 176 | return val; |
761bef75 MCA |
177 | } |
178 | ||
179 | static void esp_pdma_write(ESPState *s, uint8_t val) | |
180 | { | |
8da90e81 MCA |
181 | uint32_t dmalen = esp_get_tc(s); |
182 | ||
3c421400 | 183 | if (dmalen == 0) { |
8da90e81 MCA |
184 | return; |
185 | } | |
186 | ||
43d02df3 | 187 | if (s->do_cmd) { |
e5455b8c | 188 | esp_fifo_push(&s->cmdfifo, val); |
43d02df3 | 189 | } else { |
e5455b8c | 190 | esp_fifo_push(&s->fifo, val); |
6e3fafa8 | 191 | } |
8da90e81 | 192 | |
8da90e81 MCA |
193 | dmalen--; |
194 | esp_set_tc(s, dmalen); | |
761bef75 MCA |
195 | } |
196 | ||
c7bce09c | 197 | static int esp_select(ESPState *s) |
6130b188 LV |
198 | { |
199 | int target; | |
200 | ||
201 | target = s->wregs[ESP_WBUSID] & BUSID_DID; | |
202 | ||
203 | s->ti_size = 0; | |
042879fc | 204 | fifo8_reset(&s->fifo); |
6130b188 LV |
205 | |
206 | if (s->current_req) { | |
207 | /* Started a new command before the old one finished. Cancel it. */ | |
208 | scsi_req_cancel(s->current_req); | |
209 | s->async_len = 0; | |
210 | } | |
211 | ||
212 | s->current_dev = scsi_device_find(&s->bus, 0, target, 0); | |
213 | if (!s->current_dev) { | |
214 | /* No such drive */ | |
215 | s->rregs[ESP_RSTAT] = 0; | |
cf47a41e | 216 | s->rregs[ESP_RINTR] |= INTR_DC; |
6130b188 LV |
217 | s->rregs[ESP_RSEQ] = SEQ_0; |
218 | esp_raise_irq(s); | |
219 | return -1; | |
220 | } | |
4e78f3bf MCA |
221 | |
222 | /* | |
223 | * Note that we deliberately don't raise the IRQ here: this will be done | |
224 | * either in do_busid_cmd() for DATA OUT transfers or by the deferred | |
225 | * IRQ mechanism in esp_transfer_data() for DATA IN transfers | |
226 | */ | |
227 | s->rregs[ESP_RINTR] |= INTR_FC; | |
228 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
6130b188 LV |
229 | return 0; |
230 | } | |
231 | ||
20c8d2ed | 232 | static uint32_t get_cmd(ESPState *s, uint32_t maxlen) |
2f275b8f | 233 | { |
023666da | 234 | uint8_t buf[ESP_CMDFIFO_SZ]; |
042879fc | 235 | uint32_t dmalen, n; |
2f275b8f FB |
236 | int target; |
237 | ||
8dea1dd4 | 238 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
4f6200f0 | 239 | if (s->dma) { |
20c8d2ed MCA |
240 | dmalen = MIN(esp_get_tc(s), maxlen); |
241 | if (dmalen == 0) { | |
6c1fef6b PP |
242 | return 0; |
243 | } | |
74d71ea1 LV |
244 | if (s->dma_memory_read) { |
245 | s->dma_memory_read(s->dma_opaque, buf, dmalen); | |
fbc6510e | 246 | dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); |
023666da | 247 | fifo8_push_all(&s->cmdfifo, buf, dmalen); |
74d71ea1 | 248 | } else { |
49691315 | 249 | if (esp_select(s) < 0) { |
023666da | 250 | fifo8_reset(&s->cmdfifo); |
49691315 MCA |
251 | return -1; |
252 | } | |
74d71ea1 | 253 | esp_raise_drq(s); |
023666da | 254 | fifo8_reset(&s->cmdfifo); |
74d71ea1 LV |
255 | return 0; |
256 | } | |
4f6200f0 | 257 | } else { |
023666da | 258 | dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); |
20c8d2ed | 259 | if (dmalen == 0) { |
d3cdc491 PP |
260 | return 0; |
261 | } | |
7b320a8e MCA |
262 | n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); |
263 | if (n >= 3) { | |
20c8d2ed MCA |
264 | buf[0] = buf[2] >> 5; |
265 | } | |
fbc6510e | 266 | n = MIN(fifo8_num_free(&s->cmdfifo), n); |
7b320a8e | 267 | fifo8_push_all(&s->cmdfifo, buf, n); |
4f6200f0 | 268 | } |
bf4b9889 | 269 | trace_esp_get_cmd(dmalen, target); |
2e5d83bb | 270 | |
c7bce09c | 271 | if (esp_select(s) < 0) { |
023666da | 272 | fifo8_reset(&s->cmdfifo); |
49691315 | 273 | return -1; |
2f275b8f | 274 | } |
9f149aa9 PB |
275 | return dmalen; |
276 | } | |
277 | ||
023666da | 278 | static void do_busid_cmd(ESPState *s, uint8_t busid) |
9f149aa9 | 279 | { |
7b320a8e | 280 | uint32_t cmdlen; |
9f149aa9 PB |
281 | int32_t datalen; |
282 | int lun; | |
f48a7a6e | 283 | SCSIDevice *current_lun; |
7b320a8e | 284 | uint8_t buf[ESP_CMDFIFO_SZ]; |
9f149aa9 | 285 | |
bf4b9889 | 286 | trace_esp_do_busid_cmd(busid); |
f2818f22 | 287 | lun = busid & 7; |
023666da | 288 | cmdlen = fifo8_num_used(&s->cmdfifo); |
99545751 MCA |
289 | if (!cmdlen || !s->current_dev) { |
290 | return; | |
291 | } | |
7b320a8e | 292 | esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); |
023666da | 293 | |
0d3545e7 | 294 | current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); |
e6810db8 | 295 | s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); |
c39ce112 | 296 | datalen = scsi_req_enqueue(s->current_req); |
67e999be | 297 | s->ti_size = datalen; |
023666da | 298 | fifo8_reset(&s->cmdfifo); |
67e999be | 299 | if (datalen != 0) { |
c73f96fd | 300 | s->rregs[ESP_RSTAT] = STAT_TC; |
4e78f3bf | 301 | s->rregs[ESP_RSEQ] = SEQ_CD; |
1b9e48a5 | 302 | s->ti_cmd = 0; |
6cc88d6b | 303 | esp_set_tc(s, 0); |
2e5d83bb | 304 | if (datalen > 0) { |
4e78f3bf MCA |
305 | /* |
306 | * Switch to DATA IN phase but wait until initial data xfer is | |
307 | * complete before raising the command completion interrupt | |
308 | */ | |
309 | s->data_in_ready = false; | |
5ad6bb97 | 310 | s->rregs[ESP_RSTAT] |= STAT_DI; |
2e5d83bb | 311 | } else { |
5ad6bb97 | 312 | s->rregs[ESP_RSTAT] |= STAT_DO; |
4e78f3bf MCA |
313 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
314 | esp_raise_irq(s); | |
315 | esp_lower_drq(s); | |
b9788fc4 | 316 | } |
ad3376cc | 317 | scsi_req_continue(s->current_req); |
4e78f3bf | 318 | return; |
2f275b8f | 319 | } |
2f275b8f FB |
320 | } |
321 | ||
c959f218 | 322 | static void do_cmd(ESPState *s) |
f2818f22 | 323 | { |
fa7505c1 MCA |
324 | uint8_t busid = esp_fifo_pop(&s->cmdfifo); |
325 | int len; | |
023666da MCA |
326 | |
327 | s->cmdfifo_cdb_offset--; | |
f2818f22 | 328 | |
799d90d8 | 329 | /* Ignore extended messages for now */ |
023666da | 330 | if (s->cmdfifo_cdb_offset) { |
fa7505c1 MCA |
331 | len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); |
332 | esp_fifo_pop_buf(&s->cmdfifo, NULL, len); | |
023666da MCA |
333 | s->cmdfifo_cdb_offset = 0; |
334 | } | |
335 | ||
336 | do_busid_cmd(s, busid); | |
f2818f22 AT |
337 | } |
338 | ||
74d71ea1 LV |
339 | static void satn_pdma_cb(ESPState *s) |
340 | { | |
bb0bc7bb | 341 | s->do_cmd = 0; |
023666da MCA |
342 | if (!fifo8_is_empty(&s->cmdfifo)) { |
343 | s->cmdfifo_cdb_offset = 1; | |
c959f218 | 344 | do_cmd(s); |
74d71ea1 LV |
345 | } |
346 | } | |
347 | ||
9f149aa9 PB |
348 | static void handle_satn(ESPState *s) |
349 | { | |
49691315 MCA |
350 | int32_t cmdlen; |
351 | ||
1b26eaa1 | 352 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
353 | s->dma_cb = handle_satn; |
354 | return; | |
355 | } | |
74d71ea1 | 356 | s->pdma_cb = satn_pdma_cb; |
023666da | 357 | cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); |
49691315 | 358 | if (cmdlen > 0) { |
023666da | 359 | s->cmdfifo_cdb_offset = 1; |
c959f218 | 360 | do_cmd(s); |
49691315 | 361 | } else if (cmdlen == 0) { |
bb0bc7bb | 362 | s->do_cmd = 1; |
49691315 MCA |
363 | /* Target present, but no cmd yet - switch to command phase */ |
364 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
365 | s->rregs[ESP_RSTAT] = STAT_CD; | |
94d5c79d | 366 | } |
9f149aa9 PB |
367 | } |
368 | ||
74d71ea1 LV |
369 | static void s_without_satn_pdma_cb(ESPState *s) |
370 | { | |
023666da MCA |
371 | uint32_t len; |
372 | ||
bb0bc7bb | 373 | s->do_cmd = 0; |
023666da MCA |
374 | len = fifo8_num_used(&s->cmdfifo); |
375 | if (len) { | |
376 | s->cmdfifo_cdb_offset = 0; | |
377 | do_busid_cmd(s, 0); | |
74d71ea1 LV |
378 | } |
379 | } | |
380 | ||
f2818f22 AT |
381 | static void handle_s_without_atn(ESPState *s) |
382 | { | |
49691315 MCA |
383 | int32_t cmdlen; |
384 | ||
1b26eaa1 | 385 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
386 | s->dma_cb = handle_s_without_atn; |
387 | return; | |
388 | } | |
74d71ea1 | 389 | s->pdma_cb = s_without_satn_pdma_cb; |
023666da | 390 | cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); |
49691315 | 391 | if (cmdlen > 0) { |
023666da MCA |
392 | s->cmdfifo_cdb_offset = 0; |
393 | do_busid_cmd(s, 0); | |
49691315 | 394 | } else if (cmdlen == 0) { |
bb0bc7bb | 395 | s->do_cmd = 1; |
49691315 MCA |
396 | /* Target present, but no cmd yet - switch to command phase */ |
397 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
398 | s->rregs[ESP_RSTAT] = STAT_CD; | |
f2818f22 AT |
399 | } |
400 | } | |
401 | ||
74d71ea1 LV |
402 | static void satn_stop_pdma_cb(ESPState *s) |
403 | { | |
bb0bc7bb | 404 | s->do_cmd = 0; |
023666da MCA |
405 | if (!fifo8_is_empty(&s->cmdfifo)) { |
406 | trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); | |
74d71ea1 | 407 | s->do_cmd = 1; |
023666da | 408 | s->cmdfifo_cdb_offset = 1; |
74d71ea1 | 409 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
cf47a41e | 410 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
411 | s->rregs[ESP_RSEQ] = SEQ_CD; |
412 | esp_raise_irq(s); | |
413 | } | |
414 | } | |
415 | ||
9f149aa9 PB |
416 | static void handle_satn_stop(ESPState *s) |
417 | { | |
49691315 MCA |
418 | int32_t cmdlen; |
419 | ||
1b26eaa1 | 420 | if (s->dma && !s->dma_enabled) { |
73d74342 BS |
421 | s->dma_cb = handle_satn_stop; |
422 | return; | |
423 | } | |
c62c1fa0 | 424 | s->pdma_cb = satn_stop_pdma_cb; |
799d90d8 | 425 | cmdlen = get_cmd(s, 1); |
49691315 | 426 | if (cmdlen > 0) { |
023666da | 427 | trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); |
9f149aa9 | 428 | s->do_cmd = 1; |
023666da | 429 | s->cmdfifo_cdb_offset = 1; |
799d90d8 | 430 | s->rregs[ESP_RSTAT] = STAT_MO; |
cf47a41e | 431 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
799d90d8 | 432 | s->rregs[ESP_RSEQ] = SEQ_MO; |
c73f96fd | 433 | esp_raise_irq(s); |
49691315 | 434 | } else if (cmdlen == 0) { |
bb0bc7bb | 435 | s->do_cmd = 1; |
799d90d8 MCA |
436 | /* Target present, switch to message out phase */ |
437 | s->rregs[ESP_RSEQ] = SEQ_MO; | |
438 | s->rregs[ESP_RSTAT] = STAT_MO; | |
9f149aa9 PB |
439 | } |
440 | } | |
441 | ||
74d71ea1 LV |
442 | static void write_response_pdma_cb(ESPState *s) |
443 | { | |
444 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; | |
cf47a41e | 445 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
446 | s->rregs[ESP_RSEQ] = SEQ_CD; |
447 | esp_raise_irq(s); | |
448 | } | |
449 | ||
0fc5c15a | 450 | static void write_response(ESPState *s) |
2f275b8f | 451 | { |
e3922557 | 452 | uint8_t buf[2]; |
042879fc | 453 | |
bf4b9889 | 454 | trace_esp_write_response(s->status); |
042879fc | 455 | |
e3922557 MCA |
456 | buf[0] = s->status; |
457 | buf[1] = 0; | |
042879fc | 458 | |
4f6200f0 | 459 | if (s->dma) { |
74d71ea1 | 460 | if (s->dma_memory_write) { |
e3922557 | 461 | s->dma_memory_write(s->dma_opaque, buf, 2); |
74d71ea1 | 462 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
cf47a41e | 463 | s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; |
74d71ea1 LV |
464 | s->rregs[ESP_RSEQ] = SEQ_CD; |
465 | } else { | |
74d71ea1 LV |
466 | s->pdma_cb = write_response_pdma_cb; |
467 | esp_raise_drq(s); | |
468 | return; | |
469 | } | |
4f6200f0 | 470 | } else { |
e3922557 MCA |
471 | fifo8_reset(&s->fifo); |
472 | fifo8_push_all(&s->fifo, buf, 2); | |
5ad6bb97 | 473 | s->rregs[ESP_RFLAGS] = 2; |
4f6200f0 | 474 | } |
c73f96fd | 475 | esp_raise_irq(s); |
2f275b8f | 476 | } |
4f6200f0 | 477 | |
a917d384 PB |
478 | static void esp_dma_done(ESPState *s) |
479 | { | |
c73f96fd | 480 | s->rregs[ESP_RSTAT] |= STAT_TC; |
cf47a41e | 481 | s->rregs[ESP_RINTR] |= INTR_BS; |
5ad6bb97 BS |
482 | s->rregs[ESP_RSEQ] = 0; |
483 | s->rregs[ESP_RFLAGS] = 0; | |
c47b5835 | 484 | esp_set_tc(s, 0); |
c73f96fd | 485 | esp_raise_irq(s); |
a917d384 PB |
486 | } |
487 | ||
74d71ea1 LV |
488 | static void do_dma_pdma_cb(ESPState *s) |
489 | { | |
4ca2ba6f | 490 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
82141c8b | 491 | int len; |
042879fc | 492 | uint32_t n; |
6cc88d6b | 493 | |
74d71ea1 LV |
494 | if (s->do_cmd) { |
495 | s->ti_size = 0; | |
74d71ea1 | 496 | s->do_cmd = 0; |
c959f218 | 497 | do_cmd(s); |
82141c8b | 498 | esp_lower_drq(s); |
74d71ea1 LV |
499 | return; |
500 | } | |
82141c8b | 501 | |
0db89536 MCA |
502 | if (!s->current_req) { |
503 | return; | |
504 | } | |
505 | ||
82141c8b MCA |
506 | if (to_device) { |
507 | /* Copy FIFO data to device */ | |
7aa6baee MCA |
508 | len = MIN(s->async_len, ESP_FIFO_SZ); |
509 | len = MIN(len, fifo8_num_used(&s->fifo)); | |
7b320a8e | 510 | n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
7aa6baee MCA |
511 | s->async_buf += n; |
512 | s->async_len -= n; | |
513 | s->ti_size += n; | |
514 | ||
515 | if (n < len) { | |
516 | /* Unaligned accesses can cause FIFO wraparound */ | |
517 | len = len - n; | |
7b320a8e | 518 | n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
7aa6baee MCA |
519 | s->async_buf += n; |
520 | s->async_len -= n; | |
521 | s->ti_size += n; | |
522 | } | |
523 | ||
82141c8b MCA |
524 | if (s->async_len == 0) { |
525 | scsi_req_continue(s->current_req); | |
74d71ea1 LV |
526 | return; |
527 | } | |
74d71ea1 | 528 | |
82141c8b MCA |
529 | if (esp_get_tc(s) == 0) { |
530 | esp_lower_drq(s); | |
531 | esp_dma_done(s); | |
532 | } | |
533 | ||
534 | return; | |
535 | } else { | |
536 | if (s->async_len == 0) { | |
0db89536 MCA |
537 | /* Defer until the scsi layer has completed */ |
538 | scsi_req_continue(s->current_req); | |
539 | s->data_in_ready = false; | |
4e78f3bf | 540 | return; |
82141c8b MCA |
541 | } |
542 | ||
543 | if (esp_get_tc(s) != 0) { | |
544 | /* Copy device data to FIFO */ | |
7aa6baee MCA |
545 | len = MIN(s->async_len, esp_get_tc(s)); |
546 | len = MIN(len, fifo8_num_free(&s->fifo)); | |
042879fc | 547 | fifo8_push_all(&s->fifo, s->async_buf, len); |
82141c8b MCA |
548 | s->async_buf += len; |
549 | s->async_len -= len; | |
550 | s->ti_size -= len; | |
551 | esp_set_tc(s, esp_get_tc(s) - len); | |
7aa6baee MCA |
552 | |
553 | if (esp_get_tc(s) == 0) { | |
554 | /* Indicate transfer to FIFO is complete */ | |
555 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
556 | } | |
82141c8b MCA |
557 | return; |
558 | } | |
559 | ||
560 | /* Partially filled a scsi buffer. Complete immediately. */ | |
561 | esp_lower_drq(s); | |
562 | esp_dma_done(s); | |
563 | } | |
74d71ea1 LV |
564 | } |
565 | ||
4d611c9a PB |
566 | static void esp_do_dma(ESPState *s) |
567 | { | |
023666da | 568 | uint32_t len, cmdlen; |
4ca2ba6f | 569 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
023666da | 570 | uint8_t buf[ESP_CMDFIFO_SZ]; |
a917d384 | 571 | |
6cc88d6b | 572 | len = esp_get_tc(s); |
4d611c9a | 573 | if (s->do_cmd) { |
15407433 LV |
574 | /* |
575 | * handle_ti_cmd() case: esp_do_dma() is called only from | |
576 | * handle_ti_cmd() with do_cmd != NULL (see the assert()) | |
577 | */ | |
023666da MCA |
578 | cmdlen = fifo8_num_used(&s->cmdfifo); |
579 | trace_esp_do_dma(cmdlen, len); | |
74d71ea1 | 580 | if (s->dma_memory_read) { |
023666da MCA |
581 | s->dma_memory_read(s->dma_opaque, buf, len); |
582 | fifo8_push_all(&s->cmdfifo, buf, len); | |
74d71ea1 | 583 | } else { |
74d71ea1 LV |
584 | s->pdma_cb = do_dma_pdma_cb; |
585 | esp_raise_drq(s); | |
586 | return; | |
587 | } | |
023666da | 588 | trace_esp_handle_ti_cmd(cmdlen); |
15407433 | 589 | s->ti_size = 0; |
799d90d8 MCA |
590 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { |
591 | /* No command received */ | |
023666da | 592 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { |
799d90d8 MCA |
593 | return; |
594 | } | |
595 | ||
596 | /* Command has been received */ | |
799d90d8 MCA |
597 | s->do_cmd = 0; |
598 | do_cmd(s); | |
599 | } else { | |
600 | /* | |
023666da | 601 | * Extra message out bytes received: update cmdfifo_cdb_offset |
799d90d8 MCA |
602 | * and then switch to commmand phase |
603 | */ | |
023666da | 604 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); |
799d90d8 MCA |
605 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
606 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
607 | s->rregs[ESP_RINTR] |= INTR_BS; | |
608 | esp_raise_irq(s); | |
609 | } | |
4d611c9a | 610 | return; |
a917d384 | 611 | } |
0db89536 MCA |
612 | if (!s->current_req) { |
613 | return; | |
614 | } | |
a917d384 PB |
615 | if (s->async_len == 0) { |
616 | /* Defer until data is available. */ | |
617 | return; | |
618 | } | |
619 | if (len > s->async_len) { | |
620 | len = s->async_len; | |
621 | } | |
622 | if (to_device) { | |
74d71ea1 LV |
623 | if (s->dma_memory_read) { |
624 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); | |
625 | } else { | |
74d71ea1 LV |
626 | s->pdma_cb = do_dma_pdma_cb; |
627 | esp_raise_drq(s); | |
628 | return; | |
629 | } | |
4d611c9a | 630 | } else { |
74d71ea1 LV |
631 | if (s->dma_memory_write) { |
632 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); | |
633 | } else { | |
7aa6baee MCA |
634 | /* Adjust TC for any leftover data in the FIFO */ |
635 | if (!fifo8_is_empty(&s->fifo)) { | |
636 | esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); | |
637 | } | |
638 | ||
82141c8b | 639 | /* Copy device data to FIFO */ |
042879fc MCA |
640 | len = MIN(len, fifo8_num_free(&s->fifo)); |
641 | fifo8_push_all(&s->fifo, s->async_buf, len); | |
82141c8b MCA |
642 | s->async_buf += len; |
643 | s->async_len -= len; | |
644 | s->ti_size -= len; | |
7aa6baee MCA |
645 | |
646 | /* | |
647 | * MacOS toolbox uses a TI length of 16 bytes for all commands, so | |
648 | * commands shorter than this must be padded accordingly | |
649 | */ | |
650 | if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) { | |
651 | while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) { | |
e5455b8c | 652 | esp_fifo_push(&s->fifo, 0); |
7aa6baee MCA |
653 | len++; |
654 | } | |
655 | } | |
656 | ||
82141c8b | 657 | esp_set_tc(s, esp_get_tc(s) - len); |
74d71ea1 LV |
658 | s->pdma_cb = do_dma_pdma_cb; |
659 | esp_raise_drq(s); | |
82141c8b MCA |
660 | |
661 | /* Indicate transfer to FIFO is complete */ | |
662 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
74d71ea1 LV |
663 | return; |
664 | } | |
a917d384 | 665 | } |
6cc88d6b | 666 | esp_set_tc(s, esp_get_tc(s) - len); |
a917d384 PB |
667 | s->async_buf += len; |
668 | s->async_len -= len; | |
94d5c79d | 669 | if (to_device) { |
6787f5fa | 670 | s->ti_size += len; |
94d5c79d | 671 | } else { |
6787f5fa | 672 | s->ti_size -= len; |
94d5c79d | 673 | } |
a917d384 | 674 | if (s->async_len == 0) { |
ad3376cc | 675 | scsi_req_continue(s->current_req); |
94d5c79d MCA |
676 | /* |
677 | * If there is still data to be read from the device then | |
678 | * complete the DMA operation immediately. Otherwise defer | |
679 | * until the scsi layer has completed. | |
680 | */ | |
6cc88d6b | 681 | if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) { |
ad3376cc | 682 | return; |
4d611c9a | 683 | } |
a917d384 | 684 | } |
ad3376cc PB |
685 | |
686 | /* Partially filled a scsi buffer. Complete immediately. */ | |
687 | esp_dma_done(s); | |
82141c8b | 688 | esp_lower_drq(s); |
4d611c9a PB |
689 | } |
690 | ||
1b9e48a5 MCA |
691 | static void esp_do_nodma(ESPState *s) |
692 | { | |
693 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); | |
7b320a8e | 694 | uint32_t cmdlen; |
1b9e48a5 MCA |
695 | int len; |
696 | ||
697 | if (s->do_cmd) { | |
698 | cmdlen = fifo8_num_used(&s->cmdfifo); | |
699 | trace_esp_handle_ti_cmd(cmdlen); | |
700 | s->ti_size = 0; | |
701 | if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { | |
702 | /* No command received */ | |
703 | if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { | |
704 | return; | |
705 | } | |
706 | ||
707 | /* Command has been received */ | |
708 | s->do_cmd = 0; | |
709 | do_cmd(s); | |
710 | } else { | |
711 | /* | |
712 | * Extra message out bytes received: update cmdfifo_cdb_offset | |
713 | * and then switch to commmand phase | |
714 | */ | |
715 | s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); | |
716 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; | |
717 | s->rregs[ESP_RSEQ] = SEQ_CD; | |
718 | s->rregs[ESP_RINTR] |= INTR_BS; | |
719 | esp_raise_irq(s); | |
720 | } | |
721 | return; | |
722 | } | |
723 | ||
0db89536 MCA |
724 | if (!s->current_req) { |
725 | return; | |
726 | } | |
727 | ||
1b9e48a5 MCA |
728 | if (s->async_len == 0) { |
729 | /* Defer until data is available. */ | |
730 | return; | |
731 | } | |
732 | ||
733 | if (to_device) { | |
734 | len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ); | |
7b320a8e | 735 | esp_fifo_pop_buf(&s->fifo, s->async_buf, len); |
1b9e48a5 MCA |
736 | s->async_buf += len; |
737 | s->async_len -= len; | |
738 | s->ti_size += len; | |
739 | } else { | |
740 | len = MIN(s->ti_size, s->async_len); | |
741 | len = MIN(len, fifo8_num_free(&s->fifo)); | |
742 | fifo8_push_all(&s->fifo, s->async_buf, len); | |
743 | s->async_buf += len; | |
744 | s->async_len -= len; | |
745 | s->ti_size -= len; | |
746 | } | |
747 | ||
748 | if (s->async_len == 0) { | |
749 | scsi_req_continue(s->current_req); | |
750 | ||
751 | if (to_device || s->ti_size == 0) { | |
752 | return; | |
753 | } | |
754 | } | |
755 | ||
756 | s->rregs[ESP_RINTR] |= INTR_BS; | |
757 | esp_raise_irq(s); | |
758 | } | |
759 | ||
4aaa6ac3 | 760 | void esp_command_complete(SCSIRequest *req, size_t resid) |
2e5d83bb | 761 | { |
4aaa6ac3 MCA |
762 | ESPState *s = req->hba_private; |
763 | ||
bf4b9889 | 764 | trace_esp_command_complete(); |
c6df7102 | 765 | if (s->ti_size != 0) { |
bf4b9889 | 766 | trace_esp_command_complete_unexpected(); |
c6df7102 PB |
767 | } |
768 | s->ti_size = 0; | |
c6df7102 | 769 | s->async_len = 0; |
4aaa6ac3 | 770 | if (req->status) { |
bf4b9889 | 771 | trace_esp_command_complete_fail(); |
c6df7102 | 772 | } |
4aaa6ac3 | 773 | s->status = req->status; |
c6df7102 PB |
774 | s->rregs[ESP_RSTAT] = STAT_ST; |
775 | esp_dma_done(s); | |
82141c8b | 776 | esp_lower_drq(s); |
c6df7102 PB |
777 | if (s->current_req) { |
778 | scsi_req_unref(s->current_req); | |
779 | s->current_req = NULL; | |
780 | s->current_dev = NULL; | |
781 | } | |
782 | } | |
783 | ||
9c7e23fc | 784 | void esp_transfer_data(SCSIRequest *req, uint32_t len) |
c6df7102 | 785 | { |
e6810db8 | 786 | ESPState *s = req->hba_private; |
4e78f3bf | 787 | int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); |
6cc88d6b | 788 | uint32_t dmalen = esp_get_tc(s); |
c6df7102 | 789 | |
7f0b6e11 | 790 | assert(!s->do_cmd); |
6cc88d6b | 791 | trace_esp_transfer_data(dmalen, s->ti_size); |
aba1f023 | 792 | s->async_len = len; |
c6df7102 | 793 | s->async_buf = scsi_req_get_buf(req); |
4e78f3bf MCA |
794 | |
795 | if (!to_device && !s->data_in_ready) { | |
796 | /* | |
797 | * Initial incoming data xfer is complete so raise command | |
798 | * completion interrupt | |
799 | */ | |
800 | s->data_in_ready = true; | |
801 | s->rregs[ESP_RSTAT] |= STAT_TC; | |
802 | s->rregs[ESP_RINTR] |= INTR_BS; | |
803 | esp_raise_irq(s); | |
804 | ||
805 | /* | |
806 | * If data is ready to transfer and the TI command has already | |
807 | * been executed, start DMA immediately. Otherwise DMA will start | |
808 | * when host sends the TI command | |
809 | */ | |
810 | if (s->ti_size && (s->rregs[ESP_CMD] == (CMD_TI | CMD_DMA))) { | |
811 | esp_do_dma(s); | |
812 | } | |
813 | return; | |
814 | } | |
815 | ||
1b9e48a5 | 816 | if (s->ti_cmd == 0) { |
94d5c79d | 817 | /* |
1b9e48a5 MCA |
818 | * Always perform the initial transfer upon reception of the next TI |
819 | * command to ensure the DMA/non-DMA status of the command is correct. | |
820 | * It is not possible to use s->dma directly in the section below as | |
821 | * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the | |
822 | * async data transfer is delayed then s->dma is set incorrectly. | |
94d5c79d | 823 | */ |
1b9e48a5 MCA |
824 | return; |
825 | } | |
826 | ||
827 | if (s->ti_cmd & CMD_DMA) { | |
828 | if (dmalen) { | |
829 | esp_do_dma(s); | |
830 | } else if (s->ti_size <= 0) { | |
831 | /* | |
832 | * If this was the last part of a DMA transfer then the | |
833 | * completion interrupt is deferred to here. | |
834 | */ | |
835 | esp_dma_done(s); | |
836 | esp_lower_drq(s); | |
837 | } | |
838 | } else { | |
839 | esp_do_nodma(s); | |
4d611c9a | 840 | } |
2e5d83bb PB |
841 | } |
842 | ||
2f275b8f FB |
843 | static void handle_ti(ESPState *s) |
844 | { | |
1b9e48a5 | 845 | uint32_t dmalen; |
2f275b8f | 846 | |
7246e160 HP |
847 | if (s->dma && !s->dma_enabled) { |
848 | s->dma_cb = handle_ti; | |
849 | return; | |
850 | } | |
851 | ||
1b9e48a5 | 852 | s->ti_cmd = s->rregs[ESP_CMD]; |
4f6200f0 | 853 | if (s->dma) { |
1b9e48a5 | 854 | dmalen = esp_get_tc(s); |
b76624de | 855 | trace_esp_handle_ti(dmalen); |
5ad6bb97 | 856 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
4d611c9a | 857 | esp_do_dma(s); |
1b9e48a5 MCA |
858 | } else { |
859 | trace_esp_handle_ti(s->ti_size); | |
860 | esp_do_nodma(s); | |
9f149aa9 | 861 | } |
2f275b8f FB |
862 | } |
863 | ||
9c7e23fc | 864 | void esp_hard_reset(ESPState *s) |
6f7e9aec | 865 | { |
5aca8c3b BS |
866 | memset(s->rregs, 0, ESP_REGS); |
867 | memset(s->wregs, 0, ESP_REGS); | |
c9cf45c1 | 868 | s->tchi_written = 0; |
4e9aec74 | 869 | s->ti_size = 0; |
042879fc | 870 | fifo8_reset(&s->fifo); |
023666da | 871 | fifo8_reset(&s->cmdfifo); |
4e9aec74 | 872 | s->dma = 0; |
9f149aa9 | 873 | s->do_cmd = 0; |
73d74342 | 874 | s->dma_cb = NULL; |
8dea1dd4 BS |
875 | |
876 | s->rregs[ESP_CFG1] = 7; | |
6f7e9aec FB |
877 | } |
878 | ||
a391fdbc | 879 | static void esp_soft_reset(ESPState *s) |
85948643 | 880 | { |
85948643 | 881 | qemu_irq_lower(s->irq); |
74d71ea1 | 882 | qemu_irq_lower(s->irq_data); |
a391fdbc | 883 | esp_hard_reset(s); |
85948643 BS |
884 | } |
885 | ||
a391fdbc | 886 | static void parent_esp_reset(ESPState *s, int irq, int level) |
2d069bab | 887 | { |
85948643 | 888 | if (level) { |
a391fdbc | 889 | esp_soft_reset(s); |
85948643 | 890 | } |
2d069bab BS |
891 | } |
892 | ||
9c7e23fc | 893 | uint64_t esp_reg_read(ESPState *s, uint32_t saddr) |
73d74342 | 894 | { |
b630c075 | 895 | uint32_t val; |
73d74342 | 896 | |
6f7e9aec | 897 | switch (saddr) { |
5ad6bb97 | 898 | case ESP_FIFO: |
1b9e48a5 MCA |
899 | if (s->dma_memory_read && s->dma_memory_write && |
900 | (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { | |
ff589551 PP |
901 | /* Data out. */ |
902 | qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); | |
903 | s->rregs[ESP_FIFO] = 0; | |
042879fc | 904 | } else { |
c5fef911 | 905 | s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); |
4f6200f0 | 906 | } |
b630c075 | 907 | val = s->rregs[ESP_FIFO]; |
f930d07e | 908 | break; |
5ad6bb97 | 909 | case ESP_RINTR: |
94d5c79d MCA |
910 | /* |
911 | * Clear sequence step, interrupt register and all status bits | |
912 | * except TC | |
913 | */ | |
b630c075 | 914 | val = s->rregs[ESP_RINTR]; |
2814df28 BS |
915 | s->rregs[ESP_RINTR] = 0; |
916 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
cf47a41e | 917 | s->rregs[ESP_RSEQ] = SEQ_0; |
c73f96fd | 918 | esp_lower_irq(s); |
b630c075 | 919 | break; |
c9cf45c1 HR |
920 | case ESP_TCHI: |
921 | /* Return the unique id if the value has never been written */ | |
922 | if (!s->tchi_written) { | |
b630c075 MCA |
923 | val = s->chip_id; |
924 | } else { | |
925 | val = s->rregs[saddr]; | |
c9cf45c1 | 926 | } |
b630c075 | 927 | break; |
238ec4d7 MCA |
928 | case ESP_RFLAGS: |
929 | /* Bottom 5 bits indicate number of bytes in FIFO */ | |
930 | val = fifo8_num_used(&s->fifo); | |
931 | break; | |
6f7e9aec | 932 | default: |
b630c075 | 933 | val = s->rregs[saddr]; |
f930d07e | 934 | break; |
6f7e9aec | 935 | } |
b630c075 MCA |
936 | |
937 | trace_esp_mem_readb(saddr, val); | |
938 | return val; | |
6f7e9aec FB |
939 | } |
940 | ||
9c7e23fc | 941 | void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) |
6f7e9aec | 942 | { |
bf4b9889 | 943 | trace_esp_mem_writeb(saddr, s->wregs[saddr], val); |
6f7e9aec | 944 | switch (saddr) { |
c9cf45c1 HR |
945 | case ESP_TCHI: |
946 | s->tchi_written = true; | |
947 | /* fall through */ | |
5ad6bb97 BS |
948 | case ESP_TCLO: |
949 | case ESP_TCMID: | |
950 | s->rregs[ESP_RSTAT] &= ~STAT_TC; | |
4f6200f0 | 951 | break; |
5ad6bb97 | 952 | case ESP_FIFO: |
9f149aa9 | 953 | if (s->do_cmd) { |
e5455b8c | 954 | esp_fifo_push(&s->cmdfifo, val); |
2e5d83bb | 955 | } else { |
e5455b8c | 956 | esp_fifo_push(&s->fifo, val); |
2e5d83bb | 957 | } |
4e0ed629 MCA |
958 | |
959 | /* Non-DMA transfers raise an interrupt after every byte */ | |
960 | if (s->rregs[ESP_CMD] == CMD_TI) { | |
961 | s->rregs[ESP_RINTR] |= INTR_FC | INTR_BS; | |
962 | esp_raise_irq(s); | |
963 | } | |
f930d07e | 964 | break; |
5ad6bb97 | 965 | case ESP_CMD: |
4f6200f0 | 966 | s->rregs[saddr] = val; |
5ad6bb97 | 967 | if (val & CMD_DMA) { |
f930d07e | 968 | s->dma = 1; |
6787f5fa | 969 | /* Reload DMA counter. */ |
96676c2f MCA |
970 | if (esp_get_stc(s) == 0) { |
971 | esp_set_tc(s, 0x10000); | |
972 | } else { | |
973 | esp_set_tc(s, esp_get_stc(s)); | |
974 | } | |
f930d07e BS |
975 | } else { |
976 | s->dma = 0; | |
977 | } | |
94d5c79d | 978 | switch (val & CMD_CMD) { |
5ad6bb97 | 979 | case CMD_NOP: |
bf4b9889 | 980 | trace_esp_mem_writeb_cmd_nop(val); |
f930d07e | 981 | break; |
5ad6bb97 | 982 | case CMD_FLUSH: |
bf4b9889 | 983 | trace_esp_mem_writeb_cmd_flush(val); |
042879fc | 984 | fifo8_reset(&s->fifo); |
f930d07e | 985 | break; |
5ad6bb97 | 986 | case CMD_RESET: |
bf4b9889 | 987 | trace_esp_mem_writeb_cmd_reset(val); |
a391fdbc | 988 | esp_soft_reset(s); |
f930d07e | 989 | break; |
5ad6bb97 | 990 | case CMD_BUSRESET: |
bf4b9889 | 991 | trace_esp_mem_writeb_cmd_bus_reset(val); |
5ad6bb97 | 992 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { |
cf47a41e | 993 | s->rregs[ESP_RINTR] |= INTR_RST; |
c73f96fd | 994 | esp_raise_irq(s); |
9e61bde5 | 995 | } |
f930d07e | 996 | break; |
5ad6bb97 | 997 | case CMD_TI: |
0097d3ec | 998 | trace_esp_mem_writeb_cmd_ti(val); |
f930d07e BS |
999 | handle_ti(s); |
1000 | break; | |
5ad6bb97 | 1001 | case CMD_ICCS: |
bf4b9889 | 1002 | trace_esp_mem_writeb_cmd_iccs(val); |
f930d07e | 1003 | write_response(s); |
cf47a41e | 1004 | s->rregs[ESP_RINTR] |= INTR_FC; |
4bf5801d | 1005 | s->rregs[ESP_RSTAT] |= STAT_MI; |
f930d07e | 1006 | break; |
5ad6bb97 | 1007 | case CMD_MSGACC: |
bf4b9889 | 1008 | trace_esp_mem_writeb_cmd_msgacc(val); |
cf47a41e | 1009 | s->rregs[ESP_RINTR] |= INTR_DC; |
5ad6bb97 | 1010 | s->rregs[ESP_RSEQ] = 0; |
4e2a68c1 AT |
1011 | s->rregs[ESP_RFLAGS] = 0; |
1012 | esp_raise_irq(s); | |
f930d07e | 1013 | break; |
0fd0eb21 | 1014 | case CMD_PAD: |
bf4b9889 | 1015 | trace_esp_mem_writeb_cmd_pad(val); |
0fd0eb21 | 1016 | s->rregs[ESP_RSTAT] = STAT_TC; |
cf47a41e | 1017 | s->rregs[ESP_RINTR] |= INTR_FC; |
0fd0eb21 BS |
1018 | s->rregs[ESP_RSEQ] = 0; |
1019 | break; | |
5ad6bb97 | 1020 | case CMD_SATN: |
bf4b9889 | 1021 | trace_esp_mem_writeb_cmd_satn(val); |
f930d07e | 1022 | break; |
6915bff1 HP |
1023 | case CMD_RSTATN: |
1024 | trace_esp_mem_writeb_cmd_rstatn(val); | |
1025 | break; | |
5e1e0a3b | 1026 | case CMD_SEL: |
bf4b9889 | 1027 | trace_esp_mem_writeb_cmd_sel(val); |
f2818f22 | 1028 | handle_s_without_atn(s); |
5e1e0a3b | 1029 | break; |
5ad6bb97 | 1030 | case CMD_SELATN: |
bf4b9889 | 1031 | trace_esp_mem_writeb_cmd_selatn(val); |
f930d07e BS |
1032 | handle_satn(s); |
1033 | break; | |
5ad6bb97 | 1034 | case CMD_SELATNS: |
bf4b9889 | 1035 | trace_esp_mem_writeb_cmd_selatns(val); |
f930d07e BS |
1036 | handle_satn_stop(s); |
1037 | break; | |
5ad6bb97 | 1038 | case CMD_ENSEL: |
bf4b9889 | 1039 | trace_esp_mem_writeb_cmd_ensel(val); |
e3926838 | 1040 | s->rregs[ESP_RINTR] = 0; |
74ec6048 | 1041 | break; |
6fe84c18 HP |
1042 | case CMD_DISSEL: |
1043 | trace_esp_mem_writeb_cmd_dissel(val); | |
1044 | s->rregs[ESP_RINTR] = 0; | |
1045 | esp_raise_irq(s); | |
1046 | break; | |
f930d07e | 1047 | default: |
3af4e9aa | 1048 | trace_esp_error_unhandled_command(val); |
f930d07e BS |
1049 | break; |
1050 | } | |
1051 | break; | |
5ad6bb97 | 1052 | case ESP_WBUSID ... ESP_WSYNO: |
f930d07e | 1053 | break; |
5ad6bb97 | 1054 | case ESP_CFG1: |
9ea73f8b PB |
1055 | case ESP_CFG2: case ESP_CFG3: |
1056 | case ESP_RES3: case ESP_RES4: | |
4f6200f0 FB |
1057 | s->rregs[saddr] = val; |
1058 | break; | |
5ad6bb97 | 1059 | case ESP_WCCF ... ESP_WTEST: |
4f6200f0 | 1060 | break; |
6f7e9aec | 1061 | default: |
3af4e9aa | 1062 | trace_esp_error_invalid_write(val, saddr); |
8dea1dd4 | 1063 | return; |
6f7e9aec | 1064 | } |
2f275b8f | 1065 | s->wregs[saddr] = val; |
6f7e9aec FB |
1066 | } |
1067 | ||
a8170e5e | 1068 | static bool esp_mem_accepts(void *opaque, hwaddr addr, |
8372d383 PM |
1069 | unsigned size, bool is_write, |
1070 | MemTxAttrs attrs) | |
67bb5314 AK |
1071 | { |
1072 | return (size == 1) || (is_write && size == 4); | |
1073 | } | |
6f7e9aec | 1074 | |
6cc88d6b MCA |
1075 | static bool esp_is_before_version_5(void *opaque, int version_id) |
1076 | { | |
1077 | ESPState *s = ESP(opaque); | |
1078 | ||
1079 | version_id = MIN(version_id, s->mig_version_id); | |
1080 | return version_id < 5; | |
1081 | } | |
1082 | ||
4e78f3bf MCA |
1083 | static bool esp_is_version_5(void *opaque, int version_id) |
1084 | { | |
1085 | ESPState *s = ESP(opaque); | |
1086 | ||
1087 | version_id = MIN(version_id, s->mig_version_id); | |
1088 | return version_id == 5; | |
1089 | } | |
1090 | ||
ff4a1dab | 1091 | int esp_pre_save(void *opaque) |
0bd005be | 1092 | { |
ff4a1dab MCA |
1093 | ESPState *s = ESP(object_resolve_path_component( |
1094 | OBJECT(opaque), "esp")); | |
0bd005be MCA |
1095 | |
1096 | s->mig_version_id = vmstate_esp.version_id; | |
1097 | return 0; | |
1098 | } | |
1099 | ||
1100 | static int esp_post_load(void *opaque, int version_id) | |
1101 | { | |
1102 | ESPState *s = ESP(opaque); | |
042879fc | 1103 | int len, i; |
0bd005be | 1104 | |
6cc88d6b MCA |
1105 | version_id = MIN(version_id, s->mig_version_id); |
1106 | ||
1107 | if (version_id < 5) { | |
1108 | esp_set_tc(s, s->mig_dma_left); | |
042879fc MCA |
1109 | |
1110 | /* Migrate ti_buf to fifo */ | |
1111 | len = s->mig_ti_wptr - s->mig_ti_rptr; | |
1112 | for (i = 0; i < len; i++) { | |
1113 | fifo8_push(&s->fifo, s->mig_ti_buf[i]); | |
1114 | } | |
023666da MCA |
1115 | |
1116 | /* Migrate cmdbuf to cmdfifo */ | |
1117 | for (i = 0; i < s->mig_cmdlen; i++) { | |
1118 | fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); | |
1119 | } | |
6cc88d6b MCA |
1120 | } |
1121 | ||
0bd005be MCA |
1122 | s->mig_version_id = vmstate_esp.version_id; |
1123 | return 0; | |
1124 | } | |
1125 | ||
9c7e23fc | 1126 | const VMStateDescription vmstate_esp = { |
94d5c79d | 1127 | .name = "esp", |
0bd005be | 1128 | .version_id = 5, |
cc9952f3 | 1129 | .minimum_version_id = 3, |
0bd005be | 1130 | .post_load = esp_post_load, |
35d08458 | 1131 | .fields = (VMStateField[]) { |
cc9952f3 BS |
1132 | VMSTATE_BUFFER(rregs, ESPState), |
1133 | VMSTATE_BUFFER(wregs, ESPState), | |
1134 | VMSTATE_INT32(ti_size, ESPState), | |
042879fc MCA |
1135 | VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), |
1136 | VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), | |
1137 | VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), | |
3944966d | 1138 | VMSTATE_UINT32(status, ESPState), |
4aaa6ac3 MCA |
1139 | VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, |
1140 | esp_is_before_version_5), | |
1141 | VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, | |
1142 | esp_is_before_version_5), | |
cc9952f3 | 1143 | VMSTATE_UINT32(dma, ESPState), |
023666da MCA |
1144 | VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, |
1145 | esp_is_before_version_5, 0, 16), | |
1146 | VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, | |
1147 | esp_is_before_version_5, 16, | |
1148 | sizeof(typeof_field(ESPState, mig_cmdbuf))), | |
1149 | VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), | |
cc9952f3 | 1150 | VMSTATE_UINT32(do_cmd, ESPState), |
6cc88d6b | 1151 | VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), |
4e78f3bf | 1152 | VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), |
023666da | 1153 | VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), |
042879fc | 1154 | VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), |
023666da | 1155 | VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), |
1b9e48a5 | 1156 | VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), |
cc9952f3 | 1157 | VMSTATE_END_OF_LIST() |
74d71ea1 | 1158 | }, |
cc9952f3 | 1159 | }; |
6f7e9aec | 1160 | |
a8170e5e | 1161 | static void sysbus_esp_mem_write(void *opaque, hwaddr addr, |
a391fdbc HP |
1162 | uint64_t val, unsigned int size) |
1163 | { | |
1164 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1165 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1166 | uint32_t saddr; |
1167 | ||
1168 | saddr = addr >> sysbus->it_shift; | |
eb169c76 | 1169 | esp_reg_write(s, saddr, val); |
a391fdbc HP |
1170 | } |
1171 | ||
a8170e5e | 1172 | static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, |
a391fdbc HP |
1173 | unsigned int size) |
1174 | { | |
1175 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1176 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1177 | uint32_t saddr; |
1178 | ||
1179 | saddr = addr >> sysbus->it_shift; | |
eb169c76 | 1180 | return esp_reg_read(s, saddr); |
a391fdbc HP |
1181 | } |
1182 | ||
1183 | static const MemoryRegionOps sysbus_esp_mem_ops = { | |
1184 | .read = sysbus_esp_mem_read, | |
1185 | .write = sysbus_esp_mem_write, | |
1186 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1187 | .valid.accepts = esp_mem_accepts, | |
1188 | }; | |
1189 | ||
74d71ea1 LV |
1190 | static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, |
1191 | uint64_t val, unsigned int size) | |
1192 | { | |
1193 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1194 | ESPState *s = ESP(&sysbus->esp); |
3c421400 | 1195 | uint32_t dmalen; |
74d71ea1 | 1196 | |
960ebfd9 MCA |
1197 | trace_esp_pdma_write(size); |
1198 | ||
74d71ea1 LV |
1199 | switch (size) { |
1200 | case 1: | |
761bef75 | 1201 | esp_pdma_write(s, val); |
74d71ea1 LV |
1202 | break; |
1203 | case 2: | |
761bef75 MCA |
1204 | esp_pdma_write(s, val >> 8); |
1205 | esp_pdma_write(s, val); | |
74d71ea1 LV |
1206 | break; |
1207 | } | |
3c421400 | 1208 | dmalen = esp_get_tc(s); |
7aa6baee | 1209 | if (dmalen == 0 || fifo8_num_free(&s->fifo) < 2) { |
74d71ea1 | 1210 | s->pdma_cb(s); |
74d71ea1 LV |
1211 | } |
1212 | } | |
1213 | ||
1214 | static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, | |
1215 | unsigned int size) | |
1216 | { | |
1217 | SysBusESPState *sysbus = opaque; | |
eb169c76 | 1218 | ESPState *s = ESP(&sysbus->esp); |
74d71ea1 LV |
1219 | uint64_t val = 0; |
1220 | ||
960ebfd9 MCA |
1221 | trace_esp_pdma_read(size); |
1222 | ||
74d71ea1 LV |
1223 | switch (size) { |
1224 | case 1: | |
761bef75 | 1225 | val = esp_pdma_read(s); |
74d71ea1 LV |
1226 | break; |
1227 | case 2: | |
761bef75 MCA |
1228 | val = esp_pdma_read(s); |
1229 | val = (val << 8) | esp_pdma_read(s); | |
74d71ea1 LV |
1230 | break; |
1231 | } | |
7aa6baee | 1232 | if (fifo8_num_used(&s->fifo) < 2) { |
74d71ea1 | 1233 | s->pdma_cb(s); |
74d71ea1 LV |
1234 | } |
1235 | return val; | |
1236 | } | |
1237 | ||
1238 | static const MemoryRegionOps sysbus_esp_pdma_ops = { | |
1239 | .read = sysbus_esp_pdma_read, | |
1240 | .write = sysbus_esp_pdma_write, | |
1241 | .endianness = DEVICE_NATIVE_ENDIAN, | |
1242 | .valid.min_access_size = 1, | |
cf1b8286 MCA |
1243 | .valid.max_access_size = 4, |
1244 | .impl.min_access_size = 1, | |
1245 | .impl.max_access_size = 2, | |
74d71ea1 LV |
1246 | }; |
1247 | ||
afd4030c PB |
1248 | static const struct SCSIBusInfo esp_scsi_info = { |
1249 | .tcq = false, | |
7e0380b9 PB |
1250 | .max_target = ESP_MAX_DEVS, |
1251 | .max_lun = 7, | |
afd4030c | 1252 | |
c6df7102 | 1253 | .transfer_data = esp_transfer_data, |
94d3f98a PB |
1254 | .complete = esp_command_complete, |
1255 | .cancel = esp_request_cancelled | |
cfdc1bb0 PB |
1256 | }; |
1257 | ||
a391fdbc | 1258 | static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) |
cfb9de9c | 1259 | { |
84fbefed | 1260 | SysBusESPState *sysbus = SYSBUS_ESP(opaque); |
eb169c76 | 1261 | ESPState *s = ESP(&sysbus->esp); |
a391fdbc HP |
1262 | |
1263 | switch (irq) { | |
1264 | case 0: | |
1265 | parent_esp_reset(s, irq, level); | |
1266 | break; | |
1267 | case 1: | |
1268 | esp_dma_enable(opaque, irq, level); | |
1269 | break; | |
1270 | } | |
1271 | } | |
1272 | ||
b09318ca | 1273 | static void sysbus_esp_realize(DeviceState *dev, Error **errp) |
a391fdbc | 1274 | { |
b09318ca | 1275 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
84fbefed | 1276 | SysBusESPState *sysbus = SYSBUS_ESP(dev); |
eb169c76 MCA |
1277 | ESPState *s = ESP(&sysbus->esp); |
1278 | ||
1279 | if (!qdev_realize(DEVICE(s), NULL, errp)) { | |
1280 | return; | |
1281 | } | |
6f7e9aec | 1282 | |
b09318ca | 1283 | sysbus_init_irq(sbd, &s->irq); |
74d71ea1 | 1284 | sysbus_init_irq(sbd, &s->irq_data); |
a391fdbc | 1285 | assert(sysbus->it_shift != -1); |
6f7e9aec | 1286 | |
d32e4b3d | 1287 | s->chip_id = TCHI_FAS100A; |
29776739 | 1288 | memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, |
74d71ea1 | 1289 | sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); |
b09318ca | 1290 | sysbus_init_mmio(sbd, &sysbus->iomem); |
74d71ea1 | 1291 | memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, |
cf1b8286 | 1292 | sysbus, "esp-pdma", 4); |
74d71ea1 | 1293 | sysbus_init_mmio(sbd, &sysbus->pdma); |
6f7e9aec | 1294 | |
b09318ca | 1295 | qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); |
2d069bab | 1296 | |
b1187b51 | 1297 | scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); |
67e999be | 1298 | } |
cfb9de9c | 1299 | |
a391fdbc HP |
1300 | static void sysbus_esp_hard_reset(DeviceState *dev) |
1301 | { | |
84fbefed | 1302 | SysBusESPState *sysbus = SYSBUS_ESP(dev); |
eb169c76 MCA |
1303 | ESPState *s = ESP(&sysbus->esp); |
1304 | ||
1305 | esp_hard_reset(s); | |
1306 | } | |
1307 | ||
1308 | static void sysbus_esp_init(Object *obj) | |
1309 | { | |
1310 | SysBusESPState *sysbus = SYSBUS_ESP(obj); | |
1311 | ||
1312 | object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); | |
a391fdbc HP |
1313 | } |
1314 | ||
1315 | static const VMStateDescription vmstate_sysbus_esp_scsi = { | |
1316 | .name = "sysbusespscsi", | |
0bd005be | 1317 | .version_id = 2, |
ea84a442 | 1318 | .minimum_version_id = 1, |
ff4a1dab | 1319 | .pre_save = esp_pre_save, |
a391fdbc | 1320 | .fields = (VMStateField[]) { |
0bd005be | 1321 | VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), |
a391fdbc HP |
1322 | VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), |
1323 | VMSTATE_END_OF_LIST() | |
1324 | } | |
999e12bb AL |
1325 | }; |
1326 | ||
a391fdbc | 1327 | static void sysbus_esp_class_init(ObjectClass *klass, void *data) |
999e12bb | 1328 | { |
39bffca2 | 1329 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 1330 | |
b09318ca | 1331 | dc->realize = sysbus_esp_realize; |
a391fdbc HP |
1332 | dc->reset = sysbus_esp_hard_reset; |
1333 | dc->vmsd = &vmstate_sysbus_esp_scsi; | |
125ee0ed | 1334 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
999e12bb AL |
1335 | } |
1336 | ||
1f077308 | 1337 | static const TypeInfo sysbus_esp_info = { |
84fbefed | 1338 | .name = TYPE_SYSBUS_ESP, |
39bffca2 | 1339 | .parent = TYPE_SYS_BUS_DEVICE, |
eb169c76 | 1340 | .instance_init = sysbus_esp_init, |
a391fdbc HP |
1341 | .instance_size = sizeof(SysBusESPState), |
1342 | .class_init = sysbus_esp_class_init, | |
63235df8 BS |
1343 | }; |
1344 | ||
042879fc MCA |
1345 | static void esp_finalize(Object *obj) |
1346 | { | |
1347 | ESPState *s = ESP(obj); | |
1348 | ||
1349 | fifo8_destroy(&s->fifo); | |
023666da | 1350 | fifo8_destroy(&s->cmdfifo); |
042879fc MCA |
1351 | } |
1352 | ||
1353 | static void esp_init(Object *obj) | |
1354 | { | |
1355 | ESPState *s = ESP(obj); | |
1356 | ||
1357 | fifo8_create(&s->fifo, ESP_FIFO_SZ); | |
023666da | 1358 | fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); |
042879fc MCA |
1359 | } |
1360 | ||
eb169c76 MCA |
1361 | static void esp_class_init(ObjectClass *klass, void *data) |
1362 | { | |
1363 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1364 | ||
1365 | /* internal device for sysbusesp/pciespscsi, not user-creatable */ | |
1366 | dc->user_creatable = false; | |
1367 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | |
1368 | } | |
1369 | ||
1370 | static const TypeInfo esp_info = { | |
1371 | .name = TYPE_ESP, | |
1372 | .parent = TYPE_DEVICE, | |
042879fc MCA |
1373 | .instance_init = esp_init, |
1374 | .instance_finalize = esp_finalize, | |
eb169c76 MCA |
1375 | .instance_size = sizeof(ESPState), |
1376 | .class_init = esp_class_init, | |
1377 | }; | |
1378 | ||
83f7d43a | 1379 | static void esp_register_types(void) |
cfb9de9c | 1380 | { |
a391fdbc | 1381 | type_register_static(&sysbus_esp_info); |
eb169c76 | 1382 | type_register_static(&esp_info); |
cfb9de9c PB |
1383 | } |
1384 | ||
83f7d43a | 1385 | type_init(esp_register_types) |