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scsi: Rename scsi_*_length() to scsi_*_xfer(), add scsi_cdb_length()
[mirror_qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
83c9f4ca
PB		 21#include "hw/hw.h"
22#include "hw/pci/pci.h"
9c17d615 23#include "sysemu/dma.h"
4be74634 24#include "sysemu/block-backend.h"
4522b69c 25#include "hw/pci/msi.h"
83c9f4ca 26#include "hw/pci/msix.h"
1de7afc9 27#include "qemu/iov.h"
0d09e41a
PB		 28#include "hw/scsi/scsi.h"
29#include "block/scsi.h"
e8f943c3
HR		 30#include "trace.h"
31
47b43a1f 32#include "mfi.h"
e8f943c3
HR		 33
34#define MEGASAS_VERSION "1.70"
35#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
36#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
37#define MEGASAS_MAX_SGE 128 /* Firmware limit */
38#define MEGASAS_DEFAULT_SGE 80
39#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
40#define MEGASAS_MAX_ARRAYS 128
41
fb654157 42#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 43#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
44#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
45
e8f943c3
HR		 46#define MEGASAS_FLAG_USE_JBOD 0
47#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
4522b69c
HR		 48#define MEGASAS_FLAG_USE_MSI 1
49#define MEGASAS_MASK_USE_MSI (1 << MEGASAS_FLAG_USE_MSI)
50#define MEGASAS_FLAG_USE_MSIX 2
e8f943c3 51#define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX)
4522b69c 52#define MEGASAS_FLAG_USE_QUEUE64 3
e8f943c3
HR		 53#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
54
a97ad268 55static const char *mfi_frame_desc[] = {
e8f943c3
HR		 56 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
57 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
58
59typedef struct MegasasCmd {
60 uint32_t index;
61 uint16_t flags;
62 uint16_t count;
63 uint64_t context;
64
a8170e5e
AK		 65 hwaddr pa;
66 hwaddr pa_size;
e8f943c3
HR		 67 union mfi_frame *frame;
68 SCSIRequest *req;
69 QEMUSGList qsg;
70 void *iov_buf;
71 size_t iov_size;
72 size_t iov_offset;
73 struct MegasasState *state;
74} MegasasCmd;
75
76typedef struct MegasasState {
52190c1e
AF		 77 /*< private >*/
78 PCIDevice parent_obj;
79 /*< public >*/
80
e8f943c3
HR		 81 MemoryRegion mmio_io;
82 MemoryRegion port_io;
83 MemoryRegion queue_io;
84 uint32_t frame_hi;
85
86 int fw_state;
87 uint32_t fw_sge;
88 uint32_t fw_cmds;
89 uint32_t flags;
90 int fw_luns;
91 int intr_mask;
92 int doorbell;
93 int busy;
94
95 MegasasCmd *event_cmd;
96 int event_locale;
97 int event_class;
98 int event_count;
99 int shutdown_event;
100 int boot_event;
101
76b523db 102 uint64_t sas_addr;
fb654157 103 char *hba_serial;
76b523db 104
e8f943c3
HR		 105 uint64_t reply_queue_pa;
106 void *reply_queue;
107 int reply_queue_len;
108 int reply_queue_head;
109 int reply_queue_tail;
110 uint64_t consumer_pa;
111 uint64_t producer_pa;
112
113 MegasasCmd frames[MEGASAS_MAX_FRAMES];
114
115 SCSIBus bus;
116} MegasasState;
117
c79e16ae
PC		 118#define TYPE_MEGASAS "megasas"
119
120#define MEGASAS(obj) \
121 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS)
122
e8f943c3
HR		 123#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
124
125static bool megasas_intr_enabled(MegasasState *s)
126{
127 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
128 MEGASAS_INTR_DISABLED_MASK) {
129 return true;
130 }
131 return false;
132}
133
134static bool megasas_use_queue64(MegasasState *s)
135{
136 return s->flags & MEGASAS_MASK_USE_QUEUE64;
137}
138
4522b69c
HR		 139static bool megasas_use_msi(MegasasState *s)
140{
141 return s->flags & MEGASAS_MASK_USE_MSI;
142}
143
e8f943c3
HR		 144static bool megasas_use_msix(MegasasState *s)
145{
146 return s->flags & MEGASAS_MASK_USE_MSIX;
147}
148
149static bool megasas_is_jbod(MegasasState *s)
150{
151 return s->flags & MEGASAS_MASK_USE_JBOD;
152}
153
154static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v)
155{
db3be60d
EI		 156 stb_phys(&address_space_memory,
157 frame + offsetof(struct mfi_frame_header, cmd_status), v);
e8f943c3
HR		 158}
159
160static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
161{
db3be60d
EI		 162 stb_phys(&address_space_memory,
163 frame + offsetof(struct mfi_frame_header, scsi_status), v);
e8f943c3
HR		 164}
165
166/*
167 * Context is considered opaque, but the HBA firmware is running
168 * in little endian mode. So convert it to little endian, too.
169 */
170static uint64_t megasas_frame_get_context(unsigned long frame)
171{
2c17449b
EI		 172 return ldq_le_phys(&address_space_memory,
173 frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 174}
175
176static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
177{
178 return cmd->flags & MFI_FRAME_IEEE_SGL;
179}
180
181static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
182{
183 return cmd->flags & MFI_FRAME_SGL64;
184}
185
186static bool megasas_frame_is_sense64(MegasasCmd *cmd)
187{
188 return cmd->flags & MFI_FRAME_SENSE64;
189}
190
191static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
192 union mfi_sgl *sgl)
193{
194 uint64_t addr;
195
196 if (megasas_frame_is_ieee_sgl(cmd)) {
197 addr = le64_to_cpu(sgl->sg_skinny->addr);
198 } else if (megasas_frame_is_sgl64(cmd)) {
199 addr = le64_to_cpu(sgl->sg64->addr);
200 } else {
201 addr = le32_to_cpu(sgl->sg32->addr);
202 }
203 return addr;
204}
205
206static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
207 union mfi_sgl *sgl)
208{
209 uint32_t len;
210
211 if (megasas_frame_is_ieee_sgl(cmd)) {
212 len = le32_to_cpu(sgl->sg_skinny->len);
213 } else if (megasas_frame_is_sgl64(cmd)) {
214 len = le32_to_cpu(sgl->sg64->len);
215 } else {
216 len = le32_to_cpu(sgl->sg32->len);
217 }
218 return len;
219}
220
221static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
222 union mfi_sgl *sgl)
223{
224 uint8_t *next = (uint8_t *)sgl;
225
226 if (megasas_frame_is_ieee_sgl(cmd)) {
227 next += sizeof(struct mfi_sg_skinny);
228 } else if (megasas_frame_is_sgl64(cmd)) {
229 next += sizeof(struct mfi_sg64);
230 } else {
231 next += sizeof(struct mfi_sg32);
232 }
233
234 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
235 return NULL;
236 }
237 return (union mfi_sgl *)next;
238}
239
240static void megasas_soft_reset(MegasasState *s);
241
242static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
243{
244 int i;
245 int iov_count = 0;
246 size_t iov_size = 0;
247
248 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
249 iov_count = cmd->frame->header.sge_count;
250 if (iov_count > MEGASAS_MAX_SGE) {
251 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
252 MEGASAS_MAX_SGE);
253 return iov_count;
254 }
52190c1e 255 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 256 for (i = 0; i < iov_count; i++) {
257 dma_addr_t iov_pa, iov_size_p;
258
259 if (!sgl) {
260 trace_megasas_iovec_sgl_underflow(cmd->index, i);
261 goto unmap;
262 }
263 iov_pa = megasas_sgl_get_addr(cmd, sgl);
264 iov_size_p = megasas_sgl_get_len(cmd, sgl);
265 if (!iov_pa || !iov_size_p) {
266 trace_megasas_iovec_sgl_invalid(cmd->index, i,
267 iov_pa, iov_size_p);
268 goto unmap;
269 }
270 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
271 sgl = megasas_sgl_next(cmd, sgl);
272 iov_size += (size_t)iov_size_p;
273 }
274 if (cmd->iov_size > iov_size) {
275 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
276 } else if (cmd->iov_size < iov_size) {
277 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
278 }
279 cmd->iov_offset = 0;
280 return 0;
281unmap:
282 qemu_sglist_destroy(&cmd->qsg);
283 return iov_count - i;
284}
285
286static void megasas_unmap_sgl(MegasasCmd *cmd)
287{
288 qemu_sglist_destroy(&cmd->qsg);
289 cmd->iov_offset = 0;
290}
291
292/*
293 * passthrough sense and io sense are at the same offset
294 */
295static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
296 uint8_t sense_len)
297{
1016b239 298 PCIDevice *pcid = PCI_DEVICE(cmd->state);
e8f943c3 299 uint32_t pa_hi = 0, pa_lo;
a8170e5e 300 hwaddr pa;
e8f943c3
HR		 301
302 if (sense_len > cmd->frame->header.sense_len) {
303 sense_len = cmd->frame->header.sense_len;
304 }
305 if (sense_len) {
306 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
307 if (megasas_frame_is_sense64(cmd)) {
308 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
309 }
310 pa = ((uint64_t) pa_hi << 32) | pa_lo;
1016b239 311 pci_dma_write(pcid, pa, sense_ptr, sense_len);
e8f943c3
HR		 312 cmd->frame->header.sense_len = sense_len;
313 }
314 return sense_len;
315}
316
317static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
318{
319 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
320 uint8_t sense_len = 18;
321
322 memset(sense_buf, 0, sense_len);
323 sense_buf[0] = 0xf0;
324 sense_buf[2] = sense.key;
325 sense_buf[7] = 10;
326 sense_buf[12] = sense.asc;
327 sense_buf[13] = sense.ascq;
328 megasas_build_sense(cmd, sense_buf, sense_len);
329}
330
331static void megasas_copy_sense(MegasasCmd *cmd)
332{
333 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
334 uint8_t sense_len;
335
336 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
337 SCSI_SENSE_BUF_SIZE);
338 megasas_build_sense(cmd, sense_buf, sense_len);
339}
340
341/*
342 * Format an INQUIRY CDB
343 */
344static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
345{
346 memset(cdb, 0, 6);
347 cdb[0] = INQUIRY;
348 if (pg > 0) {
349 cdb[1] = 0x1;
350 cdb[2] = pg;
351 }
352 cdb[3] = (len >> 8) & 0xff;
353 cdb[4] = (len & 0xff);
354 return len;
355}
356
357/*
358 * Encode lba and len into a READ_16/WRITE_16 CDB
359 */
360static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
361 uint32_t len, bool is_write)
362{
363 memset(cdb, 0x0, 16);
364 if (is_write) {
365 cdb[0] = WRITE_16;
366 } else {
367 cdb[0] = READ_16;
368 }
369 cdb[2] = (lba >> 56) & 0xff;
370 cdb[3] = (lba >> 48) & 0xff;
371 cdb[4] = (lba >> 40) & 0xff;
372 cdb[5] = (lba >> 32) & 0xff;
373 cdb[6] = (lba >> 24) & 0xff;
374 cdb[7] = (lba >> 16) & 0xff;
375 cdb[8] = (lba >> 8) & 0xff;
376 cdb[9] = (lba) & 0xff;
377 cdb[10] = (len >> 24) & 0xff;
378 cdb[11] = (len >> 16) & 0xff;
379 cdb[12] = (len >> 8) & 0xff;
380 cdb[13] = (len) & 0xff;
381}
382
383/*
384 * Utility functions
385 */
386static uint64_t megasas_fw_time(void)
387{
388 struct tm curtime;
389 uint64_t bcd_time;
390
391 qemu_get_timedate(&curtime, 0);
392 bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 |
393 ((uint64_t)curtime.tm_min & 0xff) << 40 |
394 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
395 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
396 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
397 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
398
399 return bcd_time;
400}
401
76b523db
HR		 402/*
403 * Default disk sata address
404 * 0x1221 is the magic number as
405 * present in real hardware,
406 * so use it here, too.
407 */
408static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 409{
76b523db
HR		 410 uint64_t addr = (0x1221ULL << 48);
411 return addr & (id << 24);
e8f943c3
HR		 412}
413
414/*
415 * Frame handling
416 */
417static int megasas_next_index(MegasasState *s, int index, int limit)
418{
419 index++;
420 if (index == limit) {
421 index = 0;
422 }
423 return index;
424}
425
426static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 427 hwaddr frame)
e8f943c3
HR		 428{
429 MegasasCmd *cmd = NULL;
430 int num = 0, index;
431
432 index = s->reply_queue_head;
433
434 while (num < s->fw_cmds) {
435 if (s->frames[index].pa && s->frames[index].pa == frame) {
436 cmd = &s->frames[index];
437 break;
438 }
439 index = megasas_next_index(s, index, s->fw_cmds);
440 num++;
441 }
442
443 return cmd;
444}
445
446static MegasasCmd *megasas_next_frame(MegasasState *s,
a8170e5e 447 hwaddr frame)
e8f943c3
HR		 448{
449 MegasasCmd *cmd = NULL;
450 int num = 0, index;
451
452 cmd = megasas_lookup_frame(s, frame);
453 if (cmd) {
454 trace_megasas_qf_found(cmd->index, cmd->pa);
455 return cmd;
456 }
457 index = s->reply_queue_head;
458 num = 0;
459 while (num < s->fw_cmds) {
460 if (!s->frames[index].pa) {
461 cmd = &s->frames[index];
462 break;
463 }
464 index = megasas_next_index(s, index, s->fw_cmds);
465 num++;
466 }
467 if (!cmd) {
468 trace_megasas_qf_failed(frame);
469 }
470 trace_megasas_qf_new(index, cmd);
471 return cmd;
472}
473
474static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 475 hwaddr frame, uint64_t context, int count)
e8f943c3 476{
1016b239 477 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3
HR		 478 MegasasCmd *cmd = NULL;
479 int frame_size = MFI_FRAME_SIZE * 16;
a8170e5e 480 hwaddr frame_size_p = frame_size;
e8f943c3
HR		 481
482 cmd = megasas_next_frame(s, frame);
483 /* All frames busy */
484 if (!cmd) {
485 return NULL;
486 }
487 if (!cmd->pa) {
488 cmd->pa = frame;
489 /* Map all possible frames */
1016b239 490 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
e8f943c3
HR		 491 if (frame_size_p != frame_size) {
492 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
493 if (cmd->frame) {
1016b239 494 pci_dma_unmap(pcid, cmd->frame, frame_size_p, 0, 0);
e8f943c3
HR		 495 cmd->frame = NULL;
496 cmd->pa = 0;
497 }
498 s->event_count++;
499 return NULL;
500 }
501 cmd->pa_size = frame_size_p;
502 cmd->context = context;
503 if (!megasas_use_queue64(s)) {
504 cmd->context &= (uint64_t)0xFFFFFFFF;
505 }
506 }
507 cmd->count = count;
508 s->busy++;
509
510 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
511 s->reply_queue_head, s->busy);
512
513 return cmd;
514}
515
516static void megasas_complete_frame(MegasasState *s, uint64_t context)
517{
52190c1e 518 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 519 int tail, queue_offset;
520
521 /* Decrement busy count */
522 s->busy--;
523
524 if (s->reply_queue_pa) {
525 /*
526 * Put command on the reply queue.
527 * Context is opaque, but emulation is running in
528 * little endian. So convert it.
529 */
530 tail = s->reply_queue_head;
531 if (megasas_use_queue64(s)) {
532 queue_offset = tail * sizeof(uint64_t);
f606604f
EI		 533 stq_le_phys(&address_space_memory,
534 s->reply_queue_pa + queue_offset, context);
e8f943c3
HR		 535 } else {
536 queue_offset = tail * sizeof(uint32_t);
ab1da857
EI		 537 stl_le_phys(&address_space_memory,
538 s->reply_queue_pa + queue_offset, context);
e8f943c3
HR		 539 }
540 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
541 trace_megasas_qf_complete(context, tail, queue_offset,
542 s->busy, s->doorbell);
543 }
544
545 if (megasas_intr_enabled(s)) {
546 /* Notify HBA */
547 s->doorbell++;
548 if (s->doorbell == 1) {
52190c1e 549 if (msix_enabled(pci_dev)) {
e8f943c3 550 trace_megasas_msix_raise(0);
52190c1e 551 msix_notify(pci_dev, 0);
4522b69c
HR		 552 } else if (msi_enabled(pci_dev)) {
553 trace_megasas_msi_raise(0);
554 msi_notify(pci_dev, 0);
e8f943c3
HR		 555 } else {
556 trace_megasas_irq_raise();
9e64f8a3 557 pci_irq_assert(pci_dev);
e8f943c3
HR		 558 }
559 }
560 } else {
561 trace_megasas_qf_complete_noirq(context);
562 }
563}
564
565static void megasas_reset_frames(MegasasState *s)
566{
1016b239 567 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3
HR		 568 int i;
569 MegasasCmd *cmd;
570
571 for (i = 0; i < s->fw_cmds; i++) {
572 cmd = &s->frames[i];
573 if (cmd->pa) {
1016b239 574 pci_dma_unmap(pcid, cmd->frame, cmd->pa_size, 0, 0);
e8f943c3
HR		 575 cmd->frame = NULL;
576 cmd->pa = 0;
577 }
578 }
579}
580
581static void megasas_abort_command(MegasasCmd *cmd)
582{
583 if (cmd->req) {
e2b06058 584 scsi_req_cancel(cmd->req);
e8f943c3
HR		 585 cmd->req = NULL;
586 }
587}
588
589static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
590{
1016b239 591 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3 592 uint32_t pa_hi, pa_lo;
a8170e5e 593 hwaddr iq_pa, initq_size;
e8f943c3
HR		 594 struct mfi_init_qinfo *initq;
595 uint32_t flags;
596 int ret = MFI_STAT_OK;
597
598 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
599 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
600 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
601 trace_megasas_init_firmware((uint64_t)iq_pa);
602 initq_size = sizeof(*initq);
1016b239 603 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
e8f943c3
HR		 604 if (!initq || initq_size != sizeof(*initq)) {
605 trace_megasas_initq_map_failed(cmd->index);
606 s->event_count++;
607 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
608 goto out;
609 }
610 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
611 if (s->reply_queue_len > s->fw_cmds) {
612 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
613 s->event_count++;
614 ret = MFI_STAT_INVALID_PARAMETER;
615 goto out;
616 }
617 pa_lo = le32_to_cpu(initq->rq_addr_lo);
618 pa_hi = le32_to_cpu(initq->rq_addr_hi);
619 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
620 pa_lo = le32_to_cpu(initq->ci_addr_lo);
621 pa_hi = le32_to_cpu(initq->ci_addr_hi);
622 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
623 pa_lo = le32_to_cpu(initq->pi_addr_lo);
624 pa_hi = le32_to_cpu(initq->pi_addr_hi);
625 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
fdfba1a2
EI		 626 s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
627 s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
e8f943c3
HR		 628 flags = le32_to_cpu(initq->flags);
629 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
630 s->flags |= MEGASAS_MASK_USE_QUEUE64;
631 }
632 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
633 s->reply_queue_len, s->reply_queue_head,
634 s->reply_queue_tail, flags);
635 megasas_reset_frames(s);
636 s->fw_state = MFI_FWSTATE_OPERATIONAL;
637out:
638 if (initq) {
1016b239 639 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
e8f943c3
HR		 640 }
641 return ret;
642}
643
644static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
645{
646 dma_addr_t iov_pa, iov_size;
647
648 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
649 if (!cmd->frame->header.sge_count) {
650 trace_megasas_dcmd_zero_sge(cmd->index);
651 cmd->iov_size = 0;
652 return 0;
653 } else if (cmd->frame->header.sge_count > 1) {
654 trace_megasas_dcmd_invalid_sge(cmd->index,
655 cmd->frame->header.sge_count);
656 cmd->iov_size = 0;
657 return -1;
658 }
659 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
660 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 661 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 662 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
663 cmd->iov_size = iov_size;
664 return cmd->iov_size;
665}
666
667static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
668{
669 trace_megasas_finish_dcmd(cmd->index, iov_size);
670
671 if (cmd->frame->header.sge_count) {
672 qemu_sglist_destroy(&cmd->qsg);
673 }
674 if (iov_size > cmd->iov_size) {
675 if (megasas_frame_is_ieee_sgl(cmd)) {
676 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
677 } else if (megasas_frame_is_sgl64(cmd)) {
678 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
679 } else {
680 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
681 }
682 }
683 cmd->iov_size = 0;
e8f943c3
HR		 684}
685
686static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
687{
52190c1e 688 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 689 struct mfi_ctrl_info info;
690 size_t dcmd_size = sizeof(info);
691 BusChild *kid;
692 int num_ld_disks = 0;
76b523db 693 uint16_t sdev_id;
e8f943c3
HR		 694
695 memset(&info, 0x0, cmd->iov_size);
696 if (cmd->iov_size < dcmd_size) {
697 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
698 dcmd_size);
699 return MFI_STAT_INVALID_PARAMETER;
700 }
701
702 info.pci.vendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC);
703 info.pci.device = cpu_to_le16(PCI_DEVICE_ID_LSI_SAS1078);
704 info.pci.subvendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC);
705 info.pci.subdevice = cpu_to_le16(0x1013);
706
76b523db
HR		 707 /*
708 * For some reason the firmware supports
709 * only up to 8 device ports.
710 * Despite supporting a far larger number
711 * of devices for the physical devices.
712 * So just display the first 8 devices
713 * in the device port list, independent
714 * of how many logical devices are actually
715 * present.
716 */
717 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 718 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 719 info.device.port_count = 8;
720 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
721 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
722
723 if (num_ld_disks < 8) {
724 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
725 info.device.port_addr[num_ld_disks] =
726 cpu_to_le64(megasas_get_sata_addr(sdev_id));
727 }
728 num_ld_disks++;
729 }
e8f943c3
HR		 730
731 memcpy(info.product_name, "MegaRAID SAS 8708EM2", 20);
fb654157 732 snprintf(info.serial_number, 32, "%s", s->hba_serial);
e8f943c3
HR		 733 snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION);
734 memcpy(info.image_component[0].name, "APP", 3);
735 memcpy(info.image_component[0].version, MEGASAS_VERSION "-QEMU", 9);
5a7733b0
OH		 736 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
737 memcpy(info.image_component[0].build_time, "12:34:56", 8);
e8f943c3 738 info.image_component_count = 1;
52190c1e 739 if (pci_dev->has_rom) {
e8f943c3
HR		 740 uint8_t biosver[32];
741 uint8_t *ptr;
742
52190c1e 743 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 744 memcpy(biosver, ptr + 0x41, 31);
e8f943c3
HR		 745 memcpy(info.image_component[1].name, "BIOS", 4);
746 memcpy(info.image_component[1].version, biosver,
747 strlen((const char *)biosver));
748 info.image_component_count++;
749 }
750 info.current_fw_time = cpu_to_le32(megasas_fw_time());
751 info.max_arms = 32;
752 info.max_spans = 8;
753 info.max_arrays = MEGASAS_MAX_ARRAYS;
754 info.max_lds = s->fw_luns;
755 info.max_cmds = cpu_to_le16(s->fw_cmds);
756 info.max_sg_elements = cpu_to_le16(s->fw_sge);
757 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
758 info.lds_present = cpu_to_le16(num_ld_disks);
759 info.pd_present = cpu_to_le16(num_ld_disks);
760 info.pd_disks_present = cpu_to_le16(num_ld_disks);
761 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
762 MFI_INFO_HW_MEM |
763 MFI_INFO_HW_FLASH);
764 info.memory_size = cpu_to_le16(512);
765 info.nvram_size = cpu_to_le16(32);
766 info.flash_size = cpu_to_le16(16);
767 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
768 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
769 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
770 MFI_INFO_AOPS_MIXED_ARRAY);
771 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
772 MFI_INFO_LDOPS_ACCESS_POLICY |
773 MFI_INFO_LDOPS_IO_POLICY |
774 MFI_INFO_LDOPS_WRITE_POLICY |
775 MFI_INFO_LDOPS_READ_POLICY);
776 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
777 info.stripe_sz_ops.min = 3;
778 info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1;
779 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
780 info.properties.intr_throttle_cnt = cpu_to_le16(16);
781 info.properties.intr_throttle_timeout = cpu_to_le16(50);
782 info.properties.rebuild_rate = 30;
783 info.properties.patrol_read_rate = 30;
784 info.properties.bgi_rate = 30;
785 info.properties.cc_rate = 30;
786 info.properties.recon_rate = 30;
787 info.properties.cache_flush_interval = 4;
788 info.properties.spinup_drv_cnt = 2;
789 info.properties.spinup_delay = 6;
790 info.properties.ecc_bucket_size = 15;
791 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
792 info.properties.expose_encl_devices = 1;
793 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
794 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
795 MFI_INFO_PDOPS_FORCE_OFFLINE);
796 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
797 MFI_INFO_PDMIX_SATA |
798 MFI_INFO_PDMIX_LD);
799
800 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
801 return MFI_STAT_OK;
802}
803
804static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
805{
806 struct mfi_defaults info;
807 size_t dcmd_size = sizeof(struct mfi_defaults);
808
809 memset(&info, 0x0, dcmd_size);
810 if (cmd->iov_size < dcmd_size) {
811 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
812 dcmd_size);
813 return MFI_STAT_INVALID_PARAMETER;
814 }
815
76b523db 816 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 817 info.stripe_size = 3;
818 info.flush_time = 4;
819 info.background_rate = 30;
820 info.allow_mix_in_enclosure = 1;
821 info.allow_mix_in_ld = 1;
822 info.direct_pd_mapping = 1;
823 /* Enable for BIOS support */
824 info.bios_enumerate_lds = 1;
825 info.disable_ctrl_r = 1;
826 info.expose_enclosure_devices = 1;
827 info.disable_preboot_cli = 1;
828 info.cluster_disable = 1;
829
830 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
831 return MFI_STAT_OK;
832}
833
834static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
835{
836 struct mfi_bios_data info;
837 size_t dcmd_size = sizeof(info);
838
839 memset(&info, 0x0, dcmd_size);
840 if (cmd->iov_size < dcmd_size) {
841 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
842 dcmd_size);
843 return MFI_STAT_INVALID_PARAMETER;
844 }
845 info.continue_on_error = 1;
846 info.verbose = 1;
847 if (megasas_is_jbod(s)) {
848 info.expose_all_drives = 1;
849 }
850
851 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
852 return MFI_STAT_OK;
853}
854
855static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
856{
857 uint64_t fw_time;
858 size_t dcmd_size = sizeof(fw_time);
859
860 fw_time = cpu_to_le64(megasas_fw_time());
861
862 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
863 return MFI_STAT_OK;
864}
865
866static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
867{
868 uint64_t fw_time;
869
870 /* This is a dummy; setting of firmware time is not allowed */
871 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
872
873 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
874 fw_time = cpu_to_le64(megasas_fw_time());
875 return MFI_STAT_OK;
876}
877
878static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
879{
880 struct mfi_evt_log_state info;
881 size_t dcmd_size = sizeof(info);
882
883 memset(&info, 0, dcmd_size);
884
885 info.newest_seq_num = cpu_to_le32(s->event_count);
886 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
887 info.boot_seq_num = cpu_to_le32(s->boot_event);
888
889 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
890 return MFI_STAT_OK;
891}
892
893static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
894{
895 union mfi_evt event;
896
897 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
898 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
899 sizeof(struct mfi_evt_detail));
900 return MFI_STAT_INVALID_PARAMETER;
901 }
902 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
903 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
904 s->event_locale = event.members.locale;
905 s->event_class = event.members.class;
906 s->event_cmd = cmd;
907 /* Decrease busy count; event frame doesn't count here */
908 s->busy--;
909 cmd->iov_size = sizeof(struct mfi_evt_detail);
910 return MFI_STAT_INVALID_STATUS;
911}
912
913static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
914{
915 struct mfi_pd_list info;
916 size_t dcmd_size = sizeof(info);
917 BusChild *kid;
918 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
919 uint16_t sdev_id;
920
921 memset(&info, 0, dcmd_size);
922 offset = 8;
923 dcmd_limit = offset + sizeof(struct mfi_pd_address);
924 if (cmd->iov_size < dcmd_limit) {
925 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
926 dcmd_limit);
927 return MFI_STAT_INVALID_PARAMETER;
928 }
929
930 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
931 if (max_pd_disks > s->fw_luns) {
932 max_pd_disks = s->fw_luns;
933 }
934
935 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
936 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
937
938 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
939 info.addr[num_pd_disks].device_id = cpu_to_le16(sdev_id);
940 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
941 info.addr[num_pd_disks].encl_index = 0;
942 info.addr[num_pd_disks].slot_number = (sdev->id & 0xFF);
943 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
944 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
945 info.addr[num_pd_disks].sas_addr[0] =
76b523db 946 cpu_to_le64(megasas_get_sata_addr(sdev_id));
e8f943c3
HR		 947 num_pd_disks++;
948 offset += sizeof(struct mfi_pd_address);
949 }
950 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
951 max_pd_disks, offset);
952
953 info.size = cpu_to_le32(offset);
954 info.count = cpu_to_le32(num_pd_disks);
955
956 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
957 return MFI_STAT_OK;
958}
959
960static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
961{
962 uint16_t flags;
963
964 /* mbox0 contains flags */
965 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
966 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
967 if (flags == MR_PD_QUERY_TYPE_ALL ||
968 megasas_is_jbod(s)) {
969 return megasas_dcmd_pd_get_list(s, cmd);
970 }
971
972 return MFI_STAT_OK;
973}
974
975static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
976 MegasasCmd *cmd)
977{
978 struct mfi_pd_info *info = cmd->iov_buf;
979 size_t dcmd_size = sizeof(struct mfi_pd_info);
e8f943c3
HR		 980 uint64_t pd_size;
981 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF);
982 uint8_t cmdbuf[6];
983 SCSIRequest *req;
984 size_t len, resid;
985
986 if (!cmd->iov_buf) {
987 cmd->iov_buf = g_malloc(dcmd_size);
988 memset(cmd->iov_buf, 0, dcmd_size);
989 info = cmd->iov_buf;
990 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
991 info->vpd_page83[0] = 0x7f;
992 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
993 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
994 if (!req) {
995 trace_megasas_dcmd_req_alloc_failed(cmd->index,
996 "PD get info std inquiry");
997 g_free(cmd->iov_buf);
998 cmd->iov_buf = NULL;
999 return MFI_STAT_FLASH_ALLOC_FAIL;
1000 }
1001 trace_megasas_dcmd_internal_submit(cmd->index,
1002 "PD get info std inquiry", lun);
1003 len = scsi_req_enqueue(req);
1004 if (len > 0) {
1005 cmd->iov_size = len;
1006 scsi_req_continue(req);
1007 }
1008 return MFI_STAT_INVALID_STATUS;
1009 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1010 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1011 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1012 if (!req) {
1013 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1014 "PD get info vpd inquiry");
1015 return MFI_STAT_FLASH_ALLOC_FAIL;
1016 }
1017 trace_megasas_dcmd_internal_submit(cmd->index,
1018 "PD get info vpd inquiry", lun);
1019 len = scsi_req_enqueue(req);
1020 if (len > 0) {
1021 cmd->iov_size = len;
1022 scsi_req_continue(req);
1023 }
1024 return MFI_STAT_INVALID_STATUS;
1025 }
1026 /* Finished, set FW state */
1027 if ((info->inquiry_data[0] >> 5) == 0) {
1028 if (megasas_is_jbod(cmd->state)) {
1029 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1030 } else {
1031 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1032 }
1033 } else {
1034 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1035 }
1036
1037 info->ref.v.device_id = cpu_to_le16(sdev_id);
1038 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1039 MFI_PD_DDF_TYPE_INTF_SAS);
4be74634 1040 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1041 info->raw_size = cpu_to_le64(pd_size);
1042 info->non_coerced_size = cpu_to_le64(pd_size);
1043 info->coerced_size = cpu_to_le64(pd_size);
1044 info->encl_device_id = 0xFFFF;
1045 info->slot_number = (sdev->id & 0xFF);
1046 info->path_info.count = 1;
1047 info->path_info.sas_addr[0] =
76b523db 1048 cpu_to_le64(megasas_get_sata_addr(sdev_id));
e8f943c3
HR		 1049 info->connected_port_bitmap = 0x1;
1050 info->device_speed = 1;
1051 info->link_speed = 1;
1052 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1053 g_free(cmd->iov_buf);
1054 cmd->iov_size = dcmd_size - resid;
1055 cmd->iov_buf = NULL;
1056 return MFI_STAT_OK;
1057}
1058
1059static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1060{
1061 size_t dcmd_size = sizeof(struct mfi_pd_info);
1062 uint16_t pd_id;
1063 SCSIDevice *sdev = NULL;
1064 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1065
1066 if (cmd->iov_size < dcmd_size) {
1067 return MFI_STAT_INVALID_PARAMETER;
1068 }
1069
1070 /* mbox0 has the ID */
1071 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1072 sdev = scsi_device_find(&s->bus, 0, pd_id, 0);
1073 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1074
1075 if (sdev) {
1076 /* Submit inquiry */
1077 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1078 }
1079
1080 return retval;
1081}
1082
1083static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1084{
1085 struct mfi_ld_list info;
1086 size_t dcmd_size = sizeof(info), resid;
1087 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1088 uint64_t ld_size;
1089 BusChild *kid;
1090
1091 memset(&info, 0, dcmd_size);
1092 if (cmd->iov_size < dcmd_size) {
1093 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1094 dcmd_size);
1095 return MFI_STAT_INVALID_PARAMETER;
1096 }
1097
1098 if (megasas_is_jbod(s)) {
1099 max_ld_disks = 0;
1100 }
1101 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1102 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
e8f943c3
HR		 1103
1104 if (num_ld_disks >= max_ld_disks) {
1105 break;
1106 }
1107 /* Logical device size is in blocks */
4be74634 1108 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3 1109 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
4003e24f 1110 info.ld_list[num_ld_disks].ld.v.lun_id = sdev->lun;
e8f943c3
HR		 1111 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1112 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1113 num_ld_disks++;
1114 }
1115 info.ld_count = cpu_to_le32(num_ld_disks);
1116 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1117
1118 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1119 cmd->iov_size = dcmd_size - resid;
1120 return MFI_STAT_OK;
1121}
1122
34bb4d02
HR		 1123static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1124{
1125 uint16_t flags;
1126
1127 /* mbox0 contains flags */
1128 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1129 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1130 if (flags == MR_LD_QUERY_TYPE_ALL ||
1131 flags == MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1132 return megasas_dcmd_ld_get_list(s, cmd);
1133 }
1134
1135 return MFI_STAT_OK;
1136}
1137
e8f943c3
HR		 1138static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1139 MegasasCmd *cmd)
1140{
1141 struct mfi_ld_info *info = cmd->iov_buf;
1142 size_t dcmd_size = sizeof(struct mfi_ld_info);
1143 uint8_t cdb[6];
1144 SCSIRequest *req;
1145 ssize_t len, resid;
e8f943c3
HR		 1146 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF);
1147 uint64_t ld_size;
1148
1149 if (!cmd->iov_buf) {
1150 cmd->iov_buf = g_malloc(dcmd_size);
1151 memset(cmd->iov_buf, 0x0, dcmd_size);
1152 info = cmd->iov_buf;
1153 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1154 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1155 if (!req) {
1156 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1157 "LD get info vpd inquiry");
1158 g_free(cmd->iov_buf);
1159 cmd->iov_buf = NULL;
1160 return MFI_STAT_FLASH_ALLOC_FAIL;
1161 }
1162 trace_megasas_dcmd_internal_submit(cmd->index,
1163 "LD get info vpd inquiry", lun);
1164 len = scsi_req_enqueue(req);
1165 if (len > 0) {
1166 cmd->iov_size = len;
1167 scsi_req_continue(req);
1168 }
1169 return MFI_STAT_INVALID_STATUS;
1170 }
1171
1172 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1173 info->ld_config.properties.ld.v.target_id = lun;
1174 info->ld_config.params.stripe_size = 3;
1175 info->ld_config.params.num_drives = 1;
1176 info->ld_config.params.is_consistent = 1;
1177 /* Logical device size is in blocks */
4be74634 1178 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1179 info->size = cpu_to_le64(ld_size);
1180 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1181 info->ld_config.span[0].start_block = 0;
1182 info->ld_config.span[0].num_blocks = info->size;
1183 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1184
1185 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1186 g_free(cmd->iov_buf);
1187 cmd->iov_size = dcmd_size - resid;
1188 cmd->iov_buf = NULL;
1189 return MFI_STAT_OK;
1190}
1191
1192static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1193{
1194 struct mfi_ld_info info;
1195 size_t dcmd_size = sizeof(info);
1196 uint16_t ld_id;
1197 uint32_t max_ld_disks = s->fw_luns;
1198 SCSIDevice *sdev = NULL;
1199 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1200
1201 if (cmd->iov_size < dcmd_size) {
1202 return MFI_STAT_INVALID_PARAMETER;
1203 }
1204
1205 /* mbox0 has the ID */
1206 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1207 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1208
1209 if (megasas_is_jbod(s)) {
1210 return MFI_STAT_DEVICE_NOT_FOUND;
1211 }
1212
1213 if (ld_id < max_ld_disks) {
1214 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1215 }
1216
1217 if (sdev) {
1218 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1219 }
1220
1221 return retval;
1222}
1223
1224static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1225{
1226 uint8_t data[4096];
1227 struct mfi_config_data *info;
1228 int num_pd_disks = 0, array_offset, ld_offset;
1229 BusChild *kid;
1230
1231 if (cmd->iov_size > 4096) {
1232 return MFI_STAT_INVALID_PARAMETER;
1233 }
1234
1235 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1236 num_pd_disks++;
1237 }
1238 info = (struct mfi_config_data *)&data;
1239 /*
1240 * Array mapping:
1241 * - One array per SCSI device
1242 * - One logical drive per SCSI device
1243 * spanning the entire device
1244 */
1245 info->array_count = num_pd_disks;
1246 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1247 info->log_drv_count = num_pd_disks;
1248 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1249 info->spares_count = 0;
1250 info->spares_size = sizeof(struct mfi_spare);
1251 info->size = sizeof(struct mfi_config_data) + info->array_size +
1252 info->log_drv_size;
1253 if (info->size > 4096) {
1254 return MFI_STAT_INVALID_PARAMETER;
1255 }
1256
1257 array_offset = sizeof(struct mfi_config_data);
1258 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1259
1260 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1261 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
e8f943c3
HR		 1262 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
1263 struct mfi_array *array;
1264 struct mfi_ld_config *ld;
1265 uint64_t pd_size;
1266 int i;
1267
1268 array = (struct mfi_array *)(data + array_offset);
4be74634 1269 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1270 array->size = cpu_to_le64(pd_size);
1271 array->num_drives = 1;
1272 array->array_ref = cpu_to_le16(sdev_id);
1273 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1274 array->pd[0].ref.v.seq_num = 0;
1275 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1276 array->pd[0].encl.pd = 0xFF;
1277 array->pd[0].encl.slot = (sdev->id & 0xFF);
1278 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1279 array->pd[i].ref.v.device_id = 0xFFFF;
1280 array->pd[i].ref.v.seq_num = 0;
1281 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1282 array->pd[i].encl.pd = 0xFF;
1283 array->pd[i].encl.slot = 0xFF;
1284 }
1285 array_offset += sizeof(struct mfi_array);
1286 ld = (struct mfi_ld_config *)(data + ld_offset);
1287 memset(ld, 0, sizeof(struct mfi_ld_config));
1288 ld->properties.ld.v.target_id = (sdev->id & 0xFF);
1289 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1290 MR_LD_CACHE_READ_ADAPTIVE;
1291 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1292 MR_LD_CACHE_READ_ADAPTIVE;
1293 ld->params.state = MFI_LD_STATE_OPTIMAL;
1294 ld->params.stripe_size = 3;
1295 ld->params.num_drives = 1;
1296 ld->params.span_depth = 1;
1297 ld->params.is_consistent = 1;
1298 ld->span[0].start_block = 0;
1299 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1300 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1301 ld_offset += sizeof(struct mfi_ld_config);
1302 }
1303
1304 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1305 return MFI_STAT_OK;
1306}
1307
1308static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1309{
1310 struct mfi_ctrl_props info;
1311 size_t dcmd_size = sizeof(info);
1312
1313 memset(&info, 0x0, dcmd_size);
1314 if (cmd->iov_size < dcmd_size) {
1315 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1316 dcmd_size);
1317 return MFI_STAT_INVALID_PARAMETER;
1318 }
1319 info.pred_fail_poll_interval = cpu_to_le16(300);
1320 info.intr_throttle_cnt = cpu_to_le16(16);
1321 info.intr_throttle_timeout = cpu_to_le16(50);
1322 info.rebuild_rate = 30;
1323 info.patrol_read_rate = 30;
1324 info.bgi_rate = 30;
1325 info.cc_rate = 30;
1326 info.recon_rate = 30;
1327 info.cache_flush_interval = 4;
1328 info.spinup_drv_cnt = 2;
1329 info.spinup_delay = 6;
1330 info.ecc_bucket_size = 15;
1331 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1332 info.expose_encl_devices = 1;
1333
1334 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1335 return MFI_STAT_OK;
1336}
1337
1338static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1339{
4be74634 1340 blk_drain_all();
e8f943c3
HR		 1341 return MFI_STAT_OK;
1342}
1343
1344static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1345{
1346 s->fw_state = MFI_FWSTATE_READY;
1347 return MFI_STAT_OK;
1348}
1349
1350static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1351{
1352 return MFI_STAT_INVALID_DCMD;
1353}
1354
1355static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1356{
10d6530c
HR		 1357 struct mfi_ctrl_props info;
1358 size_t dcmd_size = sizeof(info);
1359
1360 if (cmd->iov_size < dcmd_size) {
1361 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1362 dcmd_size);
1363 return MFI_STAT_INVALID_PARAMETER;
1364 }
1365 dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg);
1366 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1367 return MFI_STAT_OK;
1368}
1369
1370static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1371{
1372 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1373 return MFI_STAT_OK;
1374}
1375
1376static const struct dcmd_cmd_tbl_t {
1377 int opcode;
1378 const char *desc;
1379 int (*func)(MegasasState *s, MegasasCmd *cmd);
1380} dcmd_cmd_tbl[] = {
1381 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1382 megasas_dcmd_dummy },
1383 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1384 megasas_ctrl_get_info },
1385 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1386 megasas_dcmd_get_properties },
1387 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1388 megasas_dcmd_set_properties },
1389 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1390 megasas_dcmd_dummy },
1391 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1392 megasas_dcmd_dummy },
1393 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1394 megasas_dcmd_dummy },
1395 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1396 megasas_dcmd_dummy },
1397 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1398 megasas_dcmd_dummy },
1399 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1400 megasas_event_info },
1401 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1402 megasas_dcmd_dummy },
1403 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1404 megasas_event_wait },
1405 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1406 megasas_ctrl_shutdown },
1407 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1408 megasas_dcmd_dummy },
1409 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1410 megasas_dcmd_get_fw_time },
1411 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1412 megasas_dcmd_set_fw_time },
1413 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1414 megasas_dcmd_get_bios_info },
1415 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1416 megasas_dcmd_dummy },
1417 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1418 megasas_mfc_get_defaults },
1419 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1420 megasas_dcmd_dummy },
1421 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1422 megasas_cache_flush },
1423 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1424 megasas_dcmd_pd_get_list },
1425 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1426 megasas_dcmd_pd_list_query },
1427 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1428 megasas_dcmd_pd_get_info },
1429 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1430 megasas_dcmd_dummy },
1431 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1432 megasas_dcmd_dummy },
1433 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1434 megasas_dcmd_dummy },
1435 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1436 megasas_dcmd_dummy },
1437 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1438 megasas_dcmd_ld_get_list},
34bb4d02
HR		 1439 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1440 megasas_dcmd_ld_list_query },
e8f943c3
HR		 1441 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1442 megasas_dcmd_ld_get_info },
1443 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1444 megasas_dcmd_dummy },
1445 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1446 megasas_dcmd_dummy },
1447 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1448 megasas_dcmd_dummy },
1449 { MFI_DCMD_CFG_READ, "CFG_READ",
1450 megasas_dcmd_cfg_read },
1451 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1452 megasas_dcmd_dummy },
1453 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1454 megasas_dcmd_dummy },
1455 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1456 megasas_dcmd_dummy },
1457 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1458 megasas_dcmd_dummy },
1459 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1460 megasas_dcmd_dummy },
1461 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1462 megasas_dcmd_dummy },
1463 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1464 megasas_dcmd_dummy },
1465 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1466 megasas_dcmd_dummy },
1467 { MFI_DCMD_CLUSTER, "CLUSTER",
1468 megasas_dcmd_dummy },
1469 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1470 megasas_dcmd_dummy },
1471 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1472 megasas_cluster_reset_ld },
1473 { -1, NULL, NULL }
1474};
1475
1476static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1477{
1478 int opcode, len;
1479 int retval = 0;
1480 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1481
1482 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1483 trace_megasas_handle_dcmd(cmd->index, opcode);
1484 len = megasas_map_dcmd(s, cmd);
1485 if (len < 0) {
1486 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1487 }
1488 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1489 cmdptr++;
1490 }
1491 if (cmdptr->opcode == -1) {
1492 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1493 retval = megasas_dcmd_dummy(s, cmd);
1494 } else {
1495 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1496 retval = cmdptr->func(s, cmd);
1497 }
1498 if (retval != MFI_STAT_INVALID_STATUS) {
1499 megasas_finish_dcmd(cmd, len);
1500 }
1501 return retval;
1502}
1503
1504static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1505 SCSIRequest *req)
1506{
1507 int opcode;
1508 int retval = MFI_STAT_OK;
1509 int lun = req->lun;
1510
1511 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1512 scsi_req_unref(req);
1513 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1514 switch (opcode) {
1515 case MFI_DCMD_PD_GET_INFO:
1516 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1517 break;
1518 case MFI_DCMD_LD_GET_INFO:
1519 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1520 break;
1521 default:
1522 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1523 retval = MFI_STAT_INVALID_DCMD;
1524 break;
1525 }
1526 if (retval != MFI_STAT_INVALID_STATUS) {
1527 megasas_finish_dcmd(cmd, cmd->iov_size);
1528 }
1529 return retval;
1530}
1531
1532static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1533{
1534 int len;
1535
1536 len = scsi_req_enqueue(cmd->req);
1537 if (len < 0) {
1538 len = -len;
1539 }
1540 if (len > 0) {
1541 if (len > cmd->iov_size) {
1542 if (is_write) {
1543 trace_megasas_iov_write_overflow(cmd->index, len,
1544 cmd->iov_size);
1545 } else {
1546 trace_megasas_iov_read_overflow(cmd->index, len,
1547 cmd->iov_size);
1548 }
1549 }
1550 if (len < cmd->iov_size) {
1551 if (is_write) {
1552 trace_megasas_iov_write_underflow(cmd->index, len,
1553 cmd->iov_size);
1554 } else {
1555 trace_megasas_iov_read_underflow(cmd->index, len,
1556 cmd->iov_size);
1557 }
1558 cmd->iov_size = len;
1559 }
1560 scsi_req_continue(cmd->req);
1561 }
1562 return len;
1563}
1564
1565static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1566 bool is_logical)
1567{
1568 uint8_t *cdb;
1569 int len;
1570 bool is_write;
1571 struct SCSIDevice *sdev = NULL;
1572
1573 cdb = cmd->frame->pass.cdb;
1574
1575 if (cmd->frame->header.target_id < s->fw_luns) {
1576 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1577 cmd->frame->header.lun_id);
1578 }
1579 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1580 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1581 is_logical, cmd->frame->header.target_id,
1582 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1583
1584 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1585 trace_megasas_scsi_target_not_present(
1586 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1587 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1588 return MFI_STAT_DEVICE_NOT_FOUND;
1589 }
1590
1591 if (cmd->frame->header.cdb_len > 16) {
1592 trace_megasas_scsi_invalid_cdb_len(
1593 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1594 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1595 cmd->frame->header.cdb_len);
1596 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1597 cmd->frame->header.scsi_status = CHECK_CONDITION;
1598 s->event_count++;
1599 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1600 }
1601
1602 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1603 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1604 cmd->frame->header.scsi_status = CHECK_CONDITION;
1605 s->event_count++;
1606 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1607 }
1608
1609 cmd->req = scsi_req_new(sdev, cmd->index,
1610 cmd->frame->header.lun_id, cdb, cmd);
1611 if (!cmd->req) {
1612 trace_megasas_scsi_req_alloc_failed(
1613 mfi_frame_desc[cmd->frame->header.frame_cmd],
1614 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1615 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1616 cmd->frame->header.scsi_status = BUSY;
1617 s->event_count++;
1618 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1619 }
1620
1621 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1622 len = megasas_enqueue_req(cmd, is_write);
1623 if (len > 0) {
1624 if (is_write) {
1625 trace_megasas_scsi_write_start(cmd->index, len);
1626 } else {
1627 trace_megasas_scsi_read_start(cmd->index, len);
1628 }
1629 } else {
1630 trace_megasas_scsi_nodata(cmd->index);
1631 }
1632 return MFI_STAT_INVALID_STATUS;
1633}
1634
1635static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1636{
1637 uint32_t lba_count, lba_start_hi, lba_start_lo;
1638 uint64_t lba_start;
1639 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1640 uint8_t cdb[16];
1641 int len;
1642 struct SCSIDevice *sdev = NULL;
1643
1644 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1645 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1646 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1647 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1648
1649 if (cmd->frame->header.target_id < s->fw_luns) {
1650 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1651 cmd->frame->header.lun_id);
1652 }
1653
1654 trace_megasas_handle_io(cmd->index,
1655 mfi_frame_desc[cmd->frame->header.frame_cmd],
1656 cmd->frame->header.target_id,
1657 cmd->frame->header.lun_id,
1658 (unsigned long)lba_start, (unsigned long)lba_count);
1659 if (!sdev) {
1660 trace_megasas_io_target_not_present(cmd->index,
1661 mfi_frame_desc[cmd->frame->header.frame_cmd],
1662 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1663 return MFI_STAT_DEVICE_NOT_FOUND;
1664 }
1665
1666 if (cmd->frame->header.cdb_len > 16) {
1667 trace_megasas_scsi_invalid_cdb_len(
1668 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1669 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1670 cmd->frame->header.cdb_len);
1671 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1672 cmd->frame->header.scsi_status = CHECK_CONDITION;
1673 s->event_count++;
1674 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1675 }
1676
1677 cmd->iov_size = lba_count * sdev->blocksize;
1678 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1679 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1680 cmd->frame->header.scsi_status = CHECK_CONDITION;
1681 s->event_count++;
1682 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1683 }
1684
1685 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1686 cmd->req = scsi_req_new(sdev, cmd->index,
1687 cmd->frame->header.lun_id, cdb, cmd);
1688 if (!cmd->req) {
1689 trace_megasas_scsi_req_alloc_failed(
1690 mfi_frame_desc[cmd->frame->header.frame_cmd],
1691 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1692 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1693 cmd->frame->header.scsi_status = BUSY;
1694 s->event_count++;
1695 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1696 }
1697 len = megasas_enqueue_req(cmd, is_write);
1698 if (len > 0) {
1699 if (is_write) {
1700 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1701 } else {
1702 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1703 }
1704 }
1705 return MFI_STAT_INVALID_STATUS;
1706}
1707
1708static int megasas_finish_internal_command(MegasasCmd *cmd,
1709 SCSIRequest *req, size_t resid)
1710{
1711 int retval = MFI_STAT_INVALID_CMD;
1712
1713 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1714 cmd->iov_size -= resid;
1715 retval = megasas_finish_internal_dcmd(cmd, req);
1716 }
1717 return retval;
1718}
1719
1720static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1721{
1722 MegasasCmd *cmd = req->hba_private;
1723
1724 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1725 return NULL;
1726 } else {
1727 return &cmd->qsg;
1728 }
1729}
1730
1731static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1732{
1733 MegasasCmd *cmd = req->hba_private;
1734 uint8_t *buf;
1735 uint32_t opcode;
1736
1737 trace_megasas_io_complete(cmd->index, len);
1738
1739 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1740 scsi_req_continue(req);
1741 return;
1742 }
1743
1744 buf = scsi_req_get_buf(req);
1745 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1746 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1747 struct mfi_pd_info *info = cmd->iov_buf;
1748
1749 if (info->inquiry_data[0] == 0x7f) {
1750 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1751 memcpy(info->inquiry_data, buf, len);
1752 } else if (info->vpd_page83[0] == 0x7f) {
1753 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1754 memcpy(info->vpd_page83, buf, len);
1755 }
1756 scsi_req_continue(req);
1757 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1758 struct mfi_ld_info *info = cmd->iov_buf;
1759
1760 if (cmd->iov_buf) {
1761 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1762 scsi_req_continue(req);
1763 }
1764 }
1765}
1766
1767static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1768 size_t resid)
1769{
1770 MegasasCmd *cmd = req->hba_private;
1771 uint8_t cmd_status = MFI_STAT_OK;
1772
1773 trace_megasas_command_complete(cmd->index, status, resid);
1774
1775 if (cmd->req != req) {
1776 /*
1777 * Internal command complete
1778 */
1779 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1780 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1781 return;
1782 }
1783 } else {
1784 req->status = status;
1785 trace_megasas_scsi_complete(cmd->index, req->status,
1786 cmd->iov_size, req->cmd.xfer);
1787 if (req->status != GOOD) {
1788 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1789 }
1790 if (req->status == CHECK_CONDITION) {
1791 megasas_copy_sense(cmd);
1792 }
1793
1794 megasas_unmap_sgl(cmd);
1795 cmd->frame->header.scsi_status = req->status;
1796 scsi_req_unref(cmd->req);
1797 cmd->req = NULL;
1798 }
1799 cmd->frame->header.cmd_status = cmd_status;
1800 megasas_complete_frame(cmd->state, cmd->context);
1801}
1802
1803static void megasas_command_cancel(SCSIRequest *req)
1804{
1805 MegasasCmd *cmd = req->hba_private;
1806
1807 if (cmd) {
1808 megasas_abort_command(cmd);
1809 } else {
1810 scsi_req_unref(req);
1811 }
1812}
1813
1814static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1815{
1816 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1817 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1818 MegasasCmd *abort_cmd;
1819
1820 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1821 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1822 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1823
1824 abort_cmd = megasas_lookup_frame(s, abort_addr);
1825 if (!abort_cmd) {
1826 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1827 s->event_count++;
1828 return MFI_STAT_OK;
1829 }
1830 if (!megasas_use_queue64(s)) {
1831 abort_ctx &= (uint64_t)0xFFFFFFFF;
1832 }
1833 if (abort_cmd->context != abort_ctx) {
1834 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1835 abort_cmd->context);
1836 s->event_count++;
1837 return MFI_STAT_ABORT_NOT_POSSIBLE;
1838 }
1839 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1840 megasas_abort_command(abort_cmd);
1841 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1842 s->event_cmd = NULL;
1843 }
1844 s->event_count++;
1845 return MFI_STAT_OK;
1846}
1847
1848static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1849 uint32_t frame_count)
1850{
1851 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1852 uint64_t frame_context;
1853 MegasasCmd *cmd;
1854
1855 /*
1856 * Always read 64bit context, top bits will be
1857 * masked out if required in megasas_enqueue_frame()
1858 */
1859 frame_context = megasas_frame_get_context(frame_addr);
1860
1861 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1862 if (!cmd) {
1863 /* reply queue full */
1864 trace_megasas_frame_busy(frame_addr);
1865 megasas_frame_set_scsi_status(frame_addr, BUSY);
1866 megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1867 megasas_complete_frame(s, frame_context);
1868 s->event_count++;
1869 return;
1870 }
1871 switch (cmd->frame->header.frame_cmd) {
1872 case MFI_CMD_INIT:
1873 frame_status = megasas_init_firmware(s, cmd);
1874 break;
1875 case MFI_CMD_DCMD:
1876 frame_status = megasas_handle_dcmd(s, cmd);
1877 break;
1878 case MFI_CMD_ABORT:
1879 frame_status = megasas_handle_abort(s, cmd);
1880 break;
1881 case MFI_CMD_PD_SCSI_IO:
1882 frame_status = megasas_handle_scsi(s, cmd, 0);
1883 break;
1884 case MFI_CMD_LD_SCSI_IO:
1885 frame_status = megasas_handle_scsi(s, cmd, 1);
1886 break;
1887 case MFI_CMD_LD_READ:
1888 case MFI_CMD_LD_WRITE:
1889 frame_status = megasas_handle_io(s, cmd);
1890 break;
1891 default:
1892 trace_megasas_unhandled_frame_cmd(cmd->index,
1893 cmd->frame->header.frame_cmd);
1894 s->event_count++;
1895 break;
1896 }
1897 if (frame_status != MFI_STAT_INVALID_STATUS) {
1898 if (cmd->frame) {
1899 cmd->frame->header.cmd_status = frame_status;
1900 } else {
1901 megasas_frame_set_cmd_status(frame_addr, frame_status);
1902 }
1903 megasas_complete_frame(s, cmd->context);
1904 }
1905}
1906
a8170e5e 1907static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 1908 unsigned size)
1909{
1910 MegasasState *s = opaque;
1911 uint32_t retval = 0;
1912
1913 switch (addr) {
1914 case MFI_IDB:
1915 retval = 0;
1916 break;
1917 case MFI_OMSG0:
1918 case MFI_OSP0:
1919 retval = (megasas_use_msix(s) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
1920 (s->fw_state & MFI_FWSTATE_MASK) |
1921 ((s->fw_sge & 0xff) << 16) |
1922 (s->fw_cmds & 0xFFFF);
1923 break;
1924 case MFI_OSTS:
1925 if (megasas_intr_enabled(s) && s->doorbell) {
1926 retval = MFI_1078_RM | 1;
1927 }
1928 break;
1929 case MFI_OMSK:
1930 retval = s->intr_mask;
1931 break;
1932 case MFI_ODCR0:
1933 retval = s->doorbell;
1934 break;
1935 default:
1936 trace_megasas_mmio_invalid_readl(addr);
1937 break;
1938 }
1939 trace_megasas_mmio_readl(addr, retval);
1940 return retval;
1941}
1942
a8170e5e 1943static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 1944 uint64_t val, unsigned size)
1945{
1946 MegasasState *s = opaque;
52190c1e 1947 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 1948 uint64_t frame_addr;
1949 uint32_t frame_count;
1950 int i;
1951
1952 trace_megasas_mmio_writel(addr, val);
1953 switch (addr) {
1954 case MFI_IDB:
1955 if (val & MFI_FWINIT_ABORT) {
1956 /* Abort all pending cmds */
1957 for (i = 0; i < s->fw_cmds; i++) {
1958 megasas_abort_command(&s->frames[i]);
1959 }
1960 }
1961 if (val & MFI_FWINIT_READY) {
1962 /* move to FW READY */
1963 megasas_soft_reset(s);
1964 }
1965 if (val & MFI_FWINIT_MFIMODE) {
1966 /* discard MFIs */
1967 }
1968 break;
1969 case MFI_OMSK:
1970 s->intr_mask = val;
4522b69c
HR		 1971 if (!megasas_intr_enabled(s) &&
1972 !msi_enabled(pci_dev) &&
1973 !msix_enabled(pci_dev)) {
e8f943c3 1974 trace_megasas_irq_lower();
9e64f8a3 1975 pci_irq_deassert(pci_dev);
e8f943c3
HR		 1976 }
1977 if (megasas_intr_enabled(s)) {
4522b69c
HR		 1978 if (msix_enabled(pci_dev)) {
1979 trace_megasas_msix_enabled(0);
1980 } else if (msi_enabled(pci_dev)) {
1981 trace_megasas_msi_enabled(0);
1982 } else {
1983 trace_megasas_intr_enabled();
1984 }
e8f943c3
HR		 1985 } else {
1986 trace_megasas_intr_disabled();
1987 }
1988 break;
1989 case MFI_ODCR0:
1990 s->doorbell = 0;
1991 if (s->producer_pa && megasas_intr_enabled(s)) {
1992 /* Update reply queue pointer */
1993 trace_megasas_qf_update(s->reply_queue_head, s->busy);
ab1da857
EI		 1994 stl_le_phys(&address_space_memory,
1995 s->producer_pa, s->reply_queue_head);
52190c1e 1996 if (!msix_enabled(pci_dev)) {
e8f943c3 1997 trace_megasas_irq_lower();
9e64f8a3 1998 pci_irq_deassert(pci_dev);
e8f943c3
HR		 1999 }
2000 }
2001 break;
2002 case MFI_IQPH:
2003 /* Received high 32 bits of a 64 bit MFI frame address */
2004 s->frame_hi = val;
2005 break;
2006 case MFI_IQPL:
2007 /* Received low 32 bits of a 64 bit MFI frame address */
2008 case MFI_IQP:
2009 /* Received 32 bit MFI frame address */
2010 frame_addr = (val & ~0x1F);
2011 /* Add possible 64 bit offset */
2012 frame_addr |= ((uint64_t)s->frame_hi << 32);
2013 s->frame_hi = 0;
2014 frame_count = (val >> 1) & 0xF;
2015 megasas_handle_frame(s, frame_addr, frame_count);
2016 break;
2017 default:
2018 trace_megasas_mmio_invalid_writel(addr, val);
2019 break;
2020 }
2021}
2022
2023static const MemoryRegionOps megasas_mmio_ops = {
2024 .read = megasas_mmio_read,
2025 .write = megasas_mmio_write,
2026 .endianness = DEVICE_LITTLE_ENDIAN,
2027 .impl = {
2028 .min_access_size = 8,
2029 .max_access_size = 8,
2030 }
2031};
2032
a8170e5e 2033static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2034 unsigned size)
2035{
2036 return megasas_mmio_read(opaque, addr & 0xff, size);
2037}
2038
a8170e5e 2039static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2040 uint64_t val, unsigned size)
2041{
2042 megasas_mmio_write(opaque, addr & 0xff, val, size);
2043}
2044
2045static const MemoryRegionOps megasas_port_ops = {
2046 .read = megasas_port_read,
2047 .write = megasas_port_write,
2048 .endianness = DEVICE_LITTLE_ENDIAN,
2049 .impl = {
2050 .min_access_size = 4,
2051 .max_access_size = 4,
2052 }
2053};
2054
a8170e5e 2055static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2056 unsigned size)
2057{
2058 return 0;
2059}
2060
2061static const MemoryRegionOps megasas_queue_ops = {
2062 .read = megasas_queue_read,
2063 .endianness = DEVICE_LITTLE_ENDIAN,
2064 .impl = {
2065 .min_access_size = 8,
2066 .max_access_size = 8,
2067 }
2068};
2069
2070static void megasas_soft_reset(MegasasState *s)
2071{
2072 int i;
2073 MegasasCmd *cmd;
2074
2075 trace_megasas_reset();
2076 for (i = 0; i < s->fw_cmds; i++) {
2077 cmd = &s->frames[i];
2078 megasas_abort_command(cmd);
2079 }
2080 megasas_reset_frames(s);
2081 s->reply_queue_len = s->fw_cmds;
2082 s->reply_queue_pa = 0;
2083 s->consumer_pa = 0;
2084 s->producer_pa = 0;
2085 s->fw_state = MFI_FWSTATE_READY;
2086 s->doorbell = 0;
2087 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2088 s->frame_hi = 0;
2089 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2090 s->event_count++;
2091 s->boot_event = s->event_count;
2092}
2093
2094static void megasas_scsi_reset(DeviceState *dev)
2095{
c79e16ae 2096 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2097
2098 megasas_soft_reset(s);
2099}
2100
2101static const VMStateDescription vmstate_megasas = {
2102 .name = "megasas",
2103 .version_id = 0,
2104 .minimum_version_id = 0,
d49805ae 2105 .fields = (VMStateField[]) {
52190c1e 2106 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
23335f62 2107 VMSTATE_MSIX(parent_obj, MegasasState),
e8f943c3
HR		 2108
2109 VMSTATE_INT32(fw_state, MegasasState),
2110 VMSTATE_INT32(intr_mask, MegasasState),
2111 VMSTATE_INT32(doorbell, MegasasState),
2112 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2113 VMSTATE_UINT64(consumer_pa, MegasasState),
2114 VMSTATE_UINT64(producer_pa, MegasasState),
2115 VMSTATE_END_OF_LIST()
2116 }
2117};
2118
18fc611b 2119static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2120{
c79e16ae 2121 MegasasState *s = MEGASAS(d);
e8f943c3 2122
4522b69c
HR		 2123 if (megasas_use_msix(s)) {
2124 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2125 }
2126 if (megasas_use_msi(s)) {
2127 msi_uninit(d);
2128 }
e8f943c3
HR		 2129}
2130
2131static const struct SCSIBusInfo megasas_scsi_info = {
2132 .tcq = true,
2133 .max_target = MFI_MAX_LD,
2134 .max_lun = 255,
2135
2136 .transfer_data = megasas_xfer_complete,
2137 .get_sg_list = megasas_get_sg_list,
2138 .complete = megasas_command_complete,
2139 .cancel = megasas_command_cancel,
2140};
2141
2142static int megasas_scsi_init(PCIDevice *dev)
2143{
22d6aa03 2144 DeviceState *d = DEVICE(dev);
c79e16ae 2145 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2146 uint8_t *pci_conf;
2147 int i, bar_type;
caad4eb3 2148 Error *err = NULL;
e8f943c3 2149
52190c1e 2150 pci_conf = dev->config;
e8f943c3
HR		 2151
2152 /* PCI latency timer = 0 */
2153 pci_conf[PCI_LATENCY_TIMER] = 0;
2154 /* Interrupt pin 1 */
2155 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2156
29776739 2157 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2158 "megasas-mmio", 0x4000);
29776739 2159 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2160 "megasas-io", 256);
29776739 2161 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2162 "megasas-queue", 0x40000);
2163
4522b69c
HR		 2164 if (megasas_use_msi(s) &&
2165 msi_init(dev, 0x50, 1, true, false)) {
2166 s->flags &= ~MEGASAS_MASK_USE_MSI;
2167 }
e8f943c3 2168 if (megasas_use_msix(s) &&
23335f62
HR		 2169 msix_init(dev, 15, &s->mmio_io, 0, 0x2000,
2170 &s->mmio_io, 0, 0x3800, 0x68)) {
e8f943c3
HR		 2171 s->flags &= ~MEGASAS_MASK_USE_MSIX;
2172 }
e8f943c3
HR		 2173
2174 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
52190c1e
AF		 2175 pci_register_bar(dev, 0, bar_type, &s->mmio_io);
2176 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2177 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2178
2179 if (megasas_use_msix(s)) {
52190c1e 2180 msix_vector_use(dev, 0);
e8f943c3
HR		 2181 }
2182
76b523db
HR		 2183 if (!s->sas_addr) {
2184 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2185 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2186 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2187 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2188 s->sas_addr |= PCI_FUNC(dev->devfn);
2189 }
fb654157 2190 if (!s->hba_serial) {
23335f62 2191 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
fb654157 2192 }
e8f943c3
HR		 2193 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2194 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2195 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2196 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2197 } else {
2198 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2199 }
2200 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2201 s->fw_cmds = MEGASAS_MAX_FRAMES;
2202 }
2203 trace_megasas_init(s->fw_sge, s->fw_cmds,
e8f943c3
HR		 2204 megasas_is_jbod(s) ? "jbod" : "raid");
2205 s->fw_luns = (MFI_MAX_LD > MAX_SCSI_DEVS) ?
2206 MAX_SCSI_DEVS : MFI_MAX_LD;
2207 s->producer_pa = 0;
2208 s->consumer_pa = 0;
2209 for (i = 0; i < s->fw_cmds; i++) {
2210 s->frames[i].index = i;
2211 s->frames[i].context = -1;
2212 s->frames[i].pa = 0;
2213 s->frames[i].state = s;
2214 }
2215
b1187b51
AF		 2216 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2217 &megasas_scsi_info, NULL);
22d6aa03 2218 if (!d->hotplugged) {
caad4eb3
AF		 2219 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
2220 if (err != NULL) {
2221 error_free(err);
2222 return -1;
2223 }
22d6aa03 2224 }
e8f943c3
HR		 2225 return 0;
2226}
2227
4522b69c
HR		 2228static void
2229megasas_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len)
2230{
2231 pci_default_write_config(pci, addr, val, len);
2232 msi_write_config(pci, addr, val, len);
2233}
2234
e8f943c3
HR		 2235static Property megasas_properties[] = {
2236 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2237 MEGASAS_DEFAULT_SGE),
2238 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2239 MEGASAS_DEFAULT_FRAMES),
fb654157 2240 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
c7bcc85d 2241 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
4522b69c
HR		 2242 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2243 MEGASAS_FLAG_USE_MSI, false),
e8f943c3
HR		 2244 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2245 MEGASAS_FLAG_USE_MSIX, false),
e8f943c3
HR		 2246 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2247 MEGASAS_FLAG_USE_JBOD, false),
2248 DEFINE_PROP_END_OF_LIST(),
2249};
2250
2251static void megasas_class_init(ObjectClass *oc, void *data)
2252{
2253 DeviceClass *dc = DEVICE_CLASS(oc);
2254 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2255
2256 pc->init = megasas_scsi_init;
2257 pc->exit = megasas_scsi_uninit;
2258 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2259 pc->device_id = PCI_DEVICE_ID_LSI_SAS1078;
2260 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2261 pc->subsystem_id = 0x1013;
2262 pc->class_id = PCI_CLASS_STORAGE_RAID;
2263 dc->props = megasas_properties;
2264 dc->reset = megasas_scsi_reset;
2265 dc->vmsd = &vmstate_megasas;
125ee0ed 2266 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e8f943c3 2267 dc->desc = "LSI MegaRAID SAS 1078";
4522b69c 2268 pc->config_write = megasas_write_config;
e8f943c3
HR		 2269}
2270
2271static const TypeInfo megasas_info = {
c79e16ae 2272 .name = TYPE_MEGASAS,
e8f943c3
HR		 2273 .parent = TYPE_PCI_DEVICE,
2274 .instance_size = sizeof(MegasasState),
2275 .class_init = megasas_class_init,
2276};
2277
2278static void megasas_register_types(void)
2279{
2280 type_register_static(&megasas_info);
2281}
2282
2283type_init(megasas_register_types)
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