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virtio-blk: Rename VirtIOBlkConf variables to conf
[mirror_qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
83c9f4ca
PB		 21#include "hw/hw.h"
22#include "hw/pci/pci.h"
9c17d615 23#include "sysemu/dma.h"
4522b69c 24#include "hw/pci/msi.h"
83c9f4ca 25#include "hw/pci/msix.h"
1de7afc9 26#include "qemu/iov.h"
0d09e41a
PB		 27#include "hw/scsi/scsi.h"
28#include "block/scsi.h"
e8f943c3
HR		 29#include "trace.h"
30
47b43a1f 31#include "mfi.h"
e8f943c3
HR		 32
33#define MEGASAS_VERSION "1.70"
34#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
35#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
36#define MEGASAS_MAX_SGE 128 /* Firmware limit */
37#define MEGASAS_DEFAULT_SGE 80
38#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
39#define MEGASAS_MAX_ARRAYS 128
40
fb654157 41#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 42#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
43#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
44
e8f943c3
HR		 45#define MEGASAS_FLAG_USE_JBOD 0
46#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
4522b69c
HR		 47#define MEGASAS_FLAG_USE_MSI 1
48#define MEGASAS_MASK_USE_MSI (1 << MEGASAS_FLAG_USE_MSI)
49#define MEGASAS_FLAG_USE_MSIX 2
e8f943c3 50#define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX)
4522b69c 51#define MEGASAS_FLAG_USE_QUEUE64 3
e8f943c3
HR		 52#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
53
a97ad268 54static const char *mfi_frame_desc[] = {
e8f943c3
HR		 55 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
56 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
57
58typedef struct MegasasCmd {
59 uint32_t index;
60 uint16_t flags;
61 uint16_t count;
62 uint64_t context;
63
a8170e5e
AK		 64 hwaddr pa;
65 hwaddr pa_size;
e8f943c3
HR		 66 union mfi_frame *frame;
67 SCSIRequest *req;
68 QEMUSGList qsg;
69 void *iov_buf;
70 size_t iov_size;
71 size_t iov_offset;
72 struct MegasasState *state;
73} MegasasCmd;
74
75typedef struct MegasasState {
52190c1e
AF		 76 /*< private >*/
77 PCIDevice parent_obj;
78 /*< public >*/
79
e8f943c3
HR		 80 MemoryRegion mmio_io;
81 MemoryRegion port_io;
82 MemoryRegion queue_io;
83 uint32_t frame_hi;
84
85 int fw_state;
86 uint32_t fw_sge;
87 uint32_t fw_cmds;
88 uint32_t flags;
89 int fw_luns;
90 int intr_mask;
91 int doorbell;
92 int busy;
93
94 MegasasCmd *event_cmd;
95 int event_locale;
96 int event_class;
97 int event_count;
98 int shutdown_event;
99 int boot_event;
100
76b523db 101 uint64_t sas_addr;
fb654157 102 char *hba_serial;
76b523db 103
e8f943c3
HR		 104 uint64_t reply_queue_pa;
105 void *reply_queue;
106 int reply_queue_len;
107 int reply_queue_head;
108 int reply_queue_tail;
109 uint64_t consumer_pa;
110 uint64_t producer_pa;
111
112 MegasasCmd frames[MEGASAS_MAX_FRAMES];
113
114 SCSIBus bus;
115} MegasasState;
116
c79e16ae
PC		 117#define TYPE_MEGASAS "megasas"
118
119#define MEGASAS(obj) \
120 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS)
121
e8f943c3
HR		 122#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
123
124static bool megasas_intr_enabled(MegasasState *s)
125{
126 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
127 MEGASAS_INTR_DISABLED_MASK) {
128 return true;
129 }
130 return false;
131}
132
133static bool megasas_use_queue64(MegasasState *s)
134{
135 return s->flags & MEGASAS_MASK_USE_QUEUE64;
136}
137
4522b69c
HR		 138static bool megasas_use_msi(MegasasState *s)
139{
140 return s->flags & MEGASAS_MASK_USE_MSI;
141}
142
e8f943c3
HR		 143static bool megasas_use_msix(MegasasState *s)
144{
145 return s->flags & MEGASAS_MASK_USE_MSIX;
146}
147
148static bool megasas_is_jbod(MegasasState *s)
149{
150 return s->flags & MEGASAS_MASK_USE_JBOD;
151}
152
153static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v)
154{
db3be60d
EI		 155 stb_phys(&address_space_memory,
156 frame + offsetof(struct mfi_frame_header, cmd_status), v);
e8f943c3
HR		 157}
158
159static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
160{
db3be60d
EI		 161 stb_phys(&address_space_memory,
162 frame + offsetof(struct mfi_frame_header, scsi_status), v);
e8f943c3
HR		 163}
164
165/*
166 * Context is considered opaque, but the HBA firmware is running
167 * in little endian mode. So convert it to little endian, too.
168 */
169static uint64_t megasas_frame_get_context(unsigned long frame)
170{
2c17449b
EI		 171 return ldq_le_phys(&address_space_memory,
172 frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 173}
174
175static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
176{
177 return cmd->flags & MFI_FRAME_IEEE_SGL;
178}
179
180static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
181{
182 return cmd->flags & MFI_FRAME_SGL64;
183}
184
185static bool megasas_frame_is_sense64(MegasasCmd *cmd)
186{
187 return cmd->flags & MFI_FRAME_SENSE64;
188}
189
190static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
191 union mfi_sgl *sgl)
192{
193 uint64_t addr;
194
195 if (megasas_frame_is_ieee_sgl(cmd)) {
196 addr = le64_to_cpu(sgl->sg_skinny->addr);
197 } else if (megasas_frame_is_sgl64(cmd)) {
198 addr = le64_to_cpu(sgl->sg64->addr);
199 } else {
200 addr = le32_to_cpu(sgl->sg32->addr);
201 }
202 return addr;
203}
204
205static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
206 union mfi_sgl *sgl)
207{
208 uint32_t len;
209
210 if (megasas_frame_is_ieee_sgl(cmd)) {
211 len = le32_to_cpu(sgl->sg_skinny->len);
212 } else if (megasas_frame_is_sgl64(cmd)) {
213 len = le32_to_cpu(sgl->sg64->len);
214 } else {
215 len = le32_to_cpu(sgl->sg32->len);
216 }
217 return len;
218}
219
220static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
221 union mfi_sgl *sgl)
222{
223 uint8_t *next = (uint8_t *)sgl;
224
225 if (megasas_frame_is_ieee_sgl(cmd)) {
226 next += sizeof(struct mfi_sg_skinny);
227 } else if (megasas_frame_is_sgl64(cmd)) {
228 next += sizeof(struct mfi_sg64);
229 } else {
230 next += sizeof(struct mfi_sg32);
231 }
232
233 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
234 return NULL;
235 }
236 return (union mfi_sgl *)next;
237}
238
239static void megasas_soft_reset(MegasasState *s);
240
241static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
242{
243 int i;
244 int iov_count = 0;
245 size_t iov_size = 0;
246
247 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
248 iov_count = cmd->frame->header.sge_count;
249 if (iov_count > MEGASAS_MAX_SGE) {
250 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
251 MEGASAS_MAX_SGE);
252 return iov_count;
253 }
52190c1e 254 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 255 for (i = 0; i < iov_count; i++) {
256 dma_addr_t iov_pa, iov_size_p;
257
258 if (!sgl) {
259 trace_megasas_iovec_sgl_underflow(cmd->index, i);
260 goto unmap;
261 }
262 iov_pa = megasas_sgl_get_addr(cmd, sgl);
263 iov_size_p = megasas_sgl_get_len(cmd, sgl);
264 if (!iov_pa || !iov_size_p) {
265 trace_megasas_iovec_sgl_invalid(cmd->index, i,
266 iov_pa, iov_size_p);
267 goto unmap;
268 }
269 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
270 sgl = megasas_sgl_next(cmd, sgl);
271 iov_size += (size_t)iov_size_p;
272 }
273 if (cmd->iov_size > iov_size) {
274 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
275 } else if (cmd->iov_size < iov_size) {
276 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
277 }
278 cmd->iov_offset = 0;
279 return 0;
280unmap:
281 qemu_sglist_destroy(&cmd->qsg);
282 return iov_count - i;
283}
284
285static void megasas_unmap_sgl(MegasasCmd *cmd)
286{
287 qemu_sglist_destroy(&cmd->qsg);
288 cmd->iov_offset = 0;
289}
290
291/*
292 * passthrough sense and io sense are at the same offset
293 */
294static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
295 uint8_t sense_len)
296{
1016b239 297 PCIDevice *pcid = PCI_DEVICE(cmd->state);
e8f943c3 298 uint32_t pa_hi = 0, pa_lo;
a8170e5e 299 hwaddr pa;
e8f943c3
HR		 300
301 if (sense_len > cmd->frame->header.sense_len) {
302 sense_len = cmd->frame->header.sense_len;
303 }
304 if (sense_len) {
305 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
306 if (megasas_frame_is_sense64(cmd)) {
307 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
308 }
309 pa = ((uint64_t) pa_hi << 32) | pa_lo;
1016b239 310 pci_dma_write(pcid, pa, sense_ptr, sense_len);
e8f943c3
HR		 311 cmd->frame->header.sense_len = sense_len;
312 }
313 return sense_len;
314}
315
316static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
317{
318 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
319 uint8_t sense_len = 18;
320
321 memset(sense_buf, 0, sense_len);
322 sense_buf[0] = 0xf0;
323 sense_buf[2] = sense.key;
324 sense_buf[7] = 10;
325 sense_buf[12] = sense.asc;
326 sense_buf[13] = sense.ascq;
327 megasas_build_sense(cmd, sense_buf, sense_len);
328}
329
330static void megasas_copy_sense(MegasasCmd *cmd)
331{
332 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
333 uint8_t sense_len;
334
335 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
336 SCSI_SENSE_BUF_SIZE);
337 megasas_build_sense(cmd, sense_buf, sense_len);
338}
339
340/*
341 * Format an INQUIRY CDB
342 */
343static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
344{
345 memset(cdb, 0, 6);
346 cdb[0] = INQUIRY;
347 if (pg > 0) {
348 cdb[1] = 0x1;
349 cdb[2] = pg;
350 }
351 cdb[3] = (len >> 8) & 0xff;
352 cdb[4] = (len & 0xff);
353 return len;
354}
355
356/*
357 * Encode lba and len into a READ_16/WRITE_16 CDB
358 */
359static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
360 uint32_t len, bool is_write)
361{
362 memset(cdb, 0x0, 16);
363 if (is_write) {
364 cdb[0] = WRITE_16;
365 } else {
366 cdb[0] = READ_16;
367 }
368 cdb[2] = (lba >> 56) & 0xff;
369 cdb[3] = (lba >> 48) & 0xff;
370 cdb[4] = (lba >> 40) & 0xff;
371 cdb[5] = (lba >> 32) & 0xff;
372 cdb[6] = (lba >> 24) & 0xff;
373 cdb[7] = (lba >> 16) & 0xff;
374 cdb[8] = (lba >> 8) & 0xff;
375 cdb[9] = (lba) & 0xff;
376 cdb[10] = (len >> 24) & 0xff;
377 cdb[11] = (len >> 16) & 0xff;
378 cdb[12] = (len >> 8) & 0xff;
379 cdb[13] = (len) & 0xff;
380}
381
382/*
383 * Utility functions
384 */
385static uint64_t megasas_fw_time(void)
386{
387 struct tm curtime;
388 uint64_t bcd_time;
389
390 qemu_get_timedate(&curtime, 0);
391 bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 |
392 ((uint64_t)curtime.tm_min & 0xff) << 40 |
393 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
394 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
395 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
396 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
397
398 return bcd_time;
399}
400
76b523db
HR		 401/*
402 * Default disk sata address
403 * 0x1221 is the magic number as
404 * present in real hardware,
405 * so use it here, too.
406 */
407static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 408{
76b523db
HR		 409 uint64_t addr = (0x1221ULL << 48);
410 return addr & (id << 24);
e8f943c3
HR		 411}
412
413/*
414 * Frame handling
415 */
416static int megasas_next_index(MegasasState *s, int index, int limit)
417{
418 index++;
419 if (index == limit) {
420 index = 0;
421 }
422 return index;
423}
424
425static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 426 hwaddr frame)
e8f943c3
HR		 427{
428 MegasasCmd *cmd = NULL;
429 int num = 0, index;
430
431 index = s->reply_queue_head;
432
433 while (num < s->fw_cmds) {
434 if (s->frames[index].pa && s->frames[index].pa == frame) {
435 cmd = &s->frames[index];
436 break;
437 }
438 index = megasas_next_index(s, index, s->fw_cmds);
439 num++;
440 }
441
442 return cmd;
443}
444
445static MegasasCmd *megasas_next_frame(MegasasState *s,
a8170e5e 446 hwaddr frame)
e8f943c3
HR		 447{
448 MegasasCmd *cmd = NULL;
449 int num = 0, index;
450
451 cmd = megasas_lookup_frame(s, frame);
452 if (cmd) {
453 trace_megasas_qf_found(cmd->index, cmd->pa);
454 return cmd;
455 }
456 index = s->reply_queue_head;
457 num = 0;
458 while (num < s->fw_cmds) {
459 if (!s->frames[index].pa) {
460 cmd = &s->frames[index];
461 break;
462 }
463 index = megasas_next_index(s, index, s->fw_cmds);
464 num++;
465 }
466 if (!cmd) {
467 trace_megasas_qf_failed(frame);
468 }
469 trace_megasas_qf_new(index, cmd);
470 return cmd;
471}
472
473static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 474 hwaddr frame, uint64_t context, int count)
e8f943c3 475{
1016b239 476 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3
HR		 477 MegasasCmd *cmd = NULL;
478 int frame_size = MFI_FRAME_SIZE * 16;
a8170e5e 479 hwaddr frame_size_p = frame_size;
e8f943c3
HR		 480
481 cmd = megasas_next_frame(s, frame);
482 /* All frames busy */
483 if (!cmd) {
484 return NULL;
485 }
486 if (!cmd->pa) {
487 cmd->pa = frame;
488 /* Map all possible frames */
1016b239 489 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
e8f943c3
HR		 490 if (frame_size_p != frame_size) {
491 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
492 if (cmd->frame) {
1016b239 493 pci_dma_unmap(pcid, cmd->frame, frame_size_p, 0, 0);
e8f943c3
HR		 494 cmd->frame = NULL;
495 cmd->pa = 0;
496 }
497 s->event_count++;
498 return NULL;
499 }
500 cmd->pa_size = frame_size_p;
501 cmd->context = context;
502 if (!megasas_use_queue64(s)) {
503 cmd->context &= (uint64_t)0xFFFFFFFF;
504 }
505 }
506 cmd->count = count;
507 s->busy++;
508
509 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
510 s->reply_queue_head, s->busy);
511
512 return cmd;
513}
514
515static void megasas_complete_frame(MegasasState *s, uint64_t context)
516{
52190c1e 517 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 518 int tail, queue_offset;
519
520 /* Decrement busy count */
521 s->busy--;
522
523 if (s->reply_queue_pa) {
524 /*
525 * Put command on the reply queue.
526 * Context is opaque, but emulation is running in
527 * little endian. So convert it.
528 */
529 tail = s->reply_queue_head;
530 if (megasas_use_queue64(s)) {
531 queue_offset = tail * sizeof(uint64_t);
f606604f
EI		 532 stq_le_phys(&address_space_memory,
533 s->reply_queue_pa + queue_offset, context);
e8f943c3
HR		 534 } else {
535 queue_offset = tail * sizeof(uint32_t);
ab1da857
EI		 536 stl_le_phys(&address_space_memory,
537 s->reply_queue_pa + queue_offset, context);
e8f943c3
HR		 538 }
539 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
540 trace_megasas_qf_complete(context, tail, queue_offset,
541 s->busy, s->doorbell);
542 }
543
544 if (megasas_intr_enabled(s)) {
545 /* Notify HBA */
546 s->doorbell++;
547 if (s->doorbell == 1) {
52190c1e 548 if (msix_enabled(pci_dev)) {
e8f943c3 549 trace_megasas_msix_raise(0);
52190c1e 550 msix_notify(pci_dev, 0);
4522b69c
HR		 551 } else if (msi_enabled(pci_dev)) {
552 trace_megasas_msi_raise(0);
553 msi_notify(pci_dev, 0);
e8f943c3
HR		 554 } else {
555 trace_megasas_irq_raise();
9e64f8a3 556 pci_irq_assert(pci_dev);
e8f943c3
HR		 557 }
558 }
559 } else {
560 trace_megasas_qf_complete_noirq(context);
561 }
562}
563
564static void megasas_reset_frames(MegasasState *s)
565{
1016b239 566 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3
HR		 567 int i;
568 MegasasCmd *cmd;
569
570 for (i = 0; i < s->fw_cmds; i++) {
571 cmd = &s->frames[i];
572 if (cmd->pa) {
1016b239 573 pci_dma_unmap(pcid, cmd->frame, cmd->pa_size, 0, 0);
e8f943c3
HR		 574 cmd->frame = NULL;
575 cmd->pa = 0;
576 }
577 }
578}
579
580static void megasas_abort_command(MegasasCmd *cmd)
581{
582 if (cmd->req) {
e2b06058 583 scsi_req_cancel(cmd->req);
e8f943c3
HR		 584 cmd->req = NULL;
585 }
586}
587
588static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
589{
1016b239 590 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3 591 uint32_t pa_hi, pa_lo;
a8170e5e 592 hwaddr iq_pa, initq_size;
e8f943c3
HR		 593 struct mfi_init_qinfo *initq;
594 uint32_t flags;
595 int ret = MFI_STAT_OK;
596
597 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
598 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
599 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
600 trace_megasas_init_firmware((uint64_t)iq_pa);
601 initq_size = sizeof(*initq);
1016b239 602 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
e8f943c3
HR		 603 if (!initq || initq_size != sizeof(*initq)) {
604 trace_megasas_initq_map_failed(cmd->index);
605 s->event_count++;
606 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
607 goto out;
608 }
609 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
610 if (s->reply_queue_len > s->fw_cmds) {
611 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
612 s->event_count++;
613 ret = MFI_STAT_INVALID_PARAMETER;
614 goto out;
615 }
616 pa_lo = le32_to_cpu(initq->rq_addr_lo);
617 pa_hi = le32_to_cpu(initq->rq_addr_hi);
618 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
619 pa_lo = le32_to_cpu(initq->ci_addr_lo);
620 pa_hi = le32_to_cpu(initq->ci_addr_hi);
621 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
622 pa_lo = le32_to_cpu(initq->pi_addr_lo);
623 pa_hi = le32_to_cpu(initq->pi_addr_hi);
624 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
fdfba1a2
EI		 625 s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
626 s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
e8f943c3
HR		 627 flags = le32_to_cpu(initq->flags);
628 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
629 s->flags |= MEGASAS_MASK_USE_QUEUE64;
630 }
631 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
632 s->reply_queue_len, s->reply_queue_head,
633 s->reply_queue_tail, flags);
634 megasas_reset_frames(s);
635 s->fw_state = MFI_FWSTATE_OPERATIONAL;
636out:
637 if (initq) {
1016b239 638 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
e8f943c3
HR		 639 }
640 return ret;
641}
642
643static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
644{
645 dma_addr_t iov_pa, iov_size;
646
647 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
648 if (!cmd->frame->header.sge_count) {
649 trace_megasas_dcmd_zero_sge(cmd->index);
650 cmd->iov_size = 0;
651 return 0;
652 } else if (cmd->frame->header.sge_count > 1) {
653 trace_megasas_dcmd_invalid_sge(cmd->index,
654 cmd->frame->header.sge_count);
655 cmd->iov_size = 0;
656 return -1;
657 }
658 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
659 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 660 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 661 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
662 cmd->iov_size = iov_size;
663 return cmd->iov_size;
664}
665
666static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
667{
668 trace_megasas_finish_dcmd(cmd->index, iov_size);
669
670 if (cmd->frame->header.sge_count) {
671 qemu_sglist_destroy(&cmd->qsg);
672 }
673 if (iov_size > cmd->iov_size) {
674 if (megasas_frame_is_ieee_sgl(cmd)) {
675 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
676 } else if (megasas_frame_is_sgl64(cmd)) {
677 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
678 } else {
679 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
680 }
681 }
682 cmd->iov_size = 0;
e8f943c3
HR		 683}
684
685static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
686{
52190c1e 687 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 688 struct mfi_ctrl_info info;
689 size_t dcmd_size = sizeof(info);
690 BusChild *kid;
691 int num_ld_disks = 0;
76b523db 692 uint16_t sdev_id;
e8f943c3
HR		 693
694 memset(&info, 0x0, cmd->iov_size);
695 if (cmd->iov_size < dcmd_size) {
696 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
697 dcmd_size);
698 return MFI_STAT_INVALID_PARAMETER;
699 }
700
701 info.pci.vendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC);
702 info.pci.device = cpu_to_le16(PCI_DEVICE_ID_LSI_SAS1078);
703 info.pci.subvendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC);
704 info.pci.subdevice = cpu_to_le16(0x1013);
705
76b523db
HR		 706 /*
707 * For some reason the firmware supports
708 * only up to 8 device ports.
709 * Despite supporting a far larger number
710 * of devices for the physical devices.
711 * So just display the first 8 devices
712 * in the device port list, independent
713 * of how many logical devices are actually
714 * present.
715 */
716 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 717 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 718 info.device.port_count = 8;
719 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
720 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
721
722 if (num_ld_disks < 8) {
723 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
724 info.device.port_addr[num_ld_disks] =
725 cpu_to_le64(megasas_get_sata_addr(sdev_id));
726 }
727 num_ld_disks++;
728 }
e8f943c3
HR		 729
730 memcpy(info.product_name, "MegaRAID SAS 8708EM2", 20);
fb654157 731 snprintf(info.serial_number, 32, "%s", s->hba_serial);
e8f943c3
HR		 732 snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION);
733 memcpy(info.image_component[0].name, "APP", 3);
734 memcpy(info.image_component[0].version, MEGASAS_VERSION "-QEMU", 9);
5a7733b0
OH		 735 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
736 memcpy(info.image_component[0].build_time, "12:34:56", 8);
e8f943c3 737 info.image_component_count = 1;
52190c1e 738 if (pci_dev->has_rom) {
e8f943c3
HR		 739 uint8_t biosver[32];
740 uint8_t *ptr;
741
52190c1e 742 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 743 memcpy(biosver, ptr + 0x41, 31);
e8f943c3
HR		 744 memcpy(info.image_component[1].name, "BIOS", 4);
745 memcpy(info.image_component[1].version, biosver,
746 strlen((const char *)biosver));
747 info.image_component_count++;
748 }
749 info.current_fw_time = cpu_to_le32(megasas_fw_time());
750 info.max_arms = 32;
751 info.max_spans = 8;
752 info.max_arrays = MEGASAS_MAX_ARRAYS;
753 info.max_lds = s->fw_luns;
754 info.max_cmds = cpu_to_le16(s->fw_cmds);
755 info.max_sg_elements = cpu_to_le16(s->fw_sge);
756 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
757 info.lds_present = cpu_to_le16(num_ld_disks);
758 info.pd_present = cpu_to_le16(num_ld_disks);
759 info.pd_disks_present = cpu_to_le16(num_ld_disks);
760 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
761 MFI_INFO_HW_MEM |
762 MFI_INFO_HW_FLASH);
763 info.memory_size = cpu_to_le16(512);
764 info.nvram_size = cpu_to_le16(32);
765 info.flash_size = cpu_to_le16(16);
766 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
767 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
768 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
769 MFI_INFO_AOPS_MIXED_ARRAY);
770 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
771 MFI_INFO_LDOPS_ACCESS_POLICY |
772 MFI_INFO_LDOPS_IO_POLICY |
773 MFI_INFO_LDOPS_WRITE_POLICY |
774 MFI_INFO_LDOPS_READ_POLICY);
775 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
776 info.stripe_sz_ops.min = 3;
777 info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1;
778 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
779 info.properties.intr_throttle_cnt = cpu_to_le16(16);
780 info.properties.intr_throttle_timeout = cpu_to_le16(50);
781 info.properties.rebuild_rate = 30;
782 info.properties.patrol_read_rate = 30;
783 info.properties.bgi_rate = 30;
784 info.properties.cc_rate = 30;
785 info.properties.recon_rate = 30;
786 info.properties.cache_flush_interval = 4;
787 info.properties.spinup_drv_cnt = 2;
788 info.properties.spinup_delay = 6;
789 info.properties.ecc_bucket_size = 15;
790 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
791 info.properties.expose_encl_devices = 1;
792 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
793 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
794 MFI_INFO_PDOPS_FORCE_OFFLINE);
795 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
796 MFI_INFO_PDMIX_SATA |
797 MFI_INFO_PDMIX_LD);
798
799 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
800 return MFI_STAT_OK;
801}
802
803static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
804{
805 struct mfi_defaults info;
806 size_t dcmd_size = sizeof(struct mfi_defaults);
807
808 memset(&info, 0x0, dcmd_size);
809 if (cmd->iov_size < dcmd_size) {
810 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
811 dcmd_size);
812 return MFI_STAT_INVALID_PARAMETER;
813 }
814
76b523db 815 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 816 info.stripe_size = 3;
817 info.flush_time = 4;
818 info.background_rate = 30;
819 info.allow_mix_in_enclosure = 1;
820 info.allow_mix_in_ld = 1;
821 info.direct_pd_mapping = 1;
822 /* Enable for BIOS support */
823 info.bios_enumerate_lds = 1;
824 info.disable_ctrl_r = 1;
825 info.expose_enclosure_devices = 1;
826 info.disable_preboot_cli = 1;
827 info.cluster_disable = 1;
828
829 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
830 return MFI_STAT_OK;
831}
832
833static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
834{
835 struct mfi_bios_data info;
836 size_t dcmd_size = sizeof(info);
837
838 memset(&info, 0x0, dcmd_size);
839 if (cmd->iov_size < dcmd_size) {
840 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
841 dcmd_size);
842 return MFI_STAT_INVALID_PARAMETER;
843 }
844 info.continue_on_error = 1;
845 info.verbose = 1;
846 if (megasas_is_jbod(s)) {
847 info.expose_all_drives = 1;
848 }
849
850 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
851 return MFI_STAT_OK;
852}
853
854static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
855{
856 uint64_t fw_time;
857 size_t dcmd_size = sizeof(fw_time);
858
859 fw_time = cpu_to_le64(megasas_fw_time());
860
861 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
862 return MFI_STAT_OK;
863}
864
865static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
866{
867 uint64_t fw_time;
868
869 /* This is a dummy; setting of firmware time is not allowed */
870 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
871
872 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
873 fw_time = cpu_to_le64(megasas_fw_time());
874 return MFI_STAT_OK;
875}
876
877static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
878{
879 struct mfi_evt_log_state info;
880 size_t dcmd_size = sizeof(info);
881
882 memset(&info, 0, dcmd_size);
883
884 info.newest_seq_num = cpu_to_le32(s->event_count);
885 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
886 info.boot_seq_num = cpu_to_le32(s->boot_event);
887
888 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
889 return MFI_STAT_OK;
890}
891
892static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
893{
894 union mfi_evt event;
895
896 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
897 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
898 sizeof(struct mfi_evt_detail));
899 return MFI_STAT_INVALID_PARAMETER;
900 }
901 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
902 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
903 s->event_locale = event.members.locale;
904 s->event_class = event.members.class;
905 s->event_cmd = cmd;
906 /* Decrease busy count; event frame doesn't count here */
907 s->busy--;
908 cmd->iov_size = sizeof(struct mfi_evt_detail);
909 return MFI_STAT_INVALID_STATUS;
910}
911
912static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
913{
914 struct mfi_pd_list info;
915 size_t dcmd_size = sizeof(info);
916 BusChild *kid;
917 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
918 uint16_t sdev_id;
919
920 memset(&info, 0, dcmd_size);
921 offset = 8;
922 dcmd_limit = offset + sizeof(struct mfi_pd_address);
923 if (cmd->iov_size < dcmd_limit) {
924 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
925 dcmd_limit);
926 return MFI_STAT_INVALID_PARAMETER;
927 }
928
929 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
930 if (max_pd_disks > s->fw_luns) {
931 max_pd_disks = s->fw_luns;
932 }
933
934 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
935 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
936
937 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
938 info.addr[num_pd_disks].device_id = cpu_to_le16(sdev_id);
939 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
940 info.addr[num_pd_disks].encl_index = 0;
941 info.addr[num_pd_disks].slot_number = (sdev->id & 0xFF);
942 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
943 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
944 info.addr[num_pd_disks].sas_addr[0] =
76b523db 945 cpu_to_le64(megasas_get_sata_addr(sdev_id));
e8f943c3
HR		 946 num_pd_disks++;
947 offset += sizeof(struct mfi_pd_address);
948 }
949 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
950 max_pd_disks, offset);
951
952 info.size = cpu_to_le32(offset);
953 info.count = cpu_to_le32(num_pd_disks);
954
955 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
956 return MFI_STAT_OK;
957}
958
959static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
960{
961 uint16_t flags;
962
963 /* mbox0 contains flags */
964 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
965 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
966 if (flags == MR_PD_QUERY_TYPE_ALL ||
967 megasas_is_jbod(s)) {
968 return megasas_dcmd_pd_get_list(s, cmd);
969 }
970
971 return MFI_STAT_OK;
972}
973
974static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
975 MegasasCmd *cmd)
976{
977 struct mfi_pd_info *info = cmd->iov_buf;
978 size_t dcmd_size = sizeof(struct mfi_pd_info);
979 BlockConf *conf = &sdev->conf;
980 uint64_t pd_size;
981 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF);
982 uint8_t cmdbuf[6];
983 SCSIRequest *req;
984 size_t len, resid;
985
986 if (!cmd->iov_buf) {
987 cmd->iov_buf = g_malloc(dcmd_size);
988 memset(cmd->iov_buf, 0, dcmd_size);
989 info = cmd->iov_buf;
990 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
991 info->vpd_page83[0] = 0x7f;
992 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
993 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
994 if (!req) {
995 trace_megasas_dcmd_req_alloc_failed(cmd->index,
996 "PD get info std inquiry");
997 g_free(cmd->iov_buf);
998 cmd->iov_buf = NULL;
999 return MFI_STAT_FLASH_ALLOC_FAIL;
1000 }
1001 trace_megasas_dcmd_internal_submit(cmd->index,
1002 "PD get info std inquiry", lun);
1003 len = scsi_req_enqueue(req);
1004 if (len > 0) {
1005 cmd->iov_size = len;
1006 scsi_req_continue(req);
1007 }
1008 return MFI_STAT_INVALID_STATUS;
1009 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1010 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1011 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1012 if (!req) {
1013 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1014 "PD get info vpd inquiry");
1015 return MFI_STAT_FLASH_ALLOC_FAIL;
1016 }
1017 trace_megasas_dcmd_internal_submit(cmd->index,
1018 "PD get info vpd inquiry", lun);
1019 len = scsi_req_enqueue(req);
1020 if (len > 0) {
1021 cmd->iov_size = len;
1022 scsi_req_continue(req);
1023 }
1024 return MFI_STAT_INVALID_STATUS;
1025 }
1026 /* Finished, set FW state */
1027 if ((info->inquiry_data[0] >> 5) == 0) {
1028 if (megasas_is_jbod(cmd->state)) {
1029 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1030 } else {
1031 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1032 }
1033 } else {
1034 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1035 }
1036
1037 info->ref.v.device_id = cpu_to_le16(sdev_id);
1038 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1039 MFI_PD_DDF_TYPE_INTF_SAS);
1040 bdrv_get_geometry(conf->bs, &pd_size);
1041 info->raw_size = cpu_to_le64(pd_size);
1042 info->non_coerced_size = cpu_to_le64(pd_size);
1043 info->coerced_size = cpu_to_le64(pd_size);
1044 info->encl_device_id = 0xFFFF;
1045 info->slot_number = (sdev->id & 0xFF);
1046 info->path_info.count = 1;
1047 info->path_info.sas_addr[0] =
76b523db 1048 cpu_to_le64(megasas_get_sata_addr(sdev_id));
e8f943c3
HR		 1049 info->connected_port_bitmap = 0x1;
1050 info->device_speed = 1;
1051 info->link_speed = 1;
1052 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1053 g_free(cmd->iov_buf);
1054 cmd->iov_size = dcmd_size - resid;
1055 cmd->iov_buf = NULL;
1056 return MFI_STAT_OK;
1057}
1058
1059static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1060{
1061 size_t dcmd_size = sizeof(struct mfi_pd_info);
1062 uint16_t pd_id;
1063 SCSIDevice *sdev = NULL;
1064 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1065
1066 if (cmd->iov_size < dcmd_size) {
1067 return MFI_STAT_INVALID_PARAMETER;
1068 }
1069
1070 /* mbox0 has the ID */
1071 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1072 sdev = scsi_device_find(&s->bus, 0, pd_id, 0);
1073 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1074
1075 if (sdev) {
1076 /* Submit inquiry */
1077 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1078 }
1079
1080 return retval;
1081}
1082
1083static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1084{
1085 struct mfi_ld_list info;
1086 size_t dcmd_size = sizeof(info), resid;
1087 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1088 uint64_t ld_size;
1089 BusChild *kid;
1090
1091 memset(&info, 0, dcmd_size);
1092 if (cmd->iov_size < dcmd_size) {
1093 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1094 dcmd_size);
1095 return MFI_STAT_INVALID_PARAMETER;
1096 }
1097
1098 if (megasas_is_jbod(s)) {
1099 max_ld_disks = 0;
1100 }
1101 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1102 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
1103 BlockConf *conf = &sdev->conf;
1104
1105 if (num_ld_disks >= max_ld_disks) {
1106 break;
1107 }
1108 /* Logical device size is in blocks */
1109 bdrv_get_geometry(conf->bs, &ld_size);
1110 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
4003e24f 1111 info.ld_list[num_ld_disks].ld.v.lun_id = sdev->lun;
e8f943c3
HR		 1112 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1113 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1114 num_ld_disks++;
1115 }
1116 info.ld_count = cpu_to_le32(num_ld_disks);
1117 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1118
1119 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1120 cmd->iov_size = dcmd_size - resid;
1121 return MFI_STAT_OK;
1122}
1123
34bb4d02
HR		 1124static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1125{
1126 uint16_t flags;
1127
1128 /* mbox0 contains flags */
1129 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1130 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1131 if (flags == MR_LD_QUERY_TYPE_ALL ||
1132 flags == MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1133 return megasas_dcmd_ld_get_list(s, cmd);
1134 }
1135
1136 return MFI_STAT_OK;
1137}
1138
e8f943c3
HR		 1139static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1140 MegasasCmd *cmd)
1141{
1142 struct mfi_ld_info *info = cmd->iov_buf;
1143 size_t dcmd_size = sizeof(struct mfi_ld_info);
1144 uint8_t cdb[6];
1145 SCSIRequest *req;
1146 ssize_t len, resid;
1147 BlockConf *conf = &sdev->conf;
1148 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF);
1149 uint64_t ld_size;
1150
1151 if (!cmd->iov_buf) {
1152 cmd->iov_buf = g_malloc(dcmd_size);
1153 memset(cmd->iov_buf, 0x0, dcmd_size);
1154 info = cmd->iov_buf;
1155 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1156 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1157 if (!req) {
1158 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1159 "LD get info vpd inquiry");
1160 g_free(cmd->iov_buf);
1161 cmd->iov_buf = NULL;
1162 return MFI_STAT_FLASH_ALLOC_FAIL;
1163 }
1164 trace_megasas_dcmd_internal_submit(cmd->index,
1165 "LD get info vpd inquiry", lun);
1166 len = scsi_req_enqueue(req);
1167 if (len > 0) {
1168 cmd->iov_size = len;
1169 scsi_req_continue(req);
1170 }
1171 return MFI_STAT_INVALID_STATUS;
1172 }
1173
1174 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1175 info->ld_config.properties.ld.v.target_id = lun;
1176 info->ld_config.params.stripe_size = 3;
1177 info->ld_config.params.num_drives = 1;
1178 info->ld_config.params.is_consistent = 1;
1179 /* Logical device size is in blocks */
1180 bdrv_get_geometry(conf->bs, &ld_size);
1181 info->size = cpu_to_le64(ld_size);
1182 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1183 info->ld_config.span[0].start_block = 0;
1184 info->ld_config.span[0].num_blocks = info->size;
1185 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1186
1187 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1188 g_free(cmd->iov_buf);
1189 cmd->iov_size = dcmd_size - resid;
1190 cmd->iov_buf = NULL;
1191 return MFI_STAT_OK;
1192}
1193
1194static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1195{
1196 struct mfi_ld_info info;
1197 size_t dcmd_size = sizeof(info);
1198 uint16_t ld_id;
1199 uint32_t max_ld_disks = s->fw_luns;
1200 SCSIDevice *sdev = NULL;
1201 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1202
1203 if (cmd->iov_size < dcmd_size) {
1204 return MFI_STAT_INVALID_PARAMETER;
1205 }
1206
1207 /* mbox0 has the ID */
1208 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1209 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1210
1211 if (megasas_is_jbod(s)) {
1212 return MFI_STAT_DEVICE_NOT_FOUND;
1213 }
1214
1215 if (ld_id < max_ld_disks) {
1216 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1217 }
1218
1219 if (sdev) {
1220 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1221 }
1222
1223 return retval;
1224}
1225
1226static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1227{
1228 uint8_t data[4096];
1229 struct mfi_config_data *info;
1230 int num_pd_disks = 0, array_offset, ld_offset;
1231 BusChild *kid;
1232
1233 if (cmd->iov_size > 4096) {
1234 return MFI_STAT_INVALID_PARAMETER;
1235 }
1236
1237 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1238 num_pd_disks++;
1239 }
1240 info = (struct mfi_config_data *)&data;
1241 /*
1242 * Array mapping:
1243 * - One array per SCSI device
1244 * - One logical drive per SCSI device
1245 * spanning the entire device
1246 */
1247 info->array_count = num_pd_disks;
1248 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1249 info->log_drv_count = num_pd_disks;
1250 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1251 info->spares_count = 0;
1252 info->spares_size = sizeof(struct mfi_spare);
1253 info->size = sizeof(struct mfi_config_data) + info->array_size +
1254 info->log_drv_size;
1255 if (info->size > 4096) {
1256 return MFI_STAT_INVALID_PARAMETER;
1257 }
1258
1259 array_offset = sizeof(struct mfi_config_data);
1260 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1261
1262 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1263 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
1264 BlockConf *conf = &sdev->conf;
1265 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
1266 struct mfi_array *array;
1267 struct mfi_ld_config *ld;
1268 uint64_t pd_size;
1269 int i;
1270
1271 array = (struct mfi_array *)(data + array_offset);
1272 bdrv_get_geometry(conf->bs, &pd_size);
1273 array->size = cpu_to_le64(pd_size);
1274 array->num_drives = 1;
1275 array->array_ref = cpu_to_le16(sdev_id);
1276 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1277 array->pd[0].ref.v.seq_num = 0;
1278 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1279 array->pd[0].encl.pd = 0xFF;
1280 array->pd[0].encl.slot = (sdev->id & 0xFF);
1281 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1282 array->pd[i].ref.v.device_id = 0xFFFF;
1283 array->pd[i].ref.v.seq_num = 0;
1284 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1285 array->pd[i].encl.pd = 0xFF;
1286 array->pd[i].encl.slot = 0xFF;
1287 }
1288 array_offset += sizeof(struct mfi_array);
1289 ld = (struct mfi_ld_config *)(data + ld_offset);
1290 memset(ld, 0, sizeof(struct mfi_ld_config));
1291 ld->properties.ld.v.target_id = (sdev->id & 0xFF);
1292 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1293 MR_LD_CACHE_READ_ADAPTIVE;
1294 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1295 MR_LD_CACHE_READ_ADAPTIVE;
1296 ld->params.state = MFI_LD_STATE_OPTIMAL;
1297 ld->params.stripe_size = 3;
1298 ld->params.num_drives = 1;
1299 ld->params.span_depth = 1;
1300 ld->params.is_consistent = 1;
1301 ld->span[0].start_block = 0;
1302 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1303 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1304 ld_offset += sizeof(struct mfi_ld_config);
1305 }
1306
1307 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1308 return MFI_STAT_OK;
1309}
1310
1311static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1312{
1313 struct mfi_ctrl_props info;
1314 size_t dcmd_size = sizeof(info);
1315
1316 memset(&info, 0x0, dcmd_size);
1317 if (cmd->iov_size < dcmd_size) {
1318 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1319 dcmd_size);
1320 return MFI_STAT_INVALID_PARAMETER;
1321 }
1322 info.pred_fail_poll_interval = cpu_to_le16(300);
1323 info.intr_throttle_cnt = cpu_to_le16(16);
1324 info.intr_throttle_timeout = cpu_to_le16(50);
1325 info.rebuild_rate = 30;
1326 info.patrol_read_rate = 30;
1327 info.bgi_rate = 30;
1328 info.cc_rate = 30;
1329 info.recon_rate = 30;
1330 info.cache_flush_interval = 4;
1331 info.spinup_drv_cnt = 2;
1332 info.spinup_delay = 6;
1333 info.ecc_bucket_size = 15;
1334 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1335 info.expose_encl_devices = 1;
1336
1337 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1338 return MFI_STAT_OK;
1339}
1340
1341static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1342{
b618f4a1 1343 bdrv_drain_all();
e8f943c3
HR		 1344 return MFI_STAT_OK;
1345}
1346
1347static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1348{
1349 s->fw_state = MFI_FWSTATE_READY;
1350 return MFI_STAT_OK;
1351}
1352
1353static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1354{
1355 return MFI_STAT_INVALID_DCMD;
1356}
1357
1358static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1359{
10d6530c
HR		 1360 struct mfi_ctrl_props info;
1361 size_t dcmd_size = sizeof(info);
1362
1363 if (cmd->iov_size < dcmd_size) {
1364 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1365 dcmd_size);
1366 return MFI_STAT_INVALID_PARAMETER;
1367 }
1368 dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg);
1369 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1370 return MFI_STAT_OK;
1371}
1372
1373static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1374{
1375 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1376 return MFI_STAT_OK;
1377}
1378
1379static const struct dcmd_cmd_tbl_t {
1380 int opcode;
1381 const char *desc;
1382 int (*func)(MegasasState *s, MegasasCmd *cmd);
1383} dcmd_cmd_tbl[] = {
1384 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1385 megasas_dcmd_dummy },
1386 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1387 megasas_ctrl_get_info },
1388 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1389 megasas_dcmd_get_properties },
1390 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1391 megasas_dcmd_set_properties },
1392 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1393 megasas_dcmd_dummy },
1394 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1395 megasas_dcmd_dummy },
1396 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1397 megasas_dcmd_dummy },
1398 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1399 megasas_dcmd_dummy },
1400 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1401 megasas_dcmd_dummy },
1402 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1403 megasas_event_info },
1404 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1405 megasas_dcmd_dummy },
1406 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1407 megasas_event_wait },
1408 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1409 megasas_ctrl_shutdown },
1410 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1411 megasas_dcmd_dummy },
1412 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1413 megasas_dcmd_get_fw_time },
1414 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1415 megasas_dcmd_set_fw_time },
1416 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1417 megasas_dcmd_get_bios_info },
1418 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1419 megasas_dcmd_dummy },
1420 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1421 megasas_mfc_get_defaults },
1422 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1423 megasas_dcmd_dummy },
1424 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1425 megasas_cache_flush },
1426 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1427 megasas_dcmd_pd_get_list },
1428 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1429 megasas_dcmd_pd_list_query },
1430 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1431 megasas_dcmd_pd_get_info },
1432 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1433 megasas_dcmd_dummy },
1434 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1435 megasas_dcmd_dummy },
1436 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1437 megasas_dcmd_dummy },
1438 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1439 megasas_dcmd_dummy },
1440 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1441 megasas_dcmd_ld_get_list},
34bb4d02
HR		 1442 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1443 megasas_dcmd_ld_list_query },
e8f943c3
HR		 1444 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1445 megasas_dcmd_ld_get_info },
1446 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1447 megasas_dcmd_dummy },
1448 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1449 megasas_dcmd_dummy },
1450 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1451 megasas_dcmd_dummy },
1452 { MFI_DCMD_CFG_READ, "CFG_READ",
1453 megasas_dcmd_cfg_read },
1454 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1455 megasas_dcmd_dummy },
1456 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1457 megasas_dcmd_dummy },
1458 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1459 megasas_dcmd_dummy },
1460 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1461 megasas_dcmd_dummy },
1462 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1463 megasas_dcmd_dummy },
1464 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1465 megasas_dcmd_dummy },
1466 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1467 megasas_dcmd_dummy },
1468 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1469 megasas_dcmd_dummy },
1470 { MFI_DCMD_CLUSTER, "CLUSTER",
1471 megasas_dcmd_dummy },
1472 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1473 megasas_dcmd_dummy },
1474 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1475 megasas_cluster_reset_ld },
1476 { -1, NULL, NULL }
1477};
1478
1479static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1480{
1481 int opcode, len;
1482 int retval = 0;
1483 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1484
1485 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1486 trace_megasas_handle_dcmd(cmd->index, opcode);
1487 len = megasas_map_dcmd(s, cmd);
1488 if (len < 0) {
1489 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1490 }
1491 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1492 cmdptr++;
1493 }
1494 if (cmdptr->opcode == -1) {
1495 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1496 retval = megasas_dcmd_dummy(s, cmd);
1497 } else {
1498 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1499 retval = cmdptr->func(s, cmd);
1500 }
1501 if (retval != MFI_STAT_INVALID_STATUS) {
1502 megasas_finish_dcmd(cmd, len);
1503 }
1504 return retval;
1505}
1506
1507static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1508 SCSIRequest *req)
1509{
1510 int opcode;
1511 int retval = MFI_STAT_OK;
1512 int lun = req->lun;
1513
1514 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1515 scsi_req_unref(req);
1516 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1517 switch (opcode) {
1518 case MFI_DCMD_PD_GET_INFO:
1519 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1520 break;
1521 case MFI_DCMD_LD_GET_INFO:
1522 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1523 break;
1524 default:
1525 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1526 retval = MFI_STAT_INVALID_DCMD;
1527 break;
1528 }
1529 if (retval != MFI_STAT_INVALID_STATUS) {
1530 megasas_finish_dcmd(cmd, cmd->iov_size);
1531 }
1532 return retval;
1533}
1534
1535static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1536{
1537 int len;
1538
1539 len = scsi_req_enqueue(cmd->req);
1540 if (len < 0) {
1541 len = -len;
1542 }
1543 if (len > 0) {
1544 if (len > cmd->iov_size) {
1545 if (is_write) {
1546 trace_megasas_iov_write_overflow(cmd->index, len,
1547 cmd->iov_size);
1548 } else {
1549 trace_megasas_iov_read_overflow(cmd->index, len,
1550 cmd->iov_size);
1551 }
1552 }
1553 if (len < cmd->iov_size) {
1554 if (is_write) {
1555 trace_megasas_iov_write_underflow(cmd->index, len,
1556 cmd->iov_size);
1557 } else {
1558 trace_megasas_iov_read_underflow(cmd->index, len,
1559 cmd->iov_size);
1560 }
1561 cmd->iov_size = len;
1562 }
1563 scsi_req_continue(cmd->req);
1564 }
1565 return len;
1566}
1567
1568static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1569 bool is_logical)
1570{
1571 uint8_t *cdb;
1572 int len;
1573 bool is_write;
1574 struct SCSIDevice *sdev = NULL;
1575
1576 cdb = cmd->frame->pass.cdb;
1577
1578 if (cmd->frame->header.target_id < s->fw_luns) {
1579 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1580 cmd->frame->header.lun_id);
1581 }
1582 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1583 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1584 is_logical, cmd->frame->header.target_id,
1585 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1586
1587 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1588 trace_megasas_scsi_target_not_present(
1589 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1590 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1591 return MFI_STAT_DEVICE_NOT_FOUND;
1592 }
1593
1594 if (cmd->frame->header.cdb_len > 16) {
1595 trace_megasas_scsi_invalid_cdb_len(
1596 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1597 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1598 cmd->frame->header.cdb_len);
1599 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1600 cmd->frame->header.scsi_status = CHECK_CONDITION;
1601 s->event_count++;
1602 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1603 }
1604
1605 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1606 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1607 cmd->frame->header.scsi_status = CHECK_CONDITION;
1608 s->event_count++;
1609 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1610 }
1611
1612 cmd->req = scsi_req_new(sdev, cmd->index,
1613 cmd->frame->header.lun_id, cdb, cmd);
1614 if (!cmd->req) {
1615 trace_megasas_scsi_req_alloc_failed(
1616 mfi_frame_desc[cmd->frame->header.frame_cmd],
1617 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1618 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1619 cmd->frame->header.scsi_status = BUSY;
1620 s->event_count++;
1621 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1622 }
1623
1624 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1625 len = megasas_enqueue_req(cmd, is_write);
1626 if (len > 0) {
1627 if (is_write) {
1628 trace_megasas_scsi_write_start(cmd->index, len);
1629 } else {
1630 trace_megasas_scsi_read_start(cmd->index, len);
1631 }
1632 } else {
1633 trace_megasas_scsi_nodata(cmd->index);
1634 }
1635 return MFI_STAT_INVALID_STATUS;
1636}
1637
1638static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1639{
1640 uint32_t lba_count, lba_start_hi, lba_start_lo;
1641 uint64_t lba_start;
1642 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1643 uint8_t cdb[16];
1644 int len;
1645 struct SCSIDevice *sdev = NULL;
1646
1647 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1648 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1649 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1650 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1651
1652 if (cmd->frame->header.target_id < s->fw_luns) {
1653 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1654 cmd->frame->header.lun_id);
1655 }
1656
1657 trace_megasas_handle_io(cmd->index,
1658 mfi_frame_desc[cmd->frame->header.frame_cmd],
1659 cmd->frame->header.target_id,
1660 cmd->frame->header.lun_id,
1661 (unsigned long)lba_start, (unsigned long)lba_count);
1662 if (!sdev) {
1663 trace_megasas_io_target_not_present(cmd->index,
1664 mfi_frame_desc[cmd->frame->header.frame_cmd],
1665 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1666 return MFI_STAT_DEVICE_NOT_FOUND;
1667 }
1668
1669 if (cmd->frame->header.cdb_len > 16) {
1670 trace_megasas_scsi_invalid_cdb_len(
1671 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1672 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1673 cmd->frame->header.cdb_len);
1674 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1675 cmd->frame->header.scsi_status = CHECK_CONDITION;
1676 s->event_count++;
1677 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1678 }
1679
1680 cmd->iov_size = lba_count * sdev->blocksize;
1681 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1682 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1683 cmd->frame->header.scsi_status = CHECK_CONDITION;
1684 s->event_count++;
1685 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1686 }
1687
1688 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1689 cmd->req = scsi_req_new(sdev, cmd->index,
1690 cmd->frame->header.lun_id, cdb, cmd);
1691 if (!cmd->req) {
1692 trace_megasas_scsi_req_alloc_failed(
1693 mfi_frame_desc[cmd->frame->header.frame_cmd],
1694 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1695 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1696 cmd->frame->header.scsi_status = BUSY;
1697 s->event_count++;
1698 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1699 }
1700 len = megasas_enqueue_req(cmd, is_write);
1701 if (len > 0) {
1702 if (is_write) {
1703 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1704 } else {
1705 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1706 }
1707 }
1708 return MFI_STAT_INVALID_STATUS;
1709}
1710
1711static int megasas_finish_internal_command(MegasasCmd *cmd,
1712 SCSIRequest *req, size_t resid)
1713{
1714 int retval = MFI_STAT_INVALID_CMD;
1715
1716 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1717 cmd->iov_size -= resid;
1718 retval = megasas_finish_internal_dcmd(cmd, req);
1719 }
1720 return retval;
1721}
1722
1723static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1724{
1725 MegasasCmd *cmd = req->hba_private;
1726
1727 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1728 return NULL;
1729 } else {
1730 return &cmd->qsg;
1731 }
1732}
1733
1734static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1735{
1736 MegasasCmd *cmd = req->hba_private;
1737 uint8_t *buf;
1738 uint32_t opcode;
1739
1740 trace_megasas_io_complete(cmd->index, len);
1741
1742 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1743 scsi_req_continue(req);
1744 return;
1745 }
1746
1747 buf = scsi_req_get_buf(req);
1748 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1749 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1750 struct mfi_pd_info *info = cmd->iov_buf;
1751
1752 if (info->inquiry_data[0] == 0x7f) {
1753 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1754 memcpy(info->inquiry_data, buf, len);
1755 } else if (info->vpd_page83[0] == 0x7f) {
1756 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1757 memcpy(info->vpd_page83, buf, len);
1758 }
1759 scsi_req_continue(req);
1760 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1761 struct mfi_ld_info *info = cmd->iov_buf;
1762
1763 if (cmd->iov_buf) {
1764 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1765 scsi_req_continue(req);
1766 }
1767 }
1768}
1769
1770static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1771 size_t resid)
1772{
1773 MegasasCmd *cmd = req->hba_private;
1774 uint8_t cmd_status = MFI_STAT_OK;
1775
1776 trace_megasas_command_complete(cmd->index, status, resid);
1777
1778 if (cmd->req != req) {
1779 /*
1780 * Internal command complete
1781 */
1782 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1783 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1784 return;
1785 }
1786 } else {
1787 req->status = status;
1788 trace_megasas_scsi_complete(cmd->index, req->status,
1789 cmd->iov_size, req->cmd.xfer);
1790 if (req->status != GOOD) {
1791 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1792 }
1793 if (req->status == CHECK_CONDITION) {
1794 megasas_copy_sense(cmd);
1795 }
1796
1797 megasas_unmap_sgl(cmd);
1798 cmd->frame->header.scsi_status = req->status;
1799 scsi_req_unref(cmd->req);
1800 cmd->req = NULL;
1801 }
1802 cmd->frame->header.cmd_status = cmd_status;
1803 megasas_complete_frame(cmd->state, cmd->context);
1804}
1805
1806static void megasas_command_cancel(SCSIRequest *req)
1807{
1808 MegasasCmd *cmd = req->hba_private;
1809
1810 if (cmd) {
1811 megasas_abort_command(cmd);
1812 } else {
1813 scsi_req_unref(req);
1814 }
1815}
1816
1817static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1818{
1819 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1820 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1821 MegasasCmd *abort_cmd;
1822
1823 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1824 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1825 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1826
1827 abort_cmd = megasas_lookup_frame(s, abort_addr);
1828 if (!abort_cmd) {
1829 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1830 s->event_count++;
1831 return MFI_STAT_OK;
1832 }
1833 if (!megasas_use_queue64(s)) {
1834 abort_ctx &= (uint64_t)0xFFFFFFFF;
1835 }
1836 if (abort_cmd->context != abort_ctx) {
1837 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1838 abort_cmd->context);
1839 s->event_count++;
1840 return MFI_STAT_ABORT_NOT_POSSIBLE;
1841 }
1842 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1843 megasas_abort_command(abort_cmd);
1844 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1845 s->event_cmd = NULL;
1846 }
1847 s->event_count++;
1848 return MFI_STAT_OK;
1849}
1850
1851static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1852 uint32_t frame_count)
1853{
1854 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1855 uint64_t frame_context;
1856 MegasasCmd *cmd;
1857
1858 /*
1859 * Always read 64bit context, top bits will be
1860 * masked out if required in megasas_enqueue_frame()
1861 */
1862 frame_context = megasas_frame_get_context(frame_addr);
1863
1864 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1865 if (!cmd) {
1866 /* reply queue full */
1867 trace_megasas_frame_busy(frame_addr);
1868 megasas_frame_set_scsi_status(frame_addr, BUSY);
1869 megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1870 megasas_complete_frame(s, frame_context);
1871 s->event_count++;
1872 return;
1873 }
1874 switch (cmd->frame->header.frame_cmd) {
1875 case MFI_CMD_INIT:
1876 frame_status = megasas_init_firmware(s, cmd);
1877 break;
1878 case MFI_CMD_DCMD:
1879 frame_status = megasas_handle_dcmd(s, cmd);
1880 break;
1881 case MFI_CMD_ABORT:
1882 frame_status = megasas_handle_abort(s, cmd);
1883 break;
1884 case MFI_CMD_PD_SCSI_IO:
1885 frame_status = megasas_handle_scsi(s, cmd, 0);
1886 break;
1887 case MFI_CMD_LD_SCSI_IO:
1888 frame_status = megasas_handle_scsi(s, cmd, 1);
1889 break;
1890 case MFI_CMD_LD_READ:
1891 case MFI_CMD_LD_WRITE:
1892 frame_status = megasas_handle_io(s, cmd);
1893 break;
1894 default:
1895 trace_megasas_unhandled_frame_cmd(cmd->index,
1896 cmd->frame->header.frame_cmd);
1897 s->event_count++;
1898 break;
1899 }
1900 if (frame_status != MFI_STAT_INVALID_STATUS) {
1901 if (cmd->frame) {
1902 cmd->frame->header.cmd_status = frame_status;
1903 } else {
1904 megasas_frame_set_cmd_status(frame_addr, frame_status);
1905 }
1906 megasas_complete_frame(s, cmd->context);
1907 }
1908}
1909
a8170e5e 1910static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 1911 unsigned size)
1912{
1913 MegasasState *s = opaque;
1914 uint32_t retval = 0;
1915
1916 switch (addr) {
1917 case MFI_IDB:
1918 retval = 0;
1919 break;
1920 case MFI_OMSG0:
1921 case MFI_OSP0:
1922 retval = (megasas_use_msix(s) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
1923 (s->fw_state & MFI_FWSTATE_MASK) |
1924 ((s->fw_sge & 0xff) << 16) |
1925 (s->fw_cmds & 0xFFFF);
1926 break;
1927 case MFI_OSTS:
1928 if (megasas_intr_enabled(s) && s->doorbell) {
1929 retval = MFI_1078_RM | 1;
1930 }
1931 break;
1932 case MFI_OMSK:
1933 retval = s->intr_mask;
1934 break;
1935 case MFI_ODCR0:
1936 retval = s->doorbell;
1937 break;
1938 default:
1939 trace_megasas_mmio_invalid_readl(addr);
1940 break;
1941 }
1942 trace_megasas_mmio_readl(addr, retval);
1943 return retval;
1944}
1945
a8170e5e 1946static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 1947 uint64_t val, unsigned size)
1948{
1949 MegasasState *s = opaque;
52190c1e 1950 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 1951 uint64_t frame_addr;
1952 uint32_t frame_count;
1953 int i;
1954
1955 trace_megasas_mmio_writel(addr, val);
1956 switch (addr) {
1957 case MFI_IDB:
1958 if (val & MFI_FWINIT_ABORT) {
1959 /* Abort all pending cmds */
1960 for (i = 0; i < s->fw_cmds; i++) {
1961 megasas_abort_command(&s->frames[i]);
1962 }
1963 }
1964 if (val & MFI_FWINIT_READY) {
1965 /* move to FW READY */
1966 megasas_soft_reset(s);
1967 }
1968 if (val & MFI_FWINIT_MFIMODE) {
1969 /* discard MFIs */
1970 }
1971 break;
1972 case MFI_OMSK:
1973 s->intr_mask = val;
4522b69c
HR		 1974 if (!megasas_intr_enabled(s) &&
1975 !msi_enabled(pci_dev) &&
1976 !msix_enabled(pci_dev)) {
e8f943c3 1977 trace_megasas_irq_lower();
9e64f8a3 1978 pci_irq_deassert(pci_dev);
e8f943c3
HR		 1979 }
1980 if (megasas_intr_enabled(s)) {
4522b69c
HR		 1981 if (msix_enabled(pci_dev)) {
1982 trace_megasas_msix_enabled(0);
1983 } else if (msi_enabled(pci_dev)) {
1984 trace_megasas_msi_enabled(0);
1985 } else {
1986 trace_megasas_intr_enabled();
1987 }
e8f943c3
HR		 1988 } else {
1989 trace_megasas_intr_disabled();
1990 }
1991 break;
1992 case MFI_ODCR0:
1993 s->doorbell = 0;
1994 if (s->producer_pa && megasas_intr_enabled(s)) {
1995 /* Update reply queue pointer */
1996 trace_megasas_qf_update(s->reply_queue_head, s->busy);
ab1da857
EI		 1997 stl_le_phys(&address_space_memory,
1998 s->producer_pa, s->reply_queue_head);
52190c1e 1999 if (!msix_enabled(pci_dev)) {
e8f943c3 2000 trace_megasas_irq_lower();
9e64f8a3 2001 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2002 }
2003 }
2004 break;
2005 case MFI_IQPH:
2006 /* Received high 32 bits of a 64 bit MFI frame address */
2007 s->frame_hi = val;
2008 break;
2009 case MFI_IQPL:
2010 /* Received low 32 bits of a 64 bit MFI frame address */
2011 case MFI_IQP:
2012 /* Received 32 bit MFI frame address */
2013 frame_addr = (val & ~0x1F);
2014 /* Add possible 64 bit offset */
2015 frame_addr |= ((uint64_t)s->frame_hi << 32);
2016 s->frame_hi = 0;
2017 frame_count = (val >> 1) & 0xF;
2018 megasas_handle_frame(s, frame_addr, frame_count);
2019 break;
2020 default:
2021 trace_megasas_mmio_invalid_writel(addr, val);
2022 break;
2023 }
2024}
2025
2026static const MemoryRegionOps megasas_mmio_ops = {
2027 .read = megasas_mmio_read,
2028 .write = megasas_mmio_write,
2029 .endianness = DEVICE_LITTLE_ENDIAN,
2030 .impl = {
2031 .min_access_size = 8,
2032 .max_access_size = 8,
2033 }
2034};
2035
a8170e5e 2036static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2037 unsigned size)
2038{
2039 return megasas_mmio_read(opaque, addr & 0xff, size);
2040}
2041
a8170e5e 2042static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2043 uint64_t val, unsigned size)
2044{
2045 megasas_mmio_write(opaque, addr & 0xff, val, size);
2046}
2047
2048static const MemoryRegionOps megasas_port_ops = {
2049 .read = megasas_port_read,
2050 .write = megasas_port_write,
2051 .endianness = DEVICE_LITTLE_ENDIAN,
2052 .impl = {
2053 .min_access_size = 4,
2054 .max_access_size = 4,
2055 }
2056};
2057
a8170e5e 2058static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2059 unsigned size)
2060{
2061 return 0;
2062}
2063
2064static const MemoryRegionOps megasas_queue_ops = {
2065 .read = megasas_queue_read,
2066 .endianness = DEVICE_LITTLE_ENDIAN,
2067 .impl = {
2068 .min_access_size = 8,
2069 .max_access_size = 8,
2070 }
2071};
2072
2073static void megasas_soft_reset(MegasasState *s)
2074{
2075 int i;
2076 MegasasCmd *cmd;
2077
2078 trace_megasas_reset();
2079 for (i = 0; i < s->fw_cmds; i++) {
2080 cmd = &s->frames[i];
2081 megasas_abort_command(cmd);
2082 }
2083 megasas_reset_frames(s);
2084 s->reply_queue_len = s->fw_cmds;
2085 s->reply_queue_pa = 0;
2086 s->consumer_pa = 0;
2087 s->producer_pa = 0;
2088 s->fw_state = MFI_FWSTATE_READY;
2089 s->doorbell = 0;
2090 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2091 s->frame_hi = 0;
2092 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2093 s->event_count++;
2094 s->boot_event = s->event_count;
2095}
2096
2097static void megasas_scsi_reset(DeviceState *dev)
2098{
c79e16ae 2099 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2100
2101 megasas_soft_reset(s);
2102}
2103
2104static const VMStateDescription vmstate_megasas = {
2105 .name = "megasas",
2106 .version_id = 0,
2107 .minimum_version_id = 0,
d49805ae 2108 .fields = (VMStateField[]) {
52190c1e 2109 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
23335f62 2110 VMSTATE_MSIX(parent_obj, MegasasState),
e8f943c3
HR		 2111
2112 VMSTATE_INT32(fw_state, MegasasState),
2113 VMSTATE_INT32(intr_mask, MegasasState),
2114 VMSTATE_INT32(doorbell, MegasasState),
2115 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2116 VMSTATE_UINT64(consumer_pa, MegasasState),
2117 VMSTATE_UINT64(producer_pa, MegasasState),
2118 VMSTATE_END_OF_LIST()
2119 }
2120};
2121
18fc611b 2122static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2123{
c79e16ae 2124 MegasasState *s = MEGASAS(d);
e8f943c3 2125
4522b69c
HR		 2126 if (megasas_use_msix(s)) {
2127 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2128 }
2129 if (megasas_use_msi(s)) {
2130 msi_uninit(d);
2131 }
e8f943c3
HR		 2132}
2133
2134static const struct SCSIBusInfo megasas_scsi_info = {
2135 .tcq = true,
2136 .max_target = MFI_MAX_LD,
2137 .max_lun = 255,
2138
2139 .transfer_data = megasas_xfer_complete,
2140 .get_sg_list = megasas_get_sg_list,
2141 .complete = megasas_command_complete,
2142 .cancel = megasas_command_cancel,
2143};
2144
2145static int megasas_scsi_init(PCIDevice *dev)
2146{
22d6aa03 2147 DeviceState *d = DEVICE(dev);
c79e16ae 2148 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2149 uint8_t *pci_conf;
2150 int i, bar_type;
caad4eb3 2151 Error *err = NULL;
e8f943c3 2152
52190c1e 2153 pci_conf = dev->config;
e8f943c3
HR		 2154
2155 /* PCI latency timer = 0 */
2156 pci_conf[PCI_LATENCY_TIMER] = 0;
2157 /* Interrupt pin 1 */
2158 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2159
29776739 2160 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2161 "megasas-mmio", 0x4000);
29776739 2162 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2163 "megasas-io", 256);
29776739 2164 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2165 "megasas-queue", 0x40000);
2166
4522b69c
HR		 2167 if (megasas_use_msi(s) &&
2168 msi_init(dev, 0x50, 1, true, false)) {
2169 s->flags &= ~MEGASAS_MASK_USE_MSI;
2170 }
e8f943c3 2171 if (megasas_use_msix(s) &&
23335f62
HR		 2172 msix_init(dev, 15, &s->mmio_io, 0, 0x2000,
2173 &s->mmio_io, 0, 0x3800, 0x68)) {
e8f943c3
HR		 2174 s->flags &= ~MEGASAS_MASK_USE_MSIX;
2175 }
e8f943c3
HR		 2176
2177 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
52190c1e
AF		 2178 pci_register_bar(dev, 0, bar_type, &s->mmio_io);
2179 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2180 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2181
2182 if (megasas_use_msix(s)) {
52190c1e 2183 msix_vector_use(dev, 0);
e8f943c3
HR		 2184 }
2185
76b523db
HR		 2186 if (!s->sas_addr) {
2187 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2188 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2189 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2190 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2191 s->sas_addr |= PCI_FUNC(dev->devfn);
2192 }
fb654157 2193 if (!s->hba_serial) {
23335f62 2194 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
fb654157 2195 }
e8f943c3
HR		 2196 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2197 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2198 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2199 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2200 } else {
2201 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2202 }
2203 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2204 s->fw_cmds = MEGASAS_MAX_FRAMES;
2205 }
2206 trace_megasas_init(s->fw_sge, s->fw_cmds,
e8f943c3
HR		 2207 megasas_is_jbod(s) ? "jbod" : "raid");
2208 s->fw_luns = (MFI_MAX_LD > MAX_SCSI_DEVS) ?
2209 MAX_SCSI_DEVS : MFI_MAX_LD;
2210 s->producer_pa = 0;
2211 s->consumer_pa = 0;
2212 for (i = 0; i < s->fw_cmds; i++) {
2213 s->frames[i].index = i;
2214 s->frames[i].context = -1;
2215 s->frames[i].pa = 0;
2216 s->frames[i].state = s;
2217 }
2218
b1187b51
AF		 2219 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2220 &megasas_scsi_info, NULL);
22d6aa03 2221 if (!d->hotplugged) {
caad4eb3
AF		 2222 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
2223 if (err != NULL) {
2224 error_free(err);
2225 return -1;
2226 }
22d6aa03 2227 }
e8f943c3
HR		 2228 return 0;
2229}
2230
4522b69c
HR		 2231static void
2232megasas_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len)
2233{
2234 pci_default_write_config(pci, addr, val, len);
2235 msi_write_config(pci, addr, val, len);
2236}
2237
e8f943c3
HR		 2238static Property megasas_properties[] = {
2239 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2240 MEGASAS_DEFAULT_SGE),
2241 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2242 MEGASAS_DEFAULT_FRAMES),
fb654157 2243 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
c7bcc85d 2244 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
4522b69c
HR		 2245 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2246 MEGASAS_FLAG_USE_MSI, false),
e8f943c3
HR		 2247 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2248 MEGASAS_FLAG_USE_MSIX, false),
e8f943c3
HR		 2249 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2250 MEGASAS_FLAG_USE_JBOD, false),
2251 DEFINE_PROP_END_OF_LIST(),
2252};
2253
2254static void megasas_class_init(ObjectClass *oc, void *data)
2255{
2256 DeviceClass *dc = DEVICE_CLASS(oc);
2257 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2258
2259 pc->init = megasas_scsi_init;
2260 pc->exit = megasas_scsi_uninit;
2261 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2262 pc->device_id = PCI_DEVICE_ID_LSI_SAS1078;
2263 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2264 pc->subsystem_id = 0x1013;
2265 pc->class_id = PCI_CLASS_STORAGE_RAID;
2266 dc->props = megasas_properties;
2267 dc->reset = megasas_scsi_reset;
2268 dc->vmsd = &vmstate_megasas;
125ee0ed 2269 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e8f943c3 2270 dc->desc = "LSI MegaRAID SAS 1078";
4522b69c 2271 pc->config_write = megasas_write_config;
e8f943c3
HR		 2272}
2273
2274static const TypeInfo megasas_info = {
c79e16ae 2275 .name = TYPE_MEGASAS,
e8f943c3
HR		 2276 .parent = TYPE_PCI_DEVICE,
2277 .instance_size = sizeof(MegasasState),
2278 .class_init = megasas_class_init,
2279};
2280
2281static void megasas_register_types(void)
2282{
2283 type_register_static(&megasas_info);
2284}
2285
2286type_init(megasas_register_types)
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