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megasas: remove buildtime strings
[mirror_qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
83c9f4ca
PB		 21#include "hw/hw.h"
22#include "hw/pci/pci.h"
9c17d615 23#include "sysemu/dma.h"
4522b69c 24#include "hw/pci/msi.h"
83c9f4ca 25#include "hw/pci/msix.h"
1de7afc9 26#include "qemu/iov.h"
0d09e41a
PB		 27#include "hw/scsi/scsi.h"
28#include "block/scsi.h"
e8f943c3
HR		 29#include "trace.h"
30
47b43a1f 31#include "mfi.h"
e8f943c3
HR		 32
33#define MEGASAS_VERSION "1.70"
34#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
35#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
36#define MEGASAS_MAX_SGE 128 /* Firmware limit */
37#define MEGASAS_DEFAULT_SGE 80
38#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
39#define MEGASAS_MAX_ARRAYS 128
40
fb654157 41#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 42#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
43#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
44
e8f943c3
HR		 45#define MEGASAS_FLAG_USE_JBOD 0
46#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
4522b69c
HR		 47#define MEGASAS_FLAG_USE_MSI 1
48#define MEGASAS_MASK_USE_MSI (1 << MEGASAS_FLAG_USE_MSI)
49#define MEGASAS_FLAG_USE_MSIX 2
e8f943c3 50#define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX)
4522b69c 51#define MEGASAS_FLAG_USE_QUEUE64 3
e8f943c3
HR		 52#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
53
a97ad268 54static const char *mfi_frame_desc[] = {
e8f943c3
HR		 55 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
56 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
57
58typedef struct MegasasCmd {
59 uint32_t index;
60 uint16_t flags;
61 uint16_t count;
62 uint64_t context;
63
a8170e5e
AK		 64 hwaddr pa;
65 hwaddr pa_size;
e8f943c3
HR		 66 union mfi_frame *frame;
67 SCSIRequest *req;
68 QEMUSGList qsg;
69 void *iov_buf;
70 size_t iov_size;
71 size_t iov_offset;
72 struct MegasasState *state;
73} MegasasCmd;
74
75typedef struct MegasasState {
52190c1e
AF		 76 /*< private >*/
77 PCIDevice parent_obj;
78 /*< public >*/
79
e8f943c3
HR		 80 MemoryRegion mmio_io;
81 MemoryRegion port_io;
82 MemoryRegion queue_io;
83 uint32_t frame_hi;
84
85 int fw_state;
86 uint32_t fw_sge;
87 uint32_t fw_cmds;
88 uint32_t flags;
89 int fw_luns;
90 int intr_mask;
91 int doorbell;
92 int busy;
93
94 MegasasCmd *event_cmd;
95 int event_locale;
96 int event_class;
97 int event_count;
98 int shutdown_event;
99 int boot_event;
100
76b523db 101 uint64_t sas_addr;
fb654157 102 char *hba_serial;
76b523db 103
e8f943c3
HR		 104 uint64_t reply_queue_pa;
105 void *reply_queue;
106 int reply_queue_len;
107 int reply_queue_head;
108 int reply_queue_tail;
109 uint64_t consumer_pa;
110 uint64_t producer_pa;
111
112 MegasasCmd frames[MEGASAS_MAX_FRAMES];
113
114 SCSIBus bus;
115} MegasasState;
116
c79e16ae
PC		 117#define TYPE_MEGASAS "megasas"
118
119#define MEGASAS(obj) \
120 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS)
121
e8f943c3
HR		 122#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
123
124static bool megasas_intr_enabled(MegasasState *s)
125{
126 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
127 MEGASAS_INTR_DISABLED_MASK) {
128 return true;
129 }
130 return false;
131}
132
133static bool megasas_use_queue64(MegasasState *s)
134{
135 return s->flags & MEGASAS_MASK_USE_QUEUE64;
136}
137
4522b69c
HR		 138static bool megasas_use_msi(MegasasState *s)
139{
140 return s->flags & MEGASAS_MASK_USE_MSI;
141}
142
e8f943c3
HR		 143static bool megasas_use_msix(MegasasState *s)
144{
145 return s->flags & MEGASAS_MASK_USE_MSIX;
146}
147
148static bool megasas_is_jbod(MegasasState *s)
149{
150 return s->flags & MEGASAS_MASK_USE_JBOD;
151}
152
153static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v)
154{
db3be60d
EI		 155 stb_phys(&address_space_memory,
156 frame + offsetof(struct mfi_frame_header, cmd_status), v);
e8f943c3
HR		 157}
158
159static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v)
160{
db3be60d
EI		 161 stb_phys(&address_space_memory,
162 frame + offsetof(struct mfi_frame_header, scsi_status), v);
e8f943c3
HR		 163}
164
165/*
166 * Context is considered opaque, but the HBA firmware is running
167 * in little endian mode. So convert it to little endian, too.
168 */
169static uint64_t megasas_frame_get_context(unsigned long frame)
170{
2c17449b
EI		 171 return ldq_le_phys(&address_space_memory,
172 frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 173}
174
175static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
176{
177 return cmd->flags & MFI_FRAME_IEEE_SGL;
178}
179
180static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
181{
182 return cmd->flags & MFI_FRAME_SGL64;
183}
184
185static bool megasas_frame_is_sense64(MegasasCmd *cmd)
186{
187 return cmd->flags & MFI_FRAME_SENSE64;
188}
189
190static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
191 union mfi_sgl *sgl)
192{
193 uint64_t addr;
194
195 if (megasas_frame_is_ieee_sgl(cmd)) {
196 addr = le64_to_cpu(sgl->sg_skinny->addr);
197 } else if (megasas_frame_is_sgl64(cmd)) {
198 addr = le64_to_cpu(sgl->sg64->addr);
199 } else {
200 addr = le32_to_cpu(sgl->sg32->addr);
201 }
202 return addr;
203}
204
205static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
206 union mfi_sgl *sgl)
207{
208 uint32_t len;
209
210 if (megasas_frame_is_ieee_sgl(cmd)) {
211 len = le32_to_cpu(sgl->sg_skinny->len);
212 } else if (megasas_frame_is_sgl64(cmd)) {
213 len = le32_to_cpu(sgl->sg64->len);
214 } else {
215 len = le32_to_cpu(sgl->sg32->len);
216 }
217 return len;
218}
219
220static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
221 union mfi_sgl *sgl)
222{
223 uint8_t *next = (uint8_t *)sgl;
224
225 if (megasas_frame_is_ieee_sgl(cmd)) {
226 next += sizeof(struct mfi_sg_skinny);
227 } else if (megasas_frame_is_sgl64(cmd)) {
228 next += sizeof(struct mfi_sg64);
229 } else {
230 next += sizeof(struct mfi_sg32);
231 }
232
233 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
234 return NULL;
235 }
236 return (union mfi_sgl *)next;
237}
238
239static void megasas_soft_reset(MegasasState *s);
240
241static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
242{
243 int i;
244 int iov_count = 0;
245 size_t iov_size = 0;
246
247 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
248 iov_count = cmd->frame->header.sge_count;
249 if (iov_count > MEGASAS_MAX_SGE) {
250 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
251 MEGASAS_MAX_SGE);
252 return iov_count;
253 }
52190c1e 254 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 255 for (i = 0; i < iov_count; i++) {
256 dma_addr_t iov_pa, iov_size_p;
257
258 if (!sgl) {
259 trace_megasas_iovec_sgl_underflow(cmd->index, i);
260 goto unmap;
261 }
262 iov_pa = megasas_sgl_get_addr(cmd, sgl);
263 iov_size_p = megasas_sgl_get_len(cmd, sgl);
264 if (!iov_pa || !iov_size_p) {
265 trace_megasas_iovec_sgl_invalid(cmd->index, i,
266 iov_pa, iov_size_p);
267 goto unmap;
268 }
269 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
270 sgl = megasas_sgl_next(cmd, sgl);
271 iov_size += (size_t)iov_size_p;
272 }
273 if (cmd->iov_size > iov_size) {
274 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
275 } else if (cmd->iov_size < iov_size) {
276 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
277 }
278 cmd->iov_offset = 0;
279 return 0;
280unmap:
281 qemu_sglist_destroy(&cmd->qsg);
282 return iov_count - i;
283}
284
285static void megasas_unmap_sgl(MegasasCmd *cmd)
286{
287 qemu_sglist_destroy(&cmd->qsg);
288 cmd->iov_offset = 0;
289}
290
291/*
292 * passthrough sense and io sense are at the same offset
293 */
294static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
295 uint8_t sense_len)
296{
297 uint32_t pa_hi = 0, pa_lo;
a8170e5e 298 hwaddr pa;
e8f943c3
HR		 299
300 if (sense_len > cmd->frame->header.sense_len) {
301 sense_len = cmd->frame->header.sense_len;
302 }
303 if (sense_len) {
304 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
305 if (megasas_frame_is_sense64(cmd)) {
306 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
307 }
308 pa = ((uint64_t) pa_hi << 32) | pa_lo;
309 cpu_physical_memory_write(pa, sense_ptr, sense_len);
310 cmd->frame->header.sense_len = sense_len;
311 }
312 return sense_len;
313}
314
315static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
316{
317 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
318 uint8_t sense_len = 18;
319
320 memset(sense_buf, 0, sense_len);
321 sense_buf[0] = 0xf0;
322 sense_buf[2] = sense.key;
323 sense_buf[7] = 10;
324 sense_buf[12] = sense.asc;
325 sense_buf[13] = sense.ascq;
326 megasas_build_sense(cmd, sense_buf, sense_len);
327}
328
329static void megasas_copy_sense(MegasasCmd *cmd)
330{
331 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
332 uint8_t sense_len;
333
334 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
335 SCSI_SENSE_BUF_SIZE);
336 megasas_build_sense(cmd, sense_buf, sense_len);
337}
338
339/*
340 * Format an INQUIRY CDB
341 */
342static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
343{
344 memset(cdb, 0, 6);
345 cdb[0] = INQUIRY;
346 if (pg > 0) {
347 cdb[1] = 0x1;
348 cdb[2] = pg;
349 }
350 cdb[3] = (len >> 8) & 0xff;
351 cdb[4] = (len & 0xff);
352 return len;
353}
354
355/*
356 * Encode lba and len into a READ_16/WRITE_16 CDB
357 */
358static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
359 uint32_t len, bool is_write)
360{
361 memset(cdb, 0x0, 16);
362 if (is_write) {
363 cdb[0] = WRITE_16;
364 } else {
365 cdb[0] = READ_16;
366 }
367 cdb[2] = (lba >> 56) & 0xff;
368 cdb[3] = (lba >> 48) & 0xff;
369 cdb[4] = (lba >> 40) & 0xff;
370 cdb[5] = (lba >> 32) & 0xff;
371 cdb[6] = (lba >> 24) & 0xff;
372 cdb[7] = (lba >> 16) & 0xff;
373 cdb[8] = (lba >> 8) & 0xff;
374 cdb[9] = (lba) & 0xff;
375 cdb[10] = (len >> 24) & 0xff;
376 cdb[11] = (len >> 16) & 0xff;
377 cdb[12] = (len >> 8) & 0xff;
378 cdb[13] = (len) & 0xff;
379}
380
381/*
382 * Utility functions
383 */
384static uint64_t megasas_fw_time(void)
385{
386 struct tm curtime;
387 uint64_t bcd_time;
388
389 qemu_get_timedate(&curtime, 0);
390 bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 |
391 ((uint64_t)curtime.tm_min & 0xff) << 40 |
392 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
393 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
394 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
395 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
396
397 return bcd_time;
398}
399
76b523db
HR		 400/*
401 * Default disk sata address
402 * 0x1221 is the magic number as
403 * present in real hardware,
404 * so use it here, too.
405 */
406static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 407{
76b523db
HR		 408 uint64_t addr = (0x1221ULL << 48);
409 return addr & (id << 24);
e8f943c3
HR		 410}
411
412/*
413 * Frame handling
414 */
415static int megasas_next_index(MegasasState *s, int index, int limit)
416{
417 index++;
418 if (index == limit) {
419 index = 0;
420 }
421 return index;
422}
423
424static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 425 hwaddr frame)
e8f943c3
HR		 426{
427 MegasasCmd *cmd = NULL;
428 int num = 0, index;
429
430 index = s->reply_queue_head;
431
432 while (num < s->fw_cmds) {
433 if (s->frames[index].pa && s->frames[index].pa == frame) {
434 cmd = &s->frames[index];
435 break;
436 }
437 index = megasas_next_index(s, index, s->fw_cmds);
438 num++;
439 }
440
441 return cmd;
442}
443
444static MegasasCmd *megasas_next_frame(MegasasState *s,
a8170e5e 445 hwaddr frame)
e8f943c3
HR		 446{
447 MegasasCmd *cmd = NULL;
448 int num = 0, index;
449
450 cmd = megasas_lookup_frame(s, frame);
451 if (cmd) {
452 trace_megasas_qf_found(cmd->index, cmd->pa);
453 return cmd;
454 }
455 index = s->reply_queue_head;
456 num = 0;
457 while (num < s->fw_cmds) {
458 if (!s->frames[index].pa) {
459 cmd = &s->frames[index];
460 break;
461 }
462 index = megasas_next_index(s, index, s->fw_cmds);
463 num++;
464 }
465 if (!cmd) {
466 trace_megasas_qf_failed(frame);
467 }
468 trace_megasas_qf_new(index, cmd);
469 return cmd;
470}
471
472static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 473 hwaddr frame, uint64_t context, int count)
e8f943c3
HR		 474{
475 MegasasCmd *cmd = NULL;
476 int frame_size = MFI_FRAME_SIZE * 16;
a8170e5e 477 hwaddr frame_size_p = frame_size;
e8f943c3
HR		 478
479 cmd = megasas_next_frame(s, frame);
480 /* All frames busy */
481 if (!cmd) {
482 return NULL;
483 }
484 if (!cmd->pa) {
485 cmd->pa = frame;
486 /* Map all possible frames */
487 cmd->frame = cpu_physical_memory_map(frame, &frame_size_p, 0);
488 if (frame_size_p != frame_size) {
489 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
490 if (cmd->frame) {
491 cpu_physical_memory_unmap(cmd->frame, frame_size_p, 0, 0);
492 cmd->frame = NULL;
493 cmd->pa = 0;
494 }
495 s->event_count++;
496 return NULL;
497 }
498 cmd->pa_size = frame_size_p;
499 cmd->context = context;
500 if (!megasas_use_queue64(s)) {
501 cmd->context &= (uint64_t)0xFFFFFFFF;
502 }
503 }
504 cmd->count = count;
505 s->busy++;
506
507 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
508 s->reply_queue_head, s->busy);
509
510 return cmd;
511}
512
513static void megasas_complete_frame(MegasasState *s, uint64_t context)
514{
52190c1e 515 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 516 int tail, queue_offset;
517
518 /* Decrement busy count */
519 s->busy--;
520
521 if (s->reply_queue_pa) {
522 /*
523 * Put command on the reply queue.
524 * Context is opaque, but emulation is running in
525 * little endian. So convert it.
526 */
527 tail = s->reply_queue_head;
528 if (megasas_use_queue64(s)) {
529 queue_offset = tail * sizeof(uint64_t);
f606604f
EI		 530 stq_le_phys(&address_space_memory,
531 s->reply_queue_pa + queue_offset, context);
e8f943c3
HR		 532 } else {
533 queue_offset = tail * sizeof(uint32_t);
ab1da857
EI		 534 stl_le_phys(&address_space_memory,
535 s->reply_queue_pa + queue_offset, context);
e8f943c3
HR		 536 }
537 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
538 trace_megasas_qf_complete(context, tail, queue_offset,
539 s->busy, s->doorbell);
540 }
541
542 if (megasas_intr_enabled(s)) {
543 /* Notify HBA */
544 s->doorbell++;
545 if (s->doorbell == 1) {
52190c1e 546 if (msix_enabled(pci_dev)) {
e8f943c3 547 trace_megasas_msix_raise(0);
52190c1e 548 msix_notify(pci_dev, 0);
4522b69c
HR		 549 } else if (msi_enabled(pci_dev)) {
550 trace_megasas_msi_raise(0);
551 msi_notify(pci_dev, 0);
e8f943c3
HR		 552 } else {
553 trace_megasas_irq_raise();
9e64f8a3 554 pci_irq_assert(pci_dev);
e8f943c3
HR		 555 }
556 }
557 } else {
558 trace_megasas_qf_complete_noirq(context);
559 }
560}
561
562static void megasas_reset_frames(MegasasState *s)
563{
564 int i;
565 MegasasCmd *cmd;
566
567 for (i = 0; i < s->fw_cmds; i++) {
568 cmd = &s->frames[i];
569 if (cmd->pa) {
570 cpu_physical_memory_unmap(cmd->frame, cmd->pa_size, 0, 0);
571 cmd->frame = NULL;
572 cmd->pa = 0;
573 }
574 }
575}
576
577static void megasas_abort_command(MegasasCmd *cmd)
578{
579 if (cmd->req) {
e2b06058 580 scsi_req_cancel(cmd->req);
e8f943c3
HR		 581 cmd->req = NULL;
582 }
583}
584
585static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
586{
587 uint32_t pa_hi, pa_lo;
a8170e5e 588 hwaddr iq_pa, initq_size;
e8f943c3
HR		 589 struct mfi_init_qinfo *initq;
590 uint32_t flags;
591 int ret = MFI_STAT_OK;
592
593 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
594 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
595 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
596 trace_megasas_init_firmware((uint64_t)iq_pa);
597 initq_size = sizeof(*initq);
598 initq = cpu_physical_memory_map(iq_pa, &initq_size, 0);
599 if (!initq || initq_size != sizeof(*initq)) {
600 trace_megasas_initq_map_failed(cmd->index);
601 s->event_count++;
602 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
603 goto out;
604 }
605 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
606 if (s->reply_queue_len > s->fw_cmds) {
607 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
608 s->event_count++;
609 ret = MFI_STAT_INVALID_PARAMETER;
610 goto out;
611 }
612 pa_lo = le32_to_cpu(initq->rq_addr_lo);
613 pa_hi = le32_to_cpu(initq->rq_addr_hi);
614 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
615 pa_lo = le32_to_cpu(initq->ci_addr_lo);
616 pa_hi = le32_to_cpu(initq->ci_addr_hi);
617 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
618 pa_lo = le32_to_cpu(initq->pi_addr_lo);
619 pa_hi = le32_to_cpu(initq->pi_addr_hi);
620 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
fdfba1a2
EI		 621 s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa);
622 s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa);
e8f943c3
HR		 623 flags = le32_to_cpu(initq->flags);
624 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
625 s->flags |= MEGASAS_MASK_USE_QUEUE64;
626 }
627 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
628 s->reply_queue_len, s->reply_queue_head,
629 s->reply_queue_tail, flags);
630 megasas_reset_frames(s);
631 s->fw_state = MFI_FWSTATE_OPERATIONAL;
632out:
633 if (initq) {
634 cpu_physical_memory_unmap(initq, initq_size, 0, 0);
635 }
636 return ret;
637}
638
639static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
640{
641 dma_addr_t iov_pa, iov_size;
642
643 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
644 if (!cmd->frame->header.sge_count) {
645 trace_megasas_dcmd_zero_sge(cmd->index);
646 cmd->iov_size = 0;
647 return 0;
648 } else if (cmd->frame->header.sge_count > 1) {
649 trace_megasas_dcmd_invalid_sge(cmd->index,
650 cmd->frame->header.sge_count);
651 cmd->iov_size = 0;
652 return -1;
653 }
654 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
655 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 656 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 657 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
658 cmd->iov_size = iov_size;
659 return cmd->iov_size;
660}
661
662static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
663{
664 trace_megasas_finish_dcmd(cmd->index, iov_size);
665
666 if (cmd->frame->header.sge_count) {
667 qemu_sglist_destroy(&cmd->qsg);
668 }
669 if (iov_size > cmd->iov_size) {
670 if (megasas_frame_is_ieee_sgl(cmd)) {
671 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
672 } else if (megasas_frame_is_sgl64(cmd)) {
673 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
674 } else {
675 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
676 }
677 }
678 cmd->iov_size = 0;
e8f943c3
HR		 679}
680
681static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
682{
52190c1e 683 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 684 struct mfi_ctrl_info info;
685 size_t dcmd_size = sizeof(info);
686 BusChild *kid;
687 int num_ld_disks = 0;
76b523db 688 uint16_t sdev_id;
e8f943c3
HR		 689
690 memset(&info, 0x0, cmd->iov_size);
691 if (cmd->iov_size < dcmd_size) {
692 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
693 dcmd_size);
694 return MFI_STAT_INVALID_PARAMETER;
695 }
696
697 info.pci.vendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC);
698 info.pci.device = cpu_to_le16(PCI_DEVICE_ID_LSI_SAS1078);
699 info.pci.subvendor = cpu_to_le16(PCI_VENDOR_ID_LSI_LOGIC);
700 info.pci.subdevice = cpu_to_le16(0x1013);
701
76b523db
HR		 702 /*
703 * For some reason the firmware supports
704 * only up to 8 device ports.
705 * Despite supporting a far larger number
706 * of devices for the physical devices.
707 * So just display the first 8 devices
708 * in the device port list, independent
709 * of how many logical devices are actually
710 * present.
711 */
712 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 713 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 714 info.device.port_count = 8;
715 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
716 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
717
718 if (num_ld_disks < 8) {
719 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
720 info.device.port_addr[num_ld_disks] =
721 cpu_to_le64(megasas_get_sata_addr(sdev_id));
722 }
723 num_ld_disks++;
724 }
e8f943c3
HR		 725
726 memcpy(info.product_name, "MegaRAID SAS 8708EM2", 20);
fb654157 727 snprintf(info.serial_number, 32, "%s", s->hba_serial);
e8f943c3
HR		 728 snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION);
729 memcpy(info.image_component[0].name, "APP", 3);
730 memcpy(info.image_component[0].version, MEGASAS_VERSION "-QEMU", 9);
5a7733b0
OH		 731 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
732 memcpy(info.image_component[0].build_time, "12:34:56", 8);
e8f943c3 733 info.image_component_count = 1;
52190c1e 734 if (pci_dev->has_rom) {
e8f943c3
HR		 735 uint8_t biosver[32];
736 uint8_t *ptr;
737
52190c1e 738 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 739 memcpy(biosver, ptr + 0x41, 31);
e8f943c3
HR		 740 memcpy(info.image_component[1].name, "BIOS", 4);
741 memcpy(info.image_component[1].version, biosver,
742 strlen((const char *)biosver));
743 info.image_component_count++;
744 }
745 info.current_fw_time = cpu_to_le32(megasas_fw_time());
746 info.max_arms = 32;
747 info.max_spans = 8;
748 info.max_arrays = MEGASAS_MAX_ARRAYS;
749 info.max_lds = s->fw_luns;
750 info.max_cmds = cpu_to_le16(s->fw_cmds);
751 info.max_sg_elements = cpu_to_le16(s->fw_sge);
752 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
753 info.lds_present = cpu_to_le16(num_ld_disks);
754 info.pd_present = cpu_to_le16(num_ld_disks);
755 info.pd_disks_present = cpu_to_le16(num_ld_disks);
756 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
757 MFI_INFO_HW_MEM |
758 MFI_INFO_HW_FLASH);
759 info.memory_size = cpu_to_le16(512);
760 info.nvram_size = cpu_to_le16(32);
761 info.flash_size = cpu_to_le16(16);
762 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
763 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
764 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
765 MFI_INFO_AOPS_MIXED_ARRAY);
766 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
767 MFI_INFO_LDOPS_ACCESS_POLICY |
768 MFI_INFO_LDOPS_IO_POLICY |
769 MFI_INFO_LDOPS_WRITE_POLICY |
770 MFI_INFO_LDOPS_READ_POLICY);
771 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
772 info.stripe_sz_ops.min = 3;
773 info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1;
774 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
775 info.properties.intr_throttle_cnt = cpu_to_le16(16);
776 info.properties.intr_throttle_timeout = cpu_to_le16(50);
777 info.properties.rebuild_rate = 30;
778 info.properties.patrol_read_rate = 30;
779 info.properties.bgi_rate = 30;
780 info.properties.cc_rate = 30;
781 info.properties.recon_rate = 30;
782 info.properties.cache_flush_interval = 4;
783 info.properties.spinup_drv_cnt = 2;
784 info.properties.spinup_delay = 6;
785 info.properties.ecc_bucket_size = 15;
786 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
787 info.properties.expose_encl_devices = 1;
788 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
789 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
790 MFI_INFO_PDOPS_FORCE_OFFLINE);
791 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
792 MFI_INFO_PDMIX_SATA |
793 MFI_INFO_PDMIX_LD);
794
795 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
796 return MFI_STAT_OK;
797}
798
799static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
800{
801 struct mfi_defaults info;
802 size_t dcmd_size = sizeof(struct mfi_defaults);
803
804 memset(&info, 0x0, dcmd_size);
805 if (cmd->iov_size < dcmd_size) {
806 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
807 dcmd_size);
808 return MFI_STAT_INVALID_PARAMETER;
809 }
810
76b523db 811 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 812 info.stripe_size = 3;
813 info.flush_time = 4;
814 info.background_rate = 30;
815 info.allow_mix_in_enclosure = 1;
816 info.allow_mix_in_ld = 1;
817 info.direct_pd_mapping = 1;
818 /* Enable for BIOS support */
819 info.bios_enumerate_lds = 1;
820 info.disable_ctrl_r = 1;
821 info.expose_enclosure_devices = 1;
822 info.disable_preboot_cli = 1;
823 info.cluster_disable = 1;
824
825 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
826 return MFI_STAT_OK;
827}
828
829static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
830{
831 struct mfi_bios_data info;
832 size_t dcmd_size = sizeof(info);
833
834 memset(&info, 0x0, dcmd_size);
835 if (cmd->iov_size < dcmd_size) {
836 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
837 dcmd_size);
838 return MFI_STAT_INVALID_PARAMETER;
839 }
840 info.continue_on_error = 1;
841 info.verbose = 1;
842 if (megasas_is_jbod(s)) {
843 info.expose_all_drives = 1;
844 }
845
846 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
847 return MFI_STAT_OK;
848}
849
850static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
851{
852 uint64_t fw_time;
853 size_t dcmd_size = sizeof(fw_time);
854
855 fw_time = cpu_to_le64(megasas_fw_time());
856
857 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
858 return MFI_STAT_OK;
859}
860
861static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
862{
863 uint64_t fw_time;
864
865 /* This is a dummy; setting of firmware time is not allowed */
866 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
867
868 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
869 fw_time = cpu_to_le64(megasas_fw_time());
870 return MFI_STAT_OK;
871}
872
873static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
874{
875 struct mfi_evt_log_state info;
876 size_t dcmd_size = sizeof(info);
877
878 memset(&info, 0, dcmd_size);
879
880 info.newest_seq_num = cpu_to_le32(s->event_count);
881 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
882 info.boot_seq_num = cpu_to_le32(s->boot_event);
883
884 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
885 return MFI_STAT_OK;
886}
887
888static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
889{
890 union mfi_evt event;
891
892 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
893 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
894 sizeof(struct mfi_evt_detail));
895 return MFI_STAT_INVALID_PARAMETER;
896 }
897 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
898 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
899 s->event_locale = event.members.locale;
900 s->event_class = event.members.class;
901 s->event_cmd = cmd;
902 /* Decrease busy count; event frame doesn't count here */
903 s->busy--;
904 cmd->iov_size = sizeof(struct mfi_evt_detail);
905 return MFI_STAT_INVALID_STATUS;
906}
907
908static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
909{
910 struct mfi_pd_list info;
911 size_t dcmd_size = sizeof(info);
912 BusChild *kid;
913 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
914 uint16_t sdev_id;
915
916 memset(&info, 0, dcmd_size);
917 offset = 8;
918 dcmd_limit = offset + sizeof(struct mfi_pd_address);
919 if (cmd->iov_size < dcmd_limit) {
920 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
921 dcmd_limit);
922 return MFI_STAT_INVALID_PARAMETER;
923 }
924
925 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
926 if (max_pd_disks > s->fw_luns) {
927 max_pd_disks = s->fw_luns;
928 }
929
930 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
931 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
932
933 sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
934 info.addr[num_pd_disks].device_id = cpu_to_le16(sdev_id);
935 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
936 info.addr[num_pd_disks].encl_index = 0;
937 info.addr[num_pd_disks].slot_number = (sdev->id & 0xFF);
938 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
939 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
940 info.addr[num_pd_disks].sas_addr[0] =
76b523db 941 cpu_to_le64(megasas_get_sata_addr(sdev_id));
e8f943c3
HR		 942 num_pd_disks++;
943 offset += sizeof(struct mfi_pd_address);
944 }
945 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
946 max_pd_disks, offset);
947
948 info.size = cpu_to_le32(offset);
949 info.count = cpu_to_le32(num_pd_disks);
950
951 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
952 return MFI_STAT_OK;
953}
954
955static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
956{
957 uint16_t flags;
958
959 /* mbox0 contains flags */
960 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
961 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
962 if (flags == MR_PD_QUERY_TYPE_ALL ||
963 megasas_is_jbod(s)) {
964 return megasas_dcmd_pd_get_list(s, cmd);
965 }
966
967 return MFI_STAT_OK;
968}
969
970static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
971 MegasasCmd *cmd)
972{
973 struct mfi_pd_info *info = cmd->iov_buf;
974 size_t dcmd_size = sizeof(struct mfi_pd_info);
975 BlockConf *conf = &sdev->conf;
976 uint64_t pd_size;
977 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF);
978 uint8_t cmdbuf[6];
979 SCSIRequest *req;
980 size_t len, resid;
981
982 if (!cmd->iov_buf) {
983 cmd->iov_buf = g_malloc(dcmd_size);
984 memset(cmd->iov_buf, 0, dcmd_size);
985 info = cmd->iov_buf;
986 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
987 info->vpd_page83[0] = 0x7f;
988 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
989 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
990 if (!req) {
991 trace_megasas_dcmd_req_alloc_failed(cmd->index,
992 "PD get info std inquiry");
993 g_free(cmd->iov_buf);
994 cmd->iov_buf = NULL;
995 return MFI_STAT_FLASH_ALLOC_FAIL;
996 }
997 trace_megasas_dcmd_internal_submit(cmd->index,
998 "PD get info std inquiry", lun);
999 len = scsi_req_enqueue(req);
1000 if (len > 0) {
1001 cmd->iov_size = len;
1002 scsi_req_continue(req);
1003 }
1004 return MFI_STAT_INVALID_STATUS;
1005 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1006 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1007 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1008 if (!req) {
1009 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1010 "PD get info vpd inquiry");
1011 return MFI_STAT_FLASH_ALLOC_FAIL;
1012 }
1013 trace_megasas_dcmd_internal_submit(cmd->index,
1014 "PD get info vpd inquiry", lun);
1015 len = scsi_req_enqueue(req);
1016 if (len > 0) {
1017 cmd->iov_size = len;
1018 scsi_req_continue(req);
1019 }
1020 return MFI_STAT_INVALID_STATUS;
1021 }
1022 /* Finished, set FW state */
1023 if ((info->inquiry_data[0] >> 5) == 0) {
1024 if (megasas_is_jbod(cmd->state)) {
1025 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1026 } else {
1027 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1028 }
1029 } else {
1030 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1031 }
1032
1033 info->ref.v.device_id = cpu_to_le16(sdev_id);
1034 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1035 MFI_PD_DDF_TYPE_INTF_SAS);
1036 bdrv_get_geometry(conf->bs, &pd_size);
1037 info->raw_size = cpu_to_le64(pd_size);
1038 info->non_coerced_size = cpu_to_le64(pd_size);
1039 info->coerced_size = cpu_to_le64(pd_size);
1040 info->encl_device_id = 0xFFFF;
1041 info->slot_number = (sdev->id & 0xFF);
1042 info->path_info.count = 1;
1043 info->path_info.sas_addr[0] =
76b523db 1044 cpu_to_le64(megasas_get_sata_addr(sdev_id));
e8f943c3
HR		 1045 info->connected_port_bitmap = 0x1;
1046 info->device_speed = 1;
1047 info->link_speed = 1;
1048 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1049 g_free(cmd->iov_buf);
1050 cmd->iov_size = dcmd_size - resid;
1051 cmd->iov_buf = NULL;
1052 return MFI_STAT_OK;
1053}
1054
1055static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1056{
1057 size_t dcmd_size = sizeof(struct mfi_pd_info);
1058 uint16_t pd_id;
1059 SCSIDevice *sdev = NULL;
1060 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1061
1062 if (cmd->iov_size < dcmd_size) {
1063 return MFI_STAT_INVALID_PARAMETER;
1064 }
1065
1066 /* mbox0 has the ID */
1067 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1068 sdev = scsi_device_find(&s->bus, 0, pd_id, 0);
1069 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1070
1071 if (sdev) {
1072 /* Submit inquiry */
1073 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1074 }
1075
1076 return retval;
1077}
1078
1079static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1080{
1081 struct mfi_ld_list info;
1082 size_t dcmd_size = sizeof(info), resid;
1083 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1084 uint64_t ld_size;
1085 BusChild *kid;
1086
1087 memset(&info, 0, dcmd_size);
1088 if (cmd->iov_size < dcmd_size) {
1089 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1090 dcmd_size);
1091 return MFI_STAT_INVALID_PARAMETER;
1092 }
1093
1094 if (megasas_is_jbod(s)) {
1095 max_ld_disks = 0;
1096 }
1097 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1098 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
1099 BlockConf *conf = &sdev->conf;
1100
1101 if (num_ld_disks >= max_ld_disks) {
1102 break;
1103 }
1104 /* Logical device size is in blocks */
1105 bdrv_get_geometry(conf->bs, &ld_size);
1106 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
4003e24f 1107 info.ld_list[num_ld_disks].ld.v.lun_id = sdev->lun;
e8f943c3
HR		 1108 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1109 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1110 num_ld_disks++;
1111 }
1112 info.ld_count = cpu_to_le32(num_ld_disks);
1113 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1114
1115 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1116 cmd->iov_size = dcmd_size - resid;
1117 return MFI_STAT_OK;
1118}
1119
34bb4d02
HR		 1120static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1121{
1122 uint16_t flags;
1123
1124 /* mbox0 contains flags */
1125 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1126 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1127 if (flags == MR_LD_QUERY_TYPE_ALL ||
1128 flags == MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1129 return megasas_dcmd_ld_get_list(s, cmd);
1130 }
1131
1132 return MFI_STAT_OK;
1133}
1134
e8f943c3
HR		 1135static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1136 MegasasCmd *cmd)
1137{
1138 struct mfi_ld_info *info = cmd->iov_buf;
1139 size_t dcmd_size = sizeof(struct mfi_ld_info);
1140 uint8_t cdb[6];
1141 SCSIRequest *req;
1142 ssize_t len, resid;
1143 BlockConf *conf = &sdev->conf;
1144 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (lun & 0xFF);
1145 uint64_t ld_size;
1146
1147 if (!cmd->iov_buf) {
1148 cmd->iov_buf = g_malloc(dcmd_size);
1149 memset(cmd->iov_buf, 0x0, dcmd_size);
1150 info = cmd->iov_buf;
1151 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1152 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1153 if (!req) {
1154 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1155 "LD get info vpd inquiry");
1156 g_free(cmd->iov_buf);
1157 cmd->iov_buf = NULL;
1158 return MFI_STAT_FLASH_ALLOC_FAIL;
1159 }
1160 trace_megasas_dcmd_internal_submit(cmd->index,
1161 "LD get info vpd inquiry", lun);
1162 len = scsi_req_enqueue(req);
1163 if (len > 0) {
1164 cmd->iov_size = len;
1165 scsi_req_continue(req);
1166 }
1167 return MFI_STAT_INVALID_STATUS;
1168 }
1169
1170 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1171 info->ld_config.properties.ld.v.target_id = lun;
1172 info->ld_config.params.stripe_size = 3;
1173 info->ld_config.params.num_drives = 1;
1174 info->ld_config.params.is_consistent = 1;
1175 /* Logical device size is in blocks */
1176 bdrv_get_geometry(conf->bs, &ld_size);
1177 info->size = cpu_to_le64(ld_size);
1178 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1179 info->ld_config.span[0].start_block = 0;
1180 info->ld_config.span[0].num_blocks = info->size;
1181 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1182
1183 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1184 g_free(cmd->iov_buf);
1185 cmd->iov_size = dcmd_size - resid;
1186 cmd->iov_buf = NULL;
1187 return MFI_STAT_OK;
1188}
1189
1190static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1191{
1192 struct mfi_ld_info info;
1193 size_t dcmd_size = sizeof(info);
1194 uint16_t ld_id;
1195 uint32_t max_ld_disks = s->fw_luns;
1196 SCSIDevice *sdev = NULL;
1197 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1198
1199 if (cmd->iov_size < dcmd_size) {
1200 return MFI_STAT_INVALID_PARAMETER;
1201 }
1202
1203 /* mbox0 has the ID */
1204 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1205 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1206
1207 if (megasas_is_jbod(s)) {
1208 return MFI_STAT_DEVICE_NOT_FOUND;
1209 }
1210
1211 if (ld_id < max_ld_disks) {
1212 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1213 }
1214
1215 if (sdev) {
1216 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1217 }
1218
1219 return retval;
1220}
1221
1222static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1223{
1224 uint8_t data[4096];
1225 struct mfi_config_data *info;
1226 int num_pd_disks = 0, array_offset, ld_offset;
1227 BusChild *kid;
1228
1229 if (cmd->iov_size > 4096) {
1230 return MFI_STAT_INVALID_PARAMETER;
1231 }
1232
1233 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1234 num_pd_disks++;
1235 }
1236 info = (struct mfi_config_data *)&data;
1237 /*
1238 * Array mapping:
1239 * - One array per SCSI device
1240 * - One logical drive per SCSI device
1241 * spanning the entire device
1242 */
1243 info->array_count = num_pd_disks;
1244 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1245 info->log_drv_count = num_pd_disks;
1246 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1247 info->spares_count = 0;
1248 info->spares_size = sizeof(struct mfi_spare);
1249 info->size = sizeof(struct mfi_config_data) + info->array_size +
1250 info->log_drv_size;
1251 if (info->size > 4096) {
1252 return MFI_STAT_INVALID_PARAMETER;
1253 }
1254
1255 array_offset = sizeof(struct mfi_config_data);
1256 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1257
1258 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1259 SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child);
1260 BlockConf *conf = &sdev->conf;
1261 uint16_t sdev_id = ((sdev->id & 0xFF) >> 8) | (sdev->lun & 0xFF);
1262 struct mfi_array *array;
1263 struct mfi_ld_config *ld;
1264 uint64_t pd_size;
1265 int i;
1266
1267 array = (struct mfi_array *)(data + array_offset);
1268 bdrv_get_geometry(conf->bs, &pd_size);
1269 array->size = cpu_to_le64(pd_size);
1270 array->num_drives = 1;
1271 array->array_ref = cpu_to_le16(sdev_id);
1272 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1273 array->pd[0].ref.v.seq_num = 0;
1274 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1275 array->pd[0].encl.pd = 0xFF;
1276 array->pd[0].encl.slot = (sdev->id & 0xFF);
1277 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1278 array->pd[i].ref.v.device_id = 0xFFFF;
1279 array->pd[i].ref.v.seq_num = 0;
1280 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1281 array->pd[i].encl.pd = 0xFF;
1282 array->pd[i].encl.slot = 0xFF;
1283 }
1284 array_offset += sizeof(struct mfi_array);
1285 ld = (struct mfi_ld_config *)(data + ld_offset);
1286 memset(ld, 0, sizeof(struct mfi_ld_config));
1287 ld->properties.ld.v.target_id = (sdev->id & 0xFF);
1288 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1289 MR_LD_CACHE_READ_ADAPTIVE;
1290 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1291 MR_LD_CACHE_READ_ADAPTIVE;
1292 ld->params.state = MFI_LD_STATE_OPTIMAL;
1293 ld->params.stripe_size = 3;
1294 ld->params.num_drives = 1;
1295 ld->params.span_depth = 1;
1296 ld->params.is_consistent = 1;
1297 ld->span[0].start_block = 0;
1298 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1299 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1300 ld_offset += sizeof(struct mfi_ld_config);
1301 }
1302
1303 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1304 return MFI_STAT_OK;
1305}
1306
1307static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1308{
1309 struct mfi_ctrl_props info;
1310 size_t dcmd_size = sizeof(info);
1311
1312 memset(&info, 0x0, dcmd_size);
1313 if (cmd->iov_size < dcmd_size) {
1314 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1315 dcmd_size);
1316 return MFI_STAT_INVALID_PARAMETER;
1317 }
1318 info.pred_fail_poll_interval = cpu_to_le16(300);
1319 info.intr_throttle_cnt = cpu_to_le16(16);
1320 info.intr_throttle_timeout = cpu_to_le16(50);
1321 info.rebuild_rate = 30;
1322 info.patrol_read_rate = 30;
1323 info.bgi_rate = 30;
1324 info.cc_rate = 30;
1325 info.recon_rate = 30;
1326 info.cache_flush_interval = 4;
1327 info.spinup_drv_cnt = 2;
1328 info.spinup_delay = 6;
1329 info.ecc_bucket_size = 15;
1330 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1331 info.expose_encl_devices = 1;
1332
1333 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1334 return MFI_STAT_OK;
1335}
1336
1337static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1338{
b618f4a1 1339 bdrv_drain_all();
e8f943c3
HR		 1340 return MFI_STAT_OK;
1341}
1342
1343static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1344{
1345 s->fw_state = MFI_FWSTATE_READY;
1346 return MFI_STAT_OK;
1347}
1348
1349static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1350{
1351 return MFI_STAT_INVALID_DCMD;
1352}
1353
1354static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1355{
10d6530c
HR		 1356 struct mfi_ctrl_props info;
1357 size_t dcmd_size = sizeof(info);
1358
1359 if (cmd->iov_size < dcmd_size) {
1360 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1361 dcmd_size);
1362 return MFI_STAT_INVALID_PARAMETER;
1363 }
1364 dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg);
1365 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1366 return MFI_STAT_OK;
1367}
1368
1369static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1370{
1371 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1372 return MFI_STAT_OK;
1373}
1374
1375static const struct dcmd_cmd_tbl_t {
1376 int opcode;
1377 const char *desc;
1378 int (*func)(MegasasState *s, MegasasCmd *cmd);
1379} dcmd_cmd_tbl[] = {
1380 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1381 megasas_dcmd_dummy },
1382 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1383 megasas_ctrl_get_info },
1384 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1385 megasas_dcmd_get_properties },
1386 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1387 megasas_dcmd_set_properties },
1388 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1389 megasas_dcmd_dummy },
1390 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1391 megasas_dcmd_dummy },
1392 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1393 megasas_dcmd_dummy },
1394 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1395 megasas_dcmd_dummy },
1396 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1397 megasas_dcmd_dummy },
1398 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1399 megasas_event_info },
1400 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1401 megasas_dcmd_dummy },
1402 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1403 megasas_event_wait },
1404 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1405 megasas_ctrl_shutdown },
1406 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1407 megasas_dcmd_dummy },
1408 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1409 megasas_dcmd_get_fw_time },
1410 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1411 megasas_dcmd_set_fw_time },
1412 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1413 megasas_dcmd_get_bios_info },
1414 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1415 megasas_dcmd_dummy },
1416 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1417 megasas_mfc_get_defaults },
1418 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1419 megasas_dcmd_dummy },
1420 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1421 megasas_cache_flush },
1422 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1423 megasas_dcmd_pd_get_list },
1424 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1425 megasas_dcmd_pd_list_query },
1426 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1427 megasas_dcmd_pd_get_info },
1428 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1429 megasas_dcmd_dummy },
1430 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1431 megasas_dcmd_dummy },
1432 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1433 megasas_dcmd_dummy },
1434 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1435 megasas_dcmd_dummy },
1436 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1437 megasas_dcmd_ld_get_list},
34bb4d02
HR		 1438 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1439 megasas_dcmd_ld_list_query },
e8f943c3
HR		 1440 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1441 megasas_dcmd_ld_get_info },
1442 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1443 megasas_dcmd_dummy },
1444 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1445 megasas_dcmd_dummy },
1446 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1447 megasas_dcmd_dummy },
1448 { MFI_DCMD_CFG_READ, "CFG_READ",
1449 megasas_dcmd_cfg_read },
1450 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1451 megasas_dcmd_dummy },
1452 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1453 megasas_dcmd_dummy },
1454 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1455 megasas_dcmd_dummy },
1456 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1457 megasas_dcmd_dummy },
1458 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1459 megasas_dcmd_dummy },
1460 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1461 megasas_dcmd_dummy },
1462 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1463 megasas_dcmd_dummy },
1464 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1465 megasas_dcmd_dummy },
1466 { MFI_DCMD_CLUSTER, "CLUSTER",
1467 megasas_dcmd_dummy },
1468 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1469 megasas_dcmd_dummy },
1470 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1471 megasas_cluster_reset_ld },
1472 { -1, NULL, NULL }
1473};
1474
1475static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1476{
1477 int opcode, len;
1478 int retval = 0;
1479 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1480
1481 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1482 trace_megasas_handle_dcmd(cmd->index, opcode);
1483 len = megasas_map_dcmd(s, cmd);
1484 if (len < 0) {
1485 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1486 }
1487 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1488 cmdptr++;
1489 }
1490 if (cmdptr->opcode == -1) {
1491 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1492 retval = megasas_dcmd_dummy(s, cmd);
1493 } else {
1494 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1495 retval = cmdptr->func(s, cmd);
1496 }
1497 if (retval != MFI_STAT_INVALID_STATUS) {
1498 megasas_finish_dcmd(cmd, len);
1499 }
1500 return retval;
1501}
1502
1503static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1504 SCSIRequest *req)
1505{
1506 int opcode;
1507 int retval = MFI_STAT_OK;
1508 int lun = req->lun;
1509
1510 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1511 scsi_req_unref(req);
1512 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1513 switch (opcode) {
1514 case MFI_DCMD_PD_GET_INFO:
1515 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1516 break;
1517 case MFI_DCMD_LD_GET_INFO:
1518 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1519 break;
1520 default:
1521 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1522 retval = MFI_STAT_INVALID_DCMD;
1523 break;
1524 }
1525 if (retval != MFI_STAT_INVALID_STATUS) {
1526 megasas_finish_dcmd(cmd, cmd->iov_size);
1527 }
1528 return retval;
1529}
1530
1531static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1532{
1533 int len;
1534
1535 len = scsi_req_enqueue(cmd->req);
1536 if (len < 0) {
1537 len = -len;
1538 }
1539 if (len > 0) {
1540 if (len > cmd->iov_size) {
1541 if (is_write) {
1542 trace_megasas_iov_write_overflow(cmd->index, len,
1543 cmd->iov_size);
1544 } else {
1545 trace_megasas_iov_read_overflow(cmd->index, len,
1546 cmd->iov_size);
1547 }
1548 }
1549 if (len < cmd->iov_size) {
1550 if (is_write) {
1551 trace_megasas_iov_write_underflow(cmd->index, len,
1552 cmd->iov_size);
1553 } else {
1554 trace_megasas_iov_read_underflow(cmd->index, len,
1555 cmd->iov_size);
1556 }
1557 cmd->iov_size = len;
1558 }
1559 scsi_req_continue(cmd->req);
1560 }
1561 return len;
1562}
1563
1564static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1565 bool is_logical)
1566{
1567 uint8_t *cdb;
1568 int len;
1569 bool is_write;
1570 struct SCSIDevice *sdev = NULL;
1571
1572 cdb = cmd->frame->pass.cdb;
1573
1574 if (cmd->frame->header.target_id < s->fw_luns) {
1575 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1576 cmd->frame->header.lun_id);
1577 }
1578 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1579 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1580 is_logical, cmd->frame->header.target_id,
1581 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1582
1583 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1584 trace_megasas_scsi_target_not_present(
1585 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1586 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1587 return MFI_STAT_DEVICE_NOT_FOUND;
1588 }
1589
1590 if (cmd->frame->header.cdb_len > 16) {
1591 trace_megasas_scsi_invalid_cdb_len(
1592 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1593 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1594 cmd->frame->header.cdb_len);
1595 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1596 cmd->frame->header.scsi_status = CHECK_CONDITION;
1597 s->event_count++;
1598 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1599 }
1600
1601 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1602 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1603 cmd->frame->header.scsi_status = CHECK_CONDITION;
1604 s->event_count++;
1605 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1606 }
1607
1608 cmd->req = scsi_req_new(sdev, cmd->index,
1609 cmd->frame->header.lun_id, cdb, cmd);
1610 if (!cmd->req) {
1611 trace_megasas_scsi_req_alloc_failed(
1612 mfi_frame_desc[cmd->frame->header.frame_cmd],
1613 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1614 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1615 cmd->frame->header.scsi_status = BUSY;
1616 s->event_count++;
1617 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1618 }
1619
1620 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1621 len = megasas_enqueue_req(cmd, is_write);
1622 if (len > 0) {
1623 if (is_write) {
1624 trace_megasas_scsi_write_start(cmd->index, len);
1625 } else {
1626 trace_megasas_scsi_read_start(cmd->index, len);
1627 }
1628 } else {
1629 trace_megasas_scsi_nodata(cmd->index);
1630 }
1631 return MFI_STAT_INVALID_STATUS;
1632}
1633
1634static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1635{
1636 uint32_t lba_count, lba_start_hi, lba_start_lo;
1637 uint64_t lba_start;
1638 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1639 uint8_t cdb[16];
1640 int len;
1641 struct SCSIDevice *sdev = NULL;
1642
1643 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1644 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1645 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1646 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1647
1648 if (cmd->frame->header.target_id < s->fw_luns) {
1649 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1650 cmd->frame->header.lun_id);
1651 }
1652
1653 trace_megasas_handle_io(cmd->index,
1654 mfi_frame_desc[cmd->frame->header.frame_cmd],
1655 cmd->frame->header.target_id,
1656 cmd->frame->header.lun_id,
1657 (unsigned long)lba_start, (unsigned long)lba_count);
1658 if (!sdev) {
1659 trace_megasas_io_target_not_present(cmd->index,
1660 mfi_frame_desc[cmd->frame->header.frame_cmd],
1661 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1662 return MFI_STAT_DEVICE_NOT_FOUND;
1663 }
1664
1665 if (cmd->frame->header.cdb_len > 16) {
1666 trace_megasas_scsi_invalid_cdb_len(
1667 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1668 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1669 cmd->frame->header.cdb_len);
1670 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1671 cmd->frame->header.scsi_status = CHECK_CONDITION;
1672 s->event_count++;
1673 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1674 }
1675
1676 cmd->iov_size = lba_count * sdev->blocksize;
1677 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1678 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1679 cmd->frame->header.scsi_status = CHECK_CONDITION;
1680 s->event_count++;
1681 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1682 }
1683
1684 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1685 cmd->req = scsi_req_new(sdev, cmd->index,
1686 cmd->frame->header.lun_id, cdb, cmd);
1687 if (!cmd->req) {
1688 trace_megasas_scsi_req_alloc_failed(
1689 mfi_frame_desc[cmd->frame->header.frame_cmd],
1690 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1691 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1692 cmd->frame->header.scsi_status = BUSY;
1693 s->event_count++;
1694 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1695 }
1696 len = megasas_enqueue_req(cmd, is_write);
1697 if (len > 0) {
1698 if (is_write) {
1699 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1700 } else {
1701 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1702 }
1703 }
1704 return MFI_STAT_INVALID_STATUS;
1705}
1706
1707static int megasas_finish_internal_command(MegasasCmd *cmd,
1708 SCSIRequest *req, size_t resid)
1709{
1710 int retval = MFI_STAT_INVALID_CMD;
1711
1712 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1713 cmd->iov_size -= resid;
1714 retval = megasas_finish_internal_dcmd(cmd, req);
1715 }
1716 return retval;
1717}
1718
1719static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1720{
1721 MegasasCmd *cmd = req->hba_private;
1722
1723 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1724 return NULL;
1725 } else {
1726 return &cmd->qsg;
1727 }
1728}
1729
1730static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1731{
1732 MegasasCmd *cmd = req->hba_private;
1733 uint8_t *buf;
1734 uint32_t opcode;
1735
1736 trace_megasas_io_complete(cmd->index, len);
1737
1738 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1739 scsi_req_continue(req);
1740 return;
1741 }
1742
1743 buf = scsi_req_get_buf(req);
1744 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1745 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1746 struct mfi_pd_info *info = cmd->iov_buf;
1747
1748 if (info->inquiry_data[0] == 0x7f) {
1749 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1750 memcpy(info->inquiry_data, buf, len);
1751 } else if (info->vpd_page83[0] == 0x7f) {
1752 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1753 memcpy(info->vpd_page83, buf, len);
1754 }
1755 scsi_req_continue(req);
1756 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1757 struct mfi_ld_info *info = cmd->iov_buf;
1758
1759 if (cmd->iov_buf) {
1760 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1761 scsi_req_continue(req);
1762 }
1763 }
1764}
1765
1766static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1767 size_t resid)
1768{
1769 MegasasCmd *cmd = req->hba_private;
1770 uint8_t cmd_status = MFI_STAT_OK;
1771
1772 trace_megasas_command_complete(cmd->index, status, resid);
1773
1774 if (cmd->req != req) {
1775 /*
1776 * Internal command complete
1777 */
1778 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1779 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1780 return;
1781 }
1782 } else {
1783 req->status = status;
1784 trace_megasas_scsi_complete(cmd->index, req->status,
1785 cmd->iov_size, req->cmd.xfer);
1786 if (req->status != GOOD) {
1787 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1788 }
1789 if (req->status == CHECK_CONDITION) {
1790 megasas_copy_sense(cmd);
1791 }
1792
1793 megasas_unmap_sgl(cmd);
1794 cmd->frame->header.scsi_status = req->status;
1795 scsi_req_unref(cmd->req);
1796 cmd->req = NULL;
1797 }
1798 cmd->frame->header.cmd_status = cmd_status;
1799 megasas_complete_frame(cmd->state, cmd->context);
1800}
1801
1802static void megasas_command_cancel(SCSIRequest *req)
1803{
1804 MegasasCmd *cmd = req->hba_private;
1805
1806 if (cmd) {
1807 megasas_abort_command(cmd);
1808 } else {
1809 scsi_req_unref(req);
1810 }
1811}
1812
1813static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1814{
1815 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1816 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1817 MegasasCmd *abort_cmd;
1818
1819 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1820 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1821 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1822
1823 abort_cmd = megasas_lookup_frame(s, abort_addr);
1824 if (!abort_cmd) {
1825 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1826 s->event_count++;
1827 return MFI_STAT_OK;
1828 }
1829 if (!megasas_use_queue64(s)) {
1830 abort_ctx &= (uint64_t)0xFFFFFFFF;
1831 }
1832 if (abort_cmd->context != abort_ctx) {
1833 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1834 abort_cmd->context);
1835 s->event_count++;
1836 return MFI_STAT_ABORT_NOT_POSSIBLE;
1837 }
1838 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1839 megasas_abort_command(abort_cmd);
1840 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1841 s->event_cmd = NULL;
1842 }
1843 s->event_count++;
1844 return MFI_STAT_OK;
1845}
1846
1847static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1848 uint32_t frame_count)
1849{
1850 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1851 uint64_t frame_context;
1852 MegasasCmd *cmd;
1853
1854 /*
1855 * Always read 64bit context, top bits will be
1856 * masked out if required in megasas_enqueue_frame()
1857 */
1858 frame_context = megasas_frame_get_context(frame_addr);
1859
1860 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1861 if (!cmd) {
1862 /* reply queue full */
1863 trace_megasas_frame_busy(frame_addr);
1864 megasas_frame_set_scsi_status(frame_addr, BUSY);
1865 megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1866 megasas_complete_frame(s, frame_context);
1867 s->event_count++;
1868 return;
1869 }
1870 switch (cmd->frame->header.frame_cmd) {
1871 case MFI_CMD_INIT:
1872 frame_status = megasas_init_firmware(s, cmd);
1873 break;
1874 case MFI_CMD_DCMD:
1875 frame_status = megasas_handle_dcmd(s, cmd);
1876 break;
1877 case MFI_CMD_ABORT:
1878 frame_status = megasas_handle_abort(s, cmd);
1879 break;
1880 case MFI_CMD_PD_SCSI_IO:
1881 frame_status = megasas_handle_scsi(s, cmd, 0);
1882 break;
1883 case MFI_CMD_LD_SCSI_IO:
1884 frame_status = megasas_handle_scsi(s, cmd, 1);
1885 break;
1886 case MFI_CMD_LD_READ:
1887 case MFI_CMD_LD_WRITE:
1888 frame_status = megasas_handle_io(s, cmd);
1889 break;
1890 default:
1891 trace_megasas_unhandled_frame_cmd(cmd->index,
1892 cmd->frame->header.frame_cmd);
1893 s->event_count++;
1894 break;
1895 }
1896 if (frame_status != MFI_STAT_INVALID_STATUS) {
1897 if (cmd->frame) {
1898 cmd->frame->header.cmd_status = frame_status;
1899 } else {
1900 megasas_frame_set_cmd_status(frame_addr, frame_status);
1901 }
1902 megasas_complete_frame(s, cmd->context);
1903 }
1904}
1905
a8170e5e 1906static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 1907 unsigned size)
1908{
1909 MegasasState *s = opaque;
1910 uint32_t retval = 0;
1911
1912 switch (addr) {
1913 case MFI_IDB:
1914 retval = 0;
1915 break;
1916 case MFI_OMSG0:
1917 case MFI_OSP0:
1918 retval = (megasas_use_msix(s) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
1919 (s->fw_state & MFI_FWSTATE_MASK) |
1920 ((s->fw_sge & 0xff) << 16) |
1921 (s->fw_cmds & 0xFFFF);
1922 break;
1923 case MFI_OSTS:
1924 if (megasas_intr_enabled(s) && s->doorbell) {
1925 retval = MFI_1078_RM | 1;
1926 }
1927 break;
1928 case MFI_OMSK:
1929 retval = s->intr_mask;
1930 break;
1931 case MFI_ODCR0:
1932 retval = s->doorbell;
1933 break;
1934 default:
1935 trace_megasas_mmio_invalid_readl(addr);
1936 break;
1937 }
1938 trace_megasas_mmio_readl(addr, retval);
1939 return retval;
1940}
1941
a8170e5e 1942static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 1943 uint64_t val, unsigned size)
1944{
1945 MegasasState *s = opaque;
52190c1e 1946 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 1947 uint64_t frame_addr;
1948 uint32_t frame_count;
1949 int i;
1950
1951 trace_megasas_mmio_writel(addr, val);
1952 switch (addr) {
1953 case MFI_IDB:
1954 if (val & MFI_FWINIT_ABORT) {
1955 /* Abort all pending cmds */
1956 for (i = 0; i < s->fw_cmds; i++) {
1957 megasas_abort_command(&s->frames[i]);
1958 }
1959 }
1960 if (val & MFI_FWINIT_READY) {
1961 /* move to FW READY */
1962 megasas_soft_reset(s);
1963 }
1964 if (val & MFI_FWINIT_MFIMODE) {
1965 /* discard MFIs */
1966 }
1967 break;
1968 case MFI_OMSK:
1969 s->intr_mask = val;
4522b69c
HR		 1970 if (!megasas_intr_enabled(s) &&
1971 !msi_enabled(pci_dev) &&
1972 !msix_enabled(pci_dev)) {
e8f943c3 1973 trace_megasas_irq_lower();
9e64f8a3 1974 pci_irq_deassert(pci_dev);
e8f943c3
HR		 1975 }
1976 if (megasas_intr_enabled(s)) {
4522b69c
HR		 1977 if (msix_enabled(pci_dev)) {
1978 trace_megasas_msix_enabled(0);
1979 } else if (msi_enabled(pci_dev)) {
1980 trace_megasas_msi_enabled(0);
1981 } else {
1982 trace_megasas_intr_enabled();
1983 }
e8f943c3
HR		 1984 } else {
1985 trace_megasas_intr_disabled();
1986 }
1987 break;
1988 case MFI_ODCR0:
1989 s->doorbell = 0;
1990 if (s->producer_pa && megasas_intr_enabled(s)) {
1991 /* Update reply queue pointer */
1992 trace_megasas_qf_update(s->reply_queue_head, s->busy);
ab1da857
EI		 1993 stl_le_phys(&address_space_memory,
1994 s->producer_pa, s->reply_queue_head);
52190c1e 1995 if (!msix_enabled(pci_dev)) {
e8f943c3 1996 trace_megasas_irq_lower();
9e64f8a3 1997 pci_irq_deassert(pci_dev);
e8f943c3
HR		 1998 }
1999 }
2000 break;
2001 case MFI_IQPH:
2002 /* Received high 32 bits of a 64 bit MFI frame address */
2003 s->frame_hi = val;
2004 break;
2005 case MFI_IQPL:
2006 /* Received low 32 bits of a 64 bit MFI frame address */
2007 case MFI_IQP:
2008 /* Received 32 bit MFI frame address */
2009 frame_addr = (val & ~0x1F);
2010 /* Add possible 64 bit offset */
2011 frame_addr |= ((uint64_t)s->frame_hi << 32);
2012 s->frame_hi = 0;
2013 frame_count = (val >> 1) & 0xF;
2014 megasas_handle_frame(s, frame_addr, frame_count);
2015 break;
2016 default:
2017 trace_megasas_mmio_invalid_writel(addr, val);
2018 break;
2019 }
2020}
2021
2022static const MemoryRegionOps megasas_mmio_ops = {
2023 .read = megasas_mmio_read,
2024 .write = megasas_mmio_write,
2025 .endianness = DEVICE_LITTLE_ENDIAN,
2026 .impl = {
2027 .min_access_size = 8,
2028 .max_access_size = 8,
2029 }
2030};
2031
a8170e5e 2032static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2033 unsigned size)
2034{
2035 return megasas_mmio_read(opaque, addr & 0xff, size);
2036}
2037
a8170e5e 2038static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2039 uint64_t val, unsigned size)
2040{
2041 megasas_mmio_write(opaque, addr & 0xff, val, size);
2042}
2043
2044static const MemoryRegionOps megasas_port_ops = {
2045 .read = megasas_port_read,
2046 .write = megasas_port_write,
2047 .endianness = DEVICE_LITTLE_ENDIAN,
2048 .impl = {
2049 .min_access_size = 4,
2050 .max_access_size = 4,
2051 }
2052};
2053
a8170e5e 2054static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2055 unsigned size)
2056{
2057 return 0;
2058}
2059
2060static const MemoryRegionOps megasas_queue_ops = {
2061 .read = megasas_queue_read,
2062 .endianness = DEVICE_LITTLE_ENDIAN,
2063 .impl = {
2064 .min_access_size = 8,
2065 .max_access_size = 8,
2066 }
2067};
2068
2069static void megasas_soft_reset(MegasasState *s)
2070{
2071 int i;
2072 MegasasCmd *cmd;
2073
2074 trace_megasas_reset();
2075 for (i = 0; i < s->fw_cmds; i++) {
2076 cmd = &s->frames[i];
2077 megasas_abort_command(cmd);
2078 }
2079 megasas_reset_frames(s);
2080 s->reply_queue_len = s->fw_cmds;
2081 s->reply_queue_pa = 0;
2082 s->consumer_pa = 0;
2083 s->producer_pa = 0;
2084 s->fw_state = MFI_FWSTATE_READY;
2085 s->doorbell = 0;
2086 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2087 s->frame_hi = 0;
2088 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2089 s->event_count++;
2090 s->boot_event = s->event_count;
2091}
2092
2093static void megasas_scsi_reset(DeviceState *dev)
2094{
c79e16ae 2095 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2096
2097 megasas_soft_reset(s);
2098}
2099
2100static const VMStateDescription vmstate_megasas = {
2101 .name = "megasas",
2102 .version_id = 0,
2103 .minimum_version_id = 0,
2104 .minimum_version_id_old = 0,
2105 .fields = (VMStateField[]) {
52190c1e 2106 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
23335f62 2107 VMSTATE_MSIX(parent_obj, MegasasState),
e8f943c3
HR		 2108
2109 VMSTATE_INT32(fw_state, MegasasState),
2110 VMSTATE_INT32(intr_mask, MegasasState),
2111 VMSTATE_INT32(doorbell, MegasasState),
2112 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2113 VMSTATE_UINT64(consumer_pa, MegasasState),
2114 VMSTATE_UINT64(producer_pa, MegasasState),
2115 VMSTATE_END_OF_LIST()
2116 }
2117};
2118
18fc611b 2119static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2120{
c79e16ae 2121 MegasasState *s = MEGASAS(d);
e8f943c3 2122
4522b69c
HR		 2123 if (megasas_use_msix(s)) {
2124 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2125 }
2126 if (megasas_use_msi(s)) {
2127 msi_uninit(d);
2128 }
e8f943c3
HR		 2129 memory_region_destroy(&s->mmio_io);
2130 memory_region_destroy(&s->port_io);
2131 memory_region_destroy(&s->queue_io);
e8f943c3
HR		 2132}
2133
2134static const struct SCSIBusInfo megasas_scsi_info = {
2135 .tcq = true,
2136 .max_target = MFI_MAX_LD,
2137 .max_lun = 255,
2138
2139 .transfer_data = megasas_xfer_complete,
2140 .get_sg_list = megasas_get_sg_list,
2141 .complete = megasas_command_complete,
2142 .cancel = megasas_command_cancel,
2143};
2144
2145static int megasas_scsi_init(PCIDevice *dev)
2146{
22d6aa03 2147 DeviceState *d = DEVICE(dev);
c79e16ae 2148 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2149 uint8_t *pci_conf;
2150 int i, bar_type;
caad4eb3 2151 Error *err = NULL;
e8f943c3 2152
52190c1e 2153 pci_conf = dev->config;
e8f943c3
HR		 2154
2155 /* PCI latency timer = 0 */
2156 pci_conf[PCI_LATENCY_TIMER] = 0;
2157 /* Interrupt pin 1 */
2158 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2159
29776739 2160 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2161 "megasas-mmio", 0x4000);
29776739 2162 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2163 "megasas-io", 256);
29776739 2164 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2165 "megasas-queue", 0x40000);
2166
4522b69c
HR		 2167 if (megasas_use_msi(s) &&
2168 msi_init(dev, 0x50, 1, true, false)) {
2169 s->flags &= ~MEGASAS_MASK_USE_MSI;
2170 }
e8f943c3 2171 if (megasas_use_msix(s) &&
23335f62
HR		 2172 msix_init(dev, 15, &s->mmio_io, 0, 0x2000,
2173 &s->mmio_io, 0, 0x3800, 0x68)) {
e8f943c3
HR		 2174 s->flags &= ~MEGASAS_MASK_USE_MSIX;
2175 }
e8f943c3
HR		 2176
2177 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
52190c1e
AF		 2178 pci_register_bar(dev, 0, bar_type, &s->mmio_io);
2179 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2180 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2181
2182 if (megasas_use_msix(s)) {
52190c1e 2183 msix_vector_use(dev, 0);
e8f943c3
HR		 2184 }
2185
76b523db
HR		 2186 if (!s->sas_addr) {
2187 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2188 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2189 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2190 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2191 s->sas_addr |= PCI_FUNC(dev->devfn);
2192 }
fb654157 2193 if (!s->hba_serial) {
23335f62 2194 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
fb654157 2195 }
e8f943c3
HR		 2196 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2197 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2198 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2199 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2200 } else {
2201 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2202 }
2203 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2204 s->fw_cmds = MEGASAS_MAX_FRAMES;
2205 }
2206 trace_megasas_init(s->fw_sge, s->fw_cmds,
e8f943c3
HR		 2207 megasas_is_jbod(s) ? "jbod" : "raid");
2208 s->fw_luns = (MFI_MAX_LD > MAX_SCSI_DEVS) ?
2209 MAX_SCSI_DEVS : MFI_MAX_LD;
2210 s->producer_pa = 0;
2211 s->consumer_pa = 0;
2212 for (i = 0; i < s->fw_cmds; i++) {
2213 s->frames[i].index = i;
2214 s->frames[i].context = -1;
2215 s->frames[i].pa = 0;
2216 s->frames[i].state = s;
2217 }
2218
b1187b51
AF		 2219 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2220 &megasas_scsi_info, NULL);
22d6aa03 2221 if (!d->hotplugged) {
caad4eb3
AF		 2222 scsi_bus_legacy_handle_cmdline(&s->bus, &err);
2223 if (err != NULL) {
2224 error_free(err);
2225 return -1;
2226 }
22d6aa03 2227 }
e8f943c3
HR		 2228 return 0;
2229}
2230
4522b69c
HR		 2231static void
2232megasas_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len)
2233{
2234 pci_default_write_config(pci, addr, val, len);
2235 msi_write_config(pci, addr, val, len);
2236}
2237
e8f943c3
HR		 2238static Property megasas_properties[] = {
2239 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2240 MEGASAS_DEFAULT_SGE),
2241 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2242 MEGASAS_DEFAULT_FRAMES),
fb654157 2243 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
c7bcc85d 2244 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
4522b69c
HR		 2245 DEFINE_PROP_BIT("use_msi", MegasasState, flags,
2246 MEGASAS_FLAG_USE_MSI, false),
e8f943c3
HR		 2247 DEFINE_PROP_BIT("use_msix", MegasasState, flags,
2248 MEGASAS_FLAG_USE_MSIX, false),
e8f943c3
HR		 2249 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2250 MEGASAS_FLAG_USE_JBOD, false),
2251 DEFINE_PROP_END_OF_LIST(),
2252};
2253
2254static void megasas_class_init(ObjectClass *oc, void *data)
2255{
2256 DeviceClass *dc = DEVICE_CLASS(oc);
2257 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2258
2259 pc->init = megasas_scsi_init;
2260 pc->exit = megasas_scsi_uninit;
2261 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2262 pc->device_id = PCI_DEVICE_ID_LSI_SAS1078;
2263 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2264 pc->subsystem_id = 0x1013;
2265 pc->class_id = PCI_CLASS_STORAGE_RAID;
2266 dc->props = megasas_properties;
2267 dc->reset = megasas_scsi_reset;
2268 dc->vmsd = &vmstate_megasas;
125ee0ed 2269 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e8f943c3 2270 dc->desc = "LSI MegaRAID SAS 1078";
4522b69c 2271 pc->config_write = megasas_write_config;
e8f943c3
HR		 2272}
2273
2274static const TypeInfo megasas_info = {
c79e16ae 2275 .name = TYPE_MEGASAS,
e8f943c3
HR		 2276 .parent = TYPE_PCI_DEVICE,
2277 .instance_size = sizeof(MegasasState),
2278 .class_init = megasas_class_init,
2279};
2280
2281static void megasas_register_types(void)
2282{
2283 type_register_static(&megasas_info);
2284}
2285
2286type_init(megasas_register_types)
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