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megasas: do not call pci_dma_unmap after having freed the frame once
[mirror_qemu.git] / hw / scsi / megasas.c
CommitLineData
e8f943c3
HR		 1/*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
a4ab4792 21#include "qemu/osdep.h"
83c9f4ca
PB		 22#include "hw/hw.h"
23#include "hw/pci/pci.h"
9c17d615 24#include "sysemu/dma.h"
4be74634 25#include "sysemu/block-backend.h"
4522b69c 26#include "hw/pci/msi.h"
83c9f4ca 27#include "hw/pci/msix.h"
1de7afc9 28#include "qemu/iov.h"
0d09e41a
PB		 29#include "hw/scsi/scsi.h"
30#include "block/scsi.h"
e8f943c3 31#include "trace.h"
1108b2f8 32#include "qapi/error.h"
47b43a1f 33#include "mfi.h"
e8f943c3 34
e23d0498
HR		 35#define MEGASAS_VERSION_GEN1 "1.70"
36#define MEGASAS_VERSION_GEN2 "1.80"
e8f943c3
HR		 37#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
38#define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
e23d0498 39#define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
e8f943c3
HR		 40#define MEGASAS_MAX_SGE 128 /* Firmware limit */
41#define MEGASAS_DEFAULT_SGE 80
42#define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
43#define MEGASAS_MAX_ARRAYS 128
44
fb654157 45#define MEGASAS_HBA_SERIAL "QEMU123456"
76b523db
HR		 46#define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
47#define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
48
e8f943c3
HR		 49#define MEGASAS_FLAG_USE_JBOD 0
50#define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
b4b4a57f 51#define MEGASAS_FLAG_USE_QUEUE64 1
e8f943c3
HR		 52#define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
53
a97ad268 54static const char *mfi_frame_desc[] = {
e8f943c3
HR		 55 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
56 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
57
58typedef struct MegasasCmd {
59 uint32_t index;
60 uint16_t flags;
61 uint16_t count;
62 uint64_t context;
63
a8170e5e
AK		 64 hwaddr pa;
65 hwaddr pa_size;
e8f943c3
HR		 66 union mfi_frame *frame;
67 SCSIRequest *req;
68 QEMUSGList qsg;
69 void *iov_buf;
70 size_t iov_size;
71 size_t iov_offset;
72 struct MegasasState *state;
73} MegasasCmd;
74
75typedef struct MegasasState {
52190c1e
AF		 76 /*< private >*/
77 PCIDevice parent_obj;
78 /*< public >*/
79
e8f943c3
HR		 80 MemoryRegion mmio_io;
81 MemoryRegion port_io;
82 MemoryRegion queue_io;
83 uint32_t frame_hi;
84
85 int fw_state;
86 uint32_t fw_sge;
87 uint32_t fw_cmds;
88 uint32_t flags;
89 int fw_luns;
90 int intr_mask;
91 int doorbell;
92 int busy;
e23d0498
HR		 93 int diag;
94 int adp_reset;
b4b4a57f
C		 95 OnOffAuto msi;
96 OnOffAuto msix;
e8f943c3
HR		 97
98 MegasasCmd *event_cmd;
99 int event_locale;
100 int event_class;
101 int event_count;
102 int shutdown_event;
103 int boot_event;
104
76b523db 105 uint64_t sas_addr;
fb654157 106 char *hba_serial;
76b523db 107
e8f943c3
HR		 108 uint64_t reply_queue_pa;
109 void *reply_queue;
110 int reply_queue_len;
111 int reply_queue_head;
112 int reply_queue_tail;
113 uint64_t consumer_pa;
114 uint64_t producer_pa;
115
116 MegasasCmd frames[MEGASAS_MAX_FRAMES];
6df5718b 117 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 118 SCSIBus bus;
119} MegasasState;
120
e23d0498
HR		 121typedef struct MegasasBaseClass {
122 PCIDeviceClass parent_class;
123 const char *product_name;
124 const char *product_version;
125 int mmio_bar;
126 int ioport_bar;
127 int osts;
128} MegasasBaseClass;
129
130#define TYPE_MEGASAS_BASE "megasas-base"
131#define TYPE_MEGASAS_GEN1 "megasas"
132#define TYPE_MEGASAS_GEN2 "megasas-gen2"
c79e16ae
PC		 133
134#define MEGASAS(obj) \
e23d0498
HR		 135 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
136
137#define MEGASAS_DEVICE_CLASS(oc) \
138 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
139#define MEGASAS_DEVICE_GET_CLASS(oc) \
140 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
c79e16ae 141
e8f943c3
HR		 142#define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
143
144static bool megasas_intr_enabled(MegasasState *s)
145{
146 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
147 MEGASAS_INTR_DISABLED_MASK) {
148 return true;
149 }
150 return false;
151}
152
153static bool megasas_use_queue64(MegasasState *s)
154{
155 return s->flags & MEGASAS_MASK_USE_QUEUE64;
156}
157
158static bool megasas_use_msix(MegasasState *s)
159{
b4b4a57f 160 return s->msix != ON_OFF_AUTO_OFF;
e8f943c3
HR		 161}
162
163static bool megasas_is_jbod(MegasasState *s)
164{
165 return s->flags & MEGASAS_MASK_USE_JBOD;
166}
167
16578c6f
PB		 168static void megasas_frame_set_cmd_status(MegasasState *s,
169 unsigned long frame, uint8_t v)
e8f943c3 170{
16578c6f
PB		 171 PCIDevice *pci = &s->parent_obj;
172 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
e8f943c3
HR		 173}
174
16578c6f
PB		 175static void megasas_frame_set_scsi_status(MegasasState *s,
176 unsigned long frame, uint8_t v)
e8f943c3 177{
16578c6f
PB		 178 PCIDevice *pci = &s->parent_obj;
179 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
e8f943c3
HR		 180}
181
182/*
183 * Context is considered opaque, but the HBA firmware is running
184 * in little endian mode. So convert it to little endian, too.
185 */
16578c6f
PB		 186static uint64_t megasas_frame_get_context(MegasasState *s,
187 unsigned long frame)
e8f943c3 188{
16578c6f
PB		 189 PCIDevice *pci = &s->parent_obj;
190 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
e8f943c3
HR		 191}
192
193static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
194{
195 return cmd->flags & MFI_FRAME_IEEE_SGL;
196}
197
198static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
199{
200 return cmd->flags & MFI_FRAME_SGL64;
201}
202
203static bool megasas_frame_is_sense64(MegasasCmd *cmd)
204{
205 return cmd->flags & MFI_FRAME_SENSE64;
206}
207
208static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
209 union mfi_sgl *sgl)
210{
211 uint64_t addr;
212
213 if (megasas_frame_is_ieee_sgl(cmd)) {
214 addr = le64_to_cpu(sgl->sg_skinny->addr);
215 } else if (megasas_frame_is_sgl64(cmd)) {
216 addr = le64_to_cpu(sgl->sg64->addr);
217 } else {
218 addr = le32_to_cpu(sgl->sg32->addr);
219 }
220 return addr;
221}
222
223static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
224 union mfi_sgl *sgl)
225{
226 uint32_t len;
227
228 if (megasas_frame_is_ieee_sgl(cmd)) {
229 len = le32_to_cpu(sgl->sg_skinny->len);
230 } else if (megasas_frame_is_sgl64(cmd)) {
231 len = le32_to_cpu(sgl->sg64->len);
232 } else {
233 len = le32_to_cpu(sgl->sg32->len);
234 }
235 return len;
236}
237
238static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
239 union mfi_sgl *sgl)
240{
241 uint8_t *next = (uint8_t *)sgl;
242
243 if (megasas_frame_is_ieee_sgl(cmd)) {
244 next += sizeof(struct mfi_sg_skinny);
245 } else if (megasas_frame_is_sgl64(cmd)) {
246 next += sizeof(struct mfi_sg64);
247 } else {
248 next += sizeof(struct mfi_sg32);
249 }
250
251 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
252 return NULL;
253 }
254 return (union mfi_sgl *)next;
255}
256
257static void megasas_soft_reset(MegasasState *s);
258
259static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
260{
261 int i;
262 int iov_count = 0;
263 size_t iov_size = 0;
264
265 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
266 iov_count = cmd->frame->header.sge_count;
267 if (iov_count > MEGASAS_MAX_SGE) {
268 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
269 MEGASAS_MAX_SGE);
270 return iov_count;
271 }
52190c1e 272 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
e8f943c3
HR		 273 for (i = 0; i < iov_count; i++) {
274 dma_addr_t iov_pa, iov_size_p;
275
276 if (!sgl) {
277 trace_megasas_iovec_sgl_underflow(cmd->index, i);
278 goto unmap;
279 }
280 iov_pa = megasas_sgl_get_addr(cmd, sgl);
281 iov_size_p = megasas_sgl_get_len(cmd, sgl);
282 if (!iov_pa || !iov_size_p) {
283 trace_megasas_iovec_sgl_invalid(cmd->index, i,
284 iov_pa, iov_size_p);
285 goto unmap;
286 }
287 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
288 sgl = megasas_sgl_next(cmd, sgl);
289 iov_size += (size_t)iov_size_p;
290 }
291 if (cmd->iov_size > iov_size) {
292 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
293 } else if (cmd->iov_size < iov_size) {
294 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
295 }
296 cmd->iov_offset = 0;
297 return 0;
298unmap:
299 qemu_sglist_destroy(&cmd->qsg);
300 return iov_count - i;
301}
302
303static void megasas_unmap_sgl(MegasasCmd *cmd)
304{
305 qemu_sglist_destroy(&cmd->qsg);
306 cmd->iov_offset = 0;
307}
308
309/*
310 * passthrough sense and io sense are at the same offset
311 */
312static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
313 uint8_t sense_len)
314{
1016b239 315 PCIDevice *pcid = PCI_DEVICE(cmd->state);
e8f943c3 316 uint32_t pa_hi = 0, pa_lo;
a8170e5e 317 hwaddr pa;
e8f943c3
HR		 318
319 if (sense_len > cmd->frame->header.sense_len) {
320 sense_len = cmd->frame->header.sense_len;
321 }
322 if (sense_len) {
323 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
324 if (megasas_frame_is_sense64(cmd)) {
325 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
326 }
327 pa = ((uint64_t) pa_hi << 32) | pa_lo;
1016b239 328 pci_dma_write(pcid, pa, sense_ptr, sense_len);
e8f943c3
HR		 329 cmd->frame->header.sense_len = sense_len;
330 }
331 return sense_len;
332}
333
334static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
335{
336 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
337 uint8_t sense_len = 18;
338
339 memset(sense_buf, 0, sense_len);
340 sense_buf[0] = 0xf0;
341 sense_buf[2] = sense.key;
342 sense_buf[7] = 10;
343 sense_buf[12] = sense.asc;
344 sense_buf[13] = sense.ascq;
345 megasas_build_sense(cmd, sense_buf, sense_len);
346}
347
348static void megasas_copy_sense(MegasasCmd *cmd)
349{
350 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
351 uint8_t sense_len;
352
353 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
354 SCSI_SENSE_BUF_SIZE);
355 megasas_build_sense(cmd, sense_buf, sense_len);
356}
357
358/*
359 * Format an INQUIRY CDB
360 */
361static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
362{
363 memset(cdb, 0, 6);
364 cdb[0] = INQUIRY;
365 if (pg > 0) {
366 cdb[1] = 0x1;
367 cdb[2] = pg;
368 }
369 cdb[3] = (len >> 8) & 0xff;
370 cdb[4] = (len & 0xff);
371 return len;
372}
373
374/*
375 * Encode lba and len into a READ_16/WRITE_16 CDB
376 */
377static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
378 uint32_t len, bool is_write)
379{
380 memset(cdb, 0x0, 16);
381 if (is_write) {
382 cdb[0] = WRITE_16;
383 } else {
384 cdb[0] = READ_16;
385 }
386 cdb[2] = (lba >> 56) & 0xff;
387 cdb[3] = (lba >> 48) & 0xff;
388 cdb[4] = (lba >> 40) & 0xff;
389 cdb[5] = (lba >> 32) & 0xff;
390 cdb[6] = (lba >> 24) & 0xff;
391 cdb[7] = (lba >> 16) & 0xff;
392 cdb[8] = (lba >> 8) & 0xff;
393 cdb[9] = (lba) & 0xff;
394 cdb[10] = (len >> 24) & 0xff;
395 cdb[11] = (len >> 16) & 0xff;
396 cdb[12] = (len >> 8) & 0xff;
397 cdb[13] = (len) & 0xff;
398}
399
400/*
401 * Utility functions
402 */
403static uint64_t megasas_fw_time(void)
404{
405 struct tm curtime;
e8f943c3
HR		 406
407 qemu_get_timedate(&curtime, 0);
9be38598 408 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
e8f943c3
HR		 409 ((uint64_t)curtime.tm_min & 0xff) << 40 |
410 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
411 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
412 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
413 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
e8f943c3
HR		 414}
415
76b523db
HR		 416/*
417 * Default disk sata address
418 * 0x1221 is the magic number as
419 * present in real hardware,
420 * so use it here, too.
421 */
422static uint64_t megasas_get_sata_addr(uint16_t id)
e8f943c3 423{
76b523db 424 uint64_t addr = (0x1221ULL << 48);
8ef2eb8d 425 return addr | ((uint64_t)id << 24);
e8f943c3
HR		 426}
427
428/*
429 * Frame handling
430 */
431static int megasas_next_index(MegasasState *s, int index, int limit)
432{
433 index++;
434 if (index == limit) {
435 index = 0;
436 }
437 return index;
438}
439
440static MegasasCmd *megasas_lookup_frame(MegasasState *s,
a8170e5e 441 hwaddr frame)
e8f943c3
HR		 442{
443 MegasasCmd *cmd = NULL;
444 int num = 0, index;
445
446 index = s->reply_queue_head;
447
448 while (num < s->fw_cmds) {
449 if (s->frames[index].pa && s->frames[index].pa == frame) {
450 cmd = &s->frames[index];
451 break;
452 }
453 index = megasas_next_index(s, index, s->fw_cmds);
454 num++;
455 }
456
457 return cmd;
458}
459
6df5718b 460static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
e8f943c3 461{
6df5718b 462 PCIDevice *p = PCI_DEVICE(s);
e8f943c3 463
75f19f8c
PB		 464 if (cmd->pa_size) {
465 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
466 }
6df5718b
HR		 467 cmd->frame = NULL;
468 cmd->pa = 0;
75f19f8c 469 cmd->pa_size = 0;
6df5718b 470 clear_bit(cmd->index, s->frame_map);
e8f943c3
HR		 471}
472
6df5718b
HR		 473/*
474 * This absolutely needs to be locked if
475 * qemu ever goes multithreaded.
476 */
e8f943c3 477static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
a8170e5e 478 hwaddr frame, uint64_t context, int count)
e8f943c3 479{
1016b239 480 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3
HR		 481 MegasasCmd *cmd = NULL;
482 int frame_size = MFI_FRAME_SIZE * 16;
a8170e5e 483 hwaddr frame_size_p = frame_size;
6df5718b 484 unsigned long index;
e8f943c3 485
6df5718b
HR		 486 index = 0;
487 while (index < s->fw_cmds) {
488 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
489 if (!s->frames[index].pa)
490 break;
491 /* Busy frame found */
492 trace_megasas_qf_mapped(index);
493 }
494 if (index >= s->fw_cmds) {
495 /* All frames busy */
496 trace_megasas_qf_busy(frame);
e8f943c3
HR		 497 return NULL;
498 }
6df5718b
HR		 499 cmd = &s->frames[index];
500 set_bit(index, s->frame_map);
501 trace_megasas_qf_new(index, frame);
502
503 cmd->pa = frame;
504 /* Map all possible frames */
505 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
506 if (frame_size_p != frame_size) {
507 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
508 if (cmd->frame) {
509 megasas_unmap_frame(s, cmd);
e8f943c3 510 }
6df5718b
HR		 511 s->event_count++;
512 return NULL;
513 }
514 cmd->pa_size = frame_size_p;
515 cmd->context = context;
516 if (!megasas_use_queue64(s)) {
517 cmd->context &= (uint64_t)0xFFFFFFFF;
e8f943c3
HR		 518 }
519 cmd->count = count;
520 s->busy++;
521
aaf2a859 522 if (s->consumer_pa) {
16578c6f 523 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
aaf2a859 524 }
e8f943c3 525 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
aaf2a859 526 s->reply_queue_head, s->reply_queue_tail, s->busy);
e8f943c3
HR		 527
528 return cmd;
529}
530
531static void megasas_complete_frame(MegasasState *s, uint64_t context)
532{
52190c1e 533 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 534 int tail, queue_offset;
535
536 /* Decrement busy count */
537 s->busy--;
e8f943c3
HR		 538 if (s->reply_queue_pa) {
539 /*
540 * Put command on the reply queue.
541 * Context is opaque, but emulation is running in
542 * little endian. So convert it.
543 */
e8f943c3 544 if (megasas_use_queue64(s)) {
7957ee71 545 queue_offset = s->reply_queue_head * sizeof(uint64_t);
16578c6f 546 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
e8f943c3 547 } else {
7957ee71 548 queue_offset = s->reply_queue_head * sizeof(uint32_t);
16578c6f 549 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
e8f943c3 550 }
16578c6f 551 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
aaf2a859 552 trace_megasas_qf_complete(context, s->reply_queue_head,
7957ee71 553 s->reply_queue_tail, s->busy);
e8f943c3
HR		 554 }
555
556 if (megasas_intr_enabled(s)) {
7957ee71 557 /* Update reply queue pointer */
16578c6f 558 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
7957ee71
HR		 559 tail = s->reply_queue_head;
560 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
561 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
562 s->busy);
16578c6f 563 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
e8f943c3 564 /* Notify HBA */
7957ee71
HR		 565 if (msix_enabled(pci_dev)) {
566 trace_megasas_msix_raise(0);
567 msix_notify(pci_dev, 0);
568 } else if (msi_enabled(pci_dev)) {
569 trace_megasas_msi_raise(0);
570 msi_notify(pci_dev, 0);
571 } else {
572 s->doorbell++;
573 if (s->doorbell == 1) {
e8f943c3 574 trace_megasas_irq_raise();
9e64f8a3 575 pci_irq_assert(pci_dev);
e8f943c3
HR		 576 }
577 }
578 } else {
579 trace_megasas_qf_complete_noirq(context);
580 }
581}
582
583static void megasas_reset_frames(MegasasState *s)
584{
585 int i;
586 MegasasCmd *cmd;
587
588 for (i = 0; i < s->fw_cmds; i++) {
589 cmd = &s->frames[i];
590 if (cmd->pa) {
6df5718b 591 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 592 }
593 }
6df5718b 594 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
e8f943c3
HR		 595}
596
597static void megasas_abort_command(MegasasCmd *cmd)
598{
599 if (cmd->req) {
e2b06058 600 scsi_req_cancel(cmd->req);
e8f943c3
HR		 601 cmd->req = NULL;
602 }
603}
604
605static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
606{
1016b239 607 PCIDevice *pcid = PCI_DEVICE(s);
e8f943c3 608 uint32_t pa_hi, pa_lo;
96f8f23a
HR		 609 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
610 struct mfi_init_qinfo *initq = NULL;
e8f943c3
HR		 611 uint32_t flags;
612 int ret = MFI_STAT_OK;
613
96f8f23a
HR		 614 if (s->reply_queue_pa) {
615 trace_megasas_initq_mapped(s->reply_queue_pa);
616 goto out;
617 }
e8f943c3
HR		 618 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
619 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
620 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
621 trace_megasas_init_firmware((uint64_t)iq_pa);
1016b239 622 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
e8f943c3
HR		 623 if (!initq || initq_size != sizeof(*initq)) {
624 trace_megasas_initq_map_failed(cmd->index);
625 s->event_count++;
626 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
627 goto out;
628 }
629 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
630 if (s->reply_queue_len > s->fw_cmds) {
631 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
632 s->event_count++;
633 ret = MFI_STAT_INVALID_PARAMETER;
634 goto out;
635 }
636 pa_lo = le32_to_cpu(initq->rq_addr_lo);
637 pa_hi = le32_to_cpu(initq->rq_addr_hi);
638 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
639 pa_lo = le32_to_cpu(initq->ci_addr_lo);
640 pa_hi = le32_to_cpu(initq->ci_addr_hi);
641 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
642 pa_lo = le32_to_cpu(initq->pi_addr_lo);
643 pa_hi = le32_to_cpu(initq->pi_addr_hi);
644 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
16578c6f 645 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
b60bdd1f 646 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
16578c6f 647 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
b60bdd1f 648 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
e8f943c3
HR		 649 flags = le32_to_cpu(initq->flags);
650 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
651 s->flags |= MEGASAS_MASK_USE_QUEUE64;
652 }
653 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
654 s->reply_queue_len, s->reply_queue_head,
655 s->reply_queue_tail, flags);
656 megasas_reset_frames(s);
657 s->fw_state = MFI_FWSTATE_OPERATIONAL;
658out:
659 if (initq) {
1016b239 660 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
e8f943c3
HR		 661 }
662 return ret;
663}
664
665static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
666{
667 dma_addr_t iov_pa, iov_size;
668
669 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
670 if (!cmd->frame->header.sge_count) {
671 trace_megasas_dcmd_zero_sge(cmd->index);
672 cmd->iov_size = 0;
673 return 0;
674 } else if (cmd->frame->header.sge_count > 1) {
675 trace_megasas_dcmd_invalid_sge(cmd->index,
676 cmd->frame->header.sge_count);
677 cmd->iov_size = 0;
678 return -1;
679 }
680 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
681 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
52190c1e 682 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
e8f943c3
HR		 683 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
684 cmd->iov_size = iov_size;
685 return cmd->iov_size;
686}
687
688static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
689{
690 trace_megasas_finish_dcmd(cmd->index, iov_size);
691
692 if (cmd->frame->header.sge_count) {
693 qemu_sglist_destroy(&cmd->qsg);
694 }
695 if (iov_size > cmd->iov_size) {
696 if (megasas_frame_is_ieee_sgl(cmd)) {
697 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
698 } else if (megasas_frame_is_sgl64(cmd)) {
699 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
700 } else {
701 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
702 }
703 }
704 cmd->iov_size = 0;
e8f943c3
HR		 705}
706
707static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
708{
52190c1e 709 PCIDevice *pci_dev = PCI_DEVICE(s);
e23d0498
HR		 710 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
711 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 712 struct mfi_ctrl_info info;
713 size_t dcmd_size = sizeof(info);
714 BusChild *kid;
3f2cd4dd 715 int num_pd_disks = 0;
e8f943c3 716
36fef36b 717 memset(&info, 0x0, dcmd_size);
e8f943c3
HR		 718 if (cmd->iov_size < dcmd_size) {
719 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
720 dcmd_size);
721 return MFI_STAT_INVALID_PARAMETER;
722 }
723
e23d0498
HR		 724 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
725 info.pci.device = cpu_to_le16(pci_class->device_id);
726 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
727 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
e8f943c3 728
76b523db
HR		 729 /*
730 * For some reason the firmware supports
731 * only up to 8 device ports.
732 * Despite supporting a far larger number
733 * of devices for the physical devices.
734 * So just display the first 8 devices
735 * in the device port list, independent
736 * of how many logical devices are actually
737 * present.
738 */
739 info.host.type = MFI_INFO_HOST_PCIE;
e8f943c3 740 info.device.type = MFI_INFO_DEV_SAS3G;
76b523db
HR		 741 info.device.port_count = 8;
742 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 743 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
3f2cd4dd 744 uint16_t pd_id;
76b523db 745
3f2cd4dd
HR		 746 if (num_pd_disks < 8) {
747 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
748 info.device.port_addr[num_pd_disks] =
749 cpu_to_le64(megasas_get_sata_addr(pd_id));
76b523db 750 }
3f2cd4dd 751 num_pd_disks++;
76b523db 752 }
e8f943c3 753
e23d0498 754 memcpy(info.product_name, base_class->product_name, 24);
fb654157 755 snprintf(info.serial_number, 32, "%s", s->hba_serial);
69fbd0ea 756 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
e8f943c3 757 memcpy(info.image_component[0].name, "APP", 3);
e23d0498
HR		 758 snprintf(info.image_component[0].version, 10, "%s-QEMU",
759 base_class->product_version);
5a7733b0
OH		 760 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
761 memcpy(info.image_component[0].build_time, "12:34:56", 8);
e8f943c3 762 info.image_component_count = 1;
52190c1e 763 if (pci_dev->has_rom) {
e8f943c3
HR		 764 uint8_t biosver[32];
765 uint8_t *ptr;
766
52190c1e 767 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
e8f943c3 768 memcpy(biosver, ptr + 0x41, 31);
844864fb 769 biosver[31] = 0;
e8f943c3
HR		 770 memcpy(info.image_component[1].name, "BIOS", 4);
771 memcpy(info.image_component[1].version, biosver,
772 strlen((const char *)biosver));
773 info.image_component_count++;
774 }
775 info.current_fw_time = cpu_to_le32(megasas_fw_time());
776 info.max_arms = 32;
777 info.max_spans = 8;
778 info.max_arrays = MEGASAS_MAX_ARRAYS;
3f2cd4dd 779 info.max_lds = MFI_MAX_LD;
e8f943c3
HR		 780 info.max_cmds = cpu_to_le16(s->fw_cmds);
781 info.max_sg_elements = cpu_to_le16(s->fw_sge);
782 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
3f2cd4dd
HR		 783 if (!megasas_is_jbod(s))
784 info.lds_present = cpu_to_le16(num_pd_disks);
785 info.pd_present = cpu_to_le16(num_pd_disks);
786 info.pd_disks_present = cpu_to_le16(num_pd_disks);
e8f943c3
HR		 787 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
788 MFI_INFO_HW_MEM |
789 MFI_INFO_HW_FLASH);
790 info.memory_size = cpu_to_le16(512);
791 info.nvram_size = cpu_to_le16(32);
792 info.flash_size = cpu_to_le16(16);
793 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
794 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
795 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
796 MFI_INFO_AOPS_MIXED_ARRAY);
797 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
798 MFI_INFO_LDOPS_ACCESS_POLICY |
799 MFI_INFO_LDOPS_IO_POLICY |
800 MFI_INFO_LDOPS_WRITE_POLICY |
801 MFI_INFO_LDOPS_READ_POLICY);
802 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
803 info.stripe_sz_ops.min = 3;
786a4ea8 804 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
e8f943c3
HR		 805 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
806 info.properties.intr_throttle_cnt = cpu_to_le16(16);
807 info.properties.intr_throttle_timeout = cpu_to_le16(50);
808 info.properties.rebuild_rate = 30;
809 info.properties.patrol_read_rate = 30;
810 info.properties.bgi_rate = 30;
811 info.properties.cc_rate = 30;
812 info.properties.recon_rate = 30;
813 info.properties.cache_flush_interval = 4;
814 info.properties.spinup_drv_cnt = 2;
815 info.properties.spinup_delay = 6;
816 info.properties.ecc_bucket_size = 15;
817 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
818 info.properties.expose_encl_devices = 1;
819 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
820 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
821 MFI_INFO_PDOPS_FORCE_OFFLINE);
822 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
823 MFI_INFO_PDMIX_SATA |
824 MFI_INFO_PDMIX_LD);
825
826 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
827 return MFI_STAT_OK;
828}
829
830static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
831{
832 struct mfi_defaults info;
833 size_t dcmd_size = sizeof(struct mfi_defaults);
834
835 memset(&info, 0x0, dcmd_size);
836 if (cmd->iov_size < dcmd_size) {
837 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
838 dcmd_size);
839 return MFI_STAT_INVALID_PARAMETER;
840 }
841
76b523db 842 info.sas_addr = cpu_to_le64(s->sas_addr);
e8f943c3
HR		 843 info.stripe_size = 3;
844 info.flush_time = 4;
845 info.background_rate = 30;
846 info.allow_mix_in_enclosure = 1;
847 info.allow_mix_in_ld = 1;
848 info.direct_pd_mapping = 1;
849 /* Enable for BIOS support */
850 info.bios_enumerate_lds = 1;
851 info.disable_ctrl_r = 1;
852 info.expose_enclosure_devices = 1;
853 info.disable_preboot_cli = 1;
854 info.cluster_disable = 1;
855
856 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
857 return MFI_STAT_OK;
858}
859
860static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
861{
862 struct mfi_bios_data info;
863 size_t dcmd_size = sizeof(info);
864
865 memset(&info, 0x0, dcmd_size);
866 if (cmd->iov_size < dcmd_size) {
867 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
868 dcmd_size);
869 return MFI_STAT_INVALID_PARAMETER;
870 }
871 info.continue_on_error = 1;
872 info.verbose = 1;
873 if (megasas_is_jbod(s)) {
874 info.expose_all_drives = 1;
875 }
876
877 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
878 return MFI_STAT_OK;
879}
880
881static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
882{
883 uint64_t fw_time;
884 size_t dcmd_size = sizeof(fw_time);
885
886 fw_time = cpu_to_le64(megasas_fw_time());
887
888 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
889 return MFI_STAT_OK;
890}
891
892static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
893{
894 uint64_t fw_time;
895
896 /* This is a dummy; setting of firmware time is not allowed */
897 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
898
899 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
900 fw_time = cpu_to_le64(megasas_fw_time());
901 return MFI_STAT_OK;
902}
903
904static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
905{
906 struct mfi_evt_log_state info;
907 size_t dcmd_size = sizeof(info);
908
909 memset(&info, 0, dcmd_size);
910
911 info.newest_seq_num = cpu_to_le32(s->event_count);
912 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
913 info.boot_seq_num = cpu_to_le32(s->boot_event);
914
915 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
916 return MFI_STAT_OK;
917}
918
919static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
920{
921 union mfi_evt event;
922
923 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
924 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
925 sizeof(struct mfi_evt_detail));
926 return MFI_STAT_INVALID_PARAMETER;
927 }
928 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
929 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
930 s->event_locale = event.members.locale;
931 s->event_class = event.members.class;
932 s->event_cmd = cmd;
933 /* Decrease busy count; event frame doesn't count here */
934 s->busy--;
935 cmd->iov_size = sizeof(struct mfi_evt_detail);
936 return MFI_STAT_INVALID_STATUS;
937}
938
939static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
940{
941 struct mfi_pd_list info;
942 size_t dcmd_size = sizeof(info);
943 BusChild *kid;
944 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
e8f943c3
HR		 945
946 memset(&info, 0, dcmd_size);
947 offset = 8;
948 dcmd_limit = offset + sizeof(struct mfi_pd_address);
949 if (cmd->iov_size < dcmd_limit) {
950 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
951 dcmd_limit);
952 return MFI_STAT_INVALID_PARAMETER;
953 }
954
955 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
3f2cd4dd
HR		 956 if (max_pd_disks > MFI_MAX_SYS_PDS) {
957 max_pd_disks = MFI_MAX_SYS_PDS;
e8f943c3 958 }
e8f943c3 959 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 960 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
3f2cd4dd
HR		 961 uint16_t pd_id;
962
963 if (num_pd_disks >= max_pd_disks)
964 break;
e8f943c3 965
3f2cd4dd
HR		 966 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
967 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 968 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
969 info.addr[num_pd_disks].encl_index = 0;
3f2cd4dd 970 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
e8f943c3
HR		 971 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
972 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
973 info.addr[num_pd_disks].sas_addr[0] =
3f2cd4dd 974 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 975 num_pd_disks++;
976 offset += sizeof(struct mfi_pd_address);
977 }
978 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
979 max_pd_disks, offset);
980
981 info.size = cpu_to_le32(offset);
982 info.count = cpu_to_le32(num_pd_disks);
983
984 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
985 return MFI_STAT_OK;
986}
987
988static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
989{
990 uint16_t flags;
991
992 /* mbox0 contains flags */
993 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
994 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
995 if (flags == MR_PD_QUERY_TYPE_ALL ||
996 megasas_is_jbod(s)) {
997 return megasas_dcmd_pd_get_list(s, cmd);
998 }
999
1000 return MFI_STAT_OK;
1001}
1002
1003static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1004 MegasasCmd *cmd)
1005{
1006 struct mfi_pd_info *info = cmd->iov_buf;
1007 size_t dcmd_size = sizeof(struct mfi_pd_info);
e8f943c3 1008 uint64_t pd_size;
3f2cd4dd 1009 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1010 uint8_t cmdbuf[6];
1011 SCSIRequest *req;
1012 size_t len, resid;
1013
1014 if (!cmd->iov_buf) {
0bd0adbe 1015 cmd->iov_buf = g_malloc0(dcmd_size);
e8f943c3
HR		 1016 info = cmd->iov_buf;
1017 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1018 info->vpd_page83[0] = 0x7f;
1019 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1020 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1021 if (!req) {
1022 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1023 "PD get info std inquiry");
1024 g_free(cmd->iov_buf);
1025 cmd->iov_buf = NULL;
1026 return MFI_STAT_FLASH_ALLOC_FAIL;
1027 }
1028 trace_megasas_dcmd_internal_submit(cmd->index,
1029 "PD get info std inquiry", lun);
1030 len = scsi_req_enqueue(req);
1031 if (len > 0) {
1032 cmd->iov_size = len;
1033 scsi_req_continue(req);
1034 }
1035 return MFI_STAT_INVALID_STATUS;
1036 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1037 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1038 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1039 if (!req) {
1040 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1041 "PD get info vpd inquiry");
1042 return MFI_STAT_FLASH_ALLOC_FAIL;
1043 }
1044 trace_megasas_dcmd_internal_submit(cmd->index,
1045 "PD get info vpd inquiry", lun);
1046 len = scsi_req_enqueue(req);
1047 if (len > 0) {
1048 cmd->iov_size = len;
1049 scsi_req_continue(req);
1050 }
1051 return MFI_STAT_INVALID_STATUS;
1052 }
1053 /* Finished, set FW state */
1054 if ((info->inquiry_data[0] >> 5) == 0) {
1055 if (megasas_is_jbod(cmd->state)) {
1056 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1057 } else {
1058 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1059 }
1060 } else {
1061 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1062 }
1063
3f2cd4dd 1064 info->ref.v.device_id = cpu_to_le16(pd_id);
e8f943c3
HR		 1065 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1066 MFI_PD_DDF_TYPE_INTF_SAS);
4be74634 1067 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1068 info->raw_size = cpu_to_le64(pd_size);
1069 info->non_coerced_size = cpu_to_le64(pd_size);
1070 info->coerced_size = cpu_to_le64(pd_size);
1071 info->encl_device_id = 0xFFFF;
1072 info->slot_number = (sdev->id & 0xFF);
1073 info->path_info.count = 1;
1074 info->path_info.sas_addr[0] =
3f2cd4dd 1075 cpu_to_le64(megasas_get_sata_addr(pd_id));
e8f943c3
HR		 1076 info->connected_port_bitmap = 0x1;
1077 info->device_speed = 1;
1078 info->link_speed = 1;
1079 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1080 g_free(cmd->iov_buf);
1081 cmd->iov_size = dcmd_size - resid;
1082 cmd->iov_buf = NULL;
1083 return MFI_STAT_OK;
1084}
1085
1086static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1087{
1088 size_t dcmd_size = sizeof(struct mfi_pd_info);
1089 uint16_t pd_id;
3f2cd4dd 1090 uint8_t target_id, lun_id;
e8f943c3
HR		 1091 SCSIDevice *sdev = NULL;
1092 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1093
1094 if (cmd->iov_size < dcmd_size) {
1095 return MFI_STAT_INVALID_PARAMETER;
1096 }
1097
1098 /* mbox0 has the ID */
1099 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
3f2cd4dd
HR		 1100 target_id = (pd_id >> 8) & 0xFF;
1101 lun_id = pd_id & 0xFF;
1102 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
e8f943c3
HR		 1103 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1104
1105 if (sdev) {
1106 /* Submit inquiry */
1107 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1108 }
1109
1110 return retval;
1111}
1112
1113static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1114{
1115 struct mfi_ld_list info;
1116 size_t dcmd_size = sizeof(info), resid;
3f2cd4dd 1117 uint32_t num_ld_disks = 0, max_ld_disks;
e8f943c3
HR		 1118 uint64_t ld_size;
1119 BusChild *kid;
1120
1121 memset(&info, 0, dcmd_size);
e74a4315 1122 if (cmd->iov_size > dcmd_size) {
e8f943c3
HR		 1123 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1124 dcmd_size);
1125 return MFI_STAT_INVALID_PARAMETER;
1126 }
1127
3f2cd4dd 1128 max_ld_disks = (cmd->iov_size - 8) / 16;
e8f943c3
HR		 1129 if (megasas_is_jbod(s)) {
1130 max_ld_disks = 0;
1131 }
3f2cd4dd
HR		 1132 if (max_ld_disks > MFI_MAX_LD) {
1133 max_ld_disks = MFI_MAX_LD;
1134 }
e8f943c3 1135 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 1136 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
e8f943c3
HR		 1137
1138 if (num_ld_disks >= max_ld_disks) {
1139 break;
1140 }
1141 /* Logical device size is in blocks */
4be74634 1142 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1143 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1144 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1145 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1146 num_ld_disks++;
1147 }
1148 info.ld_count = cpu_to_le32(num_ld_disks);
1149 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1150
1151 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1152 cmd->iov_size = dcmd_size - resid;
1153 return MFI_STAT_OK;
1154}
1155
34bb4d02
HR		 1156static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1157{
1158 uint16_t flags;
d97ae368
HR		 1159 struct mfi_ld_targetid_list info;
1160 size_t dcmd_size = sizeof(info), resid;
1161 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1162 BusChild *kid;
34bb4d02
HR		 1163
1164 /* mbox0 contains flags */
1165 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1166 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
d97ae368
HR		 1167 if (flags != MR_LD_QUERY_TYPE_ALL &&
1168 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1169 max_ld_disks = 0;
1170 }
1171
1172 memset(&info, 0, dcmd_size);
1173 if (cmd->iov_size < 12) {
1174 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1175 dcmd_size);
1176 return MFI_STAT_INVALID_PARAMETER;
1177 }
1178 dcmd_size = sizeof(uint32_t) * 2 + 3;
3f2cd4dd 1179 max_ld_disks = cmd->iov_size - dcmd_size;
d97ae368
HR		 1180 if (megasas_is_jbod(s)) {
1181 max_ld_disks = 0;
34bb4d02 1182 }
3f2cd4dd
HR		 1183 if (max_ld_disks > MFI_MAX_LD) {
1184 max_ld_disks = MFI_MAX_LD;
1185 }
d97ae368 1186 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 1187 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
34bb4d02 1188
d97ae368
HR		 1189 if (num_ld_disks >= max_ld_disks) {
1190 break;
1191 }
1192 info.targetid[num_ld_disks] = sdev->lun;
1193 num_ld_disks++;
1194 dcmd_size++;
1195 }
1196 info.ld_count = cpu_to_le32(num_ld_disks);
1197 info.size = dcmd_size;
1198 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1199
1200 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1201 cmd->iov_size = dcmd_size - resid;
34bb4d02
HR		 1202 return MFI_STAT_OK;
1203}
1204
e8f943c3
HR		 1205static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1206 MegasasCmd *cmd)
1207{
1208 struct mfi_ld_info *info = cmd->iov_buf;
1209 size_t dcmd_size = sizeof(struct mfi_ld_info);
1210 uint8_t cdb[6];
1211 SCSIRequest *req;
1212 ssize_t len, resid;
3f2cd4dd 1213 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
e8f943c3
HR		 1214 uint64_t ld_size;
1215
1216 if (!cmd->iov_buf) {
0bd0adbe 1217 cmd->iov_buf = g_malloc0(dcmd_size);
e8f943c3
HR		 1218 info = cmd->iov_buf;
1219 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1220 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1221 if (!req) {
1222 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1223 "LD get info vpd inquiry");
1224 g_free(cmd->iov_buf);
1225 cmd->iov_buf = NULL;
1226 return MFI_STAT_FLASH_ALLOC_FAIL;
1227 }
1228 trace_megasas_dcmd_internal_submit(cmd->index,
1229 "LD get info vpd inquiry", lun);
1230 len = scsi_req_enqueue(req);
1231 if (len > 0) {
1232 cmd->iov_size = len;
1233 scsi_req_continue(req);
1234 }
1235 return MFI_STAT_INVALID_STATUS;
1236 }
1237
1238 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1239 info->ld_config.properties.ld.v.target_id = lun;
1240 info->ld_config.params.stripe_size = 3;
1241 info->ld_config.params.num_drives = 1;
1242 info->ld_config.params.is_consistent = 1;
1243 /* Logical device size is in blocks */
4be74634 1244 blk_get_geometry(sdev->conf.blk, &ld_size);
e8f943c3
HR		 1245 info->size = cpu_to_le64(ld_size);
1246 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1247 info->ld_config.span[0].start_block = 0;
1248 info->ld_config.span[0].num_blocks = info->size;
1249 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1250
1251 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1252 g_free(cmd->iov_buf);
1253 cmd->iov_size = dcmd_size - resid;
1254 cmd->iov_buf = NULL;
1255 return MFI_STAT_OK;
1256}
1257
1258static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1259{
1260 struct mfi_ld_info info;
1261 size_t dcmd_size = sizeof(info);
1262 uint16_t ld_id;
1263 uint32_t max_ld_disks = s->fw_luns;
1264 SCSIDevice *sdev = NULL;
1265 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1266
1267 if (cmd->iov_size < dcmd_size) {
1268 return MFI_STAT_INVALID_PARAMETER;
1269 }
1270
1271 /* mbox0 has the ID */
1272 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1273 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1274
1275 if (megasas_is_jbod(s)) {
1276 return MFI_STAT_DEVICE_NOT_FOUND;
1277 }
1278
1279 if (ld_id < max_ld_disks) {
1280 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1281 }
1282
1283 if (sdev) {
1284 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1285 }
1286
1287 return retval;
1288}
1289
1290static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1291{
d37af740 1292 uint8_t data[4096] = { 0 };
e8f943c3
HR		 1293 struct mfi_config_data *info;
1294 int num_pd_disks = 0, array_offset, ld_offset;
1295 BusChild *kid;
1296
1297 if (cmd->iov_size > 4096) {
1298 return MFI_STAT_INVALID_PARAMETER;
1299 }
1300
1301 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1302 num_pd_disks++;
1303 }
1304 info = (struct mfi_config_data *)&data;
1305 /*
1306 * Array mapping:
1307 * - One array per SCSI device
1308 * - One logical drive per SCSI device
1309 * spanning the entire device
1310 */
1311 info->array_count = num_pd_disks;
1312 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1313 info->log_drv_count = num_pd_disks;
1314 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1315 info->spares_count = 0;
1316 info->spares_size = sizeof(struct mfi_spare);
1317 info->size = sizeof(struct mfi_config_data) + info->array_size +
1318 info->log_drv_size;
1319 if (info->size > 4096) {
1320 return MFI_STAT_INVALID_PARAMETER;
1321 }
1322
1323 array_offset = sizeof(struct mfi_config_data);
1324 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1325
1326 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 1327 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
3f2cd4dd 1328 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
e8f943c3
HR		 1329 struct mfi_array *array;
1330 struct mfi_ld_config *ld;
1331 uint64_t pd_size;
1332 int i;
1333
1334 array = (struct mfi_array *)(data + array_offset);
4be74634 1335 blk_get_geometry(sdev->conf.blk, &pd_size);
e8f943c3
HR		 1336 array->size = cpu_to_le64(pd_size);
1337 array->num_drives = 1;
1338 array->array_ref = cpu_to_le16(sdev_id);
1339 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1340 array->pd[0].ref.v.seq_num = 0;
1341 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1342 array->pd[0].encl.pd = 0xFF;
1343 array->pd[0].encl.slot = (sdev->id & 0xFF);
1344 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1345 array->pd[i].ref.v.device_id = 0xFFFF;
1346 array->pd[i].ref.v.seq_num = 0;
1347 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1348 array->pd[i].encl.pd = 0xFF;
1349 array->pd[i].encl.slot = 0xFF;
1350 }
1351 array_offset += sizeof(struct mfi_array);
1352 ld = (struct mfi_ld_config *)(data + ld_offset);
1353 memset(ld, 0, sizeof(struct mfi_ld_config));
3f2cd4dd 1354 ld->properties.ld.v.target_id = sdev->id;
e8f943c3
HR		 1355 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1356 MR_LD_CACHE_READ_ADAPTIVE;
1357 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1358 MR_LD_CACHE_READ_ADAPTIVE;
1359 ld->params.state = MFI_LD_STATE_OPTIMAL;
1360 ld->params.stripe_size = 3;
1361 ld->params.num_drives = 1;
1362 ld->params.span_depth = 1;
1363 ld->params.is_consistent = 1;
1364 ld->span[0].start_block = 0;
1365 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1366 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1367 ld_offset += sizeof(struct mfi_ld_config);
1368 }
1369
1370 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1371 return MFI_STAT_OK;
1372}
1373
1374static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1375{
1376 struct mfi_ctrl_props info;
1377 size_t dcmd_size = sizeof(info);
1378
1379 memset(&info, 0x0, dcmd_size);
1380 if (cmd->iov_size < dcmd_size) {
1381 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1382 dcmd_size);
1383 return MFI_STAT_INVALID_PARAMETER;
1384 }
1385 info.pred_fail_poll_interval = cpu_to_le16(300);
1386 info.intr_throttle_cnt = cpu_to_le16(16);
1387 info.intr_throttle_timeout = cpu_to_le16(50);
1388 info.rebuild_rate = 30;
1389 info.patrol_read_rate = 30;
1390 info.bgi_rate = 30;
1391 info.cc_rate = 30;
1392 info.recon_rate = 30;
1393 info.cache_flush_interval = 4;
1394 info.spinup_drv_cnt = 2;
1395 info.spinup_delay = 6;
1396 info.ecc_bucket_size = 15;
1397 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1398 info.expose_encl_devices = 1;
1399
1400 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1401 return MFI_STAT_OK;
1402}
1403
1404static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1405{
4be74634 1406 blk_drain_all();
e8f943c3
HR		 1407 return MFI_STAT_OK;
1408}
1409
1410static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1411{
1412 s->fw_state = MFI_FWSTATE_READY;
1413 return MFI_STAT_OK;
1414}
1415
200b6966 1416/* Some implementations use CLUSTER RESET LD to simulate a device reset */
e8f943c3
HR		 1417static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1418{
200b6966
HR		 1419 uint16_t target_id;
1420 int i;
1421
1422 /* mbox0 contains the device index */
1423 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1424 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1425 for (i = 0; i < s->fw_cmds; i++) {
1426 MegasasCmd *tmp_cmd = &s->frames[i];
1427 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1428 SCSIDevice *d = tmp_cmd->req->dev;
1429 qdev_reset_all(&d->qdev);
1430 }
1431 }
1432 return MFI_STAT_OK;
e8f943c3
HR		 1433}
1434
1435static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1436{
10d6530c
HR		 1437 struct mfi_ctrl_props info;
1438 size_t dcmd_size = sizeof(info);
1439
1440 if (cmd->iov_size < dcmd_size) {
1441 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1442 dcmd_size);
1443 return MFI_STAT_INVALID_PARAMETER;
1444 }
1b858980 1445 dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
10d6530c 1446 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
e8f943c3
HR		 1447 return MFI_STAT_OK;
1448}
1449
1450static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1451{
1452 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1453 return MFI_STAT_OK;
1454}
1455
1456static const struct dcmd_cmd_tbl_t {
1457 int opcode;
1458 const char *desc;
1459 int (*func)(MegasasState *s, MegasasCmd *cmd);
1460} dcmd_cmd_tbl[] = {
1461 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1462 megasas_dcmd_dummy },
1463 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1464 megasas_ctrl_get_info },
1465 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1466 megasas_dcmd_get_properties },
1467 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1468 megasas_dcmd_set_properties },
1469 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1470 megasas_dcmd_dummy },
1471 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1472 megasas_dcmd_dummy },
1473 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1474 megasas_dcmd_dummy },
1475 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1476 megasas_dcmd_dummy },
1477 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1478 megasas_dcmd_dummy },
1479 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1480 megasas_event_info },
1481 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1482 megasas_dcmd_dummy },
1483 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1484 megasas_event_wait },
1485 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1486 megasas_ctrl_shutdown },
1487 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1488 megasas_dcmd_dummy },
1489 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1490 megasas_dcmd_get_fw_time },
1491 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1492 megasas_dcmd_set_fw_time },
1493 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1494 megasas_dcmd_get_bios_info },
1495 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1496 megasas_dcmd_dummy },
1497 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1498 megasas_mfc_get_defaults },
1499 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1500 megasas_dcmd_dummy },
1501 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1502 megasas_cache_flush },
1503 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1504 megasas_dcmd_pd_get_list },
1505 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1506 megasas_dcmd_pd_list_query },
1507 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1508 megasas_dcmd_pd_get_info },
1509 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1510 megasas_dcmd_dummy },
1511 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1512 megasas_dcmd_dummy },
1513 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1514 megasas_dcmd_dummy },
1515 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1516 megasas_dcmd_dummy },
1517 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1518 megasas_dcmd_ld_get_list},
34bb4d02
HR		 1519 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1520 megasas_dcmd_ld_list_query },
e8f943c3
HR		 1521 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1522 megasas_dcmd_ld_get_info },
1523 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1524 megasas_dcmd_dummy },
1525 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1526 megasas_dcmd_dummy },
1527 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1528 megasas_dcmd_dummy },
1529 { MFI_DCMD_CFG_READ, "CFG_READ",
1530 megasas_dcmd_cfg_read },
1531 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1532 megasas_dcmd_dummy },
1533 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1534 megasas_dcmd_dummy },
1535 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1536 megasas_dcmd_dummy },
1537 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1538 megasas_dcmd_dummy },
1539 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1540 megasas_dcmd_dummy },
1541 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1542 megasas_dcmd_dummy },
1543 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1544 megasas_dcmd_dummy },
1545 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1546 megasas_dcmd_dummy },
1547 { MFI_DCMD_CLUSTER, "CLUSTER",
1548 megasas_dcmd_dummy },
1549 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1550 megasas_dcmd_dummy },
1551 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1552 megasas_cluster_reset_ld },
1553 { -1, NULL, NULL }
1554};
1555
1556static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1557{
1558 int opcode, len;
1559 int retval = 0;
1560 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1561
1562 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1563 trace_megasas_handle_dcmd(cmd->index, opcode);
1564 len = megasas_map_dcmd(s, cmd);
1565 if (len < 0) {
1566 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1567 }
1568 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1569 cmdptr++;
1570 }
1571 if (cmdptr->opcode == -1) {
1572 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1573 retval = megasas_dcmd_dummy(s, cmd);
1574 } else {
1575 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1576 retval = cmdptr->func(s, cmd);
1577 }
1578 if (retval != MFI_STAT_INVALID_STATUS) {
1579 megasas_finish_dcmd(cmd, len);
1580 }
1581 return retval;
1582}
1583
1584static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1585 SCSIRequest *req)
1586{
1587 int opcode;
1588 int retval = MFI_STAT_OK;
1589 int lun = req->lun;
1590
1591 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1592 scsi_req_unref(req);
1593 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1594 switch (opcode) {
1595 case MFI_DCMD_PD_GET_INFO:
1596 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1597 break;
1598 case MFI_DCMD_LD_GET_INFO:
1599 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1600 break;
1601 default:
1602 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1603 retval = MFI_STAT_INVALID_DCMD;
1604 break;
1605 }
1606 if (retval != MFI_STAT_INVALID_STATUS) {
1607 megasas_finish_dcmd(cmd, cmd->iov_size);
1608 }
1609 return retval;
1610}
1611
1612static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1613{
1614 int len;
1615
1616 len = scsi_req_enqueue(cmd->req);
1617 if (len < 0) {
1618 len = -len;
1619 }
1620 if (len > 0) {
1621 if (len > cmd->iov_size) {
1622 if (is_write) {
1623 trace_megasas_iov_write_overflow(cmd->index, len,
1624 cmd->iov_size);
1625 } else {
1626 trace_megasas_iov_read_overflow(cmd->index, len,
1627 cmd->iov_size);
1628 }
1629 }
1630 if (len < cmd->iov_size) {
1631 if (is_write) {
1632 trace_megasas_iov_write_underflow(cmd->index, len,
1633 cmd->iov_size);
1634 } else {
1635 trace_megasas_iov_read_underflow(cmd->index, len,
1636 cmd->iov_size);
1637 }
1638 cmd->iov_size = len;
1639 }
1640 scsi_req_continue(cmd->req);
1641 }
1642 return len;
1643}
1644
1645static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1646 bool is_logical)
1647{
1648 uint8_t *cdb;
e8f943c3
HR		 1649 bool is_write;
1650 struct SCSIDevice *sdev = NULL;
1651
1652 cdb = cmd->frame->pass.cdb;
1653
3f2cd4dd
HR		 1654 if (is_logical) {
1655 if (cmd->frame->header.target_id >= MFI_MAX_LD ||
1656 cmd->frame->header.lun_id != 0) {
1657 trace_megasas_scsi_target_not_present(
1658 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1659 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1660 return MFI_STAT_DEVICE_NOT_FOUND;
1661 }
e8f943c3 1662 }
3f2cd4dd
HR		 1663 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1664 cmd->frame->header.lun_id);
1665
e8f943c3
HR		 1666 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1667 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1668 is_logical, cmd->frame->header.target_id,
1669 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1670
1671 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1672 trace_megasas_scsi_target_not_present(
1673 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1674 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1675 return MFI_STAT_DEVICE_NOT_FOUND;
1676 }
1677
1678 if (cmd->frame->header.cdb_len > 16) {
1679 trace_megasas_scsi_invalid_cdb_len(
1680 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1681 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1682 cmd->frame->header.cdb_len);
1683 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1684 cmd->frame->header.scsi_status = CHECK_CONDITION;
1685 s->event_count++;
1686 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1687 }
1688
1689 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1690 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1691 cmd->frame->header.scsi_status = CHECK_CONDITION;
1692 s->event_count++;
1693 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1694 }
1695
1696 cmd->req = scsi_req_new(sdev, cmd->index,
1697 cmd->frame->header.lun_id, cdb, cmd);
1698 if (!cmd->req) {
1699 trace_megasas_scsi_req_alloc_failed(
1700 mfi_frame_desc[cmd->frame->header.frame_cmd],
1701 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1702 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1703 cmd->frame->header.scsi_status = BUSY;
1704 s->event_count++;
1705 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1706 }
1707
1708 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
aaf2a859 1709 if (cmd->iov_size) {
e8f943c3 1710 if (is_write) {
aaf2a859 1711 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
e8f943c3 1712 } else {
aaf2a859 1713 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
e8f943c3
HR		 1714 }
1715 } else {
1716 trace_megasas_scsi_nodata(cmd->index);
1717 }
aaf2a859 1718 megasas_enqueue_req(cmd, is_write);
e8f943c3
HR		 1719 return MFI_STAT_INVALID_STATUS;
1720}
1721
1722static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1723{
1724 uint32_t lba_count, lba_start_hi, lba_start_lo;
1725 uint64_t lba_start;
1726 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1727 uint8_t cdb[16];
1728 int len;
1729 struct SCSIDevice *sdev = NULL;
1730
1731 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1732 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1733 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1734 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1735
3f2cd4dd
HR		 1736 if (cmd->frame->header.target_id < MFI_MAX_LD &&
1737 cmd->frame->header.lun_id == 0) {
e8f943c3
HR		 1738 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1739 cmd->frame->header.lun_id);
1740 }
1741
1742 trace_megasas_handle_io(cmd->index,
1743 mfi_frame_desc[cmd->frame->header.frame_cmd],
1744 cmd->frame->header.target_id,
1745 cmd->frame->header.lun_id,
1746 (unsigned long)lba_start, (unsigned long)lba_count);
1747 if (!sdev) {
1748 trace_megasas_io_target_not_present(cmd->index,
1749 mfi_frame_desc[cmd->frame->header.frame_cmd],
1750 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1751 return MFI_STAT_DEVICE_NOT_FOUND;
1752 }
1753
1754 if (cmd->frame->header.cdb_len > 16) {
1755 trace_megasas_scsi_invalid_cdb_len(
1756 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1757 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1758 cmd->frame->header.cdb_len);
1759 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1760 cmd->frame->header.scsi_status = CHECK_CONDITION;
1761 s->event_count++;
1762 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1763 }
1764
1765 cmd->iov_size = lba_count * sdev->blocksize;
1766 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1767 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1768 cmd->frame->header.scsi_status = CHECK_CONDITION;
1769 s->event_count++;
1770 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1771 }
1772
1773 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1774 cmd->req = scsi_req_new(sdev, cmd->index,
1775 cmd->frame->header.lun_id, cdb, cmd);
1776 if (!cmd->req) {
1777 trace_megasas_scsi_req_alloc_failed(
1778 mfi_frame_desc[cmd->frame->header.frame_cmd],
1779 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1780 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1781 cmd->frame->header.scsi_status = BUSY;
1782 s->event_count++;
1783 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1784 }
1785 len = megasas_enqueue_req(cmd, is_write);
1786 if (len > 0) {
1787 if (is_write) {
1788 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1789 } else {
1790 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1791 }
1792 }
1793 return MFI_STAT_INVALID_STATUS;
1794}
1795
1796static int megasas_finish_internal_command(MegasasCmd *cmd,
1797 SCSIRequest *req, size_t resid)
1798{
1799 int retval = MFI_STAT_INVALID_CMD;
1800
1801 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1802 cmd->iov_size -= resid;
1803 retval = megasas_finish_internal_dcmd(cmd, req);
1804 }
1805 return retval;
1806}
1807
1808static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1809{
1810 MegasasCmd *cmd = req->hba_private;
1811
1812 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1813 return NULL;
1814 } else {
1815 return &cmd->qsg;
1816 }
1817}
1818
1819static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1820{
1821 MegasasCmd *cmd = req->hba_private;
1822 uint8_t *buf;
1823 uint32_t opcode;
1824
1825 trace_megasas_io_complete(cmd->index, len);
1826
1827 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1828 scsi_req_continue(req);
1829 return;
1830 }
1831
1832 buf = scsi_req_get_buf(req);
1833 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1834 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1835 struct mfi_pd_info *info = cmd->iov_buf;
1836
1837 if (info->inquiry_data[0] == 0x7f) {
1838 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1839 memcpy(info->inquiry_data, buf, len);
1840 } else if (info->vpd_page83[0] == 0x7f) {
1841 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1842 memcpy(info->vpd_page83, buf, len);
1843 }
1844 scsi_req_continue(req);
1845 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1846 struct mfi_ld_info *info = cmd->iov_buf;
1847
1848 if (cmd->iov_buf) {
1849 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1850 scsi_req_continue(req);
1851 }
1852 }
1853}
1854
1855static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1856 size_t resid)
1857{
1858 MegasasCmd *cmd = req->hba_private;
1859 uint8_t cmd_status = MFI_STAT_OK;
1860
1861 trace_megasas_command_complete(cmd->index, status, resid);
1862
1863 if (cmd->req != req) {
1864 /*
1865 * Internal command complete
1866 */
1867 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1868 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1869 return;
1870 }
1871 } else {
1872 req->status = status;
1873 trace_megasas_scsi_complete(cmd->index, req->status,
1874 cmd->iov_size, req->cmd.xfer);
1875 if (req->status != GOOD) {
1876 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1877 }
1878 if (req->status == CHECK_CONDITION) {
1879 megasas_copy_sense(cmd);
1880 }
1881
1882 megasas_unmap_sgl(cmd);
1883 cmd->frame->header.scsi_status = req->status;
1884 scsi_req_unref(cmd->req);
1885 cmd->req = NULL;
1886 }
1887 cmd->frame->header.cmd_status = cmd_status;
6df5718b 1888 megasas_unmap_frame(cmd->state, cmd);
e8f943c3
HR		 1889 megasas_complete_frame(cmd->state, cmd->context);
1890}
1891
1892static void megasas_command_cancel(SCSIRequest *req)
1893{
1894 MegasasCmd *cmd = req->hba_private;
1895
1896 if (cmd) {
1897 megasas_abort_command(cmd);
1898 } else {
1899 scsi_req_unref(req);
1900 }
1901}
1902
1903static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1904{
1905 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
a8170e5e 1906 hwaddr abort_addr, addr_hi, addr_lo;
e8f943c3
HR		 1907 MegasasCmd *abort_cmd;
1908
1909 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1910 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1911 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1912
1913 abort_cmd = megasas_lookup_frame(s, abort_addr);
1914 if (!abort_cmd) {
1915 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1916 s->event_count++;
1917 return MFI_STAT_OK;
1918 }
1919 if (!megasas_use_queue64(s)) {
1920 abort_ctx &= (uint64_t)0xFFFFFFFF;
1921 }
1922 if (abort_cmd->context != abort_ctx) {
1923 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1924 abort_cmd->context);
1925 s->event_count++;
1926 return MFI_STAT_ABORT_NOT_POSSIBLE;
1927 }
1928 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1929 megasas_abort_command(abort_cmd);
1930 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1931 s->event_cmd = NULL;
1932 }
1933 s->event_count++;
1934 return MFI_STAT_OK;
1935}
1936
1937static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1938 uint32_t frame_count)
1939{
1940 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1941 uint64_t frame_context;
1942 MegasasCmd *cmd;
1943
1944 /*
1945 * Always read 64bit context, top bits will be
1946 * masked out if required in megasas_enqueue_frame()
1947 */
16578c6f 1948 frame_context = megasas_frame_get_context(s, frame_addr);
e8f943c3
HR		 1949
1950 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1951 if (!cmd) {
1952 /* reply queue full */
1953 trace_megasas_frame_busy(frame_addr);
16578c6f
PB		 1954 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1955 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
e8f943c3
HR		 1956 megasas_complete_frame(s, frame_context);
1957 s->event_count++;
1958 return;
1959 }
1960 switch (cmd->frame->header.frame_cmd) {
1961 case MFI_CMD_INIT:
1962 frame_status = megasas_init_firmware(s, cmd);
1963 break;
1964 case MFI_CMD_DCMD:
1965 frame_status = megasas_handle_dcmd(s, cmd);
1966 break;
1967 case MFI_CMD_ABORT:
1968 frame_status = megasas_handle_abort(s, cmd);
1969 break;
1970 case MFI_CMD_PD_SCSI_IO:
1971 frame_status = megasas_handle_scsi(s, cmd, 0);
1972 break;
1973 case MFI_CMD_LD_SCSI_IO:
1974 frame_status = megasas_handle_scsi(s, cmd, 1);
1975 break;
1976 case MFI_CMD_LD_READ:
1977 case MFI_CMD_LD_WRITE:
1978 frame_status = megasas_handle_io(s, cmd);
1979 break;
1980 default:
1981 trace_megasas_unhandled_frame_cmd(cmd->index,
1982 cmd->frame->header.frame_cmd);
1983 s->event_count++;
1984 break;
1985 }
1986 if (frame_status != MFI_STAT_INVALID_STATUS) {
421cc3e7
PB		 1987 if (cmd->frame) {
1988 cmd->frame->header.cmd_status = frame_status;
1989 } else {
1990 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
1991 }
6df5718b 1992 megasas_unmap_frame(s, cmd);
e8f943c3
HR		 1993 megasas_complete_frame(s, cmd->context);
1994 }
1995}
1996
a8170e5e 1997static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
e8f943c3
HR		 1998 unsigned size)
1999{
2000 MegasasState *s = opaque;
e23d0498
HR		 2001 PCIDevice *pci_dev = PCI_DEVICE(s);
2002 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 2003 uint32_t retval = 0;
2004
2005 switch (addr) {
2006 case MFI_IDB:
2007 retval = 0;
77bb6b17 2008 trace_megasas_mmio_readl("MFI_IDB", retval);
e8f943c3
HR		 2009 break;
2010 case MFI_OMSG0:
2011 case MFI_OSP0:
e23d0498 2012 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
e8f943c3
HR		 2013 (s->fw_state & MFI_FWSTATE_MASK) |
2014 ((s->fw_sge & 0xff) << 16) |
2015 (s->fw_cmds & 0xFFFF);
77bb6b17
HR		 2016 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2017 retval);
e8f943c3
HR		 2018 break;
2019 case MFI_OSTS:
2020 if (megasas_intr_enabled(s) && s->doorbell) {
e23d0498 2021 retval = base_class->osts;
e8f943c3 2022 }
77bb6b17 2023 trace_megasas_mmio_readl("MFI_OSTS", retval);
e8f943c3
HR		 2024 break;
2025 case MFI_OMSK:
2026 retval = s->intr_mask;
77bb6b17 2027 trace_megasas_mmio_readl("MFI_OMSK", retval);
e8f943c3
HR		 2028 break;
2029 case MFI_ODCR0:
7957ee71 2030 retval = s->doorbell ? 1 : 0;
77bb6b17 2031 trace_megasas_mmio_readl("MFI_ODCR0", retval);
e8f943c3 2032 break;
e23d0498
HR		 2033 case MFI_DIAG:
2034 retval = s->diag;
77bb6b17 2035 trace_megasas_mmio_readl("MFI_DIAG", retval);
e23d0498
HR		 2036 break;
2037 case MFI_OSP1:
2038 retval = 15;
77bb6b17 2039 trace_megasas_mmio_readl("MFI_OSP1", retval);
e23d0498 2040 break;
e8f943c3
HR		 2041 default:
2042 trace_megasas_mmio_invalid_readl(addr);
2043 break;
2044 }
e8f943c3
HR		 2045 return retval;
2046}
2047
e23d0498
HR		 2048static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2049
a8170e5e 2050static void megasas_mmio_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2051 uint64_t val, unsigned size)
2052{
2053 MegasasState *s = opaque;
52190c1e 2054 PCIDevice *pci_dev = PCI_DEVICE(s);
e8f943c3
HR		 2055 uint64_t frame_addr;
2056 uint32_t frame_count;
2057 int i;
2058
e8f943c3
HR		 2059 switch (addr) {
2060 case MFI_IDB:
77bb6b17 2061 trace_megasas_mmio_writel("MFI_IDB", val);
e8f943c3
HR		 2062 if (val & MFI_FWINIT_ABORT) {
2063 /* Abort all pending cmds */
2064 for (i = 0; i < s->fw_cmds; i++) {
2065 megasas_abort_command(&s->frames[i]);
2066 }
2067 }
2068 if (val & MFI_FWINIT_READY) {
2069 /* move to FW READY */
2070 megasas_soft_reset(s);
2071 }
2072 if (val & MFI_FWINIT_MFIMODE) {
2073 /* discard MFIs */
2074 }
e23d0498
HR		 2075 if (val & MFI_FWINIT_STOP_ADP) {
2076 /* Terminal error, stop processing */
2077 s->fw_state = MFI_FWSTATE_FAULT;
2078 }
e8f943c3
HR		 2079 break;
2080 case MFI_OMSK:
77bb6b17 2081 trace_megasas_mmio_writel("MFI_OMSK", val);
e8f943c3 2082 s->intr_mask = val;
4522b69c
HR		 2083 if (!megasas_intr_enabled(s) &&
2084 !msi_enabled(pci_dev) &&
2085 !msix_enabled(pci_dev)) {
e8f943c3 2086 trace_megasas_irq_lower();
9e64f8a3 2087 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2088 }
2089 if (megasas_intr_enabled(s)) {
4522b69c
HR		 2090 if (msix_enabled(pci_dev)) {
2091 trace_megasas_msix_enabled(0);
2092 } else if (msi_enabled(pci_dev)) {
2093 trace_megasas_msi_enabled(0);
2094 } else {
2095 trace_megasas_intr_enabled();
2096 }
e8f943c3
HR		 2097 } else {
2098 trace_megasas_intr_disabled();
e23d0498 2099 megasas_soft_reset(s);
e8f943c3
HR		 2100 }
2101 break;
2102 case MFI_ODCR0:
77bb6b17 2103 trace_megasas_mmio_writel("MFI_ODCR0", val);
e8f943c3 2104 s->doorbell = 0;
7957ee71
HR		 2105 if (megasas_intr_enabled(s)) {
2106 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
e8f943c3 2107 trace_megasas_irq_lower();
9e64f8a3 2108 pci_irq_deassert(pci_dev);
e8f943c3
HR		 2109 }
2110 }
2111 break;
2112 case MFI_IQPH:
77bb6b17 2113 trace_megasas_mmio_writel("MFI_IQPH", val);
e8f943c3
HR		 2114 /* Received high 32 bits of a 64 bit MFI frame address */
2115 s->frame_hi = val;
2116 break;
2117 case MFI_IQPL:
77bb6b17 2118 trace_megasas_mmio_writel("MFI_IQPL", val);
e8f943c3 2119 /* Received low 32 bits of a 64 bit MFI frame address */
e23d0498 2120 /* Fallthrough */
e8f943c3 2121 case MFI_IQP:
77bb6b17
HR		 2122 if (addr == MFI_IQP) {
2123 trace_megasas_mmio_writel("MFI_IQP", val);
2124 /* Received 64 bit MFI frame address */
2125 s->frame_hi = 0;
2126 }
e8f943c3
HR		 2127 frame_addr = (val & ~0x1F);
2128 /* Add possible 64 bit offset */
2129 frame_addr |= ((uint64_t)s->frame_hi << 32);
2130 s->frame_hi = 0;
2131 frame_count = (val >> 1) & 0xF;
2132 megasas_handle_frame(s, frame_addr, frame_count);
2133 break;
e23d0498 2134 case MFI_SEQ:
77bb6b17 2135 trace_megasas_mmio_writel("MFI_SEQ", val);
e23d0498
HR		 2136 /* Magic sequence to start ADP reset */
2137 if (adp_reset_seq[s->adp_reset] == val) {
2138 s->adp_reset++;
2139 } else {
2140 s->adp_reset = 0;
2141 s->diag = 0;
2142 }
2143 if (s->adp_reset == 6) {
2144 s->diag = MFI_DIAG_WRITE_ENABLE;
2145 }
2146 break;
2147 case MFI_DIAG:
77bb6b17 2148 trace_megasas_mmio_writel("MFI_DIAG", val);
e23d0498
HR		 2149 /* ADP reset */
2150 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2151 (val & MFI_DIAG_RESET_ADP)) {
2152 s->diag |= MFI_DIAG_RESET_ADP;
2153 megasas_soft_reset(s);
2154 s->adp_reset = 0;
2155 s->diag = 0;
2156 }
2157 break;
e8f943c3
HR		 2158 default:
2159 trace_megasas_mmio_invalid_writel(addr, val);
2160 break;
2161 }
2162}
2163
2164static const MemoryRegionOps megasas_mmio_ops = {
2165 .read = megasas_mmio_read,
2166 .write = megasas_mmio_write,
2167 .endianness = DEVICE_LITTLE_ENDIAN,
2168 .impl = {
2169 .min_access_size = 8,
2170 .max_access_size = 8,
2171 }
2172};
2173
a8170e5e 2174static uint64_t megasas_port_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2175 unsigned size)
2176{
2177 return megasas_mmio_read(opaque, addr & 0xff, size);
2178}
2179
a8170e5e 2180static void megasas_port_write(void *opaque, hwaddr addr,
e8f943c3
HR		 2181 uint64_t val, unsigned size)
2182{
2183 megasas_mmio_write(opaque, addr & 0xff, val, size);
2184}
2185
2186static const MemoryRegionOps megasas_port_ops = {
2187 .read = megasas_port_read,
2188 .write = megasas_port_write,
2189 .endianness = DEVICE_LITTLE_ENDIAN,
2190 .impl = {
2191 .min_access_size = 4,
2192 .max_access_size = 4,
2193 }
2194};
2195
a8170e5e 2196static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
e8f943c3
HR		 2197 unsigned size)
2198{
2199 return 0;
2200}
2201
55875fc4
SP		 2202static void megasas_queue_write(void *opaque, hwaddr addr,
2203 uint64_t val, unsigned size)
2204{
2205 return;
2206}
2207
e8f943c3
HR		 2208static const MemoryRegionOps megasas_queue_ops = {
2209 .read = megasas_queue_read,
55875fc4 2210 .write = megasas_queue_write,
e8f943c3
HR		 2211 .endianness = DEVICE_LITTLE_ENDIAN,
2212 .impl = {
2213 .min_access_size = 8,
2214 .max_access_size = 8,
2215 }
2216};
2217
2218static void megasas_soft_reset(MegasasState *s)
2219{
2220 int i;
2221 MegasasCmd *cmd;
2222
8d72db68 2223 trace_megasas_reset(s->fw_state);
e8f943c3
HR		 2224 for (i = 0; i < s->fw_cmds; i++) {
2225 cmd = &s->frames[i];
2226 megasas_abort_command(cmd);
2227 }
8d72db68
HR		 2228 if (s->fw_state == MFI_FWSTATE_READY) {
2229 BusChild *kid;
2230
2231 /*
2232 * The EFI firmware doesn't handle UA,
2233 * so we need to clear the Power On/Reset UA
2234 * after the initial reset.
2235 */
2236 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
e1dc6815 2237 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
8d72db68
HR		 2238
2239 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2240 scsi_device_unit_attention_reported(sdev);
2241 }
2242 }
e8f943c3
HR		 2243 megasas_reset_frames(s);
2244 s->reply_queue_len = s->fw_cmds;
2245 s->reply_queue_pa = 0;
2246 s->consumer_pa = 0;
2247 s->producer_pa = 0;
2248 s->fw_state = MFI_FWSTATE_READY;
2249 s->doorbell = 0;
2250 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2251 s->frame_hi = 0;
2252 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2253 s->event_count++;
2254 s->boot_event = s->event_count;
2255}
2256
2257static void megasas_scsi_reset(DeviceState *dev)
2258{
c79e16ae 2259 MegasasState *s = MEGASAS(dev);
e8f943c3
HR		 2260
2261 megasas_soft_reset(s);
2262}
2263
e23d0498 2264static const VMStateDescription vmstate_megasas_gen1 = {
e8f943c3
HR		 2265 .name = "megasas",
2266 .version_id = 0,
2267 .minimum_version_id = 0,
d49805ae 2268 .fields = (VMStateField[]) {
52190c1e 2269 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
23335f62 2270 VMSTATE_MSIX(parent_obj, MegasasState),
e8f943c3
HR		 2271
2272 VMSTATE_INT32(fw_state, MegasasState),
2273 VMSTATE_INT32(intr_mask, MegasasState),
2274 VMSTATE_INT32(doorbell, MegasasState),
2275 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2276 VMSTATE_UINT64(consumer_pa, MegasasState),
2277 VMSTATE_UINT64(producer_pa, MegasasState),
2278 VMSTATE_END_OF_LIST()
2279 }
2280};
2281
e23d0498
HR		 2282static const VMStateDescription vmstate_megasas_gen2 = {
2283 .name = "megasas-gen2",
2284 .version_id = 0,
2285 .minimum_version_id = 0,
2286 .minimum_version_id_old = 0,
2287 .fields = (VMStateField[]) {
2288 VMSTATE_PCIE_DEVICE(parent_obj, MegasasState),
2289 VMSTATE_MSIX(parent_obj, MegasasState),
2290
2291 VMSTATE_INT32(fw_state, MegasasState),
2292 VMSTATE_INT32(intr_mask, MegasasState),
2293 VMSTATE_INT32(doorbell, MegasasState),
2294 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2295 VMSTATE_UINT64(consumer_pa, MegasasState),
2296 VMSTATE_UINT64(producer_pa, MegasasState),
2297 VMSTATE_END_OF_LIST()
2298 }
2299};
2300
18fc611b 2301static void megasas_scsi_uninit(PCIDevice *d)
e8f943c3 2302{
c79e16ae 2303 MegasasState *s = MEGASAS(d);
e8f943c3 2304
4522b69c
HR		 2305 if (megasas_use_msix(s)) {
2306 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2307 }
afea4e14 2308 msi_uninit(d);
e8f943c3
HR		 2309}
2310
2311static const struct SCSIBusInfo megasas_scsi_info = {
2312 .tcq = true,
2313 .max_target = MFI_MAX_LD,
2314 .max_lun = 255,
2315
2316 .transfer_data = megasas_xfer_complete,
2317 .get_sg_list = megasas_get_sg_list,
2318 .complete = megasas_command_complete,
2319 .cancel = megasas_command_cancel,
2320};
2321
ae071cc8 2322static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
e8f943c3 2323{
22d6aa03 2324 DeviceState *d = DEVICE(dev);
c79e16ae 2325 MegasasState *s = MEGASAS(dev);
e23d0498 2326 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
e8f943c3
HR		 2327 uint8_t *pci_conf;
2328 int i, bar_type;
1108b2f8
C		 2329 Error *err = NULL;
2330 int ret;
e8f943c3 2331
52190c1e 2332 pci_conf = dev->config;
e8f943c3
HR		 2333
2334 /* PCI latency timer = 0 */
2335 pci_conf[PCI_LATENCY_TIMER] = 0;
2336 /* Interrupt pin 1 */
2337 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2338
afea4e14 2339 if (s->msi != ON_OFF_AUTO_OFF) {
1108b2f8
C		 2340 ret = msi_init(dev, 0x50, 1, true, false, &err);
2341 /* Any error other than -ENOTSUP(board's MSI support is broken)
2342 * is a programming error */
2343 assert(!ret || ret == -ENOTSUP);
2344 if (ret && s->msi == ON_OFF_AUTO_ON) {
2345 /* Can't satisfy user's explicit msi=on request, fail */
2346 error_append_hint(&err, "You have to use msi=auto (default) or "
2347 "msi=off with this machine type.\n");
2348 error_propagate(errp, err);
2349 return;
2350 } else if (ret) {
2351 /* With msi=auto, we fall back to MSI off silently */
2352 s->msi = ON_OFF_AUTO_OFF;
2353 error_free(err);
2354 }
2355 }
2356
29776739 2357 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
e8f943c3 2358 "megasas-mmio", 0x4000);
29776739 2359 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
e8f943c3 2360 "megasas-io", 256);
29776739 2361 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
e8f943c3
HR		 2362 "megasas-queue", 0x40000);
2363
e8f943c3 2364 if (megasas_use_msix(s) &&
e23d0498
HR		 2365 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2366 &s->mmio_io, b->mmio_bar, 0x3800, 0x68)) {
b4b4a57f 2367 s->msix = ON_OFF_AUTO_OFF;
e8f943c3 2368 }
e23d0498
HR		 2369 if (pci_is_express(dev)) {
2370 pcie_endpoint_cap_init(dev, 0xa0);
2371 }
e8f943c3
HR		 2372
2373 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
e23d0498
HR		 2374 pci_register_bar(dev, b->ioport_bar,
2375 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2376 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
52190c1e 2377 pci_register_bar(dev, 3, bar_type, &s->queue_io);
e8f943c3
HR		 2378
2379 if (megasas_use_msix(s)) {
52190c1e 2380 msix_vector_use(dev, 0);
e8f943c3
HR		 2381 }
2382
8d72db68 2383 s->fw_state = MFI_FWSTATE_READY;
76b523db
HR		 2384 if (!s->sas_addr) {
2385 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2386 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2387 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2388 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2389 s->sas_addr |= PCI_FUNC(dev->devfn);
2390 }
fb654157 2391 if (!s->hba_serial) {
23335f62 2392 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
fb654157 2393 }
e8f943c3
HR		 2394 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2395 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2396 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2397 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2398 } else {
2399 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2400 }
2401 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2402 s->fw_cmds = MEGASAS_MAX_FRAMES;
2403 }
2404 trace_megasas_init(s->fw_sge, s->fw_cmds,
e8f943c3 2405 megasas_is_jbod(s) ? "jbod" : "raid");
3f2cd4dd
HR		 2406
2407 if (megasas_is_jbod(s)) {
2408 s->fw_luns = MFI_MAX_SYS_PDS;
2409 } else {
2410 s->fw_luns = MFI_MAX_LD;
2411 }
e8f943c3
HR		 2412 s->producer_pa = 0;
2413 s->consumer_pa = 0;
2414 for (i = 0; i < s->fw_cmds; i++) {
2415 s->frames[i].index = i;
2416 s->frames[i].context = -1;
2417 s->frames[i].pa = 0;
2418 s->frames[i].state = s;
2419 }
2420
b1187b51
AF		 2421 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2422 &megasas_scsi_info, NULL);
22d6aa03 2423 if (!d->hotplugged) {
ae071cc8 2424 scsi_bus_legacy_handle_cmdline(&s->bus, errp);
22d6aa03 2425 }
e8f943c3
HR		 2426}
2427
e23d0498 2428static Property megasas_properties_gen1[] = {
e8f943c3
HR		 2429 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2430 MEGASAS_DEFAULT_SGE),
2431 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2432 MEGASAS_DEFAULT_FRAMES),
fb654157 2433 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
c7bcc85d 2434 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
b4b4a57f
C		 2435 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2436 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
e8f943c3
HR		 2437 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2438 MEGASAS_FLAG_USE_JBOD, false),
2439 DEFINE_PROP_END_OF_LIST(),
2440};
2441
e23d0498
HR		 2442static Property megasas_properties_gen2[] = {
2443 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2444 MEGASAS_DEFAULT_SGE),
2445 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2446 MEGASAS_GEN2_DEFAULT_FRAMES),
2447 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2448 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
b4b4a57f
C		 2449 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2450 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
e23d0498
HR		 2451 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2452 MEGASAS_FLAG_USE_JBOD, false),
2453 DEFINE_PROP_END_OF_LIST(),
2454};
2455
2456typedef struct MegasasInfo {
2457 const char *name;
2458 const char *desc;
2459 const char *product_name;
2460 const char *product_version;
2461 uint16_t device_id;
2462 uint16_t subsystem_id;
2463 int ioport_bar;
2464 int mmio_bar;
2465 bool is_express;
2466 int osts;
2467 const VMStateDescription *vmsd;
2468 Property *props;
2469} MegasasInfo;
2470
2471static struct MegasasInfo megasas_devices[] = {
2472 {
2473 .name = TYPE_MEGASAS_GEN1,
2474 .desc = "LSI MegaRAID SAS 1078",
2475 .product_name = "LSI MegaRAID SAS 8708EM2",
2476 .product_version = MEGASAS_VERSION_GEN1,
2477 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2478 .subsystem_id = 0x1013,
2479 .ioport_bar = 2,
2480 .mmio_bar = 0,
2481 .osts = MFI_1078_RM | 1,
2482 .is_express = false,
2483 .vmsd = &vmstate_megasas_gen1,
2484 .props = megasas_properties_gen1,
2485 },{
2486 .name = TYPE_MEGASAS_GEN2,
2487 .desc = "LSI MegaRAID SAS 2108",
2488 .product_name = "LSI MegaRAID SAS 9260-8i",
2489 .product_version = MEGASAS_VERSION_GEN2,
2490 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2491 .subsystem_id = 0x9261,
2492 .ioport_bar = 0,
2493 .mmio_bar = 1,
2494 .osts = MFI_GEN2_RM,
2495 .is_express = true,
2496 .vmsd = &vmstate_megasas_gen2,
2497 .props = megasas_properties_gen2,
2498 }
2499};
2500
e8f943c3
HR		 2501static void megasas_class_init(ObjectClass *oc, void *data)
2502{
2503 DeviceClass *dc = DEVICE_CLASS(oc);
2504 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
e23d0498
HR		 2505 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2506 const MegasasInfo *info = data;
e8f943c3 2507
ae071cc8 2508 pc->realize = megasas_scsi_realize;
e8f943c3
HR		 2509 pc->exit = megasas_scsi_uninit;
2510 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2511 pc->device_id = info->device_id;
e8f943c3 2512 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
e23d0498 2513 pc->subsystem_id = info->subsystem_id;
e8f943c3 2514 pc->class_id = PCI_CLASS_STORAGE_RAID;
e23d0498
HR		 2515 pc->is_express = info->is_express;
2516 e->mmio_bar = info->mmio_bar;
2517 e->ioport_bar = info->ioport_bar;
2518 e->osts = info->osts;
2519 e->product_name = info->product_name;
2520 e->product_version = info->product_version;
2521 dc->props = info->props;
e8f943c3 2522 dc->reset = megasas_scsi_reset;
e23d0498 2523 dc->vmsd = info->vmsd;
125ee0ed 2524 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
e23d0498 2525 dc->desc = info->desc;
e8f943c3
HR		 2526}
2527
2528static const TypeInfo megasas_info = {
e23d0498 2529 .name = TYPE_MEGASAS_BASE,
e8f943c3
HR		 2530 .parent = TYPE_PCI_DEVICE,
2531 .instance_size = sizeof(MegasasState),
e23d0498
HR		 2532 .class_size = sizeof(MegasasBaseClass),
2533 .abstract = true,
e8f943c3
HR		 2534};
2535
2536static void megasas_register_types(void)
2537{
e23d0498
HR		 2538 int i;
2539
e8f943c3 2540 type_register_static(&megasas_info);
e23d0498
HR		 2541 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2542 const MegasasInfo *info = &megasas_devices[i];
2543 TypeInfo type_info = {};
2544
2545 type_info.name = info->name;
2546 type_info.parent = TYPE_MEGASAS_BASE;
2547 type_info.class_data = (void *)info;
2548 type_info.class_init = megasas_class_init;
2549
2550 type_register(&type_info);
2551 }
e8f943c3
HR		 2552}
2553
2554type_init(megasas_register_types)
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