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Commit | Line | Data |
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e8f943c3 HR |
1 | /* |
2 | * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation | |
3 | * Based on the linux driver code at drivers/scsi/megaraid | |
4 | * | |
5 | * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
83c9f4ca PB |
21 | #include "hw/hw.h" |
22 | #include "hw/pci/pci.h" | |
9c17d615 | 23 | #include "sysemu/dma.h" |
4be74634 | 24 | #include "sysemu/block-backend.h" |
4522b69c | 25 | #include "hw/pci/msi.h" |
83c9f4ca | 26 | #include "hw/pci/msix.h" |
1de7afc9 | 27 | #include "qemu/iov.h" |
0d09e41a PB |
28 | #include "hw/scsi/scsi.h" |
29 | #include "block/scsi.h" | |
e8f943c3 HR |
30 | #include "trace.h" |
31 | ||
47b43a1f | 32 | #include "mfi.h" |
e8f943c3 | 33 | |
e23d0498 HR |
34 | #define MEGASAS_VERSION_GEN1 "1.70" |
35 | #define MEGASAS_VERSION_GEN2 "1.80" | |
e8f943c3 HR |
36 | #define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ |
37 | #define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */ | |
e23d0498 | 38 | #define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */ |
e8f943c3 HR |
39 | #define MEGASAS_MAX_SGE 128 /* Firmware limit */ |
40 | #define MEGASAS_DEFAULT_SGE 80 | |
41 | #define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */ | |
42 | #define MEGASAS_MAX_ARRAYS 128 | |
43 | ||
fb654157 | 44 | #define MEGASAS_HBA_SERIAL "QEMU123456" |
76b523db HR |
45 | #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL |
46 | #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400 | |
47 | ||
e8f943c3 HR |
48 | #define MEGASAS_FLAG_USE_JBOD 0 |
49 | #define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD) | |
4522b69c HR |
50 | #define MEGASAS_FLAG_USE_MSI 1 |
51 | #define MEGASAS_MASK_USE_MSI (1 << MEGASAS_FLAG_USE_MSI) | |
52 | #define MEGASAS_FLAG_USE_MSIX 2 | |
e8f943c3 | 53 | #define MEGASAS_MASK_USE_MSIX (1 << MEGASAS_FLAG_USE_MSIX) |
4522b69c | 54 | #define MEGASAS_FLAG_USE_QUEUE64 3 |
e8f943c3 HR |
55 | #define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64) |
56 | ||
a97ad268 | 57 | static const char *mfi_frame_desc[] = { |
e8f943c3 HR |
58 | "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI", |
59 | "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"}; | |
60 | ||
61 | typedef struct MegasasCmd { | |
62 | uint32_t index; | |
63 | uint16_t flags; | |
64 | uint16_t count; | |
65 | uint64_t context; | |
66 | ||
a8170e5e AK |
67 | hwaddr pa; |
68 | hwaddr pa_size; | |
e8f943c3 HR |
69 | union mfi_frame *frame; |
70 | SCSIRequest *req; | |
71 | QEMUSGList qsg; | |
72 | void *iov_buf; | |
73 | size_t iov_size; | |
74 | size_t iov_offset; | |
75 | struct MegasasState *state; | |
76 | } MegasasCmd; | |
77 | ||
78 | typedef struct MegasasState { | |
52190c1e AF |
79 | /*< private >*/ |
80 | PCIDevice parent_obj; | |
81 | /*< public >*/ | |
82 | ||
e8f943c3 HR |
83 | MemoryRegion mmio_io; |
84 | MemoryRegion port_io; | |
85 | MemoryRegion queue_io; | |
86 | uint32_t frame_hi; | |
87 | ||
88 | int fw_state; | |
89 | uint32_t fw_sge; | |
90 | uint32_t fw_cmds; | |
91 | uint32_t flags; | |
92 | int fw_luns; | |
93 | int intr_mask; | |
94 | int doorbell; | |
95 | int busy; | |
e23d0498 HR |
96 | int diag; |
97 | int adp_reset; | |
e8f943c3 HR |
98 | |
99 | MegasasCmd *event_cmd; | |
100 | int event_locale; | |
101 | int event_class; | |
102 | int event_count; | |
103 | int shutdown_event; | |
104 | int boot_event; | |
105 | ||
76b523db | 106 | uint64_t sas_addr; |
fb654157 | 107 | char *hba_serial; |
76b523db | 108 | |
e8f943c3 HR |
109 | uint64_t reply_queue_pa; |
110 | void *reply_queue; | |
111 | int reply_queue_len; | |
112 | int reply_queue_head; | |
113 | int reply_queue_tail; | |
114 | uint64_t consumer_pa; | |
115 | uint64_t producer_pa; | |
116 | ||
117 | MegasasCmd frames[MEGASAS_MAX_FRAMES]; | |
118 | ||
119 | SCSIBus bus; | |
120 | } MegasasState; | |
121 | ||
e23d0498 HR |
122 | typedef struct MegasasBaseClass { |
123 | PCIDeviceClass parent_class; | |
124 | const char *product_name; | |
125 | const char *product_version; | |
126 | int mmio_bar; | |
127 | int ioport_bar; | |
128 | int osts; | |
129 | } MegasasBaseClass; | |
130 | ||
131 | #define TYPE_MEGASAS_BASE "megasas-base" | |
132 | #define TYPE_MEGASAS_GEN1 "megasas" | |
133 | #define TYPE_MEGASAS_GEN2 "megasas-gen2" | |
c79e16ae PC |
134 | |
135 | #define MEGASAS(obj) \ | |
e23d0498 HR |
136 | OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE) |
137 | ||
138 | #define MEGASAS_DEVICE_CLASS(oc) \ | |
139 | OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE) | |
140 | #define MEGASAS_DEVICE_GET_CLASS(oc) \ | |
141 | OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE) | |
c79e16ae | 142 | |
e8f943c3 HR |
143 | #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF |
144 | ||
145 | static bool megasas_intr_enabled(MegasasState *s) | |
146 | { | |
147 | if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) != | |
148 | MEGASAS_INTR_DISABLED_MASK) { | |
149 | return true; | |
150 | } | |
151 | return false; | |
152 | } | |
153 | ||
154 | static bool megasas_use_queue64(MegasasState *s) | |
155 | { | |
156 | return s->flags & MEGASAS_MASK_USE_QUEUE64; | |
157 | } | |
158 | ||
4522b69c HR |
159 | static bool megasas_use_msi(MegasasState *s) |
160 | { | |
161 | return s->flags & MEGASAS_MASK_USE_MSI; | |
162 | } | |
163 | ||
e8f943c3 HR |
164 | static bool megasas_use_msix(MegasasState *s) |
165 | { | |
166 | return s->flags & MEGASAS_MASK_USE_MSIX; | |
167 | } | |
168 | ||
169 | static bool megasas_is_jbod(MegasasState *s) | |
170 | { | |
171 | return s->flags & MEGASAS_MASK_USE_JBOD; | |
172 | } | |
173 | ||
174 | static void megasas_frame_set_cmd_status(unsigned long frame, uint8_t v) | |
175 | { | |
db3be60d EI |
176 | stb_phys(&address_space_memory, |
177 | frame + offsetof(struct mfi_frame_header, cmd_status), v); | |
e8f943c3 HR |
178 | } |
179 | ||
180 | static void megasas_frame_set_scsi_status(unsigned long frame, uint8_t v) | |
181 | { | |
db3be60d EI |
182 | stb_phys(&address_space_memory, |
183 | frame + offsetof(struct mfi_frame_header, scsi_status), v); | |
e8f943c3 HR |
184 | } |
185 | ||
186 | /* | |
187 | * Context is considered opaque, but the HBA firmware is running | |
188 | * in little endian mode. So convert it to little endian, too. | |
189 | */ | |
190 | static uint64_t megasas_frame_get_context(unsigned long frame) | |
191 | { | |
2c17449b EI |
192 | return ldq_le_phys(&address_space_memory, |
193 | frame + offsetof(struct mfi_frame_header, context)); | |
e8f943c3 HR |
194 | } |
195 | ||
196 | static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd) | |
197 | { | |
198 | return cmd->flags & MFI_FRAME_IEEE_SGL; | |
199 | } | |
200 | ||
201 | static bool megasas_frame_is_sgl64(MegasasCmd *cmd) | |
202 | { | |
203 | return cmd->flags & MFI_FRAME_SGL64; | |
204 | } | |
205 | ||
206 | static bool megasas_frame_is_sense64(MegasasCmd *cmd) | |
207 | { | |
208 | return cmd->flags & MFI_FRAME_SENSE64; | |
209 | } | |
210 | ||
211 | static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd, | |
212 | union mfi_sgl *sgl) | |
213 | { | |
214 | uint64_t addr; | |
215 | ||
216 | if (megasas_frame_is_ieee_sgl(cmd)) { | |
217 | addr = le64_to_cpu(sgl->sg_skinny->addr); | |
218 | } else if (megasas_frame_is_sgl64(cmd)) { | |
219 | addr = le64_to_cpu(sgl->sg64->addr); | |
220 | } else { | |
221 | addr = le32_to_cpu(sgl->sg32->addr); | |
222 | } | |
223 | return addr; | |
224 | } | |
225 | ||
226 | static uint32_t megasas_sgl_get_len(MegasasCmd *cmd, | |
227 | union mfi_sgl *sgl) | |
228 | { | |
229 | uint32_t len; | |
230 | ||
231 | if (megasas_frame_is_ieee_sgl(cmd)) { | |
232 | len = le32_to_cpu(sgl->sg_skinny->len); | |
233 | } else if (megasas_frame_is_sgl64(cmd)) { | |
234 | len = le32_to_cpu(sgl->sg64->len); | |
235 | } else { | |
236 | len = le32_to_cpu(sgl->sg32->len); | |
237 | } | |
238 | return len; | |
239 | } | |
240 | ||
241 | static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd, | |
242 | union mfi_sgl *sgl) | |
243 | { | |
244 | uint8_t *next = (uint8_t *)sgl; | |
245 | ||
246 | if (megasas_frame_is_ieee_sgl(cmd)) { | |
247 | next += sizeof(struct mfi_sg_skinny); | |
248 | } else if (megasas_frame_is_sgl64(cmd)) { | |
249 | next += sizeof(struct mfi_sg64); | |
250 | } else { | |
251 | next += sizeof(struct mfi_sg32); | |
252 | } | |
253 | ||
254 | if (next >= (uint8_t *)cmd->frame + cmd->pa_size) { | |
255 | return NULL; | |
256 | } | |
257 | return (union mfi_sgl *)next; | |
258 | } | |
259 | ||
260 | static void megasas_soft_reset(MegasasState *s); | |
261 | ||
262 | static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl) | |
263 | { | |
264 | int i; | |
265 | int iov_count = 0; | |
266 | size_t iov_size = 0; | |
267 | ||
268 | cmd->flags = le16_to_cpu(cmd->frame->header.flags); | |
269 | iov_count = cmd->frame->header.sge_count; | |
270 | if (iov_count > MEGASAS_MAX_SGE) { | |
271 | trace_megasas_iovec_sgl_overflow(cmd->index, iov_count, | |
272 | MEGASAS_MAX_SGE); | |
273 | return iov_count; | |
274 | } | |
52190c1e | 275 | pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count); |
e8f943c3 HR |
276 | for (i = 0; i < iov_count; i++) { |
277 | dma_addr_t iov_pa, iov_size_p; | |
278 | ||
279 | if (!sgl) { | |
280 | trace_megasas_iovec_sgl_underflow(cmd->index, i); | |
281 | goto unmap; | |
282 | } | |
283 | iov_pa = megasas_sgl_get_addr(cmd, sgl); | |
284 | iov_size_p = megasas_sgl_get_len(cmd, sgl); | |
285 | if (!iov_pa || !iov_size_p) { | |
286 | trace_megasas_iovec_sgl_invalid(cmd->index, i, | |
287 | iov_pa, iov_size_p); | |
288 | goto unmap; | |
289 | } | |
290 | qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p); | |
291 | sgl = megasas_sgl_next(cmd, sgl); | |
292 | iov_size += (size_t)iov_size_p; | |
293 | } | |
294 | if (cmd->iov_size > iov_size) { | |
295 | trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size); | |
296 | } else if (cmd->iov_size < iov_size) { | |
297 | trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size); | |
298 | } | |
299 | cmd->iov_offset = 0; | |
300 | return 0; | |
301 | unmap: | |
302 | qemu_sglist_destroy(&cmd->qsg); | |
303 | return iov_count - i; | |
304 | } | |
305 | ||
306 | static void megasas_unmap_sgl(MegasasCmd *cmd) | |
307 | { | |
308 | qemu_sglist_destroy(&cmd->qsg); | |
309 | cmd->iov_offset = 0; | |
310 | } | |
311 | ||
312 | /* | |
313 | * passthrough sense and io sense are at the same offset | |
314 | */ | |
315 | static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr, | |
316 | uint8_t sense_len) | |
317 | { | |
1016b239 | 318 | PCIDevice *pcid = PCI_DEVICE(cmd->state); |
e8f943c3 | 319 | uint32_t pa_hi = 0, pa_lo; |
a8170e5e | 320 | hwaddr pa; |
e8f943c3 HR |
321 | |
322 | if (sense_len > cmd->frame->header.sense_len) { | |
323 | sense_len = cmd->frame->header.sense_len; | |
324 | } | |
325 | if (sense_len) { | |
326 | pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo); | |
327 | if (megasas_frame_is_sense64(cmd)) { | |
328 | pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi); | |
329 | } | |
330 | pa = ((uint64_t) pa_hi << 32) | pa_lo; | |
1016b239 | 331 | pci_dma_write(pcid, pa, sense_ptr, sense_len); |
e8f943c3 HR |
332 | cmd->frame->header.sense_len = sense_len; |
333 | } | |
334 | return sense_len; | |
335 | } | |
336 | ||
337 | static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense) | |
338 | { | |
339 | uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; | |
340 | uint8_t sense_len = 18; | |
341 | ||
342 | memset(sense_buf, 0, sense_len); | |
343 | sense_buf[0] = 0xf0; | |
344 | sense_buf[2] = sense.key; | |
345 | sense_buf[7] = 10; | |
346 | sense_buf[12] = sense.asc; | |
347 | sense_buf[13] = sense.ascq; | |
348 | megasas_build_sense(cmd, sense_buf, sense_len); | |
349 | } | |
350 | ||
351 | static void megasas_copy_sense(MegasasCmd *cmd) | |
352 | { | |
353 | uint8_t sense_buf[SCSI_SENSE_BUF_SIZE]; | |
354 | uint8_t sense_len; | |
355 | ||
356 | sense_len = scsi_req_get_sense(cmd->req, sense_buf, | |
357 | SCSI_SENSE_BUF_SIZE); | |
358 | megasas_build_sense(cmd, sense_buf, sense_len); | |
359 | } | |
360 | ||
361 | /* | |
362 | * Format an INQUIRY CDB | |
363 | */ | |
364 | static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len) | |
365 | { | |
366 | memset(cdb, 0, 6); | |
367 | cdb[0] = INQUIRY; | |
368 | if (pg > 0) { | |
369 | cdb[1] = 0x1; | |
370 | cdb[2] = pg; | |
371 | } | |
372 | cdb[3] = (len >> 8) & 0xff; | |
373 | cdb[4] = (len & 0xff); | |
374 | return len; | |
375 | } | |
376 | ||
377 | /* | |
378 | * Encode lba and len into a READ_16/WRITE_16 CDB | |
379 | */ | |
380 | static void megasas_encode_lba(uint8_t *cdb, uint64_t lba, | |
381 | uint32_t len, bool is_write) | |
382 | { | |
383 | memset(cdb, 0x0, 16); | |
384 | if (is_write) { | |
385 | cdb[0] = WRITE_16; | |
386 | } else { | |
387 | cdb[0] = READ_16; | |
388 | } | |
389 | cdb[2] = (lba >> 56) & 0xff; | |
390 | cdb[3] = (lba >> 48) & 0xff; | |
391 | cdb[4] = (lba >> 40) & 0xff; | |
392 | cdb[5] = (lba >> 32) & 0xff; | |
393 | cdb[6] = (lba >> 24) & 0xff; | |
394 | cdb[7] = (lba >> 16) & 0xff; | |
395 | cdb[8] = (lba >> 8) & 0xff; | |
396 | cdb[9] = (lba) & 0xff; | |
397 | cdb[10] = (len >> 24) & 0xff; | |
398 | cdb[11] = (len >> 16) & 0xff; | |
399 | cdb[12] = (len >> 8) & 0xff; | |
400 | cdb[13] = (len) & 0xff; | |
401 | } | |
402 | ||
403 | /* | |
404 | * Utility functions | |
405 | */ | |
406 | static uint64_t megasas_fw_time(void) | |
407 | { | |
408 | struct tm curtime; | |
409 | uint64_t bcd_time; | |
410 | ||
411 | qemu_get_timedate(&curtime, 0); | |
412 | bcd_time = ((uint64_t)curtime.tm_sec & 0xff) << 48 | | |
413 | ((uint64_t)curtime.tm_min & 0xff) << 40 | | |
414 | ((uint64_t)curtime.tm_hour & 0xff) << 32 | | |
415 | ((uint64_t)curtime.tm_mday & 0xff) << 24 | | |
416 | ((uint64_t)curtime.tm_mon & 0xff) << 16 | | |
417 | ((uint64_t)(curtime.tm_year + 1900) & 0xffff); | |
418 | ||
419 | return bcd_time; | |
420 | } | |
421 | ||
76b523db HR |
422 | /* |
423 | * Default disk sata address | |
424 | * 0x1221 is the magic number as | |
425 | * present in real hardware, | |
426 | * so use it here, too. | |
427 | */ | |
428 | static uint64_t megasas_get_sata_addr(uint16_t id) | |
e8f943c3 | 429 | { |
76b523db HR |
430 | uint64_t addr = (0x1221ULL << 48); |
431 | return addr & (id << 24); | |
e8f943c3 HR |
432 | } |
433 | ||
434 | /* | |
435 | * Frame handling | |
436 | */ | |
437 | static int megasas_next_index(MegasasState *s, int index, int limit) | |
438 | { | |
439 | index++; | |
440 | if (index == limit) { | |
441 | index = 0; | |
442 | } | |
443 | return index; | |
444 | } | |
445 | ||
446 | static MegasasCmd *megasas_lookup_frame(MegasasState *s, | |
a8170e5e | 447 | hwaddr frame) |
e8f943c3 HR |
448 | { |
449 | MegasasCmd *cmd = NULL; | |
450 | int num = 0, index; | |
451 | ||
452 | index = s->reply_queue_head; | |
453 | ||
454 | while (num < s->fw_cmds) { | |
455 | if (s->frames[index].pa && s->frames[index].pa == frame) { | |
456 | cmd = &s->frames[index]; | |
457 | break; | |
458 | } | |
459 | index = megasas_next_index(s, index, s->fw_cmds); | |
460 | num++; | |
461 | } | |
462 | ||
463 | return cmd; | |
464 | } | |
465 | ||
466 | static MegasasCmd *megasas_next_frame(MegasasState *s, | |
a8170e5e | 467 | hwaddr frame) |
e8f943c3 HR |
468 | { |
469 | MegasasCmd *cmd = NULL; | |
470 | int num = 0, index; | |
471 | ||
472 | cmd = megasas_lookup_frame(s, frame); | |
473 | if (cmd) { | |
474 | trace_megasas_qf_found(cmd->index, cmd->pa); | |
475 | return cmd; | |
476 | } | |
477 | index = s->reply_queue_head; | |
478 | num = 0; | |
479 | while (num < s->fw_cmds) { | |
480 | if (!s->frames[index].pa) { | |
481 | cmd = &s->frames[index]; | |
482 | break; | |
483 | } | |
484 | index = megasas_next_index(s, index, s->fw_cmds); | |
485 | num++; | |
486 | } | |
487 | if (!cmd) { | |
488 | trace_megasas_qf_failed(frame); | |
489 | } | |
490 | trace_megasas_qf_new(index, cmd); | |
491 | return cmd; | |
492 | } | |
493 | ||
494 | static MegasasCmd *megasas_enqueue_frame(MegasasState *s, | |
a8170e5e | 495 | hwaddr frame, uint64_t context, int count) |
e8f943c3 | 496 | { |
1016b239 | 497 | PCIDevice *pcid = PCI_DEVICE(s); |
e8f943c3 HR |
498 | MegasasCmd *cmd = NULL; |
499 | int frame_size = MFI_FRAME_SIZE * 16; | |
a8170e5e | 500 | hwaddr frame_size_p = frame_size; |
e8f943c3 HR |
501 | |
502 | cmd = megasas_next_frame(s, frame); | |
503 | /* All frames busy */ | |
504 | if (!cmd) { | |
505 | return NULL; | |
506 | } | |
507 | if (!cmd->pa) { | |
508 | cmd->pa = frame; | |
509 | /* Map all possible frames */ | |
1016b239 | 510 | cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0); |
e8f943c3 HR |
511 | if (frame_size_p != frame_size) { |
512 | trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame); | |
513 | if (cmd->frame) { | |
1016b239 | 514 | pci_dma_unmap(pcid, cmd->frame, frame_size_p, 0, 0); |
e8f943c3 HR |
515 | cmd->frame = NULL; |
516 | cmd->pa = 0; | |
517 | } | |
518 | s->event_count++; | |
519 | return NULL; | |
520 | } | |
521 | cmd->pa_size = frame_size_p; | |
522 | cmd->context = context; | |
523 | if (!megasas_use_queue64(s)) { | |
524 | cmd->context &= (uint64_t)0xFFFFFFFF; | |
525 | } | |
526 | } | |
527 | cmd->count = count; | |
528 | s->busy++; | |
529 | ||
530 | trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context, | |
531 | s->reply_queue_head, s->busy); | |
532 | ||
533 | return cmd; | |
534 | } | |
535 | ||
536 | static void megasas_complete_frame(MegasasState *s, uint64_t context) | |
537 | { | |
52190c1e | 538 | PCIDevice *pci_dev = PCI_DEVICE(s); |
e8f943c3 HR |
539 | int tail, queue_offset; |
540 | ||
541 | /* Decrement busy count */ | |
542 | s->busy--; | |
543 | ||
544 | if (s->reply_queue_pa) { | |
545 | /* | |
546 | * Put command on the reply queue. | |
547 | * Context is opaque, but emulation is running in | |
548 | * little endian. So convert it. | |
549 | */ | |
550 | tail = s->reply_queue_head; | |
551 | if (megasas_use_queue64(s)) { | |
552 | queue_offset = tail * sizeof(uint64_t); | |
f606604f EI |
553 | stq_le_phys(&address_space_memory, |
554 | s->reply_queue_pa + queue_offset, context); | |
e8f943c3 HR |
555 | } else { |
556 | queue_offset = tail * sizeof(uint32_t); | |
ab1da857 EI |
557 | stl_le_phys(&address_space_memory, |
558 | s->reply_queue_pa + queue_offset, context); | |
e8f943c3 HR |
559 | } |
560 | s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds); | |
561 | trace_megasas_qf_complete(context, tail, queue_offset, | |
562 | s->busy, s->doorbell); | |
563 | } | |
564 | ||
565 | if (megasas_intr_enabled(s)) { | |
566 | /* Notify HBA */ | |
567 | s->doorbell++; | |
568 | if (s->doorbell == 1) { | |
52190c1e | 569 | if (msix_enabled(pci_dev)) { |
e8f943c3 | 570 | trace_megasas_msix_raise(0); |
52190c1e | 571 | msix_notify(pci_dev, 0); |
4522b69c HR |
572 | } else if (msi_enabled(pci_dev)) { |
573 | trace_megasas_msi_raise(0); | |
574 | msi_notify(pci_dev, 0); | |
e8f943c3 HR |
575 | } else { |
576 | trace_megasas_irq_raise(); | |
9e64f8a3 | 577 | pci_irq_assert(pci_dev); |
e8f943c3 HR |
578 | } |
579 | } | |
580 | } else { | |
581 | trace_megasas_qf_complete_noirq(context); | |
582 | } | |
583 | } | |
584 | ||
585 | static void megasas_reset_frames(MegasasState *s) | |
586 | { | |
1016b239 | 587 | PCIDevice *pcid = PCI_DEVICE(s); |
e8f943c3 HR |
588 | int i; |
589 | MegasasCmd *cmd; | |
590 | ||
591 | for (i = 0; i < s->fw_cmds; i++) { | |
592 | cmd = &s->frames[i]; | |
593 | if (cmd->pa) { | |
1016b239 | 594 | pci_dma_unmap(pcid, cmd->frame, cmd->pa_size, 0, 0); |
e8f943c3 HR |
595 | cmd->frame = NULL; |
596 | cmd->pa = 0; | |
597 | } | |
598 | } | |
599 | } | |
600 | ||
601 | static void megasas_abort_command(MegasasCmd *cmd) | |
602 | { | |
603 | if (cmd->req) { | |
e2b06058 | 604 | scsi_req_cancel(cmd->req); |
e8f943c3 HR |
605 | cmd->req = NULL; |
606 | } | |
607 | } | |
608 | ||
609 | static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd) | |
610 | { | |
1016b239 | 611 | PCIDevice *pcid = PCI_DEVICE(s); |
e8f943c3 | 612 | uint32_t pa_hi, pa_lo; |
a8170e5e | 613 | hwaddr iq_pa, initq_size; |
e8f943c3 HR |
614 | struct mfi_init_qinfo *initq; |
615 | uint32_t flags; | |
616 | int ret = MFI_STAT_OK; | |
617 | ||
618 | pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo); | |
619 | pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi); | |
620 | iq_pa = (((uint64_t) pa_hi << 32) | pa_lo); | |
621 | trace_megasas_init_firmware((uint64_t)iq_pa); | |
622 | initq_size = sizeof(*initq); | |
1016b239 | 623 | initq = pci_dma_map(pcid, iq_pa, &initq_size, 0); |
e8f943c3 HR |
624 | if (!initq || initq_size != sizeof(*initq)) { |
625 | trace_megasas_initq_map_failed(cmd->index); | |
626 | s->event_count++; | |
627 | ret = MFI_STAT_MEMORY_NOT_AVAILABLE; | |
628 | goto out; | |
629 | } | |
630 | s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF; | |
631 | if (s->reply_queue_len > s->fw_cmds) { | |
632 | trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds); | |
633 | s->event_count++; | |
634 | ret = MFI_STAT_INVALID_PARAMETER; | |
635 | goto out; | |
636 | } | |
637 | pa_lo = le32_to_cpu(initq->rq_addr_lo); | |
638 | pa_hi = le32_to_cpu(initq->rq_addr_hi); | |
639 | s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo; | |
640 | pa_lo = le32_to_cpu(initq->ci_addr_lo); | |
641 | pa_hi = le32_to_cpu(initq->ci_addr_hi); | |
642 | s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo; | |
643 | pa_lo = le32_to_cpu(initq->pi_addr_lo); | |
644 | pa_hi = le32_to_cpu(initq->pi_addr_hi); | |
645 | s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo; | |
fdfba1a2 EI |
646 | s->reply_queue_head = ldl_le_phys(&address_space_memory, s->producer_pa); |
647 | s->reply_queue_tail = ldl_le_phys(&address_space_memory, s->consumer_pa); | |
e8f943c3 HR |
648 | flags = le32_to_cpu(initq->flags); |
649 | if (flags & MFI_QUEUE_FLAG_CONTEXT64) { | |
650 | s->flags |= MEGASAS_MASK_USE_QUEUE64; | |
651 | } | |
652 | trace_megasas_init_queue((unsigned long)s->reply_queue_pa, | |
653 | s->reply_queue_len, s->reply_queue_head, | |
654 | s->reply_queue_tail, flags); | |
655 | megasas_reset_frames(s); | |
656 | s->fw_state = MFI_FWSTATE_OPERATIONAL; | |
657 | out: | |
658 | if (initq) { | |
1016b239 | 659 | pci_dma_unmap(pcid, initq, initq_size, 0, 0); |
e8f943c3 HR |
660 | } |
661 | return ret; | |
662 | } | |
663 | ||
664 | static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd) | |
665 | { | |
666 | dma_addr_t iov_pa, iov_size; | |
667 | ||
668 | cmd->flags = le16_to_cpu(cmd->frame->header.flags); | |
669 | if (!cmd->frame->header.sge_count) { | |
670 | trace_megasas_dcmd_zero_sge(cmd->index); | |
671 | cmd->iov_size = 0; | |
672 | return 0; | |
673 | } else if (cmd->frame->header.sge_count > 1) { | |
674 | trace_megasas_dcmd_invalid_sge(cmd->index, | |
675 | cmd->frame->header.sge_count); | |
676 | cmd->iov_size = 0; | |
677 | return -1; | |
678 | } | |
679 | iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl); | |
680 | iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl); | |
52190c1e | 681 | pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1); |
e8f943c3 HR |
682 | qemu_sglist_add(&cmd->qsg, iov_pa, iov_size); |
683 | cmd->iov_size = iov_size; | |
684 | return cmd->iov_size; | |
685 | } | |
686 | ||
687 | static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size) | |
688 | { | |
689 | trace_megasas_finish_dcmd(cmd->index, iov_size); | |
690 | ||
691 | if (cmd->frame->header.sge_count) { | |
692 | qemu_sglist_destroy(&cmd->qsg); | |
693 | } | |
694 | if (iov_size > cmd->iov_size) { | |
695 | if (megasas_frame_is_ieee_sgl(cmd)) { | |
696 | cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size); | |
697 | } else if (megasas_frame_is_sgl64(cmd)) { | |
698 | cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size); | |
699 | } else { | |
700 | cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size); | |
701 | } | |
702 | } | |
703 | cmd->iov_size = 0; | |
e8f943c3 HR |
704 | } |
705 | ||
706 | static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd) | |
707 | { | |
52190c1e | 708 | PCIDevice *pci_dev = PCI_DEVICE(s); |
e23d0498 HR |
709 | PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev); |
710 | MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s); | |
e8f943c3 HR |
711 | struct mfi_ctrl_info info; |
712 | size_t dcmd_size = sizeof(info); | |
713 | BusChild *kid; | |
3f2cd4dd | 714 | int num_pd_disks = 0; |
e8f943c3 HR |
715 | |
716 | memset(&info, 0x0, cmd->iov_size); | |
717 | if (cmd->iov_size < dcmd_size) { | |
718 | trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, | |
719 | dcmd_size); | |
720 | return MFI_STAT_INVALID_PARAMETER; | |
721 | } | |
722 | ||
e23d0498 HR |
723 | info.pci.vendor = cpu_to_le16(pci_class->vendor_id); |
724 | info.pci.device = cpu_to_le16(pci_class->device_id); | |
725 | info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id); | |
726 | info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id); | |
e8f943c3 | 727 | |
76b523db HR |
728 | /* |
729 | * For some reason the firmware supports | |
730 | * only up to 8 device ports. | |
731 | * Despite supporting a far larger number | |
732 | * of devices for the physical devices. | |
733 | * So just display the first 8 devices | |
734 | * in the device port list, independent | |
735 | * of how many logical devices are actually | |
736 | * present. | |
737 | */ | |
738 | info.host.type = MFI_INFO_HOST_PCIE; | |
e8f943c3 | 739 | info.device.type = MFI_INFO_DEV_SAS3G; |
76b523db HR |
740 | info.device.port_count = 8; |
741 | QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { | |
742 | SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); | |
3f2cd4dd | 743 | uint16_t pd_id; |
76b523db | 744 | |
3f2cd4dd HR |
745 | if (num_pd_disks < 8) { |
746 | pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF); | |
747 | info.device.port_addr[num_pd_disks] = | |
748 | cpu_to_le64(megasas_get_sata_addr(pd_id)); | |
76b523db | 749 | } |
3f2cd4dd | 750 | num_pd_disks++; |
76b523db | 751 | } |
e8f943c3 | 752 | |
e23d0498 | 753 | memcpy(info.product_name, base_class->product_name, 24); |
fb654157 | 754 | snprintf(info.serial_number, 32, "%s", s->hba_serial); |
e8f943c3 HR |
755 | snprintf(info.package_version, 0x60, "%s-QEMU", QEMU_VERSION); |
756 | memcpy(info.image_component[0].name, "APP", 3); | |
e23d0498 HR |
757 | snprintf(info.image_component[0].version, 10, "%s-QEMU", |
758 | base_class->product_version); | |
5a7733b0 OH |
759 | memcpy(info.image_component[0].build_date, "Apr 1 2014", 11); |
760 | memcpy(info.image_component[0].build_time, "12:34:56", 8); | |
e8f943c3 | 761 | info.image_component_count = 1; |
52190c1e | 762 | if (pci_dev->has_rom) { |
e8f943c3 HR |
763 | uint8_t biosver[32]; |
764 | uint8_t *ptr; | |
765 | ||
52190c1e | 766 | ptr = memory_region_get_ram_ptr(&pci_dev->rom); |
e8f943c3 | 767 | memcpy(biosver, ptr + 0x41, 31); |
e8f943c3 HR |
768 | memcpy(info.image_component[1].name, "BIOS", 4); |
769 | memcpy(info.image_component[1].version, biosver, | |
770 | strlen((const char *)biosver)); | |
771 | info.image_component_count++; | |
772 | } | |
773 | info.current_fw_time = cpu_to_le32(megasas_fw_time()); | |
774 | info.max_arms = 32; | |
775 | info.max_spans = 8; | |
776 | info.max_arrays = MEGASAS_MAX_ARRAYS; | |
3f2cd4dd | 777 | info.max_lds = MFI_MAX_LD; |
e8f943c3 HR |
778 | info.max_cmds = cpu_to_le16(s->fw_cmds); |
779 | info.max_sg_elements = cpu_to_le16(s->fw_sge); | |
780 | info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS); | |
3f2cd4dd HR |
781 | if (!megasas_is_jbod(s)) |
782 | info.lds_present = cpu_to_le16(num_pd_disks); | |
783 | info.pd_present = cpu_to_le16(num_pd_disks); | |
784 | info.pd_disks_present = cpu_to_le16(num_pd_disks); | |
e8f943c3 HR |
785 | info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM | |
786 | MFI_INFO_HW_MEM | | |
787 | MFI_INFO_HW_FLASH); | |
788 | info.memory_size = cpu_to_le16(512); | |
789 | info.nvram_size = cpu_to_le16(32); | |
790 | info.flash_size = cpu_to_le16(16); | |
791 | info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0); | |
792 | info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE | | |
793 | MFI_INFO_AOPS_SELF_DIAGNOSTIC | | |
794 | MFI_INFO_AOPS_MIXED_ARRAY); | |
795 | info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY | | |
796 | MFI_INFO_LDOPS_ACCESS_POLICY | | |
797 | MFI_INFO_LDOPS_IO_POLICY | | |
798 | MFI_INFO_LDOPS_WRITE_POLICY | | |
799 | MFI_INFO_LDOPS_READ_POLICY); | |
800 | info.max_strips_per_io = cpu_to_le16(s->fw_sge); | |
801 | info.stripe_sz_ops.min = 3; | |
802 | info.stripe_sz_ops.max = ffs(MEGASAS_MAX_SECTORS + 1) - 1; | |
803 | info.properties.pred_fail_poll_interval = cpu_to_le16(300); | |
804 | info.properties.intr_throttle_cnt = cpu_to_le16(16); | |
805 | info.properties.intr_throttle_timeout = cpu_to_le16(50); | |
806 | info.properties.rebuild_rate = 30; | |
807 | info.properties.patrol_read_rate = 30; | |
808 | info.properties.bgi_rate = 30; | |
809 | info.properties.cc_rate = 30; | |
810 | info.properties.recon_rate = 30; | |
811 | info.properties.cache_flush_interval = 4; | |
812 | info.properties.spinup_drv_cnt = 2; | |
813 | info.properties.spinup_delay = 6; | |
814 | info.properties.ecc_bucket_size = 15; | |
815 | info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440); | |
816 | info.properties.expose_encl_devices = 1; | |
817 | info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD); | |
818 | info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE | | |
819 | MFI_INFO_PDOPS_FORCE_OFFLINE); | |
820 | info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS | | |
821 | MFI_INFO_PDMIX_SATA | | |
822 | MFI_INFO_PDMIX_LD); | |
823 | ||
824 | cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); | |
825 | return MFI_STAT_OK; | |
826 | } | |
827 | ||
828 | static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd) | |
829 | { | |
830 | struct mfi_defaults info; | |
831 | size_t dcmd_size = sizeof(struct mfi_defaults); | |
832 | ||
833 | memset(&info, 0x0, dcmd_size); | |
834 | if (cmd->iov_size < dcmd_size) { | |
835 | trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, | |
836 | dcmd_size); | |
837 | return MFI_STAT_INVALID_PARAMETER; | |
838 | } | |
839 | ||
76b523db | 840 | info.sas_addr = cpu_to_le64(s->sas_addr); |
e8f943c3 HR |
841 | info.stripe_size = 3; |
842 | info.flush_time = 4; | |
843 | info.background_rate = 30; | |
844 | info.allow_mix_in_enclosure = 1; | |
845 | info.allow_mix_in_ld = 1; | |
846 | info.direct_pd_mapping = 1; | |
847 | /* Enable for BIOS support */ | |
848 | info.bios_enumerate_lds = 1; | |
849 | info.disable_ctrl_r = 1; | |
850 | info.expose_enclosure_devices = 1; | |
851 | info.disable_preboot_cli = 1; | |
852 | info.cluster_disable = 1; | |
853 | ||
854 | cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); | |
855 | return MFI_STAT_OK; | |
856 | } | |
857 | ||
858 | static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd) | |
859 | { | |
860 | struct mfi_bios_data info; | |
861 | size_t dcmd_size = sizeof(info); | |
862 | ||
863 | memset(&info, 0x0, dcmd_size); | |
864 | if (cmd->iov_size < dcmd_size) { | |
865 | trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, | |
866 | dcmd_size); | |
867 | return MFI_STAT_INVALID_PARAMETER; | |
868 | } | |
869 | info.continue_on_error = 1; | |
870 | info.verbose = 1; | |
871 | if (megasas_is_jbod(s)) { | |
872 | info.expose_all_drives = 1; | |
873 | } | |
874 | ||
875 | cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); | |
876 | return MFI_STAT_OK; | |
877 | } | |
878 | ||
879 | static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd) | |
880 | { | |
881 | uint64_t fw_time; | |
882 | size_t dcmd_size = sizeof(fw_time); | |
883 | ||
884 | fw_time = cpu_to_le64(megasas_fw_time()); | |
885 | ||
886 | cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg); | |
887 | return MFI_STAT_OK; | |
888 | } | |
889 | ||
890 | static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd) | |
891 | { | |
892 | uint64_t fw_time; | |
893 | ||
894 | /* This is a dummy; setting of firmware time is not allowed */ | |
895 | memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time)); | |
896 | ||
897 | trace_megasas_dcmd_set_fw_time(cmd->index, fw_time); | |
898 | fw_time = cpu_to_le64(megasas_fw_time()); | |
899 | return MFI_STAT_OK; | |
900 | } | |
901 | ||
902 | static int megasas_event_info(MegasasState *s, MegasasCmd *cmd) | |
903 | { | |
904 | struct mfi_evt_log_state info; | |
905 | size_t dcmd_size = sizeof(info); | |
906 | ||
907 | memset(&info, 0, dcmd_size); | |
908 | ||
909 | info.newest_seq_num = cpu_to_le32(s->event_count); | |
910 | info.shutdown_seq_num = cpu_to_le32(s->shutdown_event); | |
911 | info.boot_seq_num = cpu_to_le32(s->boot_event); | |
912 | ||
913 | cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); | |
914 | return MFI_STAT_OK; | |
915 | } | |
916 | ||
917 | static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd) | |
918 | { | |
919 | union mfi_evt event; | |
920 | ||
921 | if (cmd->iov_size < sizeof(struct mfi_evt_detail)) { | |
922 | trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, | |
923 | sizeof(struct mfi_evt_detail)); | |
924 | return MFI_STAT_INVALID_PARAMETER; | |
925 | } | |
926 | s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]); | |
927 | event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]); | |
928 | s->event_locale = event.members.locale; | |
929 | s->event_class = event.members.class; | |
930 | s->event_cmd = cmd; | |
931 | /* Decrease busy count; event frame doesn't count here */ | |
932 | s->busy--; | |
933 | cmd->iov_size = sizeof(struct mfi_evt_detail); | |
934 | return MFI_STAT_INVALID_STATUS; | |
935 | } | |
936 | ||
937 | static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd) | |
938 | { | |
939 | struct mfi_pd_list info; | |
940 | size_t dcmd_size = sizeof(info); | |
941 | BusChild *kid; | |
942 | uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks; | |
e8f943c3 HR |
943 | |
944 | memset(&info, 0, dcmd_size); | |
945 | offset = 8; | |
946 | dcmd_limit = offset + sizeof(struct mfi_pd_address); | |
947 | if (cmd->iov_size < dcmd_limit) { | |
948 | trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, | |
949 | dcmd_limit); | |
950 | return MFI_STAT_INVALID_PARAMETER; | |
951 | } | |
952 | ||
953 | max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address); | |
3f2cd4dd HR |
954 | if (max_pd_disks > MFI_MAX_SYS_PDS) { |
955 | max_pd_disks = MFI_MAX_SYS_PDS; | |
e8f943c3 | 956 | } |
e8f943c3 HR |
957 | QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { |
958 | SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); | |
3f2cd4dd HR |
959 | uint16_t pd_id; |
960 | ||
961 | if (num_pd_disks >= max_pd_disks) | |
962 | break; | |
e8f943c3 | 963 | |
3f2cd4dd HR |
964 | pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF); |
965 | info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id); | |
e8f943c3 HR |
966 | info.addr[num_pd_disks].encl_device_id = 0xFFFF; |
967 | info.addr[num_pd_disks].encl_index = 0; | |
3f2cd4dd | 968 | info.addr[num_pd_disks].slot_number = sdev->id & 0xFF; |
e8f943c3 HR |
969 | info.addr[num_pd_disks].scsi_dev_type = sdev->type; |
970 | info.addr[num_pd_disks].connect_port_bitmap = 0x1; | |
971 | info.addr[num_pd_disks].sas_addr[0] = | |
3f2cd4dd | 972 | cpu_to_le64(megasas_get_sata_addr(pd_id)); |
e8f943c3 HR |
973 | num_pd_disks++; |
974 | offset += sizeof(struct mfi_pd_address); | |
975 | } | |
976 | trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks, | |
977 | max_pd_disks, offset); | |
978 | ||
979 | info.size = cpu_to_le32(offset); | |
980 | info.count = cpu_to_le32(num_pd_disks); | |
981 | ||
982 | cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg); | |
983 | return MFI_STAT_OK; | |
984 | } | |
985 | ||
986 | static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd) | |
987 | { | |
988 | uint16_t flags; | |
989 | ||
990 | /* mbox0 contains flags */ | |
991 | flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]); | |
992 | trace_megasas_dcmd_pd_list_query(cmd->index, flags); | |
993 | if (flags == MR_PD_QUERY_TYPE_ALL || | |
994 | megasas_is_jbod(s)) { | |
995 | return megasas_dcmd_pd_get_list(s, cmd); | |
996 | } | |
997 | ||
998 | return MFI_STAT_OK; | |
999 | } | |
1000 | ||
1001 | static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun, | |
1002 | MegasasCmd *cmd) | |
1003 | { | |
1004 | struct mfi_pd_info *info = cmd->iov_buf; | |
1005 | size_t dcmd_size = sizeof(struct mfi_pd_info); | |
e8f943c3 | 1006 | uint64_t pd_size; |
3f2cd4dd | 1007 | uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF); |
e8f943c3 HR |
1008 | uint8_t cmdbuf[6]; |
1009 | SCSIRequest *req; | |
1010 | size_t len, resid; | |
1011 | ||
1012 | if (!cmd->iov_buf) { | |
1013 | cmd->iov_buf = g_malloc(dcmd_size); | |
1014 | memset(cmd->iov_buf, 0, dcmd_size); | |
1015 | info = cmd->iov_buf; | |
1016 | info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */ | |
1017 | info->vpd_page83[0] = 0x7f; | |
1018 | megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data)); | |
1019 | req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd); | |
1020 | if (!req) { | |
1021 | trace_megasas_dcmd_req_alloc_failed(cmd->index, | |
1022 | "PD get info std inquiry"); | |
1023 | g_free(cmd->iov_buf); | |
1024 | cmd->iov_buf = NULL; | |
1025 | return MFI_STAT_FLASH_ALLOC_FAIL; | |
1026 | } | |
1027 | trace_megasas_dcmd_internal_submit(cmd->index, | |
1028 | "PD get info std inquiry", lun); | |
1029 | len = scsi_req_enqueue(req); | |
1030 | if (len > 0) { | |
1031 | cmd->iov_size = len; | |
1032 | scsi_req_continue(req); | |
1033 | } | |
1034 | return MFI_STAT_INVALID_STATUS; | |
1035 | } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) { | |
1036 | megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83)); | |
1037 | req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd); | |
1038 | if (!req) { | |
1039 | trace_megasas_dcmd_req_alloc_failed(cmd->index, | |
1040 | "PD get info vpd inquiry"); | |
1041 | return MFI_STAT_FLASH_ALLOC_FAIL; | |
1042 | } | |
1043 | trace_megasas_dcmd_internal_submit(cmd->index, | |
1044 | "PD get info vpd inquiry", lun); | |
1045 | len = scsi_req_enqueue(req); | |
1046 | if (len > 0) { | |
1047 | cmd->iov_size = len; | |
1048 | scsi_req_continue(req); | |
1049 | } | |
1050 | return MFI_STAT_INVALID_STATUS; | |
1051 | } | |
1052 | /* Finished, set FW state */ | |
1053 | if ((info->inquiry_data[0] >> 5) == 0) { | |
1054 | if (megasas_is_jbod(cmd->state)) { | |
1055 | info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM); | |
1056 | } else { | |
1057 | info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE); | |
1058 | } | |
1059 | } else { | |
1060 | info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE); | |
1061 | } | |
1062 | ||
3f2cd4dd | 1063 | info->ref.v.device_id = cpu_to_le16(pd_id); |
e8f943c3 HR |
1064 | info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD| |
1065 | MFI_PD_DDF_TYPE_INTF_SAS); | |
4be74634 | 1066 | blk_get_geometry(sdev->conf.blk, &pd_size); |
e8f943c3 HR |
1067 | info->raw_size = cpu_to_le64(pd_size); |
1068 | info->non_coerced_size = cpu_to_le64(pd_size); | |
1069 | info->coerced_size = cpu_to_le64(pd_size); | |
1070 | info->encl_device_id = 0xFFFF; | |
1071 | info->slot_number = (sdev->id & 0xFF); | |
1072 | info->path_info.count = 1; | |
1073 | info->path_info.sas_addr[0] = | |
3f2cd4dd | 1074 | cpu_to_le64(megasas_get_sata_addr(pd_id)); |
e8f943c3 HR |
1075 | info->connected_port_bitmap = 0x1; |
1076 | info->device_speed = 1; | |
1077 | info->link_speed = 1; | |
1078 | resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg); | |
1079 | g_free(cmd->iov_buf); | |
1080 | cmd->iov_size = dcmd_size - resid; | |
1081 | cmd->iov_buf = NULL; | |
1082 | return MFI_STAT_OK; | |
1083 | } | |
1084 | ||
1085 | static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd) | |
1086 | { | |
1087 | size_t dcmd_size = sizeof(struct mfi_pd_info); | |
1088 | uint16_t pd_id; | |
3f2cd4dd | 1089 | uint8_t target_id, lun_id; |
e8f943c3 HR |
1090 | SCSIDevice *sdev = NULL; |
1091 | int retval = MFI_STAT_DEVICE_NOT_FOUND; | |
1092 | ||
1093 | if (cmd->iov_size < dcmd_size) { | |
1094 | return MFI_STAT_INVALID_PARAMETER; | |
1095 | } | |
1096 | ||
1097 | /* mbox0 has the ID */ | |
1098 | pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]); | |
3f2cd4dd HR |
1099 | target_id = (pd_id >> 8) & 0xFF; |
1100 | lun_id = pd_id & 0xFF; | |
1101 | sdev = scsi_device_find(&s->bus, 0, target_id, lun_id); | |
e8f943c3 HR |
1102 | trace_megasas_dcmd_pd_get_info(cmd->index, pd_id); |
1103 | ||
1104 | if (sdev) { | |
1105 | /* Submit inquiry */ | |
1106 | retval = megasas_pd_get_info_submit(sdev, pd_id, cmd); | |
1107 | } | |
1108 | ||
1109 | return retval; | |
1110 | } | |
1111 | ||
1112 | static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd) | |
1113 | { | |
1114 | struct mfi_ld_list info; | |
1115 | size_t dcmd_size = sizeof(info), resid; | |
3f2cd4dd | 1116 | uint32_t num_ld_disks = 0, max_ld_disks; |
e8f943c3 HR |
1117 | uint64_t ld_size; |
1118 | BusChild *kid; | |
1119 | ||
1120 | memset(&info, 0, dcmd_size); | |
1121 | if (cmd->iov_size < dcmd_size) { | |
1122 | trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, | |
1123 | dcmd_size); | |
1124 | return MFI_STAT_INVALID_PARAMETER; | |
1125 | } | |
1126 | ||
3f2cd4dd | 1127 | max_ld_disks = (cmd->iov_size - 8) / 16; |
e8f943c3 HR |
1128 | if (megasas_is_jbod(s)) { |
1129 | max_ld_disks = 0; | |
1130 | } | |
3f2cd4dd HR |
1131 | if (max_ld_disks > MFI_MAX_LD) { |
1132 | max_ld_disks = MFI_MAX_LD; | |
1133 | } | |
e8f943c3 HR |
1134 | QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { |
1135 | SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); | |
e8f943c3 HR |
1136 | |
1137 | if (num_ld_disks >= max_ld_disks) { | |
1138 | break; | |
1139 | } | |
1140 | /* Logical device size is in blocks */ | |
4be74634 | 1141 | blk_get_geometry(sdev->conf.blk, &ld_size); |
e8f943c3 HR |
1142 | info.ld_list[num_ld_disks].ld.v.target_id = sdev->id; |
1143 | info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL; | |
1144 | info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size); | |
1145 | num_ld_disks++; | |
1146 | } | |
1147 | info.ld_count = cpu_to_le32(num_ld_disks); | |
1148 | trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks); | |
1149 | ||
1150 | resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); | |
1151 | cmd->iov_size = dcmd_size - resid; | |
1152 | return MFI_STAT_OK; | |
1153 | } | |
1154 | ||
34bb4d02 HR |
1155 | static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd) |
1156 | { | |
1157 | uint16_t flags; | |
d97ae368 HR |
1158 | struct mfi_ld_targetid_list info; |
1159 | size_t dcmd_size = sizeof(info), resid; | |
1160 | uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns; | |
1161 | BusChild *kid; | |
34bb4d02 HR |
1162 | |
1163 | /* mbox0 contains flags */ | |
1164 | flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]); | |
1165 | trace_megasas_dcmd_ld_list_query(cmd->index, flags); | |
d97ae368 HR |
1166 | if (flags != MR_LD_QUERY_TYPE_ALL && |
1167 | flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) { | |
1168 | max_ld_disks = 0; | |
1169 | } | |
1170 | ||
1171 | memset(&info, 0, dcmd_size); | |
1172 | if (cmd->iov_size < 12) { | |
1173 | trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, | |
1174 | dcmd_size); | |
1175 | return MFI_STAT_INVALID_PARAMETER; | |
1176 | } | |
1177 | dcmd_size = sizeof(uint32_t) * 2 + 3; | |
3f2cd4dd | 1178 | max_ld_disks = cmd->iov_size - dcmd_size; |
d97ae368 HR |
1179 | if (megasas_is_jbod(s)) { |
1180 | max_ld_disks = 0; | |
34bb4d02 | 1181 | } |
3f2cd4dd HR |
1182 | if (max_ld_disks > MFI_MAX_LD) { |
1183 | max_ld_disks = MFI_MAX_LD; | |
1184 | } | |
d97ae368 HR |
1185 | QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { |
1186 | SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); | |
34bb4d02 | 1187 | |
d97ae368 HR |
1188 | if (num_ld_disks >= max_ld_disks) { |
1189 | break; | |
1190 | } | |
1191 | info.targetid[num_ld_disks] = sdev->lun; | |
1192 | num_ld_disks++; | |
1193 | dcmd_size++; | |
1194 | } | |
1195 | info.ld_count = cpu_to_le32(num_ld_disks); | |
1196 | info.size = dcmd_size; | |
1197 | trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks); | |
1198 | ||
1199 | resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); | |
1200 | cmd->iov_size = dcmd_size - resid; | |
34bb4d02 HR |
1201 | return MFI_STAT_OK; |
1202 | } | |
1203 | ||
e8f943c3 HR |
1204 | static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun, |
1205 | MegasasCmd *cmd) | |
1206 | { | |
1207 | struct mfi_ld_info *info = cmd->iov_buf; | |
1208 | size_t dcmd_size = sizeof(struct mfi_ld_info); | |
1209 | uint8_t cdb[6]; | |
1210 | SCSIRequest *req; | |
1211 | ssize_t len, resid; | |
3f2cd4dd | 1212 | uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF); |
e8f943c3 HR |
1213 | uint64_t ld_size; |
1214 | ||
1215 | if (!cmd->iov_buf) { | |
1216 | cmd->iov_buf = g_malloc(dcmd_size); | |
1217 | memset(cmd->iov_buf, 0x0, dcmd_size); | |
1218 | info = cmd->iov_buf; | |
1219 | megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83)); | |
1220 | req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd); | |
1221 | if (!req) { | |
1222 | trace_megasas_dcmd_req_alloc_failed(cmd->index, | |
1223 | "LD get info vpd inquiry"); | |
1224 | g_free(cmd->iov_buf); | |
1225 | cmd->iov_buf = NULL; | |
1226 | return MFI_STAT_FLASH_ALLOC_FAIL; | |
1227 | } | |
1228 | trace_megasas_dcmd_internal_submit(cmd->index, | |
1229 | "LD get info vpd inquiry", lun); | |
1230 | len = scsi_req_enqueue(req); | |
1231 | if (len > 0) { | |
1232 | cmd->iov_size = len; | |
1233 | scsi_req_continue(req); | |
1234 | } | |
1235 | return MFI_STAT_INVALID_STATUS; | |
1236 | } | |
1237 | ||
1238 | info->ld_config.params.state = MFI_LD_STATE_OPTIMAL; | |
1239 | info->ld_config.properties.ld.v.target_id = lun; | |
1240 | info->ld_config.params.stripe_size = 3; | |
1241 | info->ld_config.params.num_drives = 1; | |
1242 | info->ld_config.params.is_consistent = 1; | |
1243 | /* Logical device size is in blocks */ | |
4be74634 | 1244 | blk_get_geometry(sdev->conf.blk, &ld_size); |
e8f943c3 HR |
1245 | info->size = cpu_to_le64(ld_size); |
1246 | memset(info->ld_config.span, 0, sizeof(info->ld_config.span)); | |
1247 | info->ld_config.span[0].start_block = 0; | |
1248 | info->ld_config.span[0].num_blocks = info->size; | |
1249 | info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id); | |
1250 | ||
1251 | resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg); | |
1252 | g_free(cmd->iov_buf); | |
1253 | cmd->iov_size = dcmd_size - resid; | |
1254 | cmd->iov_buf = NULL; | |
1255 | return MFI_STAT_OK; | |
1256 | } | |
1257 | ||
1258 | static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd) | |
1259 | { | |
1260 | struct mfi_ld_info info; | |
1261 | size_t dcmd_size = sizeof(info); | |
1262 | uint16_t ld_id; | |
1263 | uint32_t max_ld_disks = s->fw_luns; | |
1264 | SCSIDevice *sdev = NULL; | |
1265 | int retval = MFI_STAT_DEVICE_NOT_FOUND; | |
1266 | ||
1267 | if (cmd->iov_size < dcmd_size) { | |
1268 | return MFI_STAT_INVALID_PARAMETER; | |
1269 | } | |
1270 | ||
1271 | /* mbox0 has the ID */ | |
1272 | ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]); | |
1273 | trace_megasas_dcmd_ld_get_info(cmd->index, ld_id); | |
1274 | ||
1275 | if (megasas_is_jbod(s)) { | |
1276 | return MFI_STAT_DEVICE_NOT_FOUND; | |
1277 | } | |
1278 | ||
1279 | if (ld_id < max_ld_disks) { | |
1280 | sdev = scsi_device_find(&s->bus, 0, ld_id, 0); | |
1281 | } | |
1282 | ||
1283 | if (sdev) { | |
1284 | retval = megasas_ld_get_info_submit(sdev, ld_id, cmd); | |
1285 | } | |
1286 | ||
1287 | return retval; | |
1288 | } | |
1289 | ||
1290 | static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd) | |
1291 | { | |
1292 | uint8_t data[4096]; | |
1293 | struct mfi_config_data *info; | |
1294 | int num_pd_disks = 0, array_offset, ld_offset; | |
1295 | BusChild *kid; | |
1296 | ||
1297 | if (cmd->iov_size > 4096) { | |
1298 | return MFI_STAT_INVALID_PARAMETER; | |
1299 | } | |
1300 | ||
1301 | QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { | |
1302 | num_pd_disks++; | |
1303 | } | |
1304 | info = (struct mfi_config_data *)&data; | |
1305 | /* | |
1306 | * Array mapping: | |
1307 | * - One array per SCSI device | |
1308 | * - One logical drive per SCSI device | |
1309 | * spanning the entire device | |
1310 | */ | |
1311 | info->array_count = num_pd_disks; | |
1312 | info->array_size = sizeof(struct mfi_array) * num_pd_disks; | |
1313 | info->log_drv_count = num_pd_disks; | |
1314 | info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks; | |
1315 | info->spares_count = 0; | |
1316 | info->spares_size = sizeof(struct mfi_spare); | |
1317 | info->size = sizeof(struct mfi_config_data) + info->array_size + | |
1318 | info->log_drv_size; | |
1319 | if (info->size > 4096) { | |
1320 | return MFI_STAT_INVALID_PARAMETER; | |
1321 | } | |
1322 | ||
1323 | array_offset = sizeof(struct mfi_config_data); | |
1324 | ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks; | |
1325 | ||
1326 | QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) { | |
1327 | SCSIDevice *sdev = DO_UPCAST(SCSIDevice, qdev, kid->child); | |
3f2cd4dd | 1328 | uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF); |
e8f943c3 HR |
1329 | struct mfi_array *array; |
1330 | struct mfi_ld_config *ld; | |
1331 | uint64_t pd_size; | |
1332 | int i; | |
1333 | ||
1334 | array = (struct mfi_array *)(data + array_offset); | |
4be74634 | 1335 | blk_get_geometry(sdev->conf.blk, &pd_size); |
e8f943c3 HR |
1336 | array->size = cpu_to_le64(pd_size); |
1337 | array->num_drives = 1; | |
1338 | array->array_ref = cpu_to_le16(sdev_id); | |
1339 | array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id); | |
1340 | array->pd[0].ref.v.seq_num = 0; | |
1341 | array->pd[0].fw_state = MFI_PD_STATE_ONLINE; | |
1342 | array->pd[0].encl.pd = 0xFF; | |
1343 | array->pd[0].encl.slot = (sdev->id & 0xFF); | |
1344 | for (i = 1; i < MFI_MAX_ROW_SIZE; i++) { | |
1345 | array->pd[i].ref.v.device_id = 0xFFFF; | |
1346 | array->pd[i].ref.v.seq_num = 0; | |
1347 | array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD; | |
1348 | array->pd[i].encl.pd = 0xFF; | |
1349 | array->pd[i].encl.slot = 0xFF; | |
1350 | } | |
1351 | array_offset += sizeof(struct mfi_array); | |
1352 | ld = (struct mfi_ld_config *)(data + ld_offset); | |
1353 | memset(ld, 0, sizeof(struct mfi_ld_config)); | |
3f2cd4dd | 1354 | ld->properties.ld.v.target_id = sdev->id; |
e8f943c3 HR |
1355 | ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD | |
1356 | MR_LD_CACHE_READ_ADAPTIVE; | |
1357 | ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD | | |
1358 | MR_LD_CACHE_READ_ADAPTIVE; | |
1359 | ld->params.state = MFI_LD_STATE_OPTIMAL; | |
1360 | ld->params.stripe_size = 3; | |
1361 | ld->params.num_drives = 1; | |
1362 | ld->params.span_depth = 1; | |
1363 | ld->params.is_consistent = 1; | |
1364 | ld->span[0].start_block = 0; | |
1365 | ld->span[0].num_blocks = cpu_to_le64(pd_size); | |
1366 | ld->span[0].array_ref = cpu_to_le16(sdev_id); | |
1367 | ld_offset += sizeof(struct mfi_ld_config); | |
1368 | } | |
1369 | ||
1370 | cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg); | |
1371 | return MFI_STAT_OK; | |
1372 | } | |
1373 | ||
1374 | static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd) | |
1375 | { | |
1376 | struct mfi_ctrl_props info; | |
1377 | size_t dcmd_size = sizeof(info); | |
1378 | ||
1379 | memset(&info, 0x0, dcmd_size); | |
1380 | if (cmd->iov_size < dcmd_size) { | |
1381 | trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, | |
1382 | dcmd_size); | |
1383 | return MFI_STAT_INVALID_PARAMETER; | |
1384 | } | |
1385 | info.pred_fail_poll_interval = cpu_to_le16(300); | |
1386 | info.intr_throttle_cnt = cpu_to_le16(16); | |
1387 | info.intr_throttle_timeout = cpu_to_le16(50); | |
1388 | info.rebuild_rate = 30; | |
1389 | info.patrol_read_rate = 30; | |
1390 | info.bgi_rate = 30; | |
1391 | info.cc_rate = 30; | |
1392 | info.recon_rate = 30; | |
1393 | info.cache_flush_interval = 4; | |
1394 | info.spinup_drv_cnt = 2; | |
1395 | info.spinup_delay = 6; | |
1396 | info.ecc_bucket_size = 15; | |
1397 | info.ecc_bucket_leak_rate = cpu_to_le16(1440); | |
1398 | info.expose_encl_devices = 1; | |
1399 | ||
1400 | cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg); | |
1401 | return MFI_STAT_OK; | |
1402 | } | |
1403 | ||
1404 | static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd) | |
1405 | { | |
4be74634 | 1406 | blk_drain_all(); |
e8f943c3 HR |
1407 | return MFI_STAT_OK; |
1408 | } | |
1409 | ||
1410 | static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd) | |
1411 | { | |
1412 | s->fw_state = MFI_FWSTATE_READY; | |
1413 | return MFI_STAT_OK; | |
1414 | } | |
1415 | ||
1416 | static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd) | |
1417 | { | |
1418 | return MFI_STAT_INVALID_DCMD; | |
1419 | } | |
1420 | ||
1421 | static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd) | |
1422 | { | |
10d6530c HR |
1423 | struct mfi_ctrl_props info; |
1424 | size_t dcmd_size = sizeof(info); | |
1425 | ||
1426 | if (cmd->iov_size < dcmd_size) { | |
1427 | trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size, | |
1428 | dcmd_size); | |
1429 | return MFI_STAT_INVALID_PARAMETER; | |
1430 | } | |
1431 | dma_buf_write((uint8_t *)&info, cmd->iov_size, &cmd->qsg); | |
1432 | trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size); | |
e8f943c3 HR |
1433 | return MFI_STAT_OK; |
1434 | } | |
1435 | ||
1436 | static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd) | |
1437 | { | |
1438 | trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size); | |
1439 | return MFI_STAT_OK; | |
1440 | } | |
1441 | ||
1442 | static const struct dcmd_cmd_tbl_t { | |
1443 | int opcode; | |
1444 | const char *desc; | |
1445 | int (*func)(MegasasState *s, MegasasCmd *cmd); | |
1446 | } dcmd_cmd_tbl[] = { | |
1447 | { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC", | |
1448 | megasas_dcmd_dummy }, | |
1449 | { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO", | |
1450 | megasas_ctrl_get_info }, | |
1451 | { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES", | |
1452 | megasas_dcmd_get_properties }, | |
1453 | { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES", | |
1454 | megasas_dcmd_set_properties }, | |
1455 | { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET", | |
1456 | megasas_dcmd_dummy }, | |
1457 | { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE", | |
1458 | megasas_dcmd_dummy }, | |
1459 | { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE", | |
1460 | megasas_dcmd_dummy }, | |
1461 | { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE", | |
1462 | megasas_dcmd_dummy }, | |
1463 | { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST", | |
1464 | megasas_dcmd_dummy }, | |
1465 | { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO", | |
1466 | megasas_event_info }, | |
1467 | { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET", | |
1468 | megasas_dcmd_dummy }, | |
1469 | { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT", | |
1470 | megasas_event_wait }, | |
1471 | { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN", | |
1472 | megasas_ctrl_shutdown }, | |
1473 | { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY", | |
1474 | megasas_dcmd_dummy }, | |
1475 | { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME", | |
1476 | megasas_dcmd_get_fw_time }, | |
1477 | { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME", | |
1478 | megasas_dcmd_set_fw_time }, | |
1479 | { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET", | |
1480 | megasas_dcmd_get_bios_info }, | |
1481 | { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS", | |
1482 | megasas_dcmd_dummy }, | |
1483 | { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET", | |
1484 | megasas_mfc_get_defaults }, | |
1485 | { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET", | |
1486 | megasas_dcmd_dummy }, | |
1487 | { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH", | |
1488 | megasas_cache_flush }, | |
1489 | { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST", | |
1490 | megasas_dcmd_pd_get_list }, | |
1491 | { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY", | |
1492 | megasas_dcmd_pd_list_query }, | |
1493 | { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO", | |
1494 | megasas_dcmd_pd_get_info }, | |
1495 | { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET", | |
1496 | megasas_dcmd_dummy }, | |
1497 | { MFI_DCMD_PD_REBUILD, "PD_REBUILD", | |
1498 | megasas_dcmd_dummy }, | |
1499 | { MFI_DCMD_PD_BLINK, "PD_BLINK", | |
1500 | megasas_dcmd_dummy }, | |
1501 | { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK", | |
1502 | megasas_dcmd_dummy }, | |
1503 | { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST", | |
1504 | megasas_dcmd_ld_get_list}, | |
34bb4d02 HR |
1505 | { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY", |
1506 | megasas_dcmd_ld_list_query }, | |
e8f943c3 HR |
1507 | { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO", |
1508 | megasas_dcmd_ld_get_info }, | |
1509 | { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP", | |
1510 | megasas_dcmd_dummy }, | |
1511 | { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP", | |
1512 | megasas_dcmd_dummy }, | |
1513 | { MFI_DCMD_LD_DELETE, "LD_DELETE", | |
1514 | megasas_dcmd_dummy }, | |
1515 | { MFI_DCMD_CFG_READ, "CFG_READ", | |
1516 | megasas_dcmd_cfg_read }, | |
1517 | { MFI_DCMD_CFG_ADD, "CFG_ADD", | |
1518 | megasas_dcmd_dummy }, | |
1519 | { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR", | |
1520 | megasas_dcmd_dummy }, | |
1521 | { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ", | |
1522 | megasas_dcmd_dummy }, | |
1523 | { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT", | |
1524 | megasas_dcmd_dummy }, | |
1525 | { MFI_DCMD_BBU_STATUS, "BBU_STATUS", | |
1526 | megasas_dcmd_dummy }, | |
1527 | { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO", | |
1528 | megasas_dcmd_dummy }, | |
1529 | { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO", | |
1530 | megasas_dcmd_dummy }, | |
1531 | { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET", | |
1532 | megasas_dcmd_dummy }, | |
1533 | { MFI_DCMD_CLUSTER, "CLUSTER", | |
1534 | megasas_dcmd_dummy }, | |
1535 | { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL", | |
1536 | megasas_dcmd_dummy }, | |
1537 | { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD", | |
1538 | megasas_cluster_reset_ld }, | |
1539 | { -1, NULL, NULL } | |
1540 | }; | |
1541 | ||
1542 | static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd) | |
1543 | { | |
1544 | int opcode, len; | |
1545 | int retval = 0; | |
1546 | const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl; | |
1547 | ||
1548 | opcode = le32_to_cpu(cmd->frame->dcmd.opcode); | |
1549 | trace_megasas_handle_dcmd(cmd->index, opcode); | |
1550 | len = megasas_map_dcmd(s, cmd); | |
1551 | if (len < 0) { | |
1552 | return MFI_STAT_MEMORY_NOT_AVAILABLE; | |
1553 | } | |
1554 | while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) { | |
1555 | cmdptr++; | |
1556 | } | |
1557 | if (cmdptr->opcode == -1) { | |
1558 | trace_megasas_dcmd_unhandled(cmd->index, opcode, len); | |
1559 | retval = megasas_dcmd_dummy(s, cmd); | |
1560 | } else { | |
1561 | trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len); | |
1562 | retval = cmdptr->func(s, cmd); | |
1563 | } | |
1564 | if (retval != MFI_STAT_INVALID_STATUS) { | |
1565 | megasas_finish_dcmd(cmd, len); | |
1566 | } | |
1567 | return retval; | |
1568 | } | |
1569 | ||
1570 | static int megasas_finish_internal_dcmd(MegasasCmd *cmd, | |
1571 | SCSIRequest *req) | |
1572 | { | |
1573 | int opcode; | |
1574 | int retval = MFI_STAT_OK; | |
1575 | int lun = req->lun; | |
1576 | ||
1577 | opcode = le32_to_cpu(cmd->frame->dcmd.opcode); | |
1578 | scsi_req_unref(req); | |
1579 | trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun); | |
1580 | switch (opcode) { | |
1581 | case MFI_DCMD_PD_GET_INFO: | |
1582 | retval = megasas_pd_get_info_submit(req->dev, lun, cmd); | |
1583 | break; | |
1584 | case MFI_DCMD_LD_GET_INFO: | |
1585 | retval = megasas_ld_get_info_submit(req->dev, lun, cmd); | |
1586 | break; | |
1587 | default: | |
1588 | trace_megasas_dcmd_internal_invalid(cmd->index, opcode); | |
1589 | retval = MFI_STAT_INVALID_DCMD; | |
1590 | break; | |
1591 | } | |
1592 | if (retval != MFI_STAT_INVALID_STATUS) { | |
1593 | megasas_finish_dcmd(cmd, cmd->iov_size); | |
1594 | } | |
1595 | return retval; | |
1596 | } | |
1597 | ||
1598 | static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write) | |
1599 | { | |
1600 | int len; | |
1601 | ||
1602 | len = scsi_req_enqueue(cmd->req); | |
1603 | if (len < 0) { | |
1604 | len = -len; | |
1605 | } | |
1606 | if (len > 0) { | |
1607 | if (len > cmd->iov_size) { | |
1608 | if (is_write) { | |
1609 | trace_megasas_iov_write_overflow(cmd->index, len, | |
1610 | cmd->iov_size); | |
1611 | } else { | |
1612 | trace_megasas_iov_read_overflow(cmd->index, len, | |
1613 | cmd->iov_size); | |
1614 | } | |
1615 | } | |
1616 | if (len < cmd->iov_size) { | |
1617 | if (is_write) { | |
1618 | trace_megasas_iov_write_underflow(cmd->index, len, | |
1619 | cmd->iov_size); | |
1620 | } else { | |
1621 | trace_megasas_iov_read_underflow(cmd->index, len, | |
1622 | cmd->iov_size); | |
1623 | } | |
1624 | cmd->iov_size = len; | |
1625 | } | |
1626 | scsi_req_continue(cmd->req); | |
1627 | } | |
1628 | return len; | |
1629 | } | |
1630 | ||
1631 | static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd, | |
1632 | bool is_logical) | |
1633 | { | |
1634 | uint8_t *cdb; | |
1635 | int len; | |
1636 | bool is_write; | |
1637 | struct SCSIDevice *sdev = NULL; | |
1638 | ||
1639 | cdb = cmd->frame->pass.cdb; | |
1640 | ||
3f2cd4dd HR |
1641 | if (is_logical) { |
1642 | if (cmd->frame->header.target_id >= MFI_MAX_LD || | |
1643 | cmd->frame->header.lun_id != 0) { | |
1644 | trace_megasas_scsi_target_not_present( | |
1645 | mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical, | |
1646 | cmd->frame->header.target_id, cmd->frame->header.lun_id); | |
1647 | return MFI_STAT_DEVICE_NOT_FOUND; | |
1648 | } | |
e8f943c3 | 1649 | } |
3f2cd4dd HR |
1650 | sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id, |
1651 | cmd->frame->header.lun_id); | |
1652 | ||
e8f943c3 HR |
1653 | cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len); |
1654 | trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd], | |
1655 | is_logical, cmd->frame->header.target_id, | |
1656 | cmd->frame->header.lun_id, sdev, cmd->iov_size); | |
1657 | ||
1658 | if (!sdev || (megasas_is_jbod(s) && is_logical)) { | |
1659 | trace_megasas_scsi_target_not_present( | |
1660 | mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical, | |
1661 | cmd->frame->header.target_id, cmd->frame->header.lun_id); | |
1662 | return MFI_STAT_DEVICE_NOT_FOUND; | |
1663 | } | |
1664 | ||
1665 | if (cmd->frame->header.cdb_len > 16) { | |
1666 | trace_megasas_scsi_invalid_cdb_len( | |
1667 | mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical, | |
1668 | cmd->frame->header.target_id, cmd->frame->header.lun_id, | |
1669 | cmd->frame->header.cdb_len); | |
1670 | megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE)); | |
1671 | cmd->frame->header.scsi_status = CHECK_CONDITION; | |
1672 | s->event_count++; | |
1673 | return MFI_STAT_SCSI_DONE_WITH_ERROR; | |
1674 | } | |
1675 | ||
1676 | if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) { | |
1677 | megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE)); | |
1678 | cmd->frame->header.scsi_status = CHECK_CONDITION; | |
1679 | s->event_count++; | |
1680 | return MFI_STAT_SCSI_DONE_WITH_ERROR; | |
1681 | } | |
1682 | ||
1683 | cmd->req = scsi_req_new(sdev, cmd->index, | |
1684 | cmd->frame->header.lun_id, cdb, cmd); | |
1685 | if (!cmd->req) { | |
1686 | trace_megasas_scsi_req_alloc_failed( | |
1687 | mfi_frame_desc[cmd->frame->header.frame_cmd], | |
1688 | cmd->frame->header.target_id, cmd->frame->header.lun_id); | |
1689 | megasas_write_sense(cmd, SENSE_CODE(NO_SENSE)); | |
1690 | cmd->frame->header.scsi_status = BUSY; | |
1691 | s->event_count++; | |
1692 | return MFI_STAT_SCSI_DONE_WITH_ERROR; | |
1693 | } | |
1694 | ||
1695 | is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV); | |
1696 | len = megasas_enqueue_req(cmd, is_write); | |
1697 | if (len > 0) { | |
1698 | if (is_write) { | |
1699 | trace_megasas_scsi_write_start(cmd->index, len); | |
1700 | } else { | |
1701 | trace_megasas_scsi_read_start(cmd->index, len); | |
1702 | } | |
1703 | } else { | |
1704 | trace_megasas_scsi_nodata(cmd->index); | |
1705 | } | |
1706 | return MFI_STAT_INVALID_STATUS; | |
1707 | } | |
1708 | ||
1709 | static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd) | |
1710 | { | |
1711 | uint32_t lba_count, lba_start_hi, lba_start_lo; | |
1712 | uint64_t lba_start; | |
1713 | bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE); | |
1714 | uint8_t cdb[16]; | |
1715 | int len; | |
1716 | struct SCSIDevice *sdev = NULL; | |
1717 | ||
1718 | lba_count = le32_to_cpu(cmd->frame->io.header.data_len); | |
1719 | lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo); | |
1720 | lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi); | |
1721 | lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo; | |
1722 | ||
3f2cd4dd HR |
1723 | if (cmd->frame->header.target_id < MFI_MAX_LD && |
1724 | cmd->frame->header.lun_id == 0) { | |
e8f943c3 HR |
1725 | sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id, |
1726 | cmd->frame->header.lun_id); | |
1727 | } | |
1728 | ||
1729 | trace_megasas_handle_io(cmd->index, | |
1730 | mfi_frame_desc[cmd->frame->header.frame_cmd], | |
1731 | cmd->frame->header.target_id, | |
1732 | cmd->frame->header.lun_id, | |
1733 | (unsigned long)lba_start, (unsigned long)lba_count); | |
1734 | if (!sdev) { | |
1735 | trace_megasas_io_target_not_present(cmd->index, | |
1736 | mfi_frame_desc[cmd->frame->header.frame_cmd], | |
1737 | cmd->frame->header.target_id, cmd->frame->header.lun_id); | |
1738 | return MFI_STAT_DEVICE_NOT_FOUND; | |
1739 | } | |
1740 | ||
1741 | if (cmd->frame->header.cdb_len > 16) { | |
1742 | trace_megasas_scsi_invalid_cdb_len( | |
1743 | mfi_frame_desc[cmd->frame->header.frame_cmd], 1, | |
1744 | cmd->frame->header.target_id, cmd->frame->header.lun_id, | |
1745 | cmd->frame->header.cdb_len); | |
1746 | megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE)); | |
1747 | cmd->frame->header.scsi_status = CHECK_CONDITION; | |
1748 | s->event_count++; | |
1749 | return MFI_STAT_SCSI_DONE_WITH_ERROR; | |
1750 | } | |
1751 | ||
1752 | cmd->iov_size = lba_count * sdev->blocksize; | |
1753 | if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) { | |
1754 | megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE)); | |
1755 | cmd->frame->header.scsi_status = CHECK_CONDITION; | |
1756 | s->event_count++; | |
1757 | return MFI_STAT_SCSI_DONE_WITH_ERROR; | |
1758 | } | |
1759 | ||
1760 | megasas_encode_lba(cdb, lba_start, lba_count, is_write); | |
1761 | cmd->req = scsi_req_new(sdev, cmd->index, | |
1762 | cmd->frame->header.lun_id, cdb, cmd); | |
1763 | if (!cmd->req) { | |
1764 | trace_megasas_scsi_req_alloc_failed( | |
1765 | mfi_frame_desc[cmd->frame->header.frame_cmd], | |
1766 | cmd->frame->header.target_id, cmd->frame->header.lun_id); | |
1767 | megasas_write_sense(cmd, SENSE_CODE(NO_SENSE)); | |
1768 | cmd->frame->header.scsi_status = BUSY; | |
1769 | s->event_count++; | |
1770 | return MFI_STAT_SCSI_DONE_WITH_ERROR; | |
1771 | } | |
1772 | len = megasas_enqueue_req(cmd, is_write); | |
1773 | if (len > 0) { | |
1774 | if (is_write) { | |
1775 | trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len); | |
1776 | } else { | |
1777 | trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len); | |
1778 | } | |
1779 | } | |
1780 | return MFI_STAT_INVALID_STATUS; | |
1781 | } | |
1782 | ||
1783 | static int megasas_finish_internal_command(MegasasCmd *cmd, | |
1784 | SCSIRequest *req, size_t resid) | |
1785 | { | |
1786 | int retval = MFI_STAT_INVALID_CMD; | |
1787 | ||
1788 | if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) { | |
1789 | cmd->iov_size -= resid; | |
1790 | retval = megasas_finish_internal_dcmd(cmd, req); | |
1791 | } | |
1792 | return retval; | |
1793 | } | |
1794 | ||
1795 | static QEMUSGList *megasas_get_sg_list(SCSIRequest *req) | |
1796 | { | |
1797 | MegasasCmd *cmd = req->hba_private; | |
1798 | ||
1799 | if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) { | |
1800 | return NULL; | |
1801 | } else { | |
1802 | return &cmd->qsg; | |
1803 | } | |
1804 | } | |
1805 | ||
1806 | static void megasas_xfer_complete(SCSIRequest *req, uint32_t len) | |
1807 | { | |
1808 | MegasasCmd *cmd = req->hba_private; | |
1809 | uint8_t *buf; | |
1810 | uint32_t opcode; | |
1811 | ||
1812 | trace_megasas_io_complete(cmd->index, len); | |
1813 | ||
1814 | if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) { | |
1815 | scsi_req_continue(req); | |
1816 | return; | |
1817 | } | |
1818 | ||
1819 | buf = scsi_req_get_buf(req); | |
1820 | opcode = le32_to_cpu(cmd->frame->dcmd.opcode); | |
1821 | if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) { | |
1822 | struct mfi_pd_info *info = cmd->iov_buf; | |
1823 | ||
1824 | if (info->inquiry_data[0] == 0x7f) { | |
1825 | memset(info->inquiry_data, 0, sizeof(info->inquiry_data)); | |
1826 | memcpy(info->inquiry_data, buf, len); | |
1827 | } else if (info->vpd_page83[0] == 0x7f) { | |
1828 | memset(info->vpd_page83, 0, sizeof(info->vpd_page83)); | |
1829 | memcpy(info->vpd_page83, buf, len); | |
1830 | } | |
1831 | scsi_req_continue(req); | |
1832 | } else if (opcode == MFI_DCMD_LD_GET_INFO) { | |
1833 | struct mfi_ld_info *info = cmd->iov_buf; | |
1834 | ||
1835 | if (cmd->iov_buf) { | |
1836 | memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83)); | |
1837 | scsi_req_continue(req); | |
1838 | } | |
1839 | } | |
1840 | } | |
1841 | ||
1842 | static void megasas_command_complete(SCSIRequest *req, uint32_t status, | |
1843 | size_t resid) | |
1844 | { | |
1845 | MegasasCmd *cmd = req->hba_private; | |
1846 | uint8_t cmd_status = MFI_STAT_OK; | |
1847 | ||
1848 | trace_megasas_command_complete(cmd->index, status, resid); | |
1849 | ||
1850 | if (cmd->req != req) { | |
1851 | /* | |
1852 | * Internal command complete | |
1853 | */ | |
1854 | cmd_status = megasas_finish_internal_command(cmd, req, resid); | |
1855 | if (cmd_status == MFI_STAT_INVALID_STATUS) { | |
1856 | return; | |
1857 | } | |
1858 | } else { | |
1859 | req->status = status; | |
1860 | trace_megasas_scsi_complete(cmd->index, req->status, | |
1861 | cmd->iov_size, req->cmd.xfer); | |
1862 | if (req->status != GOOD) { | |
1863 | cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR; | |
1864 | } | |
1865 | if (req->status == CHECK_CONDITION) { | |
1866 | megasas_copy_sense(cmd); | |
1867 | } | |
1868 | ||
1869 | megasas_unmap_sgl(cmd); | |
1870 | cmd->frame->header.scsi_status = req->status; | |
1871 | scsi_req_unref(cmd->req); | |
1872 | cmd->req = NULL; | |
1873 | } | |
1874 | cmd->frame->header.cmd_status = cmd_status; | |
1875 | megasas_complete_frame(cmd->state, cmd->context); | |
1876 | } | |
1877 | ||
1878 | static void megasas_command_cancel(SCSIRequest *req) | |
1879 | { | |
1880 | MegasasCmd *cmd = req->hba_private; | |
1881 | ||
1882 | if (cmd) { | |
1883 | megasas_abort_command(cmd); | |
1884 | } else { | |
1885 | scsi_req_unref(req); | |
1886 | } | |
1887 | } | |
1888 | ||
1889 | static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd) | |
1890 | { | |
1891 | uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context); | |
a8170e5e | 1892 | hwaddr abort_addr, addr_hi, addr_lo; |
e8f943c3 HR |
1893 | MegasasCmd *abort_cmd; |
1894 | ||
1895 | addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi); | |
1896 | addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo); | |
1897 | abort_addr = ((uint64_t)addr_hi << 32) | addr_lo; | |
1898 | ||
1899 | abort_cmd = megasas_lookup_frame(s, abort_addr); | |
1900 | if (!abort_cmd) { | |
1901 | trace_megasas_abort_no_cmd(cmd->index, abort_ctx); | |
1902 | s->event_count++; | |
1903 | return MFI_STAT_OK; | |
1904 | } | |
1905 | if (!megasas_use_queue64(s)) { | |
1906 | abort_ctx &= (uint64_t)0xFFFFFFFF; | |
1907 | } | |
1908 | if (abort_cmd->context != abort_ctx) { | |
1909 | trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index, | |
1910 | abort_cmd->context); | |
1911 | s->event_count++; | |
1912 | return MFI_STAT_ABORT_NOT_POSSIBLE; | |
1913 | } | |
1914 | trace_megasas_abort_frame(cmd->index, abort_cmd->index); | |
1915 | megasas_abort_command(abort_cmd); | |
1916 | if (!s->event_cmd || abort_cmd != s->event_cmd) { | |
1917 | s->event_cmd = NULL; | |
1918 | } | |
1919 | s->event_count++; | |
1920 | return MFI_STAT_OK; | |
1921 | } | |
1922 | ||
1923 | static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr, | |
1924 | uint32_t frame_count) | |
1925 | { | |
1926 | uint8_t frame_status = MFI_STAT_INVALID_CMD; | |
1927 | uint64_t frame_context; | |
1928 | MegasasCmd *cmd; | |
1929 | ||
1930 | /* | |
1931 | * Always read 64bit context, top bits will be | |
1932 | * masked out if required in megasas_enqueue_frame() | |
1933 | */ | |
1934 | frame_context = megasas_frame_get_context(frame_addr); | |
1935 | ||
1936 | cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count); | |
1937 | if (!cmd) { | |
1938 | /* reply queue full */ | |
1939 | trace_megasas_frame_busy(frame_addr); | |
1940 | megasas_frame_set_scsi_status(frame_addr, BUSY); | |
1941 | megasas_frame_set_cmd_status(frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR); | |
1942 | megasas_complete_frame(s, frame_context); | |
1943 | s->event_count++; | |
1944 | return; | |
1945 | } | |
1946 | switch (cmd->frame->header.frame_cmd) { | |
1947 | case MFI_CMD_INIT: | |
1948 | frame_status = megasas_init_firmware(s, cmd); | |
1949 | break; | |
1950 | case MFI_CMD_DCMD: | |
1951 | frame_status = megasas_handle_dcmd(s, cmd); | |
1952 | break; | |
1953 | case MFI_CMD_ABORT: | |
1954 | frame_status = megasas_handle_abort(s, cmd); | |
1955 | break; | |
1956 | case MFI_CMD_PD_SCSI_IO: | |
1957 | frame_status = megasas_handle_scsi(s, cmd, 0); | |
1958 | break; | |
1959 | case MFI_CMD_LD_SCSI_IO: | |
1960 | frame_status = megasas_handle_scsi(s, cmd, 1); | |
1961 | break; | |
1962 | case MFI_CMD_LD_READ: | |
1963 | case MFI_CMD_LD_WRITE: | |
1964 | frame_status = megasas_handle_io(s, cmd); | |
1965 | break; | |
1966 | default: | |
1967 | trace_megasas_unhandled_frame_cmd(cmd->index, | |
1968 | cmd->frame->header.frame_cmd); | |
1969 | s->event_count++; | |
1970 | break; | |
1971 | } | |
1972 | if (frame_status != MFI_STAT_INVALID_STATUS) { | |
1973 | if (cmd->frame) { | |
1974 | cmd->frame->header.cmd_status = frame_status; | |
1975 | } else { | |
1976 | megasas_frame_set_cmd_status(frame_addr, frame_status); | |
1977 | } | |
1978 | megasas_complete_frame(s, cmd->context); | |
1979 | } | |
1980 | } | |
1981 | ||
a8170e5e | 1982 | static uint64_t megasas_mmio_read(void *opaque, hwaddr addr, |
e8f943c3 HR |
1983 | unsigned size) |
1984 | { | |
1985 | MegasasState *s = opaque; | |
e23d0498 HR |
1986 | PCIDevice *pci_dev = PCI_DEVICE(s); |
1987 | MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s); | |
e8f943c3 HR |
1988 | uint32_t retval = 0; |
1989 | ||
1990 | switch (addr) { | |
1991 | case MFI_IDB: | |
1992 | retval = 0; | |
1993 | break; | |
1994 | case MFI_OMSG0: | |
1995 | case MFI_OSP0: | |
e23d0498 | 1996 | retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) | |
e8f943c3 HR |
1997 | (s->fw_state & MFI_FWSTATE_MASK) | |
1998 | ((s->fw_sge & 0xff) << 16) | | |
1999 | (s->fw_cmds & 0xFFFF); | |
2000 | break; | |
2001 | case MFI_OSTS: | |
2002 | if (megasas_intr_enabled(s) && s->doorbell) { | |
e23d0498 | 2003 | retval = base_class->osts; |
e8f943c3 HR |
2004 | } |
2005 | break; | |
2006 | case MFI_OMSK: | |
2007 | retval = s->intr_mask; | |
2008 | break; | |
2009 | case MFI_ODCR0: | |
2010 | retval = s->doorbell; | |
2011 | break; | |
e23d0498 HR |
2012 | case MFI_DIAG: |
2013 | retval = s->diag; | |
2014 | break; | |
2015 | case MFI_OSP1: | |
2016 | retval = 15; | |
2017 | break; | |
e8f943c3 HR |
2018 | default: |
2019 | trace_megasas_mmio_invalid_readl(addr); | |
2020 | break; | |
2021 | } | |
2022 | trace_megasas_mmio_readl(addr, retval); | |
2023 | return retval; | |
2024 | } | |
2025 | ||
e23d0498 HR |
2026 | static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d}; |
2027 | ||
a8170e5e | 2028 | static void megasas_mmio_write(void *opaque, hwaddr addr, |
e8f943c3 HR |
2029 | uint64_t val, unsigned size) |
2030 | { | |
2031 | MegasasState *s = opaque; | |
52190c1e | 2032 | PCIDevice *pci_dev = PCI_DEVICE(s); |
e8f943c3 HR |
2033 | uint64_t frame_addr; |
2034 | uint32_t frame_count; | |
2035 | int i; | |
2036 | ||
2037 | trace_megasas_mmio_writel(addr, val); | |
2038 | switch (addr) { | |
2039 | case MFI_IDB: | |
2040 | if (val & MFI_FWINIT_ABORT) { | |
2041 | /* Abort all pending cmds */ | |
2042 | for (i = 0; i < s->fw_cmds; i++) { | |
2043 | megasas_abort_command(&s->frames[i]); | |
2044 | } | |
2045 | } | |
2046 | if (val & MFI_FWINIT_READY) { | |
2047 | /* move to FW READY */ | |
2048 | megasas_soft_reset(s); | |
2049 | } | |
2050 | if (val & MFI_FWINIT_MFIMODE) { | |
2051 | /* discard MFIs */ | |
2052 | } | |
e23d0498 HR |
2053 | if (val & MFI_FWINIT_STOP_ADP) { |
2054 | /* Terminal error, stop processing */ | |
2055 | s->fw_state = MFI_FWSTATE_FAULT; | |
2056 | } | |
e8f943c3 HR |
2057 | break; |
2058 | case MFI_OMSK: | |
2059 | s->intr_mask = val; | |
4522b69c HR |
2060 | if (!megasas_intr_enabled(s) && |
2061 | !msi_enabled(pci_dev) && | |
2062 | !msix_enabled(pci_dev)) { | |
e8f943c3 | 2063 | trace_megasas_irq_lower(); |
9e64f8a3 | 2064 | pci_irq_deassert(pci_dev); |
e8f943c3 HR |
2065 | } |
2066 | if (megasas_intr_enabled(s)) { | |
4522b69c HR |
2067 | if (msix_enabled(pci_dev)) { |
2068 | trace_megasas_msix_enabled(0); | |
2069 | } else if (msi_enabled(pci_dev)) { | |
2070 | trace_megasas_msi_enabled(0); | |
2071 | } else { | |
2072 | trace_megasas_intr_enabled(); | |
2073 | } | |
e8f943c3 HR |
2074 | } else { |
2075 | trace_megasas_intr_disabled(); | |
e23d0498 | 2076 | megasas_soft_reset(s); |
e8f943c3 HR |
2077 | } |
2078 | break; | |
2079 | case MFI_ODCR0: | |
2080 | s->doorbell = 0; | |
2081 | if (s->producer_pa && megasas_intr_enabled(s)) { | |
2082 | /* Update reply queue pointer */ | |
2083 | trace_megasas_qf_update(s->reply_queue_head, s->busy); | |
ab1da857 EI |
2084 | stl_le_phys(&address_space_memory, |
2085 | s->producer_pa, s->reply_queue_head); | |
52190c1e | 2086 | if (!msix_enabled(pci_dev)) { |
e8f943c3 | 2087 | trace_megasas_irq_lower(); |
9e64f8a3 | 2088 | pci_irq_deassert(pci_dev); |
e8f943c3 HR |
2089 | } |
2090 | } | |
2091 | break; | |
2092 | case MFI_IQPH: | |
2093 | /* Received high 32 bits of a 64 bit MFI frame address */ | |
2094 | s->frame_hi = val; | |
2095 | break; | |
2096 | case MFI_IQPL: | |
2097 | /* Received low 32 bits of a 64 bit MFI frame address */ | |
e23d0498 | 2098 | /* Fallthrough */ |
e8f943c3 | 2099 | case MFI_IQP: |
e23d0498 | 2100 | /* Received 64 bit MFI frame address */ |
e8f943c3 HR |
2101 | frame_addr = (val & ~0x1F); |
2102 | /* Add possible 64 bit offset */ | |
2103 | frame_addr |= ((uint64_t)s->frame_hi << 32); | |
2104 | s->frame_hi = 0; | |
2105 | frame_count = (val >> 1) & 0xF; | |
2106 | megasas_handle_frame(s, frame_addr, frame_count); | |
2107 | break; | |
e23d0498 HR |
2108 | case MFI_SEQ: |
2109 | /* Magic sequence to start ADP reset */ | |
2110 | if (adp_reset_seq[s->adp_reset] == val) { | |
2111 | s->adp_reset++; | |
2112 | } else { | |
2113 | s->adp_reset = 0; | |
2114 | s->diag = 0; | |
2115 | } | |
2116 | if (s->adp_reset == 6) { | |
2117 | s->diag = MFI_DIAG_WRITE_ENABLE; | |
2118 | } | |
2119 | break; | |
2120 | case MFI_DIAG: | |
2121 | /* ADP reset */ | |
2122 | if ((s->diag & MFI_DIAG_WRITE_ENABLE) && | |
2123 | (val & MFI_DIAG_RESET_ADP)) { | |
2124 | s->diag |= MFI_DIAG_RESET_ADP; | |
2125 | megasas_soft_reset(s); | |
2126 | s->adp_reset = 0; | |
2127 | s->diag = 0; | |
2128 | } | |
2129 | break; | |
e8f943c3 HR |
2130 | default: |
2131 | trace_megasas_mmio_invalid_writel(addr, val); | |
2132 | break; | |
2133 | } | |
2134 | } | |
2135 | ||
2136 | static const MemoryRegionOps megasas_mmio_ops = { | |
2137 | .read = megasas_mmio_read, | |
2138 | .write = megasas_mmio_write, | |
2139 | .endianness = DEVICE_LITTLE_ENDIAN, | |
2140 | .impl = { | |
2141 | .min_access_size = 8, | |
2142 | .max_access_size = 8, | |
2143 | } | |
2144 | }; | |
2145 | ||
a8170e5e | 2146 | static uint64_t megasas_port_read(void *opaque, hwaddr addr, |
e8f943c3 HR |
2147 | unsigned size) |
2148 | { | |
2149 | return megasas_mmio_read(opaque, addr & 0xff, size); | |
2150 | } | |
2151 | ||
a8170e5e | 2152 | static void megasas_port_write(void *opaque, hwaddr addr, |
e8f943c3 HR |
2153 | uint64_t val, unsigned size) |
2154 | { | |
2155 | megasas_mmio_write(opaque, addr & 0xff, val, size); | |
2156 | } | |
2157 | ||
2158 | static const MemoryRegionOps megasas_port_ops = { | |
2159 | .read = megasas_port_read, | |
2160 | .write = megasas_port_write, | |
2161 | .endianness = DEVICE_LITTLE_ENDIAN, | |
2162 | .impl = { | |
2163 | .min_access_size = 4, | |
2164 | .max_access_size = 4, | |
2165 | } | |
2166 | }; | |
2167 | ||
a8170e5e | 2168 | static uint64_t megasas_queue_read(void *opaque, hwaddr addr, |
e8f943c3 HR |
2169 | unsigned size) |
2170 | { | |
2171 | return 0; | |
2172 | } | |
2173 | ||
2174 | static const MemoryRegionOps megasas_queue_ops = { | |
2175 | .read = megasas_queue_read, | |
2176 | .endianness = DEVICE_LITTLE_ENDIAN, | |
2177 | .impl = { | |
2178 | .min_access_size = 8, | |
2179 | .max_access_size = 8, | |
2180 | } | |
2181 | }; | |
2182 | ||
2183 | static void megasas_soft_reset(MegasasState *s) | |
2184 | { | |
2185 | int i; | |
2186 | MegasasCmd *cmd; | |
2187 | ||
2188 | trace_megasas_reset(); | |
2189 | for (i = 0; i < s->fw_cmds; i++) { | |
2190 | cmd = &s->frames[i]; | |
2191 | megasas_abort_command(cmd); | |
2192 | } | |
2193 | megasas_reset_frames(s); | |
2194 | s->reply_queue_len = s->fw_cmds; | |
2195 | s->reply_queue_pa = 0; | |
2196 | s->consumer_pa = 0; | |
2197 | s->producer_pa = 0; | |
2198 | s->fw_state = MFI_FWSTATE_READY; | |
2199 | s->doorbell = 0; | |
2200 | s->intr_mask = MEGASAS_INTR_DISABLED_MASK; | |
2201 | s->frame_hi = 0; | |
2202 | s->flags &= ~MEGASAS_MASK_USE_QUEUE64; | |
2203 | s->event_count++; | |
2204 | s->boot_event = s->event_count; | |
2205 | } | |
2206 | ||
2207 | static void megasas_scsi_reset(DeviceState *dev) | |
2208 | { | |
c79e16ae | 2209 | MegasasState *s = MEGASAS(dev); |
e8f943c3 HR |
2210 | |
2211 | megasas_soft_reset(s); | |
2212 | } | |
2213 | ||
e23d0498 | 2214 | static const VMStateDescription vmstate_megasas_gen1 = { |
e8f943c3 HR |
2215 | .name = "megasas", |
2216 | .version_id = 0, | |
2217 | .minimum_version_id = 0, | |
d49805ae | 2218 | .fields = (VMStateField[]) { |
52190c1e | 2219 | VMSTATE_PCI_DEVICE(parent_obj, MegasasState), |
23335f62 | 2220 | VMSTATE_MSIX(parent_obj, MegasasState), |
e8f943c3 HR |
2221 | |
2222 | VMSTATE_INT32(fw_state, MegasasState), | |
2223 | VMSTATE_INT32(intr_mask, MegasasState), | |
2224 | VMSTATE_INT32(doorbell, MegasasState), | |
2225 | VMSTATE_UINT64(reply_queue_pa, MegasasState), | |
2226 | VMSTATE_UINT64(consumer_pa, MegasasState), | |
2227 | VMSTATE_UINT64(producer_pa, MegasasState), | |
2228 | VMSTATE_END_OF_LIST() | |
2229 | } | |
2230 | }; | |
2231 | ||
e23d0498 HR |
2232 | static const VMStateDescription vmstate_megasas_gen2 = { |
2233 | .name = "megasas-gen2", | |
2234 | .version_id = 0, | |
2235 | .minimum_version_id = 0, | |
2236 | .minimum_version_id_old = 0, | |
2237 | .fields = (VMStateField[]) { | |
2238 | VMSTATE_PCIE_DEVICE(parent_obj, MegasasState), | |
2239 | VMSTATE_MSIX(parent_obj, MegasasState), | |
2240 | ||
2241 | VMSTATE_INT32(fw_state, MegasasState), | |
2242 | VMSTATE_INT32(intr_mask, MegasasState), | |
2243 | VMSTATE_INT32(doorbell, MegasasState), | |
2244 | VMSTATE_UINT64(reply_queue_pa, MegasasState), | |
2245 | VMSTATE_UINT64(consumer_pa, MegasasState), | |
2246 | VMSTATE_UINT64(producer_pa, MegasasState), | |
2247 | VMSTATE_END_OF_LIST() | |
2248 | } | |
2249 | }; | |
2250 | ||
18fc611b | 2251 | static void megasas_scsi_uninit(PCIDevice *d) |
e8f943c3 | 2252 | { |
c79e16ae | 2253 | MegasasState *s = MEGASAS(d); |
e8f943c3 | 2254 | |
4522b69c HR |
2255 | if (megasas_use_msix(s)) { |
2256 | msix_uninit(d, &s->mmio_io, &s->mmio_io); | |
2257 | } | |
2258 | if (megasas_use_msi(s)) { | |
2259 | msi_uninit(d); | |
2260 | } | |
e8f943c3 HR |
2261 | } |
2262 | ||
2263 | static const struct SCSIBusInfo megasas_scsi_info = { | |
2264 | .tcq = true, | |
2265 | .max_target = MFI_MAX_LD, | |
2266 | .max_lun = 255, | |
2267 | ||
2268 | .transfer_data = megasas_xfer_complete, | |
2269 | .get_sg_list = megasas_get_sg_list, | |
2270 | .complete = megasas_command_complete, | |
2271 | .cancel = megasas_command_cancel, | |
2272 | }; | |
2273 | ||
2274 | static int megasas_scsi_init(PCIDevice *dev) | |
2275 | { | |
22d6aa03 | 2276 | DeviceState *d = DEVICE(dev); |
c79e16ae | 2277 | MegasasState *s = MEGASAS(dev); |
e23d0498 | 2278 | MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s); |
e8f943c3 HR |
2279 | uint8_t *pci_conf; |
2280 | int i, bar_type; | |
caad4eb3 | 2281 | Error *err = NULL; |
e8f943c3 | 2282 | |
52190c1e | 2283 | pci_conf = dev->config; |
e8f943c3 HR |
2284 | |
2285 | /* PCI latency timer = 0 */ | |
2286 | pci_conf[PCI_LATENCY_TIMER] = 0; | |
2287 | /* Interrupt pin 1 */ | |
2288 | pci_conf[PCI_INTERRUPT_PIN] = 0x01; | |
2289 | ||
29776739 | 2290 | memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s, |
e8f943c3 | 2291 | "megasas-mmio", 0x4000); |
29776739 | 2292 | memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s, |
e8f943c3 | 2293 | "megasas-io", 256); |
29776739 | 2294 | memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s, |
e8f943c3 HR |
2295 | "megasas-queue", 0x40000); |
2296 | ||
4522b69c HR |
2297 | if (megasas_use_msi(s) && |
2298 | msi_init(dev, 0x50, 1, true, false)) { | |
2299 | s->flags &= ~MEGASAS_MASK_USE_MSI; | |
2300 | } | |
e8f943c3 | 2301 | if (megasas_use_msix(s) && |
e23d0498 HR |
2302 | msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000, |
2303 | &s->mmio_io, b->mmio_bar, 0x3800, 0x68)) { | |
e8f943c3 HR |
2304 | s->flags &= ~MEGASAS_MASK_USE_MSIX; |
2305 | } | |
e23d0498 HR |
2306 | if (pci_is_express(dev)) { |
2307 | pcie_endpoint_cap_init(dev, 0xa0); | |
2308 | } | |
e8f943c3 HR |
2309 | |
2310 | bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64; | |
e23d0498 HR |
2311 | pci_register_bar(dev, b->ioport_bar, |
2312 | PCI_BASE_ADDRESS_SPACE_IO, &s->port_io); | |
2313 | pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io); | |
52190c1e | 2314 | pci_register_bar(dev, 3, bar_type, &s->queue_io); |
e8f943c3 HR |
2315 | |
2316 | if (megasas_use_msix(s)) { | |
52190c1e | 2317 | msix_vector_use(dev, 0); |
e8f943c3 HR |
2318 | } |
2319 | ||
76b523db HR |
2320 | if (!s->sas_addr) { |
2321 | s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) | | |
2322 | IEEE_COMPANY_LOCALLY_ASSIGNED) << 36; | |
2323 | s->sas_addr |= (pci_bus_num(dev->bus) << 16); | |
2324 | s->sas_addr |= (PCI_SLOT(dev->devfn) << 8); | |
2325 | s->sas_addr |= PCI_FUNC(dev->devfn); | |
2326 | } | |
fb654157 | 2327 | if (!s->hba_serial) { |
23335f62 | 2328 | s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL); |
fb654157 | 2329 | } |
e8f943c3 HR |
2330 | if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) { |
2331 | s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE; | |
2332 | } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) { | |
2333 | s->fw_sge = 128 - MFI_PASS_FRAME_SIZE; | |
2334 | } else { | |
2335 | s->fw_sge = 64 - MFI_PASS_FRAME_SIZE; | |
2336 | } | |
2337 | if (s->fw_cmds > MEGASAS_MAX_FRAMES) { | |
2338 | s->fw_cmds = MEGASAS_MAX_FRAMES; | |
2339 | } | |
2340 | trace_megasas_init(s->fw_sge, s->fw_cmds, | |
e8f943c3 | 2341 | megasas_is_jbod(s) ? "jbod" : "raid"); |
3f2cd4dd HR |
2342 | |
2343 | if (megasas_is_jbod(s)) { | |
2344 | s->fw_luns = MFI_MAX_SYS_PDS; | |
2345 | } else { | |
2346 | s->fw_luns = MFI_MAX_LD; | |
2347 | } | |
e8f943c3 HR |
2348 | s->producer_pa = 0; |
2349 | s->consumer_pa = 0; | |
2350 | for (i = 0; i < s->fw_cmds; i++) { | |
2351 | s->frames[i].index = i; | |
2352 | s->frames[i].context = -1; | |
2353 | s->frames[i].pa = 0; | |
2354 | s->frames[i].state = s; | |
2355 | } | |
2356 | ||
b1187b51 AF |
2357 | scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev), |
2358 | &megasas_scsi_info, NULL); | |
22d6aa03 | 2359 | if (!d->hotplugged) { |
caad4eb3 AF |
2360 | scsi_bus_legacy_handle_cmdline(&s->bus, &err); |
2361 | if (err != NULL) { | |
2362 | error_free(err); | |
2363 | return -1; | |
2364 | } | |
22d6aa03 | 2365 | } |
e8f943c3 HR |
2366 | return 0; |
2367 | } | |
2368 | ||
4522b69c HR |
2369 | static void |
2370 | megasas_write_config(PCIDevice *pci, uint32_t addr, uint32_t val, int len) | |
2371 | { | |
2372 | pci_default_write_config(pci, addr, val, len); | |
2373 | msi_write_config(pci, addr, val, len); | |
2374 | } | |
2375 | ||
e23d0498 | 2376 | static Property megasas_properties_gen1[] = { |
e8f943c3 HR |
2377 | DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge, |
2378 | MEGASAS_DEFAULT_SGE), | |
2379 | DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds, | |
2380 | MEGASAS_DEFAULT_FRAMES), | |
fb654157 | 2381 | DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial), |
c7bcc85d | 2382 | DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0), |
4522b69c HR |
2383 | DEFINE_PROP_BIT("use_msi", MegasasState, flags, |
2384 | MEGASAS_FLAG_USE_MSI, false), | |
e8f943c3 HR |
2385 | DEFINE_PROP_BIT("use_msix", MegasasState, flags, |
2386 | MEGASAS_FLAG_USE_MSIX, false), | |
e8f943c3 HR |
2387 | DEFINE_PROP_BIT("use_jbod", MegasasState, flags, |
2388 | MEGASAS_FLAG_USE_JBOD, false), | |
2389 | DEFINE_PROP_END_OF_LIST(), | |
2390 | }; | |
2391 | ||
e23d0498 HR |
2392 | static Property megasas_properties_gen2[] = { |
2393 | DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge, | |
2394 | MEGASAS_DEFAULT_SGE), | |
2395 | DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds, | |
2396 | MEGASAS_GEN2_DEFAULT_FRAMES), | |
2397 | DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial), | |
2398 | DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0), | |
2399 | DEFINE_PROP_BIT("use_msi", MegasasState, flags, | |
2400 | MEGASAS_FLAG_USE_MSI, true), | |
2401 | DEFINE_PROP_BIT("use_msix", MegasasState, flags, | |
2402 | MEGASAS_FLAG_USE_MSIX, true), | |
2403 | DEFINE_PROP_BIT("use_jbod", MegasasState, flags, | |
2404 | MEGASAS_FLAG_USE_JBOD, false), | |
2405 | DEFINE_PROP_END_OF_LIST(), | |
2406 | }; | |
2407 | ||
2408 | typedef struct MegasasInfo { | |
2409 | const char *name; | |
2410 | const char *desc; | |
2411 | const char *product_name; | |
2412 | const char *product_version; | |
2413 | uint16_t device_id; | |
2414 | uint16_t subsystem_id; | |
2415 | int ioport_bar; | |
2416 | int mmio_bar; | |
2417 | bool is_express; | |
2418 | int osts; | |
2419 | const VMStateDescription *vmsd; | |
2420 | Property *props; | |
2421 | } MegasasInfo; | |
2422 | ||
2423 | static struct MegasasInfo megasas_devices[] = { | |
2424 | { | |
2425 | .name = TYPE_MEGASAS_GEN1, | |
2426 | .desc = "LSI MegaRAID SAS 1078", | |
2427 | .product_name = "LSI MegaRAID SAS 8708EM2", | |
2428 | .product_version = MEGASAS_VERSION_GEN1, | |
2429 | .device_id = PCI_DEVICE_ID_LSI_SAS1078, | |
2430 | .subsystem_id = 0x1013, | |
2431 | .ioport_bar = 2, | |
2432 | .mmio_bar = 0, | |
2433 | .osts = MFI_1078_RM | 1, | |
2434 | .is_express = false, | |
2435 | .vmsd = &vmstate_megasas_gen1, | |
2436 | .props = megasas_properties_gen1, | |
2437 | },{ | |
2438 | .name = TYPE_MEGASAS_GEN2, | |
2439 | .desc = "LSI MegaRAID SAS 2108", | |
2440 | .product_name = "LSI MegaRAID SAS 9260-8i", | |
2441 | .product_version = MEGASAS_VERSION_GEN2, | |
2442 | .device_id = PCI_DEVICE_ID_LSI_SAS0079, | |
2443 | .subsystem_id = 0x9261, | |
2444 | .ioport_bar = 0, | |
2445 | .mmio_bar = 1, | |
2446 | .osts = MFI_GEN2_RM, | |
2447 | .is_express = true, | |
2448 | .vmsd = &vmstate_megasas_gen2, | |
2449 | .props = megasas_properties_gen2, | |
2450 | } | |
2451 | }; | |
2452 | ||
e8f943c3 HR |
2453 | static void megasas_class_init(ObjectClass *oc, void *data) |
2454 | { | |
2455 | DeviceClass *dc = DEVICE_CLASS(oc); | |
2456 | PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); | |
e23d0498 HR |
2457 | MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc); |
2458 | const MegasasInfo *info = data; | |
e8f943c3 HR |
2459 | |
2460 | pc->init = megasas_scsi_init; | |
2461 | pc->exit = megasas_scsi_uninit; | |
2462 | pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC; | |
e23d0498 | 2463 | pc->device_id = info->device_id; |
e8f943c3 | 2464 | pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC; |
e23d0498 | 2465 | pc->subsystem_id = info->subsystem_id; |
e8f943c3 | 2466 | pc->class_id = PCI_CLASS_STORAGE_RAID; |
e23d0498 HR |
2467 | pc->is_express = info->is_express; |
2468 | e->mmio_bar = info->mmio_bar; | |
2469 | e->ioport_bar = info->ioport_bar; | |
2470 | e->osts = info->osts; | |
2471 | e->product_name = info->product_name; | |
2472 | e->product_version = info->product_version; | |
2473 | dc->props = info->props; | |
e8f943c3 | 2474 | dc->reset = megasas_scsi_reset; |
e23d0498 | 2475 | dc->vmsd = info->vmsd; |
125ee0ed | 2476 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
e23d0498 | 2477 | dc->desc = info->desc; |
4522b69c | 2478 | pc->config_write = megasas_write_config; |
e8f943c3 HR |
2479 | } |
2480 | ||
2481 | static const TypeInfo megasas_info = { | |
e23d0498 | 2482 | .name = TYPE_MEGASAS_BASE, |
e8f943c3 HR |
2483 | .parent = TYPE_PCI_DEVICE, |
2484 | .instance_size = sizeof(MegasasState), | |
e23d0498 HR |
2485 | .class_size = sizeof(MegasasBaseClass), |
2486 | .abstract = true, | |
e8f943c3 HR |
2487 | }; |
2488 | ||
2489 | static void megasas_register_types(void) | |
2490 | { | |
e23d0498 HR |
2491 | int i; |
2492 | ||
e8f943c3 | 2493 | type_register_static(&megasas_info); |
e23d0498 HR |
2494 | for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) { |
2495 | const MegasasInfo *info = &megasas_devices[i]; | |
2496 | TypeInfo type_info = {}; | |
2497 | ||
2498 | type_info.name = info->name; | |
2499 | type_info.parent = TYPE_MEGASAS_BASE; | |
2500 | type_info.class_data = (void *)info; | |
2501 | type_info.class_init = megasas_class_init; | |
2502 | ||
2503 | type_register(&type_info); | |
2504 | } | |
e8f943c3 HR |
2505 | } |
2506 | ||
2507 | type_init(megasas_register_types) |