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881d588a DF |
1 | /* |
2 | * QEMU VMWARE PVSCSI paravirtual SCSI bus | |
3 | * | |
4 | * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) | |
5 | * | |
6 | * Developed by Daynix Computing LTD (http://www.daynix.com) | |
7 | * | |
8 | * Based on implementation by Paolo Bonzini | |
9 | * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html | |
10 | * | |
11 | * Authors: | |
12 | * Paolo Bonzini <pbonzini@redhat.com> | |
13 | * Dmitry Fleytman <dmitry@daynix.com> | |
14 | * Yan Vugenfirer <yan@daynix.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. | |
17 | * See the COPYING file in the top-level directory. | |
18 | * | |
19 | * NOTE about MSI-X: | |
20 | * MSI-X support has been removed for the moment because it leads Windows OS | |
21 | * to crash on startup. The crash happens because Windows driver requires | |
22 | * MSI-X shared memory to be part of the same BAR used for rings state | |
23 | * registers, etc. This is not supported by QEMU infrastructure so separate | |
24 | * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs. | |
25 | * | |
26 | */ | |
27 | ||
a4ab4792 | 28 | #include "qemu/osdep.h" |
881d588a DF |
29 | #include "hw/scsi/scsi.h" |
30 | #include <block/scsi.h> | |
31 | #include "hw/pci/msi.h" | |
32 | #include "vmw_pvscsi.h" | |
33 | #include "trace.h" | |
34 | ||
35 | ||
881d588a DF |
36 | #define PVSCSI_USE_64BIT (true) |
37 | #define PVSCSI_PER_VECTOR_MASK (false) | |
38 | ||
39 | #define PVSCSI_MAX_DEVS (64) | |
40 | #define PVSCSI_MSIX_NUM_VECTORS (1) | |
41 | ||
42 | #define PVSCSI_MAX_CMD_DATA_WORDS \ | |
43 | (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t)) | |
44 | ||
0dc40f28 PB |
45 | #define RS_GET_FIELD(m, field) \ |
46 | (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ | |
47 | (m)->rs_pa + offsetof(struct PVSCSIRingsState, field))) | |
48 | #define RS_SET_FIELD(m, field, val) \ | |
49 | (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ | |
50 | (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val)) | |
881d588a | 51 | |
e2d4f3f7 SL |
52 | typedef struct PVSCSIClass { |
53 | PCIDeviceClass parent_class; | |
1dd1305e | 54 | DeviceRealize parent_dc_realize; |
e2d4f3f7 SL |
55 | } PVSCSIClass; |
56 | ||
881d588a DF |
57 | #define TYPE_PVSCSI "pvscsi" |
58 | #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI) | |
59 | ||
e2d4f3f7 SL |
60 | #define PVSCSI_DEVICE_CLASS(klass) \ |
61 | OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI) | |
62 | #define PVSCSI_DEVICE_GET_CLASS(obj) \ | |
63 | OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI) | |
64 | ||
d29d4ff8 SL |
65 | /* Compatability flags for migration */ |
66 | #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0 | |
67 | #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \ | |
68 | (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT) | |
1dd1305e SL |
69 | #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1 |
70 | #define PVSCSI_COMPAT_DISABLE_PCIE \ | |
71 | (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT) | |
d29d4ff8 SL |
72 | |
73 | #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \ | |
74 | ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION) | |
836fc48c SL |
75 | #define PVSCSI_MSI_OFFSET(s) \ |
76 | (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c) | |
1dd1305e | 77 | #define PVSCSI_EXP_EP_OFFSET (0x40) |
d29d4ff8 | 78 | |
881d588a DF |
79 | typedef struct PVSCSIRingInfo { |
80 | uint64_t rs_pa; | |
81 | uint32_t txr_len_mask; | |
82 | uint32_t rxr_len_mask; | |
83 | uint32_t msg_len_mask; | |
84 | uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; | |
85 | uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; | |
86 | uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES]; | |
87 | uint64_t consumed_ptr; | |
88 | uint64_t filled_cmp_ptr; | |
89 | uint64_t filled_msg_ptr; | |
90 | } PVSCSIRingInfo; | |
91 | ||
92 | typedef struct PVSCSISGState { | |
93 | hwaddr elemAddr; | |
94 | hwaddr dataAddr; | |
95 | uint32_t resid; | |
96 | } PVSCSISGState; | |
97 | ||
98 | typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList; | |
99 | ||
100 | typedef struct { | |
101 | PCIDevice parent_obj; | |
102 | MemoryRegion io_space; | |
103 | SCSIBus bus; | |
104 | QEMUBH *completion_worker; | |
105 | PVSCSIRequestList pending_queue; | |
106 | PVSCSIRequestList completion_queue; | |
107 | ||
108 | uint64_t reg_interrupt_status; /* Interrupt status register value */ | |
109 | uint64_t reg_interrupt_enabled; /* Interrupt mask register value */ | |
110 | uint64_t reg_command_status; /* Command status register value */ | |
111 | ||
112 | /* Command data adoption mechanism */ | |
113 | uint64_t curr_cmd; /* Last command arrived */ | |
114 | uint32_t curr_cmd_data_cntr; /* Amount of data for last command */ | |
115 | ||
116 | /* Collector for current command data */ | |
117 | uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS]; | |
118 | ||
119 | uint8_t rings_info_valid; /* Whether data rings initialized */ | |
120 | uint8_t msg_ring_info_valid; /* Whether message ring initialized */ | |
121 | uint8_t use_msg; /* Whether to use message ring */ | |
122 | ||
123 | uint8_t msi_used; /* Whether MSI support was installed successfully */ | |
124 | ||
125 | PVSCSIRingInfo rings; /* Data transfer rings manager */ | |
126 | uint32_t resetting; /* Reset in progress */ | |
d29d4ff8 SL |
127 | |
128 | uint32_t compat_flags; | |
881d588a DF |
129 | } PVSCSIState; |
130 | ||
131 | typedef struct PVSCSIRequest { | |
132 | SCSIRequest *sreq; | |
133 | PVSCSIState *dev; | |
134 | uint8_t sense_key; | |
135 | uint8_t completed; | |
136 | int lun; | |
137 | QEMUSGList sgl; | |
138 | PVSCSISGState sg; | |
139 | struct PVSCSIRingReqDesc req; | |
140 | struct PVSCSIRingCmpDesc cmp; | |
141 | QTAILQ_ENTRY(PVSCSIRequest) next; | |
142 | } PVSCSIRequest; | |
143 | ||
144 | /* Integer binary logarithm */ | |
145 | static int | |
146 | pvscsi_log2(uint32_t input) | |
147 | { | |
148 | int log = 0; | |
149 | assert(input > 0); | |
150 | while (input >> ++log) { | |
151 | } | |
152 | return log; | |
153 | } | |
154 | ||
155 | static void | |
156 | pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri) | |
157 | { | |
158 | int i; | |
159 | uint32_t txr_len_log2, rxr_len_log2; | |
160 | uint32_t req_ring_size, cmp_ring_size; | |
161 | m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT; | |
162 | ||
163 | req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; | |
164 | cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; | |
165 | txr_len_log2 = pvscsi_log2(req_ring_size - 1); | |
166 | rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1); | |
167 | ||
168 | m->txr_len_mask = MASK(txr_len_log2); | |
169 | m->rxr_len_mask = MASK(rxr_len_log2); | |
170 | ||
171 | m->consumed_ptr = 0; | |
172 | m->filled_cmp_ptr = 0; | |
173 | ||
174 | for (i = 0; i < ri->reqRingNumPages; i++) { | |
175 | m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT; | |
176 | } | |
177 | ||
178 | for (i = 0; i < ri->cmpRingNumPages; i++) { | |
179 | m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT; | |
180 | } | |
181 | ||
0dc40f28 PB |
182 | RS_SET_FIELD(m, reqProdIdx, 0); |
183 | RS_SET_FIELD(m, reqConsIdx, 0); | |
184 | RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2); | |
881d588a | 185 | |
0dc40f28 PB |
186 | RS_SET_FIELD(m, cmpProdIdx, 0); |
187 | RS_SET_FIELD(m, cmpConsIdx, 0); | |
188 | RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2); | |
881d588a DF |
189 | |
190 | trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2); | |
191 | ||
192 | /* Flush ring state page changes */ | |
193 | smp_wmb(); | |
194 | } | |
195 | ||
196 | static void | |
197 | pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri) | |
198 | { | |
199 | int i; | |
200 | uint32_t len_log2; | |
201 | uint32_t ring_size; | |
202 | ||
203 | ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; | |
204 | len_log2 = pvscsi_log2(ring_size - 1); | |
205 | ||
206 | m->msg_len_mask = MASK(len_log2); | |
207 | ||
208 | m->filled_msg_ptr = 0; | |
209 | ||
210 | for (i = 0; i < ri->numPages; i++) { | |
211 | m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT; | |
212 | } | |
213 | ||
0dc40f28 PB |
214 | RS_SET_FIELD(m, msgProdIdx, 0); |
215 | RS_SET_FIELD(m, msgConsIdx, 0); | |
216 | RS_SET_FIELD(m, msgNumEntriesLog2, len_log2); | |
881d588a DF |
217 | |
218 | trace_pvscsi_ring_init_msg(len_log2); | |
219 | ||
220 | /* Flush ring state page changes */ | |
221 | smp_wmb(); | |
222 | } | |
223 | ||
224 | static void | |
225 | pvscsi_ring_cleanup(PVSCSIRingInfo *mgr) | |
226 | { | |
227 | mgr->rs_pa = 0; | |
228 | mgr->txr_len_mask = 0; | |
229 | mgr->rxr_len_mask = 0; | |
230 | mgr->msg_len_mask = 0; | |
231 | mgr->consumed_ptr = 0; | |
232 | mgr->filled_cmp_ptr = 0; | |
233 | mgr->filled_msg_ptr = 0; | |
234 | memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa)); | |
235 | memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa)); | |
236 | memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa)); | |
237 | } | |
238 | ||
239 | static hwaddr | |
240 | pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr) | |
241 | { | |
0dc40f28 | 242 | uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx); |
881d588a DF |
243 | |
244 | if (ready_ptr != mgr->consumed_ptr) { | |
245 | uint32_t next_ready_ptr = | |
246 | mgr->consumed_ptr++ & mgr->txr_len_mask; | |
247 | uint32_t next_ready_page = | |
248 | next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; | |
249 | uint32_t inpage_idx = | |
250 | next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; | |
251 | ||
252 | return mgr->req_ring_pages_pa[next_ready_page] + | |
253 | inpage_idx * sizeof(PVSCSIRingReqDesc); | |
254 | } else { | |
255 | return 0; | |
256 | } | |
257 | } | |
258 | ||
259 | static void | |
260 | pvscsi_ring_flush_req(PVSCSIRingInfo *mgr) | |
261 | { | |
0dc40f28 | 262 | RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr); |
881d588a DF |
263 | } |
264 | ||
265 | static hwaddr | |
266 | pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr) | |
267 | { | |
268 | /* | |
269 | * According to Linux driver code it explicitly verifies that number | |
270 | * of requests being processed by device is less then the size of | |
271 | * completion queue, so device may omit completion queue overflow | |
272 | * conditions check. We assume that this is true for other (Windows) | |
273 | * drivers as well. | |
274 | */ | |
275 | ||
276 | uint32_t free_cmp_ptr = | |
277 | mgr->filled_cmp_ptr++ & mgr->rxr_len_mask; | |
278 | uint32_t free_cmp_page = | |
279 | free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; | |
280 | uint32_t inpage_idx = | |
281 | free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; | |
282 | return mgr->cmp_ring_pages_pa[free_cmp_page] + | |
283 | inpage_idx * sizeof(PVSCSIRingCmpDesc); | |
284 | } | |
285 | ||
286 | static hwaddr | |
287 | pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr) | |
288 | { | |
289 | uint32_t free_msg_ptr = | |
290 | mgr->filled_msg_ptr++ & mgr->msg_len_mask; | |
291 | uint32_t free_msg_page = | |
292 | free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; | |
293 | uint32_t inpage_idx = | |
294 | free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; | |
295 | return mgr->msg_ring_pages_pa[free_msg_page] + | |
296 | inpage_idx * sizeof(PVSCSIRingMsgDesc); | |
297 | } | |
298 | ||
299 | static void | |
300 | pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr) | |
301 | { | |
302 | /* Flush descriptor changes */ | |
303 | smp_wmb(); | |
304 | ||
305 | trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr); | |
306 | ||
0dc40f28 | 307 | RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr); |
881d588a DF |
308 | } |
309 | ||
310 | static bool | |
311 | pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr) | |
312 | { | |
0dc40f28 PB |
313 | uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx); |
314 | uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx); | |
881d588a DF |
315 | |
316 | return (prodIdx - consIdx) < (mgr->msg_len_mask + 1); | |
317 | } | |
318 | ||
319 | static void | |
320 | pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr) | |
321 | { | |
322 | /* Flush descriptor changes */ | |
323 | smp_wmb(); | |
324 | ||
325 | trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr); | |
326 | ||
0dc40f28 | 327 | RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr); |
881d588a DF |
328 | } |
329 | ||
330 | static void | |
331 | pvscsi_reset_state(PVSCSIState *s) | |
332 | { | |
333 | s->curr_cmd = PVSCSI_CMD_FIRST; | |
334 | s->curr_cmd_data_cntr = 0; | |
335 | s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED; | |
336 | s->reg_interrupt_status = 0; | |
337 | pvscsi_ring_cleanup(&s->rings); | |
338 | s->rings_info_valid = FALSE; | |
339 | s->msg_ring_info_valid = FALSE; | |
340 | QTAILQ_INIT(&s->pending_queue); | |
341 | QTAILQ_INIT(&s->completion_queue); | |
342 | } | |
343 | ||
344 | static void | |
345 | pvscsi_update_irq_status(PVSCSIState *s) | |
346 | { | |
347 | PCIDevice *d = PCI_DEVICE(s); | |
348 | bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status; | |
349 | ||
350 | trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled, | |
351 | s->reg_interrupt_status); | |
352 | ||
353 | if (s->msi_used && msi_enabled(d)) { | |
354 | if (should_raise) { | |
355 | trace_pvscsi_update_irq_msi(); | |
356 | msi_notify(d, PVSCSI_VECTOR_COMPLETION); | |
357 | } | |
358 | return; | |
359 | } | |
360 | ||
9e64f8a3 | 361 | pci_set_irq(d, !!should_raise); |
881d588a DF |
362 | } |
363 | ||
364 | static void | |
365 | pvscsi_raise_completion_interrupt(PVSCSIState *s) | |
366 | { | |
367 | s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0; | |
368 | ||
369 | /* Memory barrier to flush interrupt status register changes*/ | |
370 | smp_wmb(); | |
371 | ||
372 | pvscsi_update_irq_status(s); | |
373 | } | |
374 | ||
375 | static void | |
376 | pvscsi_raise_message_interrupt(PVSCSIState *s) | |
377 | { | |
378 | s->reg_interrupt_status |= PVSCSI_INTR_MSG_0; | |
379 | ||
380 | /* Memory barrier to flush interrupt status register changes*/ | |
381 | smp_wmb(); | |
382 | ||
383 | pvscsi_update_irq_status(s); | |
384 | } | |
385 | ||
386 | static void | |
387 | pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc) | |
388 | { | |
389 | hwaddr cmp_descr_pa; | |
390 | ||
391 | cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); | |
392 | trace_pvscsi_cmp_ring_put(cmp_descr_pa); | |
393 | cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc, | |
394 | sizeof(*cmp_desc)); | |
395 | } | |
396 | ||
397 | static void | |
398 | pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc) | |
399 | { | |
400 | hwaddr msg_descr_pa; | |
401 | ||
402 | msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); | |
403 | trace_pvscsi_msg_ring_put(msg_descr_pa); | |
404 | cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc, | |
405 | sizeof(*msg_desc)); | |
406 | } | |
407 | ||
408 | static void | |
409 | pvscsi_process_completion_queue(void *opaque) | |
410 | { | |
411 | PVSCSIState *s = opaque; | |
412 | PVSCSIRequest *pvscsi_req; | |
413 | bool has_completed = false; | |
414 | ||
415 | while (!QTAILQ_EMPTY(&s->completion_queue)) { | |
416 | pvscsi_req = QTAILQ_FIRST(&s->completion_queue); | |
417 | QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next); | |
418 | pvscsi_cmp_ring_put(s, &pvscsi_req->cmp); | |
419 | g_free(pvscsi_req); | |
dcb07809 | 420 | has_completed = true; |
881d588a DF |
421 | } |
422 | ||
423 | if (has_completed) { | |
424 | pvscsi_ring_flush_cmp(&s->rings); | |
425 | pvscsi_raise_completion_interrupt(s); | |
426 | } | |
427 | } | |
428 | ||
429 | static void | |
430 | pvscsi_reset_adapter(PVSCSIState *s) | |
431 | { | |
432 | s->resetting++; | |
433 | qbus_reset_all_fn(&s->bus); | |
434 | s->resetting--; | |
435 | pvscsi_process_completion_queue(s); | |
436 | assert(QTAILQ_EMPTY(&s->pending_queue)); | |
437 | pvscsi_reset_state(s); | |
438 | } | |
439 | ||
440 | static void | |
441 | pvscsi_schedule_completion_processing(PVSCSIState *s) | |
442 | { | |
443 | /* Try putting more complete requests on the ring. */ | |
444 | if (!QTAILQ_EMPTY(&s->completion_queue)) { | |
445 | qemu_bh_schedule(s->completion_worker); | |
446 | } | |
447 | } | |
448 | ||
449 | static void | |
450 | pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r) | |
451 | { | |
452 | assert(!r->completed); | |
453 | ||
454 | trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen, | |
455 | r->sense_key); | |
456 | if (r->sreq != NULL) { | |
457 | scsi_req_unref(r->sreq); | |
458 | r->sreq = NULL; | |
459 | } | |
460 | r->completed = 1; | |
461 | QTAILQ_REMOVE(&s->pending_queue, r, next); | |
462 | QTAILQ_INSERT_TAIL(&s->completion_queue, r, next); | |
463 | pvscsi_schedule_completion_processing(s); | |
464 | } | |
465 | ||
466 | static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r) | |
467 | { | |
468 | PVSCSIRequest *req = r->hba_private; | |
469 | ||
470 | trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size); | |
471 | ||
472 | return &req->sgl; | |
473 | } | |
474 | ||
475 | static void | |
476 | pvscsi_get_next_sg_elem(PVSCSISGState *sg) | |
477 | { | |
478 | struct PVSCSISGElement elem; | |
479 | ||
480 | cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem)); | |
481 | if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) { | |
482 | /* | |
483 | * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in | |
484 | * header file but its value is unknown. This flag requires | |
485 | * additional processing, so we put warning here to catch it | |
486 | * some day and make proper implementation | |
487 | */ | |
488 | trace_pvscsi_get_next_sg_elem(elem.flags); | |
489 | } | |
490 | ||
491 | sg->elemAddr += sizeof(elem); | |
492 | sg->dataAddr = elem.addr; | |
493 | sg->resid = elem.length; | |
494 | } | |
495 | ||
496 | static void | |
497 | pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len) | |
498 | { | |
499 | r->cmp.senseLen = MIN(r->req.senseLen, len); | |
500 | r->sense_key = sense[(sense[0] & 2) ? 1 : 2]; | |
501 | cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen); | |
502 | } | |
503 | ||
504 | static void | |
505 | pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid) | |
506 | { | |
507 | PVSCSIRequest *pvscsi_req = req->hba_private; | |
b0f49d13 | 508 | PVSCSIState *s; |
881d588a DF |
509 | |
510 | if (!pvscsi_req) { | |
511 | trace_pvscsi_command_complete_not_found(req->tag); | |
512 | return; | |
513 | } | |
b0f49d13 | 514 | s = pvscsi_req->dev; |
881d588a DF |
515 | |
516 | if (resid) { | |
517 | /* Short transfer. */ | |
518 | trace_pvscsi_command_complete_data_run(); | |
519 | pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN; | |
520 | } | |
521 | ||
522 | pvscsi_req->cmp.scsiStatus = status; | |
523 | if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) { | |
524 | uint8_t sense[SCSI_SENSE_BUF_SIZE]; | |
525 | int sense_len = | |
526 | scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense)); | |
527 | ||
528 | trace_pvscsi_command_complete_sense_len(sense_len); | |
529 | pvscsi_write_sense(pvscsi_req, sense, sense_len); | |
530 | } | |
531 | qemu_sglist_destroy(&pvscsi_req->sgl); | |
532 | pvscsi_complete_request(s, pvscsi_req); | |
533 | } | |
534 | ||
535 | static void | |
536 | pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type) | |
537 | { | |
538 | if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) { | |
539 | PVSCSIMsgDescDevStatusChanged msg = {0}; | |
540 | ||
541 | msg.type = msg_type; | |
542 | msg.bus = dev->channel; | |
543 | msg.target = dev->id; | |
544 | msg.lun[1] = dev->lun; | |
545 | ||
546 | pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg); | |
547 | pvscsi_ring_flush_msg(&s->rings); | |
548 | pvscsi_raise_message_interrupt(s); | |
549 | } | |
550 | } | |
551 | ||
552 | static void | |
91c8daad | 553 | pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) |
881d588a | 554 | { |
91c8daad IM |
555 | PVSCSIState *s = PVSCSI(hotplug_dev); |
556 | ||
557 | pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED); | |
881d588a DF |
558 | } |
559 | ||
560 | static void | |
91c8daad | 561 | pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) |
881d588a | 562 | { |
91c8daad IM |
563 | PVSCSIState *s = PVSCSI(hotplug_dev); |
564 | ||
565 | pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED); | |
566 | qdev_simple_device_unplug_cb(hotplug_dev, dev, errp); | |
881d588a DF |
567 | } |
568 | ||
569 | static void | |
570 | pvscsi_request_cancelled(SCSIRequest *req) | |
571 | { | |
572 | PVSCSIRequest *pvscsi_req = req->hba_private; | |
573 | PVSCSIState *s = pvscsi_req->dev; | |
574 | ||
575 | if (pvscsi_req->completed) { | |
576 | return; | |
577 | } | |
578 | ||
579 | if (pvscsi_req->dev->resetting) { | |
580 | pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET; | |
581 | } else { | |
582 | pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE; | |
583 | } | |
584 | ||
585 | pvscsi_complete_request(s, pvscsi_req); | |
586 | } | |
587 | ||
588 | static SCSIDevice* | |
589 | pvscsi_device_find(PVSCSIState *s, int channel, int target, | |
590 | uint8_t *requested_lun, uint8_t *target_lun) | |
591 | { | |
592 | if (requested_lun[0] || requested_lun[2] || requested_lun[3] || | |
593 | requested_lun[4] || requested_lun[5] || requested_lun[6] || | |
594 | requested_lun[7] || (target > PVSCSI_MAX_DEVS)) { | |
595 | return NULL; | |
596 | } else { | |
597 | *target_lun = requested_lun[1]; | |
598 | return scsi_device_find(&s->bus, channel, target, *target_lun); | |
599 | } | |
600 | } | |
601 | ||
602 | static PVSCSIRequest * | |
603 | pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d, | |
604 | struct PVSCSIRingReqDesc *descr) | |
605 | { | |
606 | PVSCSIRequest *pvscsi_req; | |
607 | uint8_t lun; | |
608 | ||
609 | pvscsi_req = g_malloc0(sizeof(*pvscsi_req)); | |
610 | pvscsi_req->dev = s; | |
611 | pvscsi_req->req = *descr; | |
612 | pvscsi_req->cmp.context = pvscsi_req->req.context; | |
613 | QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next); | |
614 | ||
615 | *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun); | |
616 | if (*d) { | |
617 | pvscsi_req->lun = lun; | |
618 | } | |
619 | ||
620 | return pvscsi_req; | |
621 | } | |
622 | ||
623 | static void | |
624 | pvscsi_convert_sglist(PVSCSIRequest *r) | |
625 | { | |
626 | int chunk_size; | |
627 | uint64_t data_length = r->req.dataLen; | |
628 | PVSCSISGState sg = r->sg; | |
629 | while (data_length) { | |
630 | while (!sg.resid) { | |
631 | pvscsi_get_next_sg_elem(&sg); | |
632 | trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr, | |
633 | r->sg.resid); | |
634 | } | |
635 | assert(data_length > 0); | |
636 | chunk_size = MIN((unsigned) data_length, sg.resid); | |
637 | if (chunk_size) { | |
638 | qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size); | |
639 | } | |
640 | ||
641 | sg.dataAddr += chunk_size; | |
642 | data_length -= chunk_size; | |
643 | sg.resid -= chunk_size; | |
644 | } | |
645 | } | |
646 | ||
647 | static void | |
648 | pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r) | |
649 | { | |
650 | PCIDevice *d = PCI_DEVICE(s); | |
651 | ||
df32fd1c | 652 | pci_dma_sglist_init(&r->sgl, d, 1); |
881d588a DF |
653 | if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { |
654 | pvscsi_convert_sglist(r); | |
655 | } else { | |
656 | qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen); | |
657 | } | |
658 | } | |
659 | ||
660 | static void | |
661 | pvscsi_process_request_descriptor(PVSCSIState *s, | |
662 | struct PVSCSIRingReqDesc *descr) | |
663 | { | |
664 | SCSIDevice *d; | |
665 | PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr); | |
666 | int64_t n; | |
667 | ||
668 | trace_pvscsi_process_req_descr(descr->cdb[0], descr->context); | |
669 | ||
670 | if (!d) { | |
671 | r->cmp.hostStatus = BTSTAT_SELTIMEO; | |
672 | trace_pvscsi_process_req_descr_unknown_device(); | |
673 | pvscsi_complete_request(s, r); | |
674 | return; | |
675 | } | |
676 | ||
677 | if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { | |
678 | r->sg.elemAddr = descr->dataAddr; | |
679 | } | |
680 | ||
681 | r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r); | |
682 | if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV && | |
683 | (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) { | |
684 | r->cmp.hostStatus = BTSTAT_BADMSG; | |
685 | trace_pvscsi_process_req_descr_invalid_dir(); | |
686 | scsi_req_cancel(r->sreq); | |
687 | return; | |
688 | } | |
689 | if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV && | |
690 | (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) { | |
691 | r->cmp.hostStatus = BTSTAT_BADMSG; | |
692 | trace_pvscsi_process_req_descr_invalid_dir(); | |
693 | scsi_req_cancel(r->sreq); | |
694 | return; | |
695 | } | |
696 | ||
697 | pvscsi_build_sglist(s, r); | |
698 | n = scsi_req_enqueue(r->sreq); | |
699 | ||
700 | if (n) { | |
701 | scsi_req_continue(r->sreq); | |
702 | } | |
703 | } | |
704 | ||
705 | static void | |
706 | pvscsi_process_io(PVSCSIState *s) | |
707 | { | |
708 | PVSCSIRingReqDesc descr; | |
709 | hwaddr next_descr_pa; | |
710 | ||
711 | assert(s->rings_info_valid); | |
712 | while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) { | |
713 | ||
714 | /* Only read after production index verification */ | |
715 | smp_rmb(); | |
716 | ||
717 | trace_pvscsi_process_io(next_descr_pa); | |
718 | cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr)); | |
719 | pvscsi_process_request_descriptor(s, &descr); | |
720 | } | |
721 | ||
722 | pvscsi_ring_flush_req(&s->rings); | |
723 | } | |
724 | ||
725 | static void | |
726 | pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc) | |
727 | { | |
728 | int i; | |
729 | trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN); | |
730 | ||
731 | trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages); | |
732 | for (i = 0; i < rc->reqRingNumPages; i++) { | |
733 | trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]); | |
734 | } | |
735 | ||
736 | trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages); | |
737 | for (i = 0; i < rc->cmpRingNumPages; i++) { | |
738 | trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->reqRingPPNs[i]); | |
739 | } | |
740 | } | |
741 | ||
742 | static uint64_t | |
743 | pvscsi_on_cmd_config(PVSCSIState *s) | |
744 | { | |
745 | trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG"); | |
746 | return PVSCSI_COMMAND_PROCESSING_FAILED; | |
747 | } | |
748 | ||
749 | static uint64_t | |
750 | pvscsi_on_cmd_unplug(PVSCSIState *s) | |
751 | { | |
752 | trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG"); | |
753 | return PVSCSI_COMMAND_PROCESSING_FAILED; | |
754 | } | |
755 | ||
756 | static uint64_t | |
757 | pvscsi_on_issue_scsi(PVSCSIState *s) | |
758 | { | |
759 | trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI"); | |
760 | return PVSCSI_COMMAND_PROCESSING_FAILED; | |
761 | } | |
762 | ||
763 | static uint64_t | |
764 | pvscsi_on_cmd_setup_rings(PVSCSIState *s) | |
765 | { | |
766 | PVSCSICmdDescSetupRings *rc = | |
767 | (PVSCSICmdDescSetupRings *) s->curr_cmd_data; | |
768 | ||
769 | trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS"); | |
770 | ||
771 | pvscsi_dbg_dump_tx_rings_config(rc); | |
772 | pvscsi_ring_init_data(&s->rings, rc); | |
773 | s->rings_info_valid = TRUE; | |
774 | return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; | |
775 | } | |
776 | ||
777 | static uint64_t | |
778 | pvscsi_on_cmd_abort(PVSCSIState *s) | |
779 | { | |
780 | PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data; | |
781 | PVSCSIRequest *r, *next; | |
782 | ||
783 | trace_pvscsi_on_cmd_abort(cmd->context, cmd->target); | |
784 | ||
785 | QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) { | |
786 | if (r->req.context == cmd->context) { | |
787 | break; | |
788 | } | |
789 | } | |
790 | if (r) { | |
791 | assert(!r->completed); | |
792 | r->cmp.hostStatus = BTSTAT_ABORTQUEUE; | |
793 | scsi_req_cancel(r->sreq); | |
794 | } | |
795 | ||
796 | return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; | |
797 | } | |
798 | ||
799 | static uint64_t | |
800 | pvscsi_on_cmd_unknown(PVSCSIState *s) | |
801 | { | |
802 | trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]); | |
803 | return PVSCSI_COMMAND_PROCESSING_FAILED; | |
804 | } | |
805 | ||
806 | static uint64_t | |
807 | pvscsi_on_cmd_reset_device(PVSCSIState *s) | |
808 | { | |
809 | uint8_t target_lun = 0; | |
810 | struct PVSCSICmdDescResetDevice *cmd = | |
811 | (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data; | |
812 | SCSIDevice *sdev; | |
813 | ||
814 | sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun); | |
815 | ||
816 | trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev); | |
817 | ||
818 | if (sdev != NULL) { | |
819 | s->resetting++; | |
820 | device_reset(&sdev->qdev); | |
821 | s->resetting--; | |
822 | return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; | |
823 | } | |
824 | ||
825 | return PVSCSI_COMMAND_PROCESSING_FAILED; | |
826 | } | |
827 | ||
828 | static uint64_t | |
829 | pvscsi_on_cmd_reset_bus(PVSCSIState *s) | |
830 | { | |
831 | trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS"); | |
832 | ||
833 | s->resetting++; | |
834 | qbus_reset_all_fn(&s->bus); | |
835 | s->resetting--; | |
836 | return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; | |
837 | } | |
838 | ||
839 | static uint64_t | |
840 | pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s) | |
841 | { | |
842 | PVSCSICmdDescSetupMsgRing *rc = | |
843 | (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data; | |
844 | ||
845 | trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING"); | |
846 | ||
847 | if (!s->use_msg) { | |
848 | return PVSCSI_COMMAND_PROCESSING_FAILED; | |
849 | } | |
850 | ||
851 | if (s->rings_info_valid) { | |
852 | pvscsi_ring_init_msg(&s->rings, rc); | |
853 | s->msg_ring_info_valid = TRUE; | |
854 | } | |
855 | return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t); | |
856 | } | |
857 | ||
858 | static uint64_t | |
859 | pvscsi_on_cmd_adapter_reset(PVSCSIState *s) | |
860 | { | |
861 | trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET"); | |
862 | ||
863 | pvscsi_reset_adapter(s); | |
864 | return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; | |
865 | } | |
866 | ||
867 | static const struct { | |
868 | int data_size; | |
869 | uint64_t (*handler_fn)(PVSCSIState *s); | |
870 | } pvscsi_commands[] = { | |
871 | [PVSCSI_CMD_FIRST] = { | |
872 | .data_size = 0, | |
873 | .handler_fn = pvscsi_on_cmd_unknown, | |
874 | }, | |
875 | ||
876 | /* Not implemented, data size defined based on what arrives on windows */ | |
877 | [PVSCSI_CMD_CONFIG] = { | |
878 | .data_size = 6 * sizeof(uint32_t), | |
879 | .handler_fn = pvscsi_on_cmd_config, | |
880 | }, | |
881 | ||
882 | /* Command not implemented, data size is unknown */ | |
883 | [PVSCSI_CMD_ISSUE_SCSI] = { | |
884 | .data_size = 0, | |
885 | .handler_fn = pvscsi_on_issue_scsi, | |
886 | }, | |
887 | ||
888 | /* Command not implemented, data size is unknown */ | |
889 | [PVSCSI_CMD_DEVICE_UNPLUG] = { | |
890 | .data_size = 0, | |
891 | .handler_fn = pvscsi_on_cmd_unplug, | |
892 | }, | |
893 | ||
894 | [PVSCSI_CMD_SETUP_RINGS] = { | |
895 | .data_size = sizeof(PVSCSICmdDescSetupRings), | |
896 | .handler_fn = pvscsi_on_cmd_setup_rings, | |
897 | }, | |
898 | ||
899 | [PVSCSI_CMD_RESET_DEVICE] = { | |
900 | .data_size = sizeof(struct PVSCSICmdDescResetDevice), | |
901 | .handler_fn = pvscsi_on_cmd_reset_device, | |
902 | }, | |
903 | ||
904 | [PVSCSI_CMD_RESET_BUS] = { | |
905 | .data_size = 0, | |
906 | .handler_fn = pvscsi_on_cmd_reset_bus, | |
907 | }, | |
908 | ||
909 | [PVSCSI_CMD_SETUP_MSG_RING] = { | |
910 | .data_size = sizeof(PVSCSICmdDescSetupMsgRing), | |
911 | .handler_fn = pvscsi_on_cmd_setup_msg_ring, | |
912 | }, | |
913 | ||
914 | [PVSCSI_CMD_ADAPTER_RESET] = { | |
915 | .data_size = 0, | |
916 | .handler_fn = pvscsi_on_cmd_adapter_reset, | |
917 | }, | |
918 | ||
919 | [PVSCSI_CMD_ABORT_CMD] = { | |
920 | .data_size = sizeof(struct PVSCSICmdDescAbortCmd), | |
921 | .handler_fn = pvscsi_on_cmd_abort, | |
922 | }, | |
923 | }; | |
924 | ||
925 | static void | |
926 | pvscsi_do_command_processing(PVSCSIState *s) | |
927 | { | |
928 | size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); | |
929 | ||
930 | assert(s->curr_cmd < PVSCSI_CMD_LAST); | |
931 | if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) { | |
932 | s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s); | |
933 | s->curr_cmd = PVSCSI_CMD_FIRST; | |
934 | s->curr_cmd_data_cntr = 0; | |
935 | } | |
936 | } | |
937 | ||
938 | static void | |
939 | pvscsi_on_command_data(PVSCSIState *s, uint32_t value) | |
940 | { | |
941 | size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); | |
942 | ||
943 | assert(bytes_arrived < sizeof(s->curr_cmd_data)); | |
944 | s->curr_cmd_data[s->curr_cmd_data_cntr++] = value; | |
945 | ||
946 | pvscsi_do_command_processing(s); | |
947 | } | |
948 | ||
949 | static void | |
950 | pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id) | |
951 | { | |
952 | if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) { | |
953 | s->curr_cmd = cmd_id; | |
954 | } else { | |
955 | s->curr_cmd = PVSCSI_CMD_FIRST; | |
956 | trace_pvscsi_on_cmd_unknown(cmd_id); | |
957 | } | |
958 | ||
959 | s->curr_cmd_data_cntr = 0; | |
960 | s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA; | |
961 | ||
962 | pvscsi_do_command_processing(s); | |
963 | } | |
964 | ||
965 | static void | |
966 | pvscsi_io_write(void *opaque, hwaddr addr, | |
967 | uint64_t val, unsigned size) | |
968 | { | |
969 | PVSCSIState *s = opaque; | |
970 | ||
971 | switch (addr) { | |
972 | case PVSCSI_REG_OFFSET_COMMAND: | |
973 | pvscsi_on_command(s, val); | |
974 | break; | |
975 | ||
976 | case PVSCSI_REG_OFFSET_COMMAND_DATA: | |
977 | pvscsi_on_command_data(s, (uint32_t) val); | |
978 | break; | |
979 | ||
980 | case PVSCSI_REG_OFFSET_INTR_STATUS: | |
981 | trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val); | |
982 | s->reg_interrupt_status &= ~val; | |
983 | pvscsi_update_irq_status(s); | |
984 | pvscsi_schedule_completion_processing(s); | |
985 | break; | |
986 | ||
987 | case PVSCSI_REG_OFFSET_INTR_MASK: | |
988 | trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val); | |
989 | s->reg_interrupt_enabled = val; | |
990 | pvscsi_update_irq_status(s); | |
991 | break; | |
992 | ||
993 | case PVSCSI_REG_OFFSET_KICK_NON_RW_IO: | |
994 | trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val); | |
995 | pvscsi_process_io(s); | |
996 | break; | |
997 | ||
998 | case PVSCSI_REG_OFFSET_KICK_RW_IO: | |
999 | trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val); | |
1000 | pvscsi_process_io(s); | |
1001 | break; | |
1002 | ||
1003 | case PVSCSI_REG_OFFSET_DEBUG: | |
1004 | trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val); | |
1005 | break; | |
1006 | ||
1007 | default: | |
1008 | trace_pvscsi_io_write_unknown(addr, size, val); | |
1009 | break; | |
1010 | } | |
1011 | ||
1012 | } | |
1013 | ||
1014 | static uint64_t | |
1015 | pvscsi_io_read(void *opaque, hwaddr addr, unsigned size) | |
1016 | { | |
1017 | PVSCSIState *s = opaque; | |
1018 | ||
1019 | switch (addr) { | |
1020 | case PVSCSI_REG_OFFSET_INTR_STATUS: | |
1021 | trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS", | |
1022 | s->reg_interrupt_status); | |
1023 | return s->reg_interrupt_status; | |
1024 | ||
1025 | case PVSCSI_REG_OFFSET_INTR_MASK: | |
1026 | trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK", | |
1027 | s->reg_interrupt_status); | |
1028 | return s->reg_interrupt_enabled; | |
1029 | ||
1030 | case PVSCSI_REG_OFFSET_COMMAND_STATUS: | |
1031 | trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS", | |
1032 | s->reg_interrupt_status); | |
1033 | return s->reg_command_status; | |
1034 | ||
1035 | default: | |
1036 | trace_pvscsi_io_read_unknown(addr, size); | |
1037 | return 0; | |
1038 | } | |
1039 | } | |
1040 | ||
1041 | ||
1042 | static bool | |
1043 | pvscsi_init_msi(PVSCSIState *s) | |
1044 | { | |
1045 | int res; | |
1046 | PCIDevice *d = PCI_DEVICE(s); | |
1047 | ||
836fc48c | 1048 | res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS, |
881d588a DF |
1049 | PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK); |
1050 | if (res < 0) { | |
1051 | trace_pvscsi_init_msi_fail(res); | |
1052 | s->msi_used = false; | |
1053 | } else { | |
1054 | s->msi_used = true; | |
1055 | } | |
1056 | ||
1057 | return s->msi_used; | |
1058 | } | |
1059 | ||
1060 | static void | |
1061 | pvscsi_cleanup_msi(PVSCSIState *s) | |
1062 | { | |
1063 | PCIDevice *d = PCI_DEVICE(s); | |
1064 | ||
1065 | if (s->msi_used) { | |
1066 | msi_uninit(d); | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | static const MemoryRegionOps pvscsi_ops = { | |
1071 | .read = pvscsi_io_read, | |
1072 | .write = pvscsi_io_write, | |
1073 | .endianness = DEVICE_LITTLE_ENDIAN, | |
1074 | .impl = { | |
1075 | .min_access_size = 4, | |
1076 | .max_access_size = 4, | |
1077 | }, | |
1078 | }; | |
1079 | ||
1080 | static const struct SCSIBusInfo pvscsi_scsi_info = { | |
1081 | .tcq = true, | |
1082 | .max_target = PVSCSI_MAX_DEVS, | |
1083 | .max_channel = 0, | |
1084 | .max_lun = 0, | |
1085 | ||
1086 | .get_sg_list = pvscsi_get_sg_list, | |
1087 | .complete = pvscsi_command_complete, | |
1088 | .cancel = pvscsi_request_cancelled, | |
881d588a DF |
1089 | }; |
1090 | ||
1091 | static int | |
1092 | pvscsi_init(PCIDevice *pci_dev) | |
1093 | { | |
1094 | PVSCSIState *s = PVSCSI(pci_dev); | |
1095 | ||
1096 | trace_pvscsi_state("init"); | |
1097 | ||
d29d4ff8 SL |
1098 | /* PCI subsystem ID, subsystem vendor ID, revision */ |
1099 | if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) { | |
1100 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000); | |
1101 | } else { | |
1102 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, | |
1103 | PCI_VENDOR_ID_VMWARE); | |
1104 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, | |
1105 | PCI_DEVICE_ID_VMWARE_PVSCSI); | |
1106 | pci_config_set_revision(pci_dev->config, 0x2); | |
1107 | } | |
881d588a DF |
1108 | |
1109 | /* PCI latency timer = 255 */ | |
1110 | pci_dev->config[PCI_LATENCY_TIMER] = 0xff; | |
1111 | ||
1112 | /* Interrupt pin A */ | |
1113 | pci_config_set_interrupt_pin(pci_dev->config, 1); | |
1114 | ||
29776739 | 1115 | memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s, |
881d588a DF |
1116 | "pvscsi-io", PVSCSI_MEM_SPACE_SIZE); |
1117 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space); | |
1118 | ||
1119 | pvscsi_init_msi(s); | |
1120 | ||
1dd1305e SL |
1121 | if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) { |
1122 | pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET); | |
1123 | } | |
1124 | ||
881d588a DF |
1125 | s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s); |
1126 | if (!s->completion_worker) { | |
1127 | pvscsi_cleanup_msi(s); | |
881d588a DF |
1128 | return -ENOMEM; |
1129 | } | |
1130 | ||
b1187b51 AF |
1131 | scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev), |
1132 | &pvscsi_scsi_info, NULL); | |
91c8daad IM |
1133 | /* override default SCSI bus hotplug-handler, with pvscsi's one */ |
1134 | qbus_set_hotplug_handler(BUS(&s->bus), DEVICE(s), &error_abort); | |
881d588a DF |
1135 | pvscsi_reset_state(s); |
1136 | ||
1137 | return 0; | |
1138 | } | |
1139 | ||
1140 | static void | |
1141 | pvscsi_uninit(PCIDevice *pci_dev) | |
1142 | { | |
1143 | PVSCSIState *s = PVSCSI(pci_dev); | |
1144 | ||
1145 | trace_pvscsi_state("uninit"); | |
1146 | qemu_bh_delete(s->completion_worker); | |
1147 | ||
1148 | pvscsi_cleanup_msi(s); | |
881d588a DF |
1149 | } |
1150 | ||
1151 | static void | |
1152 | pvscsi_reset(DeviceState *dev) | |
1153 | { | |
1154 | PCIDevice *d = PCI_DEVICE(dev); | |
1155 | PVSCSIState *s = PVSCSI(d); | |
1156 | ||
1157 | trace_pvscsi_state("reset"); | |
1158 | pvscsi_reset_adapter(s); | |
1159 | } | |
1160 | ||
1161 | static void | |
1162 | pvscsi_pre_save(void *opaque) | |
1163 | { | |
1164 | PVSCSIState *s = (PVSCSIState *) opaque; | |
1165 | ||
1166 | trace_pvscsi_state("presave"); | |
1167 | ||
1168 | assert(QTAILQ_EMPTY(&s->pending_queue)); | |
1169 | assert(QTAILQ_EMPTY(&s->completion_queue)); | |
1170 | } | |
1171 | ||
1172 | static int | |
1173 | pvscsi_post_load(void *opaque, int version_id) | |
1174 | { | |
1175 | trace_pvscsi_state("postload"); | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1dd1305e SL |
1179 | static bool pvscsi_vmstate_need_pcie_device(void *opaque) |
1180 | { | |
1181 | PVSCSIState *s = PVSCSI(opaque); | |
1182 | ||
1183 | return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE); | |
1184 | } | |
1185 | ||
1186 | static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id) | |
1187 | { | |
1188 | return !pvscsi_vmstate_need_pcie_device(opaque); | |
1189 | } | |
1190 | ||
1191 | static const VMStateDescription vmstate_pvscsi_pcie_device = { | |
1192 | .name = "pvscsi/pcie", | |
1193 | .needed = pvscsi_vmstate_need_pcie_device, | |
1194 | .fields = (VMStateField[]) { | |
1195 | VMSTATE_PCIE_DEVICE(parent_obj, PVSCSIState), | |
1196 | VMSTATE_END_OF_LIST() | |
1197 | } | |
1198 | }; | |
1199 | ||
881d588a | 1200 | static const VMStateDescription vmstate_pvscsi = { |
6783ecf1 | 1201 | .name = "pvscsi", |
881d588a DF |
1202 | .version_id = 0, |
1203 | .minimum_version_id = 0, | |
881d588a DF |
1204 | .pre_save = pvscsi_pre_save, |
1205 | .post_load = pvscsi_post_load, | |
d49805ae | 1206 | .fields = (VMStateField[]) { |
1dd1305e SL |
1207 | VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState, |
1208 | pvscsi_vmstate_test_pci_device, 0, | |
1209 | vmstate_pci_device, PCIDevice), | |
881d588a DF |
1210 | VMSTATE_UINT8(msi_used, PVSCSIState), |
1211 | VMSTATE_UINT32(resetting, PVSCSIState), | |
1212 | VMSTATE_UINT64(reg_interrupt_status, PVSCSIState), | |
1213 | VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState), | |
1214 | VMSTATE_UINT64(reg_command_status, PVSCSIState), | |
1215 | VMSTATE_UINT64(curr_cmd, PVSCSIState), | |
1216 | VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState), | |
1217 | VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState, | |
1218 | ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)), | |
1219 | VMSTATE_UINT8(rings_info_valid, PVSCSIState), | |
1220 | VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState), | |
1221 | VMSTATE_UINT8(use_msg, PVSCSIState), | |
1222 | ||
1223 | VMSTATE_UINT64(rings.rs_pa, PVSCSIState), | |
1224 | VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState), | |
1225 | VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState), | |
1226 | VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState, | |
1227 | PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), | |
1228 | VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState, | |
1229 | PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), | |
1230 | VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState), | |
1231 | VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState), | |
1232 | ||
1233 | VMSTATE_END_OF_LIST() | |
1dd1305e SL |
1234 | }, |
1235 | .subsections = (const VMStateDescription*[]) { | |
1236 | &vmstate_pvscsi_pcie_device, | |
1237 | NULL | |
881d588a DF |
1238 | } |
1239 | }; | |
1240 | ||
881d588a DF |
1241 | static Property pvscsi_properties[] = { |
1242 | DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1), | |
952970ba SL |
1243 | DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags, |
1244 | PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false), | |
d5da3ef2 SL |
1245 | DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags, |
1246 | PVSCSI_COMPAT_DISABLE_PCIE_BIT, false), | |
881d588a DF |
1247 | DEFINE_PROP_END_OF_LIST(), |
1248 | }; | |
1249 | ||
1dd1305e SL |
1250 | static void pvscsi_realize(DeviceState *qdev, Error **errp) |
1251 | { | |
1252 | PVSCSIClass *pvs_c = PVSCSI_DEVICE_GET_CLASS(qdev); | |
1253 | PCIDevice *pci_dev = PCI_DEVICE(qdev); | |
1254 | PVSCSIState *s = PVSCSI(qdev); | |
1255 | ||
1256 | if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) { | |
1257 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; | |
1258 | } | |
1259 | ||
1260 | pvs_c->parent_dc_realize(qdev, errp); | |
1261 | } | |
1262 | ||
881d588a DF |
1263 | static void pvscsi_class_init(ObjectClass *klass, void *data) |
1264 | { | |
1265 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1266 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
1dd1305e | 1267 | PVSCSIClass *pvs_k = PVSCSI_DEVICE_CLASS(klass); |
91c8daad | 1268 | HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); |
881d588a DF |
1269 | |
1270 | k->init = pvscsi_init; | |
1271 | k->exit = pvscsi_uninit; | |
1272 | k->vendor_id = PCI_VENDOR_ID_VMWARE; | |
1273 | k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI; | |
1274 | k->class_id = PCI_CLASS_STORAGE_SCSI; | |
1275 | k->subsystem_id = 0x1000; | |
1dd1305e SL |
1276 | pvs_k->parent_dc_realize = dc->realize; |
1277 | dc->realize = pvscsi_realize; | |
881d588a DF |
1278 | dc->reset = pvscsi_reset; |
1279 | dc->vmsd = &vmstate_pvscsi; | |
1280 | dc->props = pvscsi_properties; | |
125ee0ed | 1281 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
91c8daad IM |
1282 | hc->unplug = pvscsi_hot_unplug; |
1283 | hc->plug = pvscsi_hotplug; | |
881d588a DF |
1284 | } |
1285 | ||
1286 | static const TypeInfo pvscsi_info = { | |
6783ecf1 | 1287 | .name = TYPE_PVSCSI, |
881d588a | 1288 | .parent = TYPE_PCI_DEVICE, |
e2d4f3f7 | 1289 | .class_size = sizeof(PVSCSIClass), |
881d588a DF |
1290 | .instance_size = sizeof(PVSCSIState), |
1291 | .class_init = pvscsi_class_init, | |
91c8daad IM |
1292 | .interfaces = (InterfaceInfo[]) { |
1293 | { TYPE_HOTPLUG_HANDLER }, | |
1294 | { } | |
1295 | } | |
881d588a DF |
1296 | }; |
1297 | ||
1298 | static void | |
1299 | pvscsi_register_types(void) | |
1300 | { | |
1301 | type_register_static(&pvscsi_info); | |
1302 | } | |
1303 | ||
1304 | type_init(pvscsi_register_types); |