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b4e37d98 MW |
1 | /* |
2 | * QEMU model of the Milkymist SD Card Controller. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * | |
20 | * Specification available at: | |
6dbbe243 | 21 | * http://milkymist.walle.cc/socdoc/memcard.pdf |
b4e37d98 MW |
22 | */ |
23 | ||
ea99dde1 | 24 | #include "qemu/osdep.h" |
d9f98aab | 25 | #include "qemu/log.h" |
0b8fa32f | 26 | #include "qemu/module.h" |
83c9f4ca | 27 | #include "hw/sysbus.h" |
d6454270 | 28 | #include "migration/vmstate.h" |
b4e37d98 | 29 | #include "trace.h" |
222ee196 | 30 | #include "qapi/error.h" |
fa1d36df | 31 | #include "sysemu/block-backend.h" |
9c17d615 | 32 | #include "sysemu/blockdev.h" |
a27bd6c7 | 33 | #include "hw/qdev-properties.h" |
e3382ef0 | 34 | #include "hw/sd/sd.h" |
b4e37d98 MW |
35 | |
36 | enum { | |
37 | ENABLE_CMD_TX = (1<<0), | |
38 | ENABLE_CMD_RX = (1<<1), | |
39 | ENABLE_DAT_TX = (1<<2), | |
40 | ENABLE_DAT_RX = (1<<3), | |
41 | }; | |
42 | ||
43 | enum { | |
44 | PENDING_CMD_TX = (1<<0), | |
45 | PENDING_CMD_RX = (1<<1), | |
46 | PENDING_DAT_TX = (1<<2), | |
47 | PENDING_DAT_RX = (1<<3), | |
48 | }; | |
49 | ||
50 | enum { | |
51 | START_CMD_TX = (1<<0), | |
52 | START_DAT_RX = (1<<1), | |
53 | }; | |
54 | ||
55 | enum { | |
56 | R_CLK2XDIV = 0, | |
57 | R_ENABLE, | |
58 | R_PENDING, | |
59 | R_START, | |
60 | R_CMD, | |
61 | R_DAT, | |
62 | R_MAX | |
63 | }; | |
64 | ||
7a239e46 AF |
65 | #define TYPE_MILKYMIST_MEMCARD "milkymist-memcard" |
66 | #define MILKYMIST_MEMCARD(obj) \ | |
67 | OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD) | |
68 | ||
a8c73ca2 PMD |
69 | #define TYPE_MILKYMIST_SDBUS "milkymist-sdbus" |
70 | ||
b4e37d98 | 71 | struct MilkymistMemcardState { |
7a239e46 AF |
72 | SysBusDevice parent_obj; |
73 | ||
8c85d15b | 74 | MemoryRegion regs_region; |
3d0369ba | 75 | SDBus sdbus; |
b4e37d98 MW |
76 | |
77 | int command_write_ptr; | |
78 | int response_read_ptr; | |
79 | int response_len; | |
80 | int ignore_next_cmd; | |
81 | int enabled; | |
82 | uint8_t command[6]; | |
83 | uint8_t response[17]; | |
84 | uint32_t regs[R_MAX]; | |
85 | }; | |
86 | typedef struct MilkymistMemcardState MilkymistMemcardState; | |
87 | ||
88 | static void update_pending_bits(MilkymistMemcardState *s) | |
89 | { | |
90 | /* transmits are instantaneous, thus tx pending bits are never set */ | |
91 | s->regs[R_PENDING] = 0; | |
92 | /* if rx is enabled the corresponding pending bits are always set */ | |
93 | if (s->regs[R_ENABLE] & ENABLE_CMD_RX) { | |
94 | s->regs[R_PENDING] |= PENDING_CMD_RX; | |
95 | } | |
96 | if (s->regs[R_ENABLE] & ENABLE_DAT_RX) { | |
97 | s->regs[R_PENDING] |= PENDING_DAT_RX; | |
98 | } | |
99 | } | |
100 | ||
101 | static void memcard_sd_command(MilkymistMemcardState *s) | |
102 | { | |
103 | SDRequest req; | |
104 | ||
105 | req.cmd = s->command[0] & 0x3f; | |
b3141c06 | 106 | req.arg = ldl_be_p(s->command + 1); |
b4e37d98 MW |
107 | req.crc = s->command[5]; |
108 | ||
109 | s->response[0] = req.cmd; | |
3d0369ba | 110 | s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1); |
b4e37d98 MW |
111 | s->response_read_ptr = 0; |
112 | ||
113 | if (s->response_len == 16) { | |
114 | /* R2 response */ | |
115 | s->response[0] = 0x3f; | |
116 | s->response_len += 1; | |
117 | } else if (s->response_len == 4) { | |
118 | /* no crc calculation, insert dummy byte */ | |
119 | s->response[5] = 0; | |
120 | s->response_len += 2; | |
121 | } | |
122 | ||
123 | if (req.cmd == 0) { | |
124 | /* next write is a dummy byte to clock the initialization of the sd | |
125 | * card */ | |
126 | s->ignore_next_cmd = 1; | |
127 | } | |
128 | } | |
129 | ||
a8170e5e | 130 | static uint64_t memcard_read(void *opaque, hwaddr addr, |
8c85d15b | 131 | unsigned size) |
b4e37d98 MW |
132 | { |
133 | MilkymistMemcardState *s = opaque; | |
134 | uint32_t r = 0; | |
135 | ||
136 | addr >>= 2; | |
137 | switch (addr) { | |
138 | case R_CMD: | |
139 | if (!s->enabled) { | |
140 | r = 0xff; | |
141 | } else { | |
142 | r = s->response[s->response_read_ptr++]; | |
143 | if (s->response_read_ptr > s->response_len) { | |
d9f98aab | 144 | qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: " |
c78d6a64 | 145 | "read more cmd bytes than available: clipping\n"); |
b4e37d98 MW |
146 | s->response_read_ptr = 0; |
147 | } | |
148 | } | |
149 | break; | |
150 | case R_DAT: | |
151 | if (!s->enabled) { | |
152 | r = 0xffffffff; | |
153 | } else { | |
154 | r = 0; | |
3d0369ba PMD |
155 | r |= sdbus_read_data(&s->sdbus) << 24; |
156 | r |= sdbus_read_data(&s->sdbus) << 16; | |
157 | r |= sdbus_read_data(&s->sdbus) << 8; | |
158 | r |= sdbus_read_data(&s->sdbus); | |
b4e37d98 MW |
159 | } |
160 | break; | |
161 | case R_CLK2XDIV: | |
162 | case R_ENABLE: | |
163 | case R_PENDING: | |
164 | case R_START: | |
165 | r = s->regs[addr]; | |
166 | break; | |
167 | ||
168 | default: | |
d9f98aab PMD |
169 | qemu_log_mask(LOG_UNIMP, "milkymist_memcard: " |
170 | "read access to unknown register 0x%" HWADDR_PRIx "\n", | |
171 | addr << 2); | |
b4e37d98 MW |
172 | break; |
173 | } | |
174 | ||
175 | trace_milkymist_memcard_memory_read(addr << 2, r); | |
176 | ||
177 | return r; | |
178 | } | |
179 | ||
a8170e5e | 180 | static void memcard_write(void *opaque, hwaddr addr, uint64_t value, |
8c85d15b | 181 | unsigned size) |
b4e37d98 MW |
182 | { |
183 | MilkymistMemcardState *s = opaque; | |
184 | ||
185 | trace_milkymist_memcard_memory_write(addr, value); | |
186 | ||
187 | addr >>= 2; | |
188 | switch (addr) { | |
189 | case R_PENDING: | |
190 | /* clear rx pending bits */ | |
191 | s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX)); | |
192 | update_pending_bits(s); | |
193 | break; | |
194 | case R_CMD: | |
195 | if (!s->enabled) { | |
196 | break; | |
197 | } | |
198 | if (s->ignore_next_cmd) { | |
199 | s->ignore_next_cmd = 0; | |
200 | break; | |
201 | } | |
202 | s->command[s->command_write_ptr] = value & 0xff; | |
203 | s->command_write_ptr = (s->command_write_ptr + 1) % 6; | |
204 | if (s->command_write_ptr == 0) { | |
205 | memcard_sd_command(s); | |
206 | } | |
207 | break; | |
208 | case R_DAT: | |
209 | if (!s->enabled) { | |
210 | break; | |
211 | } | |
39017143 PMD |
212 | sdbus_write_byte(&s->sdbus, (value >> 24) & 0xff); |
213 | sdbus_write_byte(&s->sdbus, (value >> 16) & 0xff); | |
214 | sdbus_write_byte(&s->sdbus, (value >> 8) & 0xff); | |
215 | sdbus_write_byte(&s->sdbus, value & 0xff); | |
b4e37d98 MW |
216 | break; |
217 | case R_ENABLE: | |
218 | s->regs[addr] = value; | |
219 | update_pending_bits(s); | |
220 | break; | |
221 | case R_CLK2XDIV: | |
222 | case R_START: | |
223 | s->regs[addr] = value; | |
224 | break; | |
225 | ||
226 | default: | |
d9f98aab PMD |
227 | qemu_log_mask(LOG_UNIMP, "milkymist_memcard: " |
228 | "write access to unknown register 0x%" HWADDR_PRIx " " | |
229 | "(value 0x%" PRIx64 ")\n", addr << 2, value); | |
b4e37d98 MW |
230 | break; |
231 | } | |
232 | } | |
233 | ||
8c85d15b MW |
234 | static const MemoryRegionOps memcard_mmio_ops = { |
235 | .read = memcard_read, | |
236 | .write = memcard_write, | |
237 | .valid = { | |
238 | .min_access_size = 4, | |
239 | .max_access_size = 4, | |
240 | }, | |
241 | .endianness = DEVICE_NATIVE_ENDIAN, | |
b4e37d98 MW |
242 | }; |
243 | ||
244 | static void milkymist_memcard_reset(DeviceState *d) | |
245 | { | |
7a239e46 | 246 | MilkymistMemcardState *s = MILKYMIST_MEMCARD(d); |
b4e37d98 MW |
247 | int i; |
248 | ||
249 | s->command_write_ptr = 0; | |
250 | s->response_read_ptr = 0; | |
251 | s->response_len = 0; | |
252 | ||
253 | for (i = 0; i < R_MAX; i++) { | |
254 | s->regs[i] = 0; | |
255 | } | |
256 | } | |
257 | ||
a8c73ca2 PMD |
258 | static void milkymist_memcard_set_readonly(DeviceState *dev, bool level) |
259 | { | |
260 | qemu_log_mask(LOG_UNIMP, | |
261 | "milkymist_memcard: read-only mode not supported\n"); | |
262 | } | |
263 | ||
264 | static void milkymist_memcard_set_inserted(DeviceState *dev, bool level) | |
265 | { | |
266 | MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev); | |
267 | ||
268 | s->enabled = !!level; | |
269 | } | |
270 | ||
85fd6e5d PMD |
271 | static void milkymist_memcard_init(Object *obj) |
272 | { | |
273 | MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj); | |
274 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
275 | ||
276 | memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s, | |
277 | "milkymist-memcard", R_MAX * 4); | |
278 | sysbus_init_mmio(dev, &s->regs_region); | |
ae7ba8e0 PMD |
279 | |
280 | qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, | |
281 | DEVICE(obj), "sd-bus"); | |
85fd6e5d PMD |
282 | } |
283 | ||
b4e37d98 MW |
284 | static const VMStateDescription vmstate_milkymist_memcard = { |
285 | .name = "milkymist-memcard", | |
286 | .version_id = 1, | |
287 | .minimum_version_id = 1, | |
35d08458 | 288 | .fields = (VMStateField[]) { |
b4e37d98 MW |
289 | VMSTATE_INT32(command_write_ptr, MilkymistMemcardState), |
290 | VMSTATE_INT32(response_read_ptr, MilkymistMemcardState), | |
291 | VMSTATE_INT32(response_len, MilkymistMemcardState), | |
292 | VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState), | |
293 | VMSTATE_INT32(enabled, MilkymistMemcardState), | |
294 | VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6), | |
295 | VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17), | |
296 | VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX), | |
297 | VMSTATE_END_OF_LIST() | |
298 | } | |
299 | }; | |
300 | ||
999e12bb AL |
301 | static void milkymist_memcard_class_init(ObjectClass *klass, void *data) |
302 | { | |
39bffca2 | 303 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 304 | |
39bffca2 AL |
305 | dc->reset = milkymist_memcard_reset; |
306 | dc->vmsd = &vmstate_milkymist_memcard; | |
a8c73ca2 | 307 | /* Reason: output IRQs should be wired up */ |
e90f2a8c | 308 | dc->user_creatable = false; |
999e12bb AL |
309 | } |
310 | ||
8c43a6f0 | 311 | static const TypeInfo milkymist_memcard_info = { |
7a239e46 | 312 | .name = TYPE_MILKYMIST_MEMCARD, |
39bffca2 AL |
313 | .parent = TYPE_SYS_BUS_DEVICE, |
314 | .instance_size = sizeof(MilkymistMemcardState), | |
85fd6e5d | 315 | .instance_init = milkymist_memcard_init, |
39bffca2 | 316 | .class_init = milkymist_memcard_class_init, |
b4e37d98 MW |
317 | }; |
318 | ||
a8c73ca2 PMD |
319 | static void milkymist_sdbus_class_init(ObjectClass *klass, void *data) |
320 | { | |
321 | SDBusClass *sbc = SD_BUS_CLASS(klass); | |
322 | ||
323 | sbc->set_inserted = milkymist_memcard_set_inserted; | |
324 | sbc->set_readonly = milkymist_memcard_set_readonly; | |
325 | } | |
326 | ||
327 | static const TypeInfo milkymist_sdbus_info = { | |
328 | .name = TYPE_MILKYMIST_SDBUS, | |
329 | .parent = TYPE_SD_BUS, | |
330 | .instance_size = sizeof(SDBus), | |
331 | .class_init = milkymist_sdbus_class_init, | |
332 | }; | |
333 | ||
83f7d43a | 334 | static void milkymist_memcard_register_types(void) |
b4e37d98 | 335 | { |
39bffca2 | 336 | type_register_static(&milkymist_memcard_info); |
a8c73ca2 | 337 | type_register_static(&milkymist_sdbus_info); |
b4e37d98 MW |
338 | } |
339 | ||
83f7d43a | 340 | type_init(milkymist_memcard_register_types) |