[mirror_qemu.git] / hw / sd / milkymist-memcard.c

/*
 *  QEMU model of the Milkymist SD Card Controller.
 *
 *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://milkymist.walle.cc/socdoc/memcard.pdf
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "trace.h"
#include "qapi/error.h"
#include "sysemu/block-backend.h"
#include "sysemu/blockdev.h"
#include "hw/qdev-properties.h"
#include "hw/sd/sd.h"
#include "qom/object.h"

enum {
    ENABLE_CMD_TX   = (1<<0),
    ENABLE_CMD_RX   = (1<<1),
    ENABLE_DAT_TX   = (1<<2),
    ENABLE_DAT_RX   = (1<<3),
};

enum {
    PENDING_CMD_TX   = (1<<0),
    PENDING_CMD_RX   = (1<<1),
    PENDING_DAT_TX   = (1<<2),
    PENDING_DAT_RX   = (1<<3),
};

enum {
    START_CMD_TX    = (1<<0),
    START_DAT_RX    = (1<<1),
};

enum {
    R_CLK2XDIV = 0,
    R_ENABLE,
    R_PENDING,
    R_START,
    R_CMD,
    R_DAT,
    R_MAX
};

#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
typedef struct MilkymistMemcardState MilkymistMemcardState;
#define MILKYMIST_MEMCARD(obj) \
    OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)

#define TYPE_MILKYMIST_SDBUS "milkymist-sdbus"

struct MilkymistMemcardState {
    SysBusDevice parent_obj;

    MemoryRegion regs_region;
    SDBus sdbus;

    int command_write_ptr;
    int response_read_ptr;
    int response_len;
    int ignore_next_cmd;
    int enabled;
    uint8_t command[6];
    uint8_t response[17];
    uint32_t regs[R_MAX];
};

static void update_pending_bits(MilkymistMemcardState *s)
{
    /* transmits are instantaneous, thus tx pending bits are never set */
    s->regs[R_PENDING] = 0;
    /* if rx is enabled the corresponding pending bits are always set */
    if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
        s->regs[R_PENDING] |= PENDING_CMD_RX;
    }
    if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
        s->regs[R_PENDING] |= PENDING_DAT_RX;
    }
}

static void memcard_sd_command(MilkymistMemcardState *s)
{
    SDRequest req;

    req.cmd = s->command[0] & 0x3f;
    req.arg = ldl_be_p(s->command + 1);
    req.crc = s->command[5];

    s->response[0] = req.cmd;
    s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
    s->response_read_ptr = 0;

    if (s->response_len == 16) {
        /* R2 response */
        s->response[0] = 0x3f;
        s->response_len += 1;
    } else if (s->response_len == 4) {
        /* no crc calculation, insert dummy byte */
        s->response[5] = 0;
        s->response_len += 2;
    }

    if (req.cmd == 0) {
        /* next write is a dummy byte to clock the initialization of the sd
         * card */
        s->ignore_next_cmd = 1;
    }
}

static uint64_t memcard_read(void *opaque, hwaddr addr,
                             unsigned size)
{
    MilkymistMemcardState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_CMD:
        if (!s->enabled) {
            r = 0xff;
        } else {
            r = s->response[s->response_read_ptr++];
            if (s->response_read_ptr > s->response_len) {
                qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
                              "read more cmd bytes than available: clipping\n");
                s->response_read_ptr = 0;
            }
        }
        break;
    case R_DAT:
        if (!s->enabled) {
            r = 0xffffffff;
        } else {
            sdbus_read_data(&s->sdbus, &r, sizeof(r));
            be32_to_cpus(&r);
        }
        break;
    case R_CLK2XDIV:
    case R_ENABLE:
    case R_PENDING:
    case R_START:
        r = s->regs[addr];
        break;

    default:
        qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
                      "read access to unknown register 0x%" HWADDR_PRIx "\n",
                      addr << 2);
        break;
    }

    trace_milkymist_memcard_memory_read(addr << 2, r);

    return r;
}

static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
                          unsigned size)
{
    MilkymistMemcardState *s = opaque;
    uint32_t val32;

    trace_milkymist_memcard_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_PENDING:
        /* clear rx pending bits */
        s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
        update_pending_bits(s);
        break;
    case R_CMD:
        if (!s->enabled) {
            break;
        }
        if (s->ignore_next_cmd) {
            s->ignore_next_cmd = 0;
            break;
        }
        s->command[s->command_write_ptr] = value & 0xff;
        s->command_write_ptr = (s->command_write_ptr + 1) % 6;
        if (s->command_write_ptr == 0) {
            memcard_sd_command(s);
        }
        break;
    case R_DAT:
        if (!s->enabled) {
            break;
        }
        val32 = cpu_to_be32(value);
        sdbus_write_data(&s->sdbus, &val32, sizeof(val32));
        break;
    case R_ENABLE:
        s->regs[addr] = value;
        update_pending_bits(s);
        break;
    case R_CLK2XDIV:
    case R_START:
        s->regs[addr] = value;
        break;

    default:
        qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
                      "write access to unknown register 0x%" HWADDR_PRIx " "
                      "(value 0x%" PRIx64 ")\n", addr << 2, value);
        break;
    }
}

static const MemoryRegionOps memcard_mmio_ops = {
    .read = memcard_read,
    .write = memcard_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void milkymist_memcard_reset(DeviceState *d)
{
    MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
    int i;

    s->command_write_ptr = 0;
    s->response_read_ptr = 0;
    s->response_len = 0;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }
}

static void milkymist_memcard_set_readonly(DeviceState *dev, bool level)
{
    qemu_log_mask(LOG_UNIMP,
                  "milkymist_memcard: read-only mode not supported\n");
}

static void milkymist_memcard_set_inserted(DeviceState *dev, bool level)
{
    MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);

    s->enabled = !!level;
}

static void milkymist_memcard_init(Object *obj)
{
    MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
            "milkymist-memcard", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);

    qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
                        DEVICE(obj), "sd-bus");
}

static const VMStateDescription vmstate_milkymist_memcard = {
    .name = "milkymist-memcard",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
        VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
        VMSTATE_INT32(response_len, MilkymistMemcardState),
        VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
        VMSTATE_INT32(enabled, MilkymistMemcardState),
        VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
        VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
        VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = milkymist_memcard_reset;
    dc->vmsd = &vmstate_milkymist_memcard;
    /* Reason: output IRQs should be wired up */
    dc->user_creatable = false;
}

static const TypeInfo milkymist_memcard_info = {
    .name          = TYPE_MILKYMIST_MEMCARD,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistMemcardState),
    .instance_init = milkymist_memcard_init,
    .class_init    = milkymist_memcard_class_init,
};

static void milkymist_sdbus_class_init(ObjectClass *klass, void *data)
{
    SDBusClass *sbc = SD_BUS_CLASS(klass);

    sbc->set_inserted = milkymist_memcard_set_inserted;
    sbc->set_readonly = milkymist_memcard_set_readonly;
}

static const TypeInfo milkymist_sdbus_info = {
    .name = TYPE_MILKYMIST_SDBUS,
    .parent = TYPE_SD_BUS,
    .instance_size = sizeof(SDBus),
    .class_init = milkymist_sdbus_class_init,
};

static void milkymist_memcard_register_types(void)
{
    type_register_static(&milkymist_memcard_info);
    type_register_static(&milkymist_sdbus_info);
}

type_init(milkymist_memcard_register_types)
Commit	Line	Data
b4e37d98 MW	1	/*
	2	* QEMU model of the Milkymist SD Card Controller.
	3	*
	4	* Copyright (c) 2010 Michael Walle <michael@walle.cc>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
6dbbe243	21	* http://milkymist.walle.cc/socdoc/memcard.pdf
b4e37d98 MW	22	*/
b4e37d98 MW	23
ea99dde1	24	#include "qemu/osdep.h"
d9f98aab	25	#include "qemu/log.h"
0b8fa32f	26	#include "qemu/module.h"
83c9f4ca	27	#include "hw/sysbus.h"
d6454270	28	#include "migration/vmstate.h"
b4e37d98	29	#include "trace.h"
222ee196	30	#include "qapi/error.h"
fa1d36df	31	#include "sysemu/block-backend.h"
9c17d615	32	#include "sysemu/blockdev.h"
a27bd6c7	33	#include "hw/qdev-properties.h"
e3382ef0	34	#include "hw/sd/sd.h"
db1015e9	35	#include "qom/object.h"
b4e37d98 MW	36
	37	enum {
	38	ENABLE_CMD_TX = (1<<0),
	39	ENABLE_CMD_RX = (1<<1),
	40	ENABLE_DAT_TX = (1<<2),
	41	ENABLE_DAT_RX = (1<<3),
	42	};
	43
	44	enum {
	45	PENDING_CMD_TX = (1<<0),
	46	PENDING_CMD_RX = (1<<1),
	47	PENDING_DAT_TX = (1<<2),
	48	PENDING_DAT_RX = (1<<3),
	49	};
	50
	51	enum {
	52	START_CMD_TX = (1<<0),
	53	START_DAT_RX = (1<<1),
	54	};
	55
	56	enum {
	57	R_CLK2XDIV = 0,
	58	R_ENABLE,
	59	R_PENDING,
	60	R_START,
	61	R_CMD,
	62	R_DAT,
	63	R_MAX
	64	};
	65
7a239e46	66	#define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
db1015e9	67	typedef struct MilkymistMemcardState MilkymistMemcardState;
7a239e46 AF	68	#define MILKYMIST_MEMCARD(obj) \
	69	OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
	70
a8c73ca2 PMD	71	#define TYPE_MILKYMIST_SDBUS "milkymist-sdbus"
a8c73ca2 PMD	72
b4e37d98	73	struct MilkymistMemcardState {
7a239e46 AF	74	SysBusDevice parent_obj;
7a239e46 AF	75
8c85d15b	76	MemoryRegion regs_region;
3d0369ba	77	SDBus sdbus;
b4e37d98 MW	78
	79	int command_write_ptr;
	80	int response_read_ptr;
	81	int response_len;
	82	int ignore_next_cmd;
	83	int enabled;
	84	uint8_t command[6];
	85	uint8_t response[17];
	86	uint32_t regs[R_MAX];
	87	};
b4e37d98 MW	88
	89	static void update_pending_bits(MilkymistMemcardState *s)
	90	{
	91	/* transmits are instantaneous, thus tx pending bits are never set */
	92	s->regs[R_PENDING] = 0;
	93	/* if rx is enabled the corresponding pending bits are always set */
	94	if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
	95	s->regs[R_PENDING] \|= PENDING_CMD_RX;
	96	}
	97	if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
	98	s->regs[R_PENDING] \|= PENDING_DAT_RX;
	99	}
	100	}
	101
	102	static void memcard_sd_command(MilkymistMemcardState *s)
	103	{
	104	SDRequest req;
	105
	106	req.cmd = s->command[0] & 0x3f;
b3141c06	107	req.arg = ldl_be_p(s->command + 1);
b4e37d98 MW	108	req.crc = s->command[5];
	109
	110	s->response[0] = req.cmd;
3d0369ba	111	s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
b4e37d98 MW	112	s->response_read_ptr = 0;
	113
	114	if (s->response_len == 16) {
	115	/* R2 response */
	116	s->response[0] = 0x3f;
	117	s->response_len += 1;
	118	} else if (s->response_len == 4) {
	119	/* no crc calculation, insert dummy byte */
	120	s->response[5] = 0;
	121	s->response_len += 2;
	122	}
	123
	124	if (req.cmd == 0) {
	125	/* next write is a dummy byte to clock the initialization of the sd
	126	* card */
	127	s->ignore_next_cmd = 1;
	128	}
	129	}
	130
a8170e5e	131	static uint64_t memcard_read(void *opaque, hwaddr addr,
8c85d15b	132	unsigned size)
b4e37d98 MW	133	{
	134	MilkymistMemcardState *s = opaque;
	135	uint32_t r = 0;
	136
	137	addr >>= 2;
	138	switch (addr) {
	139	case R_CMD:
	140	if (!s->enabled) {
	141	r = 0xff;
	142	} else {
	143	r = s->response[s->response_read_ptr++];
	144	if (s->response_read_ptr > s->response_len) {
d9f98aab	145	qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
c78d6a64	146	"read more cmd bytes than available: clipping\n");
b4e37d98 MW	147	s->response_read_ptr = 0;
	148	}
	149	}
	150	break;
	151	case R_DAT:
	152	if (!s->enabled) {
	153	r = 0xffffffff;
	154	} else {
618e0be1 PMD	155	sdbus_read_data(&s->sdbus, &r, sizeof(r));
618e0be1 PMD	156	be32_to_cpus(&r);
b4e37d98 MW	157	}
	158	break;
	159	case R_CLK2XDIV:
	160	case R_ENABLE:
	161	case R_PENDING:
	162	case R_START:
	163	r = s->regs[addr];
	164	break;
	165
	166	default:
d9f98aab PMD	167	qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
	168	"read access to unknown register 0x%" HWADDR_PRIx "\n",
	169	addr << 2);
b4e37d98 MW	170	break;
	171	}
	172
	173	trace_milkymist_memcard_memory_read(addr << 2, r);
	174
	175	return r;
	176	}
	177
a8170e5e	178	static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
8c85d15b	179	unsigned size)
b4e37d98 MW	180	{
b4e37d98 MW	181	MilkymistMemcardState *s = opaque;
62a21be6	182	uint32_t val32;
b4e37d98 MW	183
	184	trace_milkymist_memcard_memory_write(addr, value);
	185
	186	addr >>= 2;
	187	switch (addr) {
	188	case R_PENDING:
	189	/* clear rx pending bits */
	190	s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX \| PENDING_DAT_RX));
	191	update_pending_bits(s);
	192	break;
	193	case R_CMD:
	194	if (!s->enabled) {
	195	break;
	196	}
	197	if (s->ignore_next_cmd) {
	198	s->ignore_next_cmd = 0;
	199	break;
	200	}
	201	s->command[s->command_write_ptr] = value & 0xff;
	202	s->command_write_ptr = (s->command_write_ptr + 1) % 6;
	203	if (s->command_write_ptr == 0) {
	204	memcard_sd_command(s);
	205	}
	206	break;
	207	case R_DAT:
	208	if (!s->enabled) {
	209	break;
	210	}
62a21be6 PMD	211	val32 = cpu_to_be32(value);
62a21be6 PMD	212	sdbus_write_data(&s->sdbus, &val32, sizeof(val32));
b4e37d98 MW	213	break;
	214	case R_ENABLE:
	215	s->regs[addr] = value;
	216	update_pending_bits(s);
	217	break;
	218	case R_CLK2XDIV:
	219	case R_START:
	220	s->regs[addr] = value;
	221	break;
	222
	223	default:
d9f98aab PMD	224	qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
	225	"write access to unknown register 0x%" HWADDR_PRIx " "
	226	"(value 0x%" PRIx64 ")\n", addr << 2, value);
b4e37d98 MW	227	break;
	228	}
	229	}
	230
8c85d15b MW	231	static const MemoryRegionOps memcard_mmio_ops = {
	232	.read = memcard_read,
	233	.write = memcard_write,
	234	.valid = {
	235	.min_access_size = 4,
	236	.max_access_size = 4,
	237	},
	238	.endianness = DEVICE_NATIVE_ENDIAN,
b4e37d98 MW	239	};
	240
	241	static void milkymist_memcard_reset(DeviceState *d)
	242	{
7a239e46	243	MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
b4e37d98 MW	244	int i;
	245
	246	s->command_write_ptr = 0;
	247	s->response_read_ptr = 0;
	248	s->response_len = 0;
	249
	250	for (i = 0; i < R_MAX; i++) {
	251	s->regs[i] = 0;
	252	}
	253	}
	254
a8c73ca2 PMD	255	static void milkymist_memcard_set_readonly(DeviceState *dev, bool level)
	256	{
	257	qemu_log_mask(LOG_UNIMP,
	258	"milkymist_memcard: read-only mode not supported\n");
	259	}
	260
	261	static void milkymist_memcard_set_inserted(DeviceState *dev, bool level)
	262	{
	263	MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
	264
	265	s->enabled = !!level;
	266	}
	267
85fd6e5d PMD	268	static void milkymist_memcard_init(Object *obj)
	269	{
	270	MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
	271	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
	272
	273	memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
	274	"milkymist-memcard", R_MAX * 4);
	275	sysbus_init_mmio(dev, &s->regs_region);
ae7ba8e0 PMD	276
	277	qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
	278	DEVICE(obj), "sd-bus");
85fd6e5d PMD	279	}
85fd6e5d PMD	280
b4e37d98 MW	281	static const VMStateDescription vmstate_milkymist_memcard = {
	282	.name = "milkymist-memcard",
	283	.version_id = 1,
	284	.minimum_version_id = 1,
35d08458	285	.fields = (VMStateField[]) {
b4e37d98 MW	286	VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
	287	VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
	288	VMSTATE_INT32(response_len, MilkymistMemcardState),
	289	VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
	290	VMSTATE_INT32(enabled, MilkymistMemcardState),
	291	VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
	292	VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
	293	VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
	294	VMSTATE_END_OF_LIST()
	295	}
	296	};
	297
999e12bb AL	298	static void milkymist_memcard_class_init(ObjectClass klass, void data)
999e12bb AL	299	{
39bffca2	300	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	301
39bffca2 AL	302	dc->reset = milkymist_memcard_reset;
39bffca2 AL	303	dc->vmsd = &vmstate_milkymist_memcard;
a8c73ca2	304	/* Reason: output IRQs should be wired up */
e90f2a8c	305	dc->user_creatable = false;
999e12bb AL	306	}
999e12bb AL	307
8c43a6f0	308	static const TypeInfo milkymist_memcard_info = {
7a239e46	309	.name = TYPE_MILKYMIST_MEMCARD,
39bffca2 AL	310	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	311	.instance_size = sizeof(MilkymistMemcardState),
85fd6e5d	312	.instance_init = milkymist_memcard_init,
39bffca2	313	.class_init = milkymist_memcard_class_init,
b4e37d98 MW	314	};
b4e37d98 MW	315
a8c73ca2 PMD	316	static void milkymist_sdbus_class_init(ObjectClass klass, void data)
	317	{
	318	SDBusClass *sbc = SD_BUS_CLASS(klass);
	319
	320	sbc->set_inserted = milkymist_memcard_set_inserted;
	321	sbc->set_readonly = milkymist_memcard_set_readonly;
	322	}
	323
	324	static const TypeInfo milkymist_sdbus_info = {
	325	.name = TYPE_MILKYMIST_SDBUS,
	326	.parent = TYPE_SD_BUS,
	327	.instance_size = sizeof(SDBus),
	328	.class_init = milkymist_sdbus_class_init,
	329	};
	330
83f7d43a	331	static void milkymist_memcard_register_types(void)
b4e37d98	332	{
39bffca2	333	type_register_static(&milkymist_memcard_info);
a8c73ca2	334	type_register_static(&milkymist_sdbus_info);
b4e37d98 MW	335	}
b4e37d98 MW	336
83f7d43a	337	type_init(milkymist_memcard_register_types)