[mirror_qemu.git] / hw / sd / omap_mmc.c

/*
 * OMAP on-chip MMC/SD host emulation.
 *
 * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
 *
 * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/irq.h"
#include "hw/arm/omap.h"
#include "hw/sd/sdcard_legacy.h"

struct omap_mmc_s {
    qemu_irq irq;
    qemu_irq *dma;
    qemu_irq coverswitch;
    MemoryRegion iomem;
    omap_clk clk;
    SDState *card;
    uint16_t last_cmd;
    uint16_t sdio;
    uint16_t rsp[8];
    uint32_t arg;
    int lines;
    int dw;
    int mode;
    int enable;
    int be;
    int rev;
    uint16_t status;
    uint16_t mask;
    uint8_t cto;
    uint16_t dto;
    int clkdiv;
    uint16_t fifo[32];
    int fifo_start;
    int fifo_len;
    uint16_t blen;
    uint16_t blen_counter;
    uint16_t nblk;
    uint16_t nblk_counter;
    int tx_dma;
    int rx_dma;
    int af_level;
    int ae_level;

    int ddir;
    int transfer;

    int cdet_wakeup;
    int cdet_enable;
    int cdet_state;
    qemu_irq cdet;
};

static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
{
    qemu_set_irq(s->irq, !!(s->status & s->mask));
}

static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
{
    if (!host->transfer && !host->fifo_len) {
        host->status &= 0xf3ff;
        return;
    }

    if (host->fifo_len > host->af_level && host->ddir) {
        if (host->rx_dma) {
            host->status &= 0xfbff;
            qemu_irq_raise(host->dma[1]);
        } else
            host->status |= 0x0400;
    } else {
        host->status &= 0xfbff;
        qemu_irq_lower(host->dma[1]);
    }

    if (host->fifo_len < host->ae_level && !host->ddir) {
        if (host->tx_dma) {
            host->status &= 0xf7ff;
            qemu_irq_raise(host->dma[0]);
        } else
            host->status |= 0x0800;
    } else {
        qemu_irq_lower(host->dma[0]);
        host->status &= 0xf7ff;
    }
}

typedef enum {
    sd_nore = 0,	/* no response */
    sd_r1,		/* normal response command */
    sd_r2,		/* CID, CSD registers */
    sd_r3,		/* OCR register */
    sd_r6 = 6,		/* Published RCA response */
    sd_r1b = -1,
} sd_rsp_type_t;

static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
                sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
{
    uint32_t rspstatus, mask;
    int rsplen, timeout;
    SDRequest request;
    uint8_t response[16];

    if (init && cmd == 0) {
        host->status |= 0x0001;
        return;
    }

    if (resptype == sd_r1 && busy)
        resptype = sd_r1b;

    if (type == sd_adtc) {
        host->fifo_start = 0;
        host->fifo_len = 0;
        host->transfer = 1;
        host->ddir = dir;
    } else
        host->transfer = 0;
    timeout = 0;
    mask = 0;
    rspstatus = 0;

    request.cmd = cmd;
    request.arg = host->arg;
    request.crc = 0; /* FIXME */

    rsplen = sd_do_command(host->card, &request, response);

    /* TODO: validate CRCs */
    switch (resptype) {
    case sd_nore:
        rsplen = 0;
        break;

    case sd_r1:
    case sd_r1b:
        if (rsplen < 4) {
            timeout = 1;
            break;
        }
        rsplen = 4;

        mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
                ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
                LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
                CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
                CID_CSD_OVERWRITE;
        if (host->sdio & (1 << 13))
            mask |= AKE_SEQ_ERROR;
        rspstatus = ldl_be_p(response);
        break;

    case sd_r2:
        if (rsplen < 16) {
            timeout = 1;
            break;
        }
        rsplen = 16;
        break;

    case sd_r3:
        if (rsplen < 4) {
            timeout = 1;
            break;
        }
        rsplen = 4;

        rspstatus = ldl_be_p(response);
        if (rspstatus & 0x80000000)
            host->status &= 0xe000;
        else
            host->status |= 0x1000;
        break;

    case sd_r6:
        if (rsplen < 4) {
            timeout = 1;
            break;
        }
        rsplen = 4;

        mask = 0xe000 | AKE_SEQ_ERROR;
        rspstatus = (response[2] << 8) | (response[3] << 0);
    }

    if (rspstatus & mask)
        host->status |= 0x4000;
    else
        host->status &= 0xb000;

    if (rsplen)
        for (rsplen = 0; rsplen < 8; rsplen ++)
            host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
                    (response[(rsplen << 1) | 0] << 8);

    if (timeout)
        host->status |= 0x0080;
    else if (cmd == 12)
        host->status |= 0x0005;	/* Makes it more real */
    else
        host->status |= 0x0001;
}

static void omap_mmc_transfer(struct omap_mmc_s *host)
{
    uint8_t value;

    if (!host->transfer)
        return;

    while (1) {
        if (host->ddir) {
            if (host->fifo_len > host->af_level)
                break;

            value = sd_read_byte(host->card);
            host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
            if (-- host->blen_counter) {
                value = sd_read_byte(host->card);
                host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
                        value << 8;
                host->blen_counter --;
            }

            host->fifo_len ++;
        } else {
            if (!host->fifo_len)
                break;

            value = host->fifo[host->fifo_start] & 0xff;
            sd_write_byte(host->card, value);
            if (-- host->blen_counter) {
                value = host->fifo[host->fifo_start] >> 8;
                sd_write_byte(host->card, value);
                host->blen_counter --;
            }

            host->fifo_start ++;
            host->fifo_len --;
            host->fifo_start &= 31;
        }

        if (host->blen_counter == 0) {
            host->nblk_counter --;
            host->blen_counter = host->blen;

            if (host->nblk_counter == 0) {
                host->nblk_counter = host->nblk;
                host->transfer = 0;
                host->status |= 0x0008;
                break;
            }
        }
    }
}

static void omap_mmc_update(void *opaque)
{
    struct omap_mmc_s *s = opaque;
    omap_mmc_transfer(s);
    omap_mmc_fifolevel_update(s);
    omap_mmc_interrupts_update(s);
}

static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
{
    host->status = 0;
    host->fifo_len = 0;
}

void omap_mmc_reset(struct omap_mmc_s *host)
{
    host->last_cmd = 0;
    memset(host->rsp, 0, sizeof(host->rsp));
    host->arg = 0;
    host->dw = 0;
    host->mode = 0;
    host->enable = 0;
    host->mask = 0;
    host->cto = 0;
    host->dto = 0;
    host->blen = 0;
    host->blen_counter = 0;
    host->nblk = 0;
    host->nblk_counter = 0;
    host->tx_dma = 0;
    host->rx_dma = 0;
    host->ae_level = 0x00;
    host->af_level = 0x1f;
    host->transfer = 0;
    host->cdet_wakeup = 0;
    host->cdet_enable = 0;
    qemu_set_irq(host->coverswitch, host->cdet_state);
    host->clkdiv = 0;

    omap_mmc_pseudo_reset(host);

    /* Since we're still using the legacy SD API the card is not plugged
     * into any bus, and we must reset it manually. When omap_mmc is
     * QOMified this must move into the QOM reset function.
     */
    device_cold_reset(DEVICE(host->card));
}

static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size)
{
    uint16_t i;
    struct omap_mmc_s *s = opaque;

    if (size != 2) {
        return omap_badwidth_read16(opaque, offset);
    }

    switch (offset) {
    case 0x00:	/* MMC_CMD */
        return s->last_cmd;

    case 0x04:	/* MMC_ARGL */
        return s->arg & 0x0000ffff;

    case 0x08:	/* MMC_ARGH */
        return s->arg >> 16;

    case 0x0c:	/* MMC_CON */
        return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | 
                (s->be << 10) | s->clkdiv;

    case 0x10:	/* MMC_STAT */
        return s->status;

    case 0x14:	/* MMC_IE */
        return s->mask;

    case 0x18:	/* MMC_CTO */
        return s->cto;

    case 0x1c:	/* MMC_DTO */
        return s->dto;

    case 0x20:	/* MMC_DATA */
        /* TODO: support 8-bit access */
        i = s->fifo[s->fifo_start];
        if (s->fifo_len == 0) {
            printf("MMC: FIFO underrun\n");
            return i;
        }
        s->fifo_start ++;
        s->fifo_len --;
        s->fifo_start &= 31;
        omap_mmc_transfer(s);
        omap_mmc_fifolevel_update(s);
        omap_mmc_interrupts_update(s);
        return i;

    case 0x24:	/* MMC_BLEN */
        return s->blen_counter;

    case 0x28:	/* MMC_NBLK */
        return s->nblk_counter;

    case 0x2c:	/* MMC_BUF */
        return (s->rx_dma << 15) | (s->af_level << 8) |
            (s->tx_dma << 7) | s->ae_level;

    case 0x30:	/* MMC_SPI */
        return 0x0000;
    case 0x34:	/* MMC_SDIO */
        return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
    case 0x38:	/* MMC_SYST */
        return 0x0000;

    case 0x3c:	/* MMC_REV */
        return s->rev;

    case 0x40:	/* MMC_RSP0 */
    case 0x44:	/* MMC_RSP1 */
    case 0x48:	/* MMC_RSP2 */
    case 0x4c:	/* MMC_RSP3 */
    case 0x50:	/* MMC_RSP4 */
    case 0x54:	/* MMC_RSP5 */
    case 0x58:	/* MMC_RSP6 */
    case 0x5c:	/* MMC_RSP7 */
        return s->rsp[(offset - 0x40) >> 2];

    /* OMAP2-specific */
    case 0x60:	/* MMC_IOSR */
    case 0x64:	/* MMC_SYSC */
        return 0;
    case 0x68:	/* MMC_SYSS */
        return 1;						/* RSTD */
    }

    OMAP_BAD_REG(offset);
    return 0;
}

static void omap_mmc_write(void *opaque, hwaddr offset,
                           uint64_t value, unsigned size)
{
    int i;
    struct omap_mmc_s *s = opaque;

    if (size != 2) {
        omap_badwidth_write16(opaque, offset, value);
        return;
    }

    switch (offset) {
    case 0x00:	/* MMC_CMD */
        if (!s->enable)
            break;

        s->last_cmd = value;
        for (i = 0; i < 8; i ++)
            s->rsp[i] = 0x0000;
        omap_mmc_command(s, value & 63, (value >> 15) & 1,
                (sd_cmd_type_t) ((value >> 12) & 3),
                (value >> 11) & 1,
                (sd_rsp_type_t) ((value >> 8) & 7),
                (value >> 7) & 1);
        omap_mmc_update(s);
        break;

    case 0x04:	/* MMC_ARGL */
        s->arg &= 0xffff0000;
        s->arg |= 0x0000ffff & value;
        break;

    case 0x08:	/* MMC_ARGH */
        s->arg &= 0x0000ffff;
        s->arg |= value << 16;
        break;

    case 0x0c:	/* MMC_CON */
        s->dw = (value >> 15) & 1;
        s->mode = (value >> 12) & 3;
        s->enable = (value >> 11) & 1;
        s->be = (value >> 10) & 1;
        s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
        if (s->mode != 0) {
            qemu_log_mask(LOG_UNIMP,
                          "omap_mmc_wr: mode #%i unimplemented\n", s->mode);
        }
        if (s->be != 0) {
            qemu_log_mask(LOG_UNIMP,
                          "omap_mmc_wr: Big Endian not implemented\n");
        }
        if (s->dw != 0 && s->lines < 4)
            printf("4-bit SD bus enabled\n");
        if (!s->enable)
            omap_mmc_pseudo_reset(s);
        break;

    case 0x10:	/* MMC_STAT */
        s->status &= ~value;
        omap_mmc_interrupts_update(s);
        break;

    case 0x14:	/* MMC_IE */
        s->mask = value & 0x7fff;
        omap_mmc_interrupts_update(s);
        break;

    case 0x18:	/* MMC_CTO */
        s->cto = value & 0xff;
        if (s->cto > 0xfd && s->rev <= 1)
            printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
        break;

    case 0x1c:	/* MMC_DTO */
        s->dto = value & 0xffff;
        break;

    case 0x20:	/* MMC_DATA */
        /* TODO: support 8-bit access */
        if (s->fifo_len == 32)
            break;
        s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
        s->fifo_len ++;
        omap_mmc_transfer(s);
        omap_mmc_fifolevel_update(s);
        omap_mmc_interrupts_update(s);
        break;

    case 0x24:	/* MMC_BLEN */
        s->blen = (value & 0x07ff) + 1;
        s->blen_counter = s->blen;
        break;

    case 0x28:	/* MMC_NBLK */
        s->nblk = (value & 0x07ff) + 1;
        s->nblk_counter = s->nblk;
        s->blen_counter = s->blen;
        break;

    case 0x2c:	/* MMC_BUF */
        s->rx_dma = (value >> 15) & 1;
        s->af_level = (value >> 8) & 0x1f;
        s->tx_dma = (value >> 7) & 1;
        s->ae_level = value & 0x1f;

        if (s->rx_dma)
            s->status &= 0xfbff;
        if (s->tx_dma)
            s->status &= 0xf7ff;
        omap_mmc_fifolevel_update(s);
        omap_mmc_interrupts_update(s);
        break;

    /* SPI, SDIO and TEST modes unimplemented */
    case 0x30:	/* MMC_SPI (OMAP1 only) */
        break;
    case 0x34:	/* MMC_SDIO */
        s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
        s->cdet_wakeup = (value >> 9) & 1;
        s->cdet_enable = (value >> 2) & 1;
        break;
    case 0x38:	/* MMC_SYST */
        break;

    case 0x3c:	/* MMC_REV */
    case 0x40:	/* MMC_RSP0 */
    case 0x44:	/* MMC_RSP1 */
    case 0x48:	/* MMC_RSP2 */
    case 0x4c:	/* MMC_RSP3 */
    case 0x50:	/* MMC_RSP4 */
    case 0x54:	/* MMC_RSP5 */
    case 0x58:	/* MMC_RSP6 */
    case 0x5c:	/* MMC_RSP7 */
        OMAP_RO_REG(offset);
        break;

    /* OMAP2-specific */
    case 0x60:	/* MMC_IOSR */
        if (value & 0xf)
            printf("MMC: SDIO bits used!\n");
        break;
    case 0x64:	/* MMC_SYSC */
        if (value & (1 << 2))					/* SRTS */
            omap_mmc_reset(s);
        break;
    case 0x68:	/* MMC_SYSS */
        OMAP_RO_REG(offset);
        break;

    default:
        OMAP_BAD_REG(offset);
    }
}

static const MemoryRegionOps omap_mmc_ops = {
    .read = omap_mmc_read,
    .write = omap_mmc_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void omap_mmc_cover_cb(void *opaque, int line, int level)
{
    struct omap_mmc_s *host = opaque;

    if (!host->cdet_state && level) {
        host->status |= 0x0002;
        omap_mmc_interrupts_update(host);
        if (host->cdet_wakeup) {
            /* TODO: Assert wake-up */
        }
    }

    if (host->cdet_state != level) {
        qemu_set_irq(host->coverswitch, level);
        host->cdet_state = level;
    }
}

struct omap_mmc_s *omap_mmc_init(hwaddr base,
                MemoryRegion *sysmem,
                BlockBackend *blk,
                qemu_irq irq, qemu_irq dma[], omap_clk clk)
{
    struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);

    s->irq = irq;
    s->dma = dma;
    s->clk = clk;
    s->lines = 1;	/* TODO: needs to be settable per-board */
    s->rev = 1;

    memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
    memory_region_add_subregion(sysmem, base, &s->iomem);

    /* Instantiate the storage */
    s->card = sd_init(blk, false);
    if (s->card == NULL) {
        exit(1);
    }

    omap_mmc_reset(s);

    return s;
}

struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
                BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
                omap_clk fclk, omap_clk iclk)
{
    struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);

    s->irq = irq;
    s->dma = dma;
    s->clk = fclk;
    s->lines = 4;
    s->rev = 2;

    memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
                          omap_l4_region_size(ta, 0));
    omap_l4_attach(ta, 0, &s->iomem);

    /* Instantiate the storage */
    s->card = sd_init(blk, false);
    if (s->card == NULL) {
        exit(1);
    }

    s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
    sd_set_cb(s->card, NULL, s->cdet);

    omap_mmc_reset(s);

    return s;
}

void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
{
    if (s->cdet) {
        sd_set_cb(s->card, ro, s->cdet);
        s->coverswitch = cover;
        qemu_set_irq(cover, s->cdet_state);
    } else
        sd_set_cb(s->card, ro, cover);
}

void omap_mmc_enable(struct omap_mmc_s *s, int enable)
{
    sd_enable(s->card, enable);
}
Commit	Line	Data
b30bb3a2 AZ	1	/*
	2	* OMAP on-chip MMC/SD host emulation.
	3	*
7abf56ee PMD	4	* Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
7abf56ee PMD	5	*
b30bb3a2 AZ	6	* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
827df9f3 AZ	10	* published by the Free Software Foundation; either version 2 or
827df9f3 AZ	11	* (at your option) version 3 of the License.
b30bb3a2 AZ	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
fad6cb1a	18	* You should have received a copy of the GNU General Public License along
8167ee88	19	* with this program; if not, see <http://www.gnu.org/licenses/>.
b30bb3a2	20	*/
64552b6b	21
17b7f2db	22	#include "qemu/osdep.h"
25b98b96	23	#include "qemu/log.h"
64552b6b	24	#include "hw/irq.h"
0d09e41a	25	#include "hw/arm/omap.h"
9006f1e7	26	#include "hw/sd/sdcard_legacy.h"
b30bb3a2 AZ	27
b30bb3a2 AZ	28	struct omap_mmc_s {
b30bb3a2 AZ	29	qemu_irq irq;
b30bb3a2 AZ	30	qemu_irq *dma;
827df9f3	31	qemu_irq coverswitch;
c304fed7	32	MemoryRegion iomem;
b30bb3a2 AZ	33	omap_clk clk;
	34	SDState *card;
	35	uint16_t last_cmd;
	36	uint16_t sdio;
	37	uint16_t rsp[8];
	38	uint32_t arg;
827df9f3	39	int lines;
b30bb3a2 AZ	40	int dw;
	41	int mode;
	42	int enable;
827df9f3 AZ	43	int be;
827df9f3 AZ	44	int rev;
b30bb3a2 AZ	45	uint16_t status;
	46	uint16_t mask;
	47	uint8_t cto;
	48	uint16_t dto;
827df9f3	49	int clkdiv;
b30bb3a2 AZ	50	uint16_t fifo[32];
	51	int fifo_start;
	52	int fifo_len;
	53	uint16_t blen;
	54	uint16_t blen_counter;
	55	uint16_t nblk;
	56	uint16_t nblk_counter;
	57	int tx_dma;
	58	int rx_dma;
	59	int af_level;
	60	int ae_level;
	61
	62	int ddir;
	63	int transfer;
827df9f3 AZ	64
	65	int cdet_wakeup;
	66	int cdet_enable;
	67	int cdet_state;
	68	qemu_irq cdet;
b30bb3a2 AZ	69	};
	70
	71	static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
	72	{
	73	qemu_set_irq(s->irq, !!(s->status & s->mask));
	74	}
	75
	76	static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
	77	{
	78	if (!host->transfer && !host->fifo_len) {
	79	host->status &= 0xf3ff;
	80	return;
	81	}
	82
	83	if (host->fifo_len > host->af_level && host->ddir) {
	84	if (host->rx_dma) {
	85	host->status &= 0xfbff;
	86	qemu_irq_raise(host->dma[1]);
	87	} else
	88	host->status \|= 0x0400;
	89	} else {
	90	host->status &= 0xfbff;
	91	qemu_irq_lower(host->dma[1]);
	92	}
	93
	94	if (host->fifo_len < host->ae_level && !host->ddir) {
	95	if (host->tx_dma) {
	96	host->status &= 0xf7ff;
	97	qemu_irq_raise(host->dma[0]);
	98	} else
	99	host->status \|= 0x0800;
	100	} else {
	101	qemu_irq_lower(host->dma[0]);
	102	host->status &= 0xf7ff;
	103	}
	104	}
	105
	106	typedef enum {
	107	sd_nore = 0, /* no response */
	108	sd_r1, /* normal response command */
	109	sd_r2, /* CID, CSD registers */
	110	sd_r3, /* OCR register */
	111	sd_r6 = 6, /* Published RCA response */
	112	sd_r1b = -1,
c227f099	113	} sd_rsp_type_t;
b30bb3a2 AZ	114
b30bb3a2 AZ	115	static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
c227f099	116	sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
b30bb3a2 AZ	117	{
	118	uint32_t rspstatus, mask;
	119	int rsplen, timeout;
bc24a225	120	SDRequest request;
b30bb3a2 AZ	121	uint8_t response[16];
b30bb3a2 AZ	122
827df9f3 AZ	123	if (init && cmd == 0) {
	124	host->status \|= 0x0001;
	125	return;
	126	}
	127
b30bb3a2 AZ	128	if (resptype == sd_r1 && busy)
	129	resptype = sd_r1b;
	130
	131	if (type == sd_adtc) {
	132	host->fifo_start = 0;
	133	host->fifo_len = 0;
	134	host->transfer = 1;
	135	host->ddir = dir;
	136	} else
	137	host->transfer = 0;
	138	timeout = 0;
	139	mask = 0;
	140	rspstatus = 0;
	141
	142	request.cmd = cmd;
	143	request.arg = host->arg;
	144	request.crc = 0; /* FIXME */
	145
	146	rsplen = sd_do_command(host->card, &request, response);
	147
	148	/* TODO: validate CRCs */
	149	switch (resptype) {
	150	case sd_nore:
	151	rsplen = 0;
	152	break;
	153
	154	case sd_r1:
	155	case sd_r1b:
	156	if (rsplen < 4) {
	157	timeout = 1;
	158	break;
	159	}
	160	rsplen = 4;
	161
	162	mask = OUT_OF_RANGE \| ADDRESS_ERROR \| BLOCK_LEN_ERROR \|
	163	ERASE_SEQ_ERROR \| ERASE_PARAM \| WP_VIOLATION \|
	164	LOCK_UNLOCK_FAILED \| COM_CRC_ERROR \| ILLEGAL_COMMAND \|
	165	CARD_ECC_FAILED \| CC_ERROR \| SD_ERROR \|
	166	CID_CSD_OVERWRITE;
	167	if (host->sdio & (1 << 13))
	168	mask \|= AKE_SEQ_ERROR;
b3141c06	169	rspstatus = ldl_be_p(response);
b30bb3a2 AZ	170	break;
	171
	172	case sd_r2:
	173	if (rsplen < 16) {
	174	timeout = 1;
	175	break;
	176	}
	177	rsplen = 16;
	178	break;
	179
	180	case sd_r3:
	181	if (rsplen < 4) {
	182	timeout = 1;
	183	break;
	184	}
	185	rsplen = 4;
	186
b3141c06	187	rspstatus = ldl_be_p(response);
b30bb3a2 AZ	188	if (rspstatus & 0x80000000)
	189	host->status &= 0xe000;
	190	else
	191	host->status \|= 0x1000;
	192	break;
	193
	194	case sd_r6:
	195	if (rsplen < 4) {
	196	timeout = 1;
	197	break;
	198	}
	199	rsplen = 4;
	200
	201	mask = 0xe000 \| AKE_SEQ_ERROR;
	202	rspstatus = (response[2] << 8) \| (response[3] << 0);
	203	}
	204
	205	if (rspstatus & mask)
	206	host->status \|= 0x4000;
	207	else
	208	host->status &= 0xb000;
	209
	210	if (rsplen)
	211	for (rsplen = 0; rsplen < 8; rsplen ++)
	212	host->rsp[~rsplen & 7] = response[(rsplen << 1) \| 1] \|
	213	(response[(rsplen << 1) \| 0] << 8);
	214
	215	if (timeout)
	216	host->status \|= 0x0080;
	217	else if (cmd == 12)
	218	host->status \|= 0x0005; /* Makes it more real */
	219	else
	220	host->status \|= 0x0001;
	221	}
	222
	223	static void omap_mmc_transfer(struct omap_mmc_s *host)
	224	{
	225	uint8_t value;
	226
	227	if (!host->transfer)
	228	return;
	229
	230	while (1) {
	231	if (host->ddir) {
	232	if (host->fifo_len > host->af_level)
	233	break;
	234
c769a88d	235	value = sd_read_byte(host->card);
b30bb3a2 AZ	236	host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
b30bb3a2 AZ	237	if (-- host->blen_counter) {
c769a88d	238	value = sd_read_byte(host->card);
b30bb3a2 AZ	239	host->fifo[(host->fifo_start + host->fifo_len) & 31] \|=
	240	value << 8;
	241	host->blen_counter --;
	242	}
	243
	244	host->fifo_len ++;
	245	} else {
	246	if (!host->fifo_len)
	247	break;
	248
	249	value = host->fifo[host->fifo_start] & 0xff;
c769a88d	250	sd_write_byte(host->card, value);
b30bb3a2 AZ	251	if (-- host->blen_counter) {
b30bb3a2 AZ	252	value = host->fifo[host->fifo_start] >> 8;
c769a88d	253	sd_write_byte(host->card, value);
b30bb3a2 AZ	254	host->blen_counter --;
	255	}
	256
	257	host->fifo_start ++;
	258	host->fifo_len --;
	259	host->fifo_start &= 31;
	260	}
	261
	262	if (host->blen_counter == 0) {
	263	host->nblk_counter --;
	264	host->blen_counter = host->blen;
	265
	266	if (host->nblk_counter == 0) {
	267	host->nblk_counter = host->nblk;
	268	host->transfer = 0;
	269	host->status \|= 0x0008;
	270	break;
	271	}
	272	}
	273	}
	274	}
	275
	276	static void omap_mmc_update(void *opaque)
	277	{
	278	struct omap_mmc_s *s = opaque;
	279	omap_mmc_transfer(s);
	280	omap_mmc_fifolevel_update(s);
	281	omap_mmc_interrupts_update(s);
	282	}
	283
7abf56ee PMD	284	static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
	285	{
	286	host->status = 0;
	287	host->fifo_len = 0;
	288	}
	289
827df9f3 AZ	290	void omap_mmc_reset(struct omap_mmc_s *host)
	291	{
	292	host->last_cmd = 0;
	293	memset(host->rsp, 0, sizeof(host->rsp));
	294	host->arg = 0;
	295	host->dw = 0;
	296	host->mode = 0;
	297	host->enable = 0;
827df9f3 AZ	298	host->mask = 0;
	299	host->cto = 0;
	300	host->dto = 0;
827df9f3 AZ	301	host->blen = 0;
	302	host->blen_counter = 0;
	303	host->nblk = 0;
	304	host->nblk_counter = 0;
	305	host->tx_dma = 0;
	306	host->rx_dma = 0;
	307	host->ae_level = 0x00;
	308	host->af_level = 0x1f;
	309	host->transfer = 0;
	310	host->cdet_wakeup = 0;
	311	host->cdet_enable = 0;
	312	qemu_set_irq(host->coverswitch, host->cdet_state);
	313	host->clkdiv = 0;
ecd219f7	314
7abf56ee PMD	315	omap_mmc_pseudo_reset(host);
7abf56ee PMD	316
ecd219f7 PM	317	/* Since we're still using the legacy SD API the card is not plugged
	318	* into any bus, and we must reset it manually. When omap_mmc is
	319	* QOMified this must move into the QOM reset function.
	320	*/
f16a3bf8	321	device_cold_reset(DEVICE(host->card));
827df9f3 AZ	322	}
827df9f3 AZ	323
a75ed3c4	324	static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size)
b30bb3a2 AZ	325	{
b30bb3a2 AZ	326	uint16_t i;
a75ed3c4	327	struct omap_mmc_s *s = opaque;
c304fed7 AK	328
	329	if (size != 2) {
	330	return omap_badwidth_read16(opaque, offset);
	331	}
b30bb3a2 AZ	332
	333	switch (offset) {
	334	case 0x00: /* MMC_CMD */
	335	return s->last_cmd;
	336
	337	case 0x04: /* MMC_ARGL */
	338	return s->arg & 0x0000ffff;
	339
	340	case 0x08: /* MMC_ARGH */
	341	return s->arg >> 16;
	342
	343	case 0x0c: /* MMC_CON */
827df9f3 AZ	344	return (s->dw << 15) \| (s->mode << 12) \| (s->enable << 11) \|
827df9f3 AZ	345	(s->be << 10) \| s->clkdiv;
b30bb3a2 AZ	346
	347	case 0x10: /* MMC_STAT */
	348	return s->status;
	349
	350	case 0x14: /* MMC_IE */
	351	return s->mask;
	352
	353	case 0x18: /* MMC_CTO */
	354	return s->cto;
	355
	356	case 0x1c: /* MMC_DTO */
	357	return s->dto;
	358
	359	case 0x20: /* MMC_DATA */
	360	/* TODO: support 8-bit access */
	361	i = s->fifo[s->fifo_start];
	362	if (s->fifo_len == 0) {
	363	printf("MMC: FIFO underrun\n");
	364	return i;
	365	}
	366	s->fifo_start ++;
	367	s->fifo_len --;
	368	s->fifo_start &= 31;
	369	omap_mmc_transfer(s);
	370	omap_mmc_fifolevel_update(s);
	371	omap_mmc_interrupts_update(s);
	372	return i;
	373
	374	case 0x24: /* MMC_BLEN */
	375	return s->blen_counter;
	376
	377	case 0x28: /* MMC_NBLK */
	378	return s->nblk_counter;
	379
	380	case 0x2c: /* MMC_BUF */
	381	return (s->rx_dma << 15) \| (s->af_level << 8) \|
	382	(s->tx_dma << 7) \| s->ae_level;
	383
	384	case 0x30: /* MMC_SPI */
	385	return 0x0000;
	386	case 0x34: /* MMC_SDIO */
827df9f3	387	return (s->cdet_wakeup << 2) \| (s->cdet_enable) \| s->sdio;
b30bb3a2 AZ	388	case 0x38: /* MMC_SYST */
	389	return 0x0000;
	390
	391	case 0x3c: /* MMC_REV */
827df9f3	392	return s->rev;
b30bb3a2 AZ	393
	394	case 0x40: /* MMC_RSP0 */
	395	case 0x44: /* MMC_RSP1 */
	396	case 0x48: /* MMC_RSP2 */
	397	case 0x4c: /* MMC_RSP3 */
	398	case 0x50: /* MMC_RSP4 */
	399	case 0x54: /* MMC_RSP5 */
	400	case 0x58: /* MMC_RSP6 */
	401	case 0x5c: /* MMC_RSP7 */
	402	return s->rsp[(offset - 0x40) >> 2];
827df9f3 AZ	403
	404	/* OMAP2-specific */
	405	case 0x60: /* MMC_IOSR */
	406	case 0x64: /* MMC_SYSC */
	407	return 0;
	408	case 0x68: /* MMC_SYSS */
	409	return 1; /* RSTD */
b30bb3a2 AZ	410	}
	411
	412	OMAP_BAD_REG(offset);
	413	return 0;
	414	}
	415
a8170e5e	416	static void omap_mmc_write(void *opaque, hwaddr offset,
c304fed7	417	uint64_t value, unsigned size)
b30bb3a2 AZ	418	{
b30bb3a2 AZ	419	int i;
a75ed3c4	420	struct omap_mmc_s *s = opaque;
c304fed7 AK	421
c304fed7 AK	422	if (size != 2) {
77a8257e SW	423	omap_badwidth_write16(opaque, offset, value);
77a8257e SW	424	return;
c304fed7	425	}
b30bb3a2 AZ	426
	427	switch (offset) {
	428	case 0x00: /* MMC_CMD */
	429	if (!s->enable)
	430	break;
	431
	432	s->last_cmd = value;
	433	for (i = 0; i < 8; i ++)
	434	s->rsp[i] = 0x0000;
	435	omap_mmc_command(s, value & 63, (value >> 15) & 1,
c227f099	436	(sd_cmd_type_t) ((value >> 12) & 3),
b30bb3a2	437	(value >> 11) & 1,
c227f099	438	(sd_rsp_type_t) ((value >> 8) & 7),
b30bb3a2 AZ	439	(value >> 7) & 1);
	440	omap_mmc_update(s);
	441	break;
	442
	443	case 0x04: /* MMC_ARGL */
	444	s->arg &= 0xffff0000;
	445	s->arg \|= 0x0000ffff & value;
	446	break;
	447
	448	case 0x08: /* MMC_ARGH */
	449	s->arg &= 0x0000ffff;
	450	s->arg \|= value << 16;
	451	break;
	452
	453	case 0x0c: /* MMC_CON */
	454	s->dw = (value >> 15) & 1;
	455	s->mode = (value >> 12) & 3;
	456	s->enable = (value >> 11) & 1;
827df9f3 AZ	457	s->be = (value >> 10) & 1;
827df9f3 AZ	458	s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
25b98b96 PMD	459	if (s->mode != 0) {
	460	qemu_log_mask(LOG_UNIMP,
	461	"omap_mmc_wr: mode #%i unimplemented\n", s->mode);
	462	}
	463	if (s->be != 0) {
	464	qemu_log_mask(LOG_UNIMP,
	465	"omap_mmc_wr: Big Endian not implemented\n");
	466	}
827df9f3	467	if (s->dw != 0 && s->lines < 4)
b30bb3a2	468	printf("4-bit SD bus enabled\n");
827df9f3	469	if (!s->enable)
7abf56ee	470	omap_mmc_pseudo_reset(s);
b30bb3a2 AZ	471	break;
	472
	473	case 0x10: /* MMC_STAT */
	474	s->status &= ~value;
	475	omap_mmc_interrupts_update(s);
	476	break;
	477
	478	case 0x14: /* MMC_IE */
827df9f3	479	s->mask = value & 0x7fff;
b30bb3a2 AZ	480	omap_mmc_interrupts_update(s);
	481	break;
	482
	483	case 0x18: /* MMC_CTO */
	484	s->cto = value & 0xff;
827df9f3	485	if (s->cto > 0xfd && s->rev <= 1)
b30bb3a2 AZ	486	printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
	487	break;
	488
	489	case 0x1c: /* MMC_DTO */
	490	s->dto = value & 0xffff;
	491	break;
	492
	493	case 0x20: /* MMC_DATA */
	494	/* TODO: support 8-bit access */
	495	if (s->fifo_len == 32)
	496	break;
	497	s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
	498	s->fifo_len ++;
	499	omap_mmc_transfer(s);
	500	omap_mmc_fifolevel_update(s);
	501	omap_mmc_interrupts_update(s);
	502	break;
	503
	504	case 0x24: /* MMC_BLEN */
	505	s->blen = (value & 0x07ff) + 1;
	506	s->blen_counter = s->blen;
	507	break;
	508
	509	case 0x28: /* MMC_NBLK */
	510	s->nblk = (value & 0x07ff) + 1;
	511	s->nblk_counter = s->nblk;
	512	s->blen_counter = s->blen;
	513	break;
	514
	515	case 0x2c: /* MMC_BUF */
	516	s->rx_dma = (value >> 15) & 1;
	517	s->af_level = (value >> 8) & 0x1f;
	518	s->tx_dma = (value >> 7) & 1;
	519	s->ae_level = value & 0x1f;
	520
	521	if (s->rx_dma)
	522	s->status &= 0xfbff;
	523	if (s->tx_dma)
	524	s->status &= 0xf7ff;
	525	omap_mmc_fifolevel_update(s);
	526	omap_mmc_interrupts_update(s);
	527	break;
	528
	529	/* SPI, SDIO and TEST modes unimplemented */
827df9f3	530	case 0x30: /* MMC_SPI (OMAP1 only) */
b30bb3a2 AZ	531	break;
b30bb3a2 AZ	532	case 0x34: /* MMC_SDIO */
827df9f3 AZ	533	s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
	534	s->cdet_wakeup = (value >> 9) & 1;
	535	s->cdet_enable = (value >> 2) & 1;
b30bb3a2 AZ	536	break;
	537	case 0x38: /* MMC_SYST */
	538	break;
	539
	540	case 0x3c: /* MMC_REV */
	541	case 0x40: /* MMC_RSP0 */
	542	case 0x44: /* MMC_RSP1 */
	543	case 0x48: /* MMC_RSP2 */
	544	case 0x4c: /* MMC_RSP3 */
	545	case 0x50: /* MMC_RSP4 */
	546	case 0x54: /* MMC_RSP5 */
	547	case 0x58: /* MMC_RSP6 */
	548	case 0x5c: /* MMC_RSP7 */
	549	OMAP_RO_REG(offset);
	550	break;
	551
827df9f3 AZ	552	/* OMAP2-specific */
	553	case 0x60: /* MMC_IOSR */
	554	if (value & 0xf)
	555	printf("MMC: SDIO bits used!\n");
	556	break;
	557	case 0x64: /* MMC_SYSC */
	558	if (value & (1 << 2)) /* SRTS */
	559	omap_mmc_reset(s);
	560	break;
	561	case 0x68: /* MMC_SYSS */
	562	OMAP_RO_REG(offset);
	563	break;
	564
b30bb3a2 AZ	565	default:
	566	OMAP_BAD_REG(offset);
	567	}
	568	}
	569
c304fed7 AK	570	static const MemoryRegionOps omap_mmc_ops = {
	571	.read = omap_mmc_read,
	572	.write = omap_mmc_write,
	573	.endianness = DEVICE_NATIVE_ENDIAN,
b30bb3a2 AZ	574	};
b30bb3a2 AZ	575
827df9f3	576	static void omap_mmc_cover_cb(void *opaque, int line, int level)
b30bb3a2	577	{
a75ed3c4	578	struct omap_mmc_s *host = opaque;
827df9f3 AZ	579
	580	if (!host->cdet_state && level) {
	581	host->status \|= 0x0002;
	582	omap_mmc_interrupts_update(host);
3ffd710e BS	583	if (host->cdet_wakeup) {
	584	/* TODO: Assert wake-up */
	585	}
827df9f3 AZ	586	}
	587
	588	if (host->cdet_state != level) {
	589	qemu_set_irq(host->coverswitch, level);
	590	host->cdet_state = level;
	591	}
b30bb3a2 AZ	592	}
b30bb3a2 AZ	593
a8170e5e	594	struct omap_mmc_s *omap_mmc_init(hwaddr base,
c304fed7	595	MemoryRegion *sysmem,
4be74634	596	BlockBackend *blk,
b30bb3a2 AZ	597	qemu_irq irq, qemu_irq dma[], omap_clk clk)
b30bb3a2 AZ	598	{
b45c03f5	599	struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
b30bb3a2 AZ	600
b30bb3a2 AZ	601	s->irq = irq;
b30bb3a2 AZ	602	s->dma = dma;
b30bb3a2 AZ	603	s->clk = clk;
827df9f3 AZ	604	s->lines = 1; /* TODO: needs to be settable per-board */
	605	s->rev = 1;
	606
2c9b15ca	607	memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
c304fed7	608	memory_region_add_subregion(sysmem, base, &s->iomem);
b30bb3a2 AZ	609
b30bb3a2 AZ	610	/* Instantiate the storage */
4be74634	611	s->card = sd_init(blk, false);
4f8a066b KW	612	if (s->card == NULL) {
	613	exit(1);
	614	}
b30bb3a2	615
ecd219f7 PM	616	omap_mmc_reset(s);
ecd219f7 PM	617
b30bb3a2 AZ	618	return s;
	619	}
	620
827df9f3	621	struct omap_mmc_s omap2_mmc_init(struct omap_target_agent_s ta,
4be74634	622	BlockBackend *blk, qemu_irq irq, qemu_irq dma[],
827df9f3 AZ	623	omap_clk fclk, omap_clk iclk)
827df9f3 AZ	624	{
b45c03f5	625	struct omap_mmc_s *s = g_new0(struct omap_mmc_s, 1);
827df9f3 AZ	626
	627	s->irq = irq;
	628	s->dma = dma;
	629	s->clk = fclk;
	630	s->lines = 4;
	631	s->rev = 2;
	632
2c9b15ca	633	memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
c304fed7	634	omap_l4_region_size(ta, 0));
f44336c5	635	omap_l4_attach(ta, 0, &s->iomem);
827df9f3 AZ	636
827df9f3 AZ	637	/* Instantiate the storage */
4be74634	638	s->card = sd_init(blk, false);
4f8a066b KW	639	if (s->card == NULL) {
	640	exit(1);
	641	}
827df9f3	642
f3c7d038	643	s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
b9d38e95	644	sd_set_cb(s->card, NULL, s->cdet);
827df9f3	645
ecd219f7 PM	646	omap_mmc_reset(s);
ecd219f7 PM	647
827df9f3 AZ	648	return s;
	649	}
	650
8e129e07 AZ	651	void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
8e129e07 AZ	652	{
827df9f3 AZ	653	if (s->cdet) {
	654	sd_set_cb(s->card, ro, s->cdet);
	655	s->coverswitch = cover;
	656	qemu_set_irq(cover, s->cdet_state);
	657	} else
	658	sd_set_cb(s->card, ro, cover);
	659	}
	660
	661	void omap_mmc_enable(struct omap_mmc_s *s, int enable)
	662	{
	663	sd_enable(s->card, enable);
8e129e07	664	}