[mirror_qemu.git] / hw / sd / pxa2xx_mmci.c

/*
 * Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GPLv2.
 *
 * Contributions after 2012-01-13 are licensed under the terms of the
 * GNU GPL, version 2 or (at your option) any later version.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sysbus.h"
#include "hw/arm/pxa.h"
#include "hw/sd/sd.h"
#include "hw/qdev.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"

#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)

#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
#define PXA2XX_MMCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_PXA2XX_MMCI_BUS)

struct PXA2xxMMCIState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq rx_dma;
    qemu_irq tx_dma;
    qemu_irq inserted;
    qemu_irq readonly;

    BlockBackend *blk;
    SDBus sdbus;

    uint32_t status;
    uint32_t clkrt;
    uint32_t spi;
    uint32_t cmdat;
    uint32_t resp_tout;
    uint32_t read_tout;
    int blklen;
    int numblk;
    uint32_t intmask;
    uint32_t intreq;
    int cmd;
    uint32_t arg;

    int active;
    int bytesleft;
    uint8_t tx_fifo[64];
    int tx_start;
    int tx_len;
    uint8_t rx_fifo[32];
    int rx_start;
    int rx_len;
    uint16_t resp_fifo[9];
    int resp_len;

    int cmdreq;
};

#define MMC_STRPCL	0x00	/* MMC Clock Start/Stop register */
#define MMC_STAT	0x04	/* MMC Status register */
#define MMC_CLKRT	0x08	/* MMC Clock Rate register */
#define MMC_SPI		0x0c	/* MMC SPI Mode register */
#define MMC_CMDAT	0x10	/* MMC Command/Data register */
#define MMC_RESTO	0x14	/* MMC Response Time-Out register */
#define MMC_RDTO	0x18	/* MMC Read Time-Out register */
#define MMC_BLKLEN	0x1c	/* MMC Block Length register */
#define MMC_NUMBLK	0x20	/* MMC Number of Blocks register */
#define MMC_PRTBUF	0x24	/* MMC Buffer Partly Full register */
#define MMC_I_MASK	0x28	/* MMC Interrupt Mask register */
#define MMC_I_REG	0x2c	/* MMC Interrupt Request register */
#define MMC_CMD		0x30	/* MMC Command register */
#define MMC_ARGH	0x34	/* MMC Argument High register */
#define MMC_ARGL	0x38	/* MMC Argument Low register */
#define MMC_RES		0x3c	/* MMC Response FIFO */
#define MMC_RXFIFO	0x40	/* MMC Receive FIFO */
#define MMC_TXFIFO	0x44	/* MMC Transmit FIFO */
#define MMC_RDWAIT	0x48	/* MMC RD_WAIT register */
#define MMC_BLKS_REM	0x4c	/* MMC Blocks Remaining register */

/* Bitfield masks */
#define STRPCL_STOP_CLK	(1 << 0)
#define STRPCL_STRT_CLK	(1 << 1)
#define STAT_TOUT_RES	(1 << 1)
#define STAT_CLK_EN	(1 << 8)
#define STAT_DATA_DONE	(1 << 11)
#define STAT_PRG_DONE	(1 << 12)
#define STAT_END_CMDRES	(1 << 13)
#define SPI_SPI_MODE	(1 << 0)
#define CMDAT_RES_TYPE	(3 << 0)
#define CMDAT_DATA_EN	(1 << 2)
#define CMDAT_WR_RD	(1 << 3)
#define CMDAT_DMA_EN	(1 << 7)
#define CMDAT_STOP_TRAN	(1 << 10)
#define INT_DATA_DONE	(1 << 0)
#define INT_PRG_DONE	(1 << 1)
#define INT_END_CMD	(1 << 2)
#define INT_STOP_CMD	(1 << 3)
#define INT_CLK_OFF	(1 << 4)
#define INT_RXFIFO_REQ	(1 << 5)
#define INT_TXFIFO_REQ	(1 << 6)
#define INT_TINT	(1 << 7)
#define INT_DAT_ERR	(1 << 8)
#define INT_RES_ERR	(1 << 9)
#define INT_RD_STALLED	(1 << 10)
#define INT_SDIO_INT	(1 << 11)
#define INT_SDIO_SACK	(1 << 12)
#define PRTBUF_PRT_BUF	(1 << 0)

/* Route internal interrupt lines to the global IC and DMA */
static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
{
    uint32_t mask = s->intmask;
    if (s->cmdat & CMDAT_DMA_EN) {
        mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;

        qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
        qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
    }

    qemu_set_irq(s->irq, !!(s->intreq & ~mask));
}

static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
{
    if (!s->active)
        return;

    if (s->cmdat & CMDAT_WR_RD) {
        while (s->bytesleft && s->tx_len) {
            sdbus_write_data(&s->sdbus, s->tx_fifo[s->tx_start++]);
            s->tx_start &= 0x1f;
            s->tx_len --;
            s->bytesleft --;
        }
        if (s->bytesleft)
            s->intreq |= INT_TXFIFO_REQ;
    } else
        while (s->bytesleft && s->rx_len < 32) {
            s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
                sdbus_read_data(&s->sdbus);
            s->bytesleft --;
            s->intreq |= INT_RXFIFO_REQ;
        }

    if (!s->bytesleft) {
        s->active = 0;
        s->intreq |= INT_DATA_DONE;
        s->status |= STAT_DATA_DONE;

        if (s->cmdat & CMDAT_WR_RD) {
            s->intreq |= INT_PRG_DONE;
            s->status |= STAT_PRG_DONE;
        }
    }

    pxa2xx_mmci_int_update(s);
}

static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
{
    int rsplen, i;
    SDRequest request;
    uint8_t response[16];

    s->active = 1;
    s->rx_len = 0;
    s->tx_len = 0;
    s->cmdreq = 0;

    request.cmd = s->cmd;
    request.arg = s->arg;
    request.crc = 0;	/* FIXME */

    rsplen = sdbus_do_command(&s->sdbus, &request, response);
    s->intreq |= INT_END_CMD;

    memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
    switch (s->cmdat & CMDAT_RES_TYPE) {
#define PXAMMCI_RESP(wd, value0, value1)	\
        s->resp_fifo[(wd) + 0] |= (value0);	\
        s->resp_fifo[(wd) + 1] |= (value1) << 8;
    case 0:	/* No response */
        goto complete;

    case 1:	/* R1, R4, R5 or R6 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    case 2:	/* R2 */
        if (rsplen < 16)
            goto timeout;
        goto complete;

    case 3:	/* R3 */
        if (rsplen < 4)
            goto timeout;
        goto complete;

    complete:
        for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
            PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
        }
        s->status |= STAT_END_CMDRES;

        if (!(s->cmdat & CMDAT_DATA_EN))
            s->active = 0;
        else
            s->bytesleft = s->numblk * s->blklen;

        s->resp_len = 0;
        break;

    timeout:
        s->active = 0;
        s->status |= STAT_TOUT_RES;
        break;
    }

    pxa2xx_mmci_fifo_update(s);
}

static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    uint32_t ret;

    switch (offset) {
    case MMC_STRPCL:
        return 0;
    case MMC_STAT:
        return s->status;
    case MMC_CLKRT:
        return s->clkrt;
    case MMC_SPI:
        return s->spi;
    case MMC_CMDAT:
        return s->cmdat;
    case MMC_RESTO:
        return s->resp_tout;
    case MMC_RDTO:
        return s->read_tout;
    case MMC_BLKLEN:
        return s->blklen;
    case MMC_NUMBLK:
        return s->numblk;
    case MMC_PRTBUF:
        return 0;
    case MMC_I_MASK:
        return s->intmask;
    case MMC_I_REG:
        return s->intreq;
    case MMC_CMD:
        return s->cmd | 0x40;
    case MMC_ARGH:
        return s->arg >> 16;
    case MMC_ARGL:
        return s->arg & 0xffff;
    case MMC_RES:
        if (s->resp_len < 9)
            return s->resp_fifo[s->resp_len ++];
        return 0;
    case MMC_RXFIFO:
        ret = 0;
        while (size-- && s->rx_len) {
            ret |= s->rx_fifo[s->rx_start++] << (size << 3);
            s->rx_start &= 0x1f;
            s->rx_len --;
        }
        s->intreq &= ~INT_RXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        return ret;
    case MMC_RDWAIT:
        return 0;
    case MMC_BLKS_REM:
        return s->numblk;
    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }

    return 0;
}

static void pxa2xx_mmci_write(void *opaque,
                              hwaddr offset, uint64_t value, unsigned size)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;

    switch (offset) {
    case MMC_STRPCL:
        if (value & STRPCL_STRT_CLK) {
            s->status |= STAT_CLK_EN;
            s->intreq &= ~INT_CLK_OFF;

            if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
                s->status &= STAT_CLK_EN;
                pxa2xx_mmci_wakequeues(s);
            }
        }

        if (value & STRPCL_STOP_CLK) {
            s->status &= ~STAT_CLK_EN;
            s->intreq |= INT_CLK_OFF;
            s->active = 0;
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CLKRT:
        s->clkrt = value & 7;
        break;

    case MMC_SPI:
        s->spi = value & 0xf;
        if (value & SPI_SPI_MODE)
            printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
        break;

    case MMC_CMDAT:
        s->cmdat = value & 0x3dff;
        s->active = 0;
        s->cmdreq = 1;
        if (!(value & CMDAT_STOP_TRAN)) {
            s->status &= STAT_CLK_EN;

            if (s->status & STAT_CLK_EN)
                pxa2xx_mmci_wakequeues(s);
        }

        pxa2xx_mmci_int_update(s);
        break;

    case MMC_RESTO:
        s->resp_tout = value & 0x7f;
        break;

    case MMC_RDTO:
        s->read_tout = value & 0xffff;
        break;

    case MMC_BLKLEN:
        s->blklen = value & 0xfff;
        break;

    case MMC_NUMBLK:
        s->numblk = value & 0xffff;
        break;

    case MMC_PRTBUF:
        if (value & PRTBUF_PRT_BUF) {
            s->tx_start ^= 32;
            s->tx_len = 0;
        }
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_I_MASK:
        s->intmask = value & 0x1fff;
        pxa2xx_mmci_int_update(s);
        break;

    case MMC_CMD:
        s->cmd = value & 0x3f;
        break;

    case MMC_ARGH:
        s->arg &= 0x0000ffff;
        s->arg |= value << 16;
        break;

    case MMC_ARGL:
        s->arg &= 0xffff0000;
        s->arg |= value & 0x0000ffff;
        break;

    case MMC_TXFIFO:
        while (size-- && s->tx_len < 0x20)
            s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
                    (value >> (size << 3)) & 0xff;
        s->intreq &= ~INT_TXFIFO_REQ;
        pxa2xx_mmci_fifo_update(s);
        break;

    case MMC_RDWAIT:
    case MMC_BLKS_REM:
        break;

    default:
        hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
    }
}

static const MemoryRegionOps pxa2xx_mmci_ops = {
    .read = pxa2xx_mmci_read,
    .write = pxa2xx_mmci_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void pxa2xx_mmci_save(QEMUFile *f, void *opaque)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    int i;

    qemu_put_be32s(f, &s->status);
    qemu_put_be32s(f, &s->clkrt);
    qemu_put_be32s(f, &s->spi);
    qemu_put_be32s(f, &s->cmdat);
    qemu_put_be32s(f, &s->resp_tout);
    qemu_put_be32s(f, &s->read_tout);
    qemu_put_be32(f, s->blklen);
    qemu_put_be32(f, s->numblk);
    qemu_put_be32s(f, &s->intmask);
    qemu_put_be32s(f, &s->intreq);
    qemu_put_be32(f, s->cmd);
    qemu_put_be32s(f, &s->arg);
    qemu_put_be32(f, s->cmdreq);
    qemu_put_be32(f, s->active);
    qemu_put_be32(f, s->bytesleft);

    qemu_put_byte(f, s->tx_len);
    for (i = 0; i < s->tx_len; i ++)
        qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);

    qemu_put_byte(f, s->rx_len);
    for (i = 0; i < s->rx_len; i ++)
        qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);

    qemu_put_byte(f, s->resp_len);
    for (i = s->resp_len; i < 9; i ++)
        qemu_put_be16s(f, &s->resp_fifo[i]);
}

static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
{
    PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
    int i;

    qemu_get_be32s(f, &s->status);
    qemu_get_be32s(f, &s->clkrt);
    qemu_get_be32s(f, &s->spi);
    qemu_get_be32s(f, &s->cmdat);
    qemu_get_be32s(f, &s->resp_tout);
    qemu_get_be32s(f, &s->read_tout);
    s->blklen = qemu_get_be32(f);
    s->numblk = qemu_get_be32(f);
    qemu_get_be32s(f, &s->intmask);
    qemu_get_be32s(f, &s->intreq);
    s->cmd = qemu_get_be32(f);
    qemu_get_be32s(f, &s->arg);
    s->cmdreq = qemu_get_be32(f);
    s->active = qemu_get_be32(f);
    s->bytesleft = qemu_get_be32(f);

    s->tx_len = qemu_get_byte(f);
    s->tx_start = 0;
    if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0)
        return -EINVAL;
    for (i = 0; i < s->tx_len; i ++)
        s->tx_fifo[i] = qemu_get_byte(f);

    s->rx_len = qemu_get_byte(f);
    s->rx_start = 0;
    if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0)
        return -EINVAL;
    for (i = 0; i < s->rx_len; i ++)
        s->rx_fifo[i] = qemu_get_byte(f);

    s->resp_len = qemu_get_byte(f);
    if (s->resp_len > 9 || s->resp_len < 0)
        return -EINVAL;
    for (i = s->resp_len; i < 9; i ++)
         qemu_get_be16s(f, &s->resp_fifo[i]);

    return 0;
}

PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
                hwaddr base,
                BlockBackend *blk, qemu_irq irq,
                qemu_irq rx_dma, qemu_irq tx_dma)
{
    DeviceState *dev, *carddev;
    SysBusDevice *sbd;
    PXA2xxMMCIState *s;
    Error *err = NULL;

    dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
    s = PXA2XX_MMCI(dev);
    sbd = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(sbd, 0, base);
    sysbus_connect_irq(sbd, 0, irq);
    qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
    qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);

    /* Create and plug in the sd card */
    carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
    qdev_prop_set_drive(carddev, "drive", blk, &err);
    if (err) {
        error_report("failed to init SD card: %s", error_get_pretty(err));
        return NULL;
    }
    object_property_set_bool(OBJECT(carddev), true, "realized", &err);
    if (err) {
        error_report("failed to init SD card: %s", error_get_pretty(err));
        return NULL;
    }

    return s;
}

static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(dev);

    qemu_set_irq(s->inserted, inserted);
}

static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(dev);

    qemu_set_irq(s->readonly, readonly);
}

void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
                          qemu_irq coverswitch)
{
    DeviceState *dev = DEVICE(s);

    s->readonly = readonly;
    s->inserted = coverswitch;

    pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
    pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
}

static void pxa2xx_mmci_instance_init(Object *obj)
{
    PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    DeviceState *dev = DEVICE(obj);

    memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
                          "pxa2xx-mmci", 0x00100000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
    qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);

    register_savevm(NULL, "pxa2xx_mmci", 0, 0,
                    pxa2xx_mmci_save, pxa2xx_mmci_load, s);

    qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
                        TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
}

static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
{
    SDBusClass *sbc = SD_BUS_CLASS(klass);

    sbc->set_inserted = pxa2xx_mmci_set_inserted;
    sbc->set_readonly = pxa2xx_mmci_set_readonly;
}

static const TypeInfo pxa2xx_mmci_info = {
    .name = TYPE_PXA2XX_MMCI,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PXA2xxMMCIState),
    .instance_init = pxa2xx_mmci_instance_init,
};

static const TypeInfo pxa2xx_mmci_bus_info = {
    .name = TYPE_PXA2XX_MMCI_BUS,
    .parent = TYPE_SD_BUS,
    .instance_size = sizeof(SDBus),
    .class_init = pxa2xx_mmci_bus_class_init,
};

static void pxa2xx_mmci_register_types(void)
{
    type_register_static(&pxa2xx_mmci_info);
    type_register_static(&pxa2xx_mmci_bus_info);
}

type_init(pxa2xx_mmci_register_types)
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 MultiMediaCard/SD/SDIO Controller emulation.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
	7	* This code is licensed under the GPLv2.
6b620ca3 PB	8	*
	9	* Contributions after 2012-01-13 are licensed under the terms of the
	10	* GNU GPL, version 2 or (at your option) any later version.
a171fe39 AZ	11	*/
a171fe39 AZ	12
8ef94f0b	13	#include "qemu/osdep.h"
83c9f4ca	14	#include "hw/hw.h"
7a9468c9	15	#include "hw/sysbus.h"
0d09e41a	16	#include "hw/arm/pxa.h"
e3382ef0	17	#include "hw/sd/sd.h"
83c9f4ca	18	#include "hw/qdev.h"
7a9468c9	19	#include "hw/qdev-properties.h"
a9563e75	20	#include "qemu/error-report.h"
7a9468c9 PM	21
	22	#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
	23	#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
a171fe39	24
a9563e75 PM	25	#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
	26	#define PXA2XX_MMCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_PXA2XX_MMCI_BUS)
	27
bc24a225	28	struct PXA2xxMMCIState {
7a9468c9 PM	29	SysBusDevice parent_obj;
7a9468c9 PM	30
2bf90458	31	MemoryRegion iomem;
a171fe39	32	qemu_irq irq;
2115c019 AZ	33	qemu_irq rx_dma;
2115c019 AZ	34	qemu_irq tx_dma;
a9563e75 PM	35	qemu_irq inserted;
a9563e75 PM	36	qemu_irq readonly;
a171fe39	37
7a9468c9	38	BlockBackend *blk;
a9563e75	39	SDBus sdbus;
a171fe39 AZ	40
	41	uint32_t status;
	42	uint32_t clkrt;
	43	uint32_t spi;
	44	uint32_t cmdat;
	45	uint32_t resp_tout;
	46	uint32_t read_tout;
	47	int blklen;
	48	int numblk;
	49	uint32_t intmask;
	50	uint32_t intreq;
	51	int cmd;
	52	uint32_t arg;
	53
	54	int active;
	55	int bytesleft;
	56	uint8_t tx_fifo[64];
	57	int tx_start;
	58	int tx_len;
	59	uint8_t rx_fifo[32];
	60	int rx_start;
	61	int rx_len;
	62	uint16_t resp_fifo[9];
	63	int resp_len;
	64
	65	int cmdreq;
a171fe39 AZ	66	};
	67
	68	#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
	69	#define MMC_STAT 0x04 /* MMC Status register */
	70	#define MMC_CLKRT 0x08 /* MMC Clock Rate register */
	71	#define MMC_SPI 0x0c /* MMC SPI Mode register */
	72	#define MMC_CMDAT 0x10 /* MMC Command/Data register */
	73	#define MMC_RESTO 0x14 /* MMC Response Time-Out register */
	74	#define MMC_RDTO 0x18 /* MMC Read Time-Out register */
	75	#define MMC_BLKLEN 0x1c /* MMC Block Length register */
	76	#define MMC_NUMBLK 0x20 /* MMC Number of Blocks register */
	77	#define MMC_PRTBUF 0x24 /* MMC Buffer Partly Full register */
	78	#define MMC_I_MASK 0x28 /* MMC Interrupt Mask register */
	79	#define MMC_I_REG 0x2c /* MMC Interrupt Request register */
	80	#define MMC_CMD 0x30 /* MMC Command register */
	81	#define MMC_ARGH 0x34 /* MMC Argument High register */
	82	#define MMC_ARGL 0x38 /* MMC Argument Low register */
	83	#define MMC_RES 0x3c /* MMC Response FIFO */
	84	#define MMC_RXFIFO 0x40 /* MMC Receive FIFO */
	85	#define MMC_TXFIFO 0x44 /* MMC Transmit FIFO */
	86	#define MMC_RDWAIT 0x48 /* MMC RD_WAIT register */
	87	#define MMC_BLKS_REM 0x4c /* MMC Blocks Remaining register */
	88
	89	/* Bitfield masks */
	90	#define STRPCL_STOP_CLK (1 << 0)
	91	#define STRPCL_STRT_CLK (1 << 1)
	92	#define STAT_TOUT_RES (1 << 1)
	93	#define STAT_CLK_EN (1 << 8)
	94	#define STAT_DATA_DONE (1 << 11)
	95	#define STAT_PRG_DONE (1 << 12)
	96	#define STAT_END_CMDRES (1 << 13)
	97	#define SPI_SPI_MODE (1 << 0)
	98	#define CMDAT_RES_TYPE (3 << 0)
	99	#define CMDAT_DATA_EN (1 << 2)
	100	#define CMDAT_WR_RD (1 << 3)
	101	#define CMDAT_DMA_EN (1 << 7)
	102	#define CMDAT_STOP_TRAN (1 << 10)
	103	#define INT_DATA_DONE (1 << 0)
	104	#define INT_PRG_DONE (1 << 1)
	105	#define INT_END_CMD (1 << 2)
	106	#define INT_STOP_CMD (1 << 3)
	107	#define INT_CLK_OFF (1 << 4)
	108	#define INT_RXFIFO_REQ (1 << 5)
	109	#define INT_TXFIFO_REQ (1 << 6)
	110	#define INT_TINT (1 << 7)
	111	#define INT_DAT_ERR (1 << 8)
	112	#define INT_RES_ERR (1 << 9)
	113	#define INT_RD_STALLED (1 << 10)
	114	#define INT_SDIO_INT (1 << 11)
	115	#define INT_SDIO_SACK (1 << 12)
	116	#define PRTBUF_PRT_BUF (1 << 0)
	117
	118	/* Route internal interrupt lines to the global IC and DMA */
bc24a225	119	static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
a171fe39 AZ	120	{
	121	uint32_t mask = s->intmask;
	122	if (s->cmdat & CMDAT_DMA_EN) {
	123	mask \|= INT_RXFIFO_REQ \| INT_TXFIFO_REQ;
	124
2115c019 AZ	125	qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
2115c019 AZ	126	qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
a171fe39 AZ	127	}
	128
	129	qemu_set_irq(s->irq, !!(s->intreq & ~mask));
	130	}
	131
bc24a225	132	static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
a171fe39 AZ	133	{
	134	if (!s->active)
	135	return;
	136
	137	if (s->cmdat & CMDAT_WR_RD) {
	138	while (s->bytesleft && s->tx_len) {
a9563e75	139	sdbus_write_data(&s->sdbus, s->tx_fifo[s->tx_start++]);
a171fe39 AZ	140	s->tx_start &= 0x1f;
	141	s->tx_len --;
	142	s->bytesleft --;
	143	}
	144	if (s->bytesleft)
	145	s->intreq \|= INT_TXFIFO_REQ;
	146	} else
	147	while (s->bytesleft && s->rx_len < 32) {
	148	s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
a9563e75	149	sdbus_read_data(&s->sdbus);
a171fe39 AZ	150	s->bytesleft --;
	151	s->intreq \|= INT_RXFIFO_REQ;
	152	}
	153
	154	if (!s->bytesleft) {
	155	s->active = 0;
	156	s->intreq \|= INT_DATA_DONE;
	157	s->status \|= STAT_DATA_DONE;
	158
	159	if (s->cmdat & CMDAT_WR_RD) {
	160	s->intreq \|= INT_PRG_DONE;
	161	s->status \|= STAT_PRG_DONE;
	162	}
	163	}
	164
	165	pxa2xx_mmci_int_update(s);
	166	}
	167
bc24a225	168	static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
a171fe39 AZ	169	{
a171fe39 AZ	170	int rsplen, i;
bc24a225	171	SDRequest request;
a171fe39 AZ	172	uint8_t response[16];
	173
	174	s->active = 1;
	175	s->rx_len = 0;
	176	s->tx_len = 0;
	177	s->cmdreq = 0;
	178
	179	request.cmd = s->cmd;
	180	request.arg = s->arg;
	181	request.crc = 0; /* FIXME */
	182
a9563e75	183	rsplen = sdbus_do_command(&s->sdbus, &request, response);
a171fe39 AZ	184	s->intreq \|= INT_END_CMD;
	185
	186	memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
	187	switch (s->cmdat & CMDAT_RES_TYPE) {
	188	#define PXAMMCI_RESP(wd, value0, value1) \
	189	s->resp_fifo[(wd) + 0] \|= (value0); \
	190	s->resp_fifo[(wd) + 1] \|= (value1) << 8;
	191	case 0: /* No response */
	192	goto complete;
	193
	194	case 1: /* R1, R4, R5 or R6 */
	195	if (rsplen < 4)
	196	goto timeout;
	197	goto complete;
	198
	199	case 2: /* R2 */
	200	if (rsplen < 16)
	201	goto timeout;
	202	goto complete;
	203
	204	case 3: /* R3 */
	205	if (rsplen < 4)
	206	goto timeout;
	207	goto complete;
	208
	209	complete:
	210	for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
	211	PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
	212	}
	213	s->status \|= STAT_END_CMDRES;
	214
	215	if (!(s->cmdat & CMDAT_DATA_EN))
	216	s->active = 0;
	217	else
	218	s->bytesleft = s->numblk * s->blklen;
	219
	220	s->resp_len = 0;
	221	break;
	222
	223	timeout:
	224	s->active = 0;
	225	s->status \|= STAT_TOUT_RES;
	226	break;
	227	}
	228
	229	pxa2xx_mmci_fifo_update(s);
	230	}
	231
13e1e476	232	static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
a171fe39	233	{
bc24a225	234	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39	235	uint32_t ret;
a171fe39 AZ	236
	237	switch (offset) {
	238	case MMC_STRPCL:
	239	return 0;
	240	case MMC_STAT:
	241	return s->status;
	242	case MMC_CLKRT:
	243	return s->clkrt;
	244	case MMC_SPI:
	245	return s->spi;
	246	case MMC_CMDAT:
	247	return s->cmdat;
	248	case MMC_RESTO:
	249	return s->resp_tout;
	250	case MMC_RDTO:
	251	return s->read_tout;
	252	case MMC_BLKLEN:
	253	return s->blklen;
	254	case MMC_NUMBLK:
	255	return s->numblk;
	256	case MMC_PRTBUF:
	257	return 0;
	258	case MMC_I_MASK:
	259	return s->intmask;
	260	case MMC_I_REG:
	261	return s->intreq;
	262	case MMC_CMD:
	263	return s->cmd \| 0x40;
	264	case MMC_ARGH:
	265	return s->arg >> 16;
	266	case MMC_ARGL:
	267	return s->arg & 0xffff;
	268	case MMC_RES:
	269	if (s->resp_len < 9)
	270	return s->resp_fifo[s->resp_len ++];
	271	return 0;
	272	case MMC_RXFIFO:
	273	ret = 0;
13e1e476 PM	274	while (size-- && s->rx_len) {
13e1e476 PM	275	ret \|= s->rx_fifo[s->rx_start++] << (size << 3);
a171fe39 AZ	276	s->rx_start &= 0x1f;
	277	s->rx_len --;
	278	}
	279	s->intreq &= ~INT_RXFIFO_REQ;
	280	pxa2xx_mmci_fifo_update(s);
	281	return ret;
	282	case MMC_RDWAIT:
	283	return 0;
	284	case MMC_BLKS_REM:
	285	return s->numblk;
	286	default:
2ac71179	287	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39 AZ	288	}
	289
	290	return 0;
	291	}
	292
	293	static void pxa2xx_mmci_write(void *opaque,
13e1e476	294	hwaddr offset, uint64_t value, unsigned size)
a171fe39	295	{
bc24a225	296	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
a171fe39 AZ	297
	298	switch (offset) {
	299	case MMC_STRPCL:
	300	if (value & STRPCL_STRT_CLK) {
	301	s->status \|= STAT_CLK_EN;
	302	s->intreq &= ~INT_CLK_OFF;
	303
	304	if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
	305	s->status &= STAT_CLK_EN;
	306	pxa2xx_mmci_wakequeues(s);
	307	}
	308	}
	309
	310	if (value & STRPCL_STOP_CLK) {
	311	s->status &= ~STAT_CLK_EN;
	312	s->intreq \|= INT_CLK_OFF;
	313	s->active = 0;
	314	}
	315
	316	pxa2xx_mmci_int_update(s);
	317	break;
	318
	319	case MMC_CLKRT:
	320	s->clkrt = value & 7;
	321	break;
	322
	323	case MMC_SPI:
	324	s->spi = value & 0xf;
	325	if (value & SPI_SPI_MODE)
	326	printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
	327	break;
	328
	329	case MMC_CMDAT:
	330	s->cmdat = value & 0x3dff;
	331	s->active = 0;
	332	s->cmdreq = 1;
	333	if (!(value & CMDAT_STOP_TRAN)) {
	334	s->status &= STAT_CLK_EN;
	335
	336	if (s->status & STAT_CLK_EN)
	337	pxa2xx_mmci_wakequeues(s);
	338	}
	339
	340	pxa2xx_mmci_int_update(s);
	341	break;
	342
	343	case MMC_RESTO:
	344	s->resp_tout = value & 0x7f;
	345	break;
	346
	347	case MMC_RDTO:
	348	s->read_tout = value & 0xffff;
	349	break;
	350
	351	case MMC_BLKLEN:
	352	s->blklen = value & 0xfff;
	353	break;
	354
	355	case MMC_NUMBLK:
	356	s->numblk = value & 0xffff;
	357	break;
	358
	359	case MMC_PRTBUF:
	360	if (value & PRTBUF_PRT_BUF) {
361	s->tx_start ^= 32;
362	s->tx_len = 0;
363	}
364	pxa2xx_mmci_fifo_update(s);
365	break;
366
367	case MMC_I_MASK:
368	s->intmask = value & 0x1fff;
369	pxa2xx_mmci_int_update(s);
370	break;
371
372	case MMC_CMD:
373	s->cmd = value & 0x3f;
374	break;
375
376	case MMC_ARGH:
377	s->arg &= 0x0000ffff;
378	s->arg \|= value << 16;
379	break;
380
381	case MMC_ARGL:
382	s->arg &= 0xffff0000;
383	s->arg \|= value & 0x0000ffff;
384	break;
385
386	case MMC_TXFIFO:
13e1e476	387	while (size-- && s->tx_len < 0x20)
a171fe39	388	s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
13e1e476	389	(value >> (size << 3)) & 0xff;
a171fe39 AZ	390	s->intreq &= ~INT_TXFIFO_REQ;
	391	pxa2xx_mmci_fifo_update(s);
	392	break;
	393
	394	case MMC_RDWAIT:
	395	case MMC_BLKS_REM:
	396	break;
	397
	398	default:
2ac71179	399	hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
a171fe39 AZ	400	}
	401	}
	402
2bf90458	403	static const MemoryRegionOps pxa2xx_mmci_ops = {
13e1e476 PM	404	.read = pxa2xx_mmci_read,
13e1e476 PM	405	.write = pxa2xx_mmci_write,
2bf90458	406	.endianness = DEVICE_NATIVE_ENDIAN,
a171fe39 AZ	407	};
a171fe39 AZ	408
aa941b94 AZ	409	static void pxa2xx_mmci_save(QEMUFile f, void opaque)
aa941b94 AZ	410	{
bc24a225	411	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
aa941b94 AZ	412	int i;
	413
	414	qemu_put_be32s(f, &s->status);
	415	qemu_put_be32s(f, &s->clkrt);
	416	qemu_put_be32s(f, &s->spi);
	417	qemu_put_be32s(f, &s->cmdat);
	418	qemu_put_be32s(f, &s->resp_tout);
	419	qemu_put_be32s(f, &s->read_tout);
	420	qemu_put_be32(f, s->blklen);
	421	qemu_put_be32(f, s->numblk);
	422	qemu_put_be32s(f, &s->intmask);
	423	qemu_put_be32s(f, &s->intreq);
	424	qemu_put_be32(f, s->cmd);
	425	qemu_put_be32s(f, &s->arg);
	426	qemu_put_be32(f, s->cmdreq);
	427	qemu_put_be32(f, s->active);
	428	qemu_put_be32(f, s->bytesleft);
	429
	430	qemu_put_byte(f, s->tx_len);
	431	for (i = 0; i < s->tx_len; i ++)
	432	qemu_put_byte(f, s->tx_fifo[(s->tx_start + i) & 63]);
	433
	434	qemu_put_byte(f, s->rx_len);
	435	for (i = 0; i < s->rx_len; i ++)
	436	qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 31]);
	437
	438	qemu_put_byte(f, s->resp_len);
	439	for (i = s->resp_len; i < 9; i ++)
	440	qemu_put_be16s(f, &s->resp_fifo[i]);
	441	}
	442
	443	static int pxa2xx_mmci_load(QEMUFile f, void opaque, int version_id)
	444	{
bc24a225	445	PXA2xxMMCIState s = (PXA2xxMMCIState ) opaque;
aa941b94 AZ	446	int i;
	447
	448	qemu_get_be32s(f, &s->status);
	449	qemu_get_be32s(f, &s->clkrt);
	450	qemu_get_be32s(f, &s->spi);
	451	qemu_get_be32s(f, &s->cmdat);
	452	qemu_get_be32s(f, &s->resp_tout);
	453	qemu_get_be32s(f, &s->read_tout);
	454	s->blklen = qemu_get_be32(f);
	455	s->numblk = qemu_get_be32(f);
	456	qemu_get_be32s(f, &s->intmask);
	457	qemu_get_be32s(f, &s->intreq);
	458	s->cmd = qemu_get_be32(f);
	459	qemu_get_be32s(f, &s->arg);
	460	s->cmdreq = qemu_get_be32(f);
	461	s->active = qemu_get_be32(f);
	462	s->bytesleft = qemu_get_be32(f);
	463
	464	s->tx_len = qemu_get_byte(f);
	465	s->tx_start = 0;
	466	if (s->tx_len >= sizeof(s->tx_fifo) \|\| s->tx_len < 0)
	467	return -EINVAL;
	468	for (i = 0; i < s->tx_len; i ++)
	469	s->tx_fifo[i] = qemu_get_byte(f);
	470
	471	s->rx_len = qemu_get_byte(f);
	472	s->rx_start = 0;
	473	if (s->rx_len >= sizeof(s->rx_fifo) \|\| s->rx_len < 0)
	474	return -EINVAL;
	475	for (i = 0; i < s->rx_len; i ++)
	476	s->rx_fifo[i] = qemu_get_byte(f);
	477
	478	s->resp_len = qemu_get_byte(f);
	479	if (s->resp_len > 9 \|\| s->resp_len < 0)
	480	return -EINVAL;
	481	for (i = s->resp_len; i < 9; i ++)
	482	qemu_get_be16s(f, &s->resp_fifo[i]);
	483
	484	return 0;
	485	}
	486
2bf90458	487	PXA2xxMMCIState pxa2xx_mmci_init(MemoryRegion sysmem,
a8170e5e	488	hwaddr base,
4be74634	489	BlockBackend *blk, qemu_irq irq,
2115c019	490	qemu_irq rx_dma, qemu_irq tx_dma)
a171fe39	491	{
a9563e75	492	DeviceState dev, carddev;
7a9468c9	493	SysBusDevice *sbd;
bc24a225	494	PXA2xxMMCIState *s;
a9563e75	495	Error *err = NULL;
a171fe39	496
7a9468c9 PM	497	dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
7a9468c9 PM	498	s = PXA2XX_MMCI(dev);
7a9468c9 PM	499	sbd = SYS_BUS_DEVICE(dev);
	500	sysbus_mmio_map(sbd, 0, base);
	501	sysbus_connect_irq(sbd, 0, irq);
	502	qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
	503	qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
a9563e75 PM	504
	505	/* Create and plug in the sd card */
	506	carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
	507	qdev_prop_set_drive(carddev, "drive", blk, &err);
	508	if (err) {
	509	error_report("failed to init SD card: %s", error_get_pretty(err));
	510	return NULL;
	511	}
	512	object_property_set_bool(OBJECT(carddev), true, "realized", &err);
	513	if (err) {
	514	error_report("failed to init SD card: %s", error_get_pretty(err));
	515	return NULL;
	516	}
	517
a171fe39 AZ	518	return s;
	519	}
	520
a9563e75 PM	521	static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
	522	{
	523	PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
	524
	525	qemu_set_irq(s->inserted, inserted);
	526	}
	527
	528	static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
	529	{
	530	PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
	531
	532	qemu_set_irq(s->readonly, readonly);
	533	}
	534
bc24a225	535	void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
7a9468c9	536	qemu_irq coverswitch)
a171fe39	537	{
a9563e75 PM	538	DeviceState *dev = DEVICE(s);
	539
	540	s->readonly = readonly;
	541	s->inserted = coverswitch;
	542
	543	pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
	544	pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
a171fe39	545	}
7a9468c9 PM	546
	547	static void pxa2xx_mmci_instance_init(Object *obj)
	548	{
	549	PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
	550	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	551	DeviceState *dev = DEVICE(obj);
	552
	553	memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
	554	"pxa2xx-mmci", 0x00100000);
	555	sysbus_init_mmio(sbd, &s->iomem);
	556	sysbus_init_irq(sbd, &s->irq);
	557	qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
	558	qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
	559
	560	register_savevm(NULL, "pxa2xx_mmci", 0, 0,
	561	pxa2xx_mmci_save, pxa2xx_mmci_load, s);
a9563e75 PM	562
	563	qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
	564	TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
	565	}
	566
	567	static void pxa2xx_mmci_bus_class_init(ObjectClass klass, void data)
	568	{
	569	SDBusClass *sbc = SD_BUS_CLASS(klass);
	570
	571	sbc->set_inserted = pxa2xx_mmci_set_inserted;
	572	sbc->set_readonly = pxa2xx_mmci_set_readonly;
7a9468c9 PM	573	}
	574
	575	static const TypeInfo pxa2xx_mmci_info = {
	576	.name = TYPE_PXA2XX_MMCI,
	577	.parent = TYPE_SYS_BUS_DEVICE,
	578	.instance_size = sizeof(PXA2xxMMCIState),
	579	.instance_init = pxa2xx_mmci_instance_init,
	580	};
	581
a9563e75 PM	582	static const TypeInfo pxa2xx_mmci_bus_info = {
	583	.name = TYPE_PXA2XX_MMCI_BUS,
	584	.parent = TYPE_SD_BUS,
	585	.instance_size = sizeof(SDBus),
	586	.class_init = pxa2xx_mmci_bus_class_init,
	587	};
	588
7a9468c9 PM	589	static void pxa2xx_mmci_register_types(void)
	590	{
	591	type_register_static(&pxa2xx_mmci_info);
a9563e75	592	type_register_static(&pxa2xx_mmci_bus_info);
7a9468c9 PM	593	}
	594
	595	type_init(pxa2xx_mmci_register_types)