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0d78f544
TS
1/*
2 * Renesas SH7751R R2D-PLUS emulation
3 *
4 * Copyright (c) 2007 Magnus Damm
b319feb7 5 * Copyright (c) 2008 Paul Mundt
0d78f544
TS
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
83c9f4ca
PB
26#include "hw/sysbus.h"
27#include "hw/hw.h"
0d09e41a 28#include "hw/sh4/sh.h"
bd2be150 29#include "hw/devices.h"
9c17d615 30#include "sysemu/sysemu.h"
83c9f4ca
PB
31#include "hw/boards.h"
32#include "hw/pci/pci.h"
1422e32d 33#include "net/net.h"
47b43a1f 34#include "sh7750_regs.h"
83c9f4ca
PB
35#include "hw/ide.h"
36#include "hw/loader.h"
37#include "hw/usb.h"
0d09e41a 38#include "hw/block/flash.h"
9c17d615 39#include "sysemu/blockdev.h"
022c62cb 40#include "exec/address-spaces.h"
56839a19
AJ
41
42#define FLASH_BASE 0x00000000
43#define FLASH_SIZE 0x02000000
0d78f544
TS
44
45#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
46#define SDRAM_SIZE 0x04000000
47
ffd39257
BS
48#define SM501_VRAM_SIZE 0x800000
49
73f19035 50#define BOOT_PARAMS_OFFSET 0x0010000
e8afa065 51/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
73f19035
AJ
52#define LINUX_LOAD_OFFSET 0x0800000
53#define INITRD_LOAD_OFFSET 0x1800000
e8afa065 54
d47ede60 55#define PA_IRLMSK 0x00
b319feb7
AJ
56#define PA_POWOFF 0x30
57#define PA_VERREG 0x32
58#define PA_OUTPORT 0x36
59
60typedef struct {
b319feb7 61 uint16_t bcr;
d47ede60 62 uint16_t irlmsk;
b319feb7
AJ
63 uint16_t irlmon;
64 uint16_t cfctl;
65 uint16_t cfpow;
66 uint16_t dispctl;
67 uint16_t sdmpow;
68 uint16_t rtcce;
69 uint16_t pcicd;
70 uint16_t voyagerrts;
71 uint16_t cfrst;
72 uint16_t admrts;
73 uint16_t extrst;
74 uint16_t cfcdintclr;
75 uint16_t keyctlclr;
76 uint16_t pad0;
77 uint16_t pad1;
b319feb7
AJ
78 uint16_t verreg;
79 uint16_t inport;
80 uint16_t outport;
81 uint16_t bverreg;
d47ede60
AZ
82
83/* output pin */
84 qemu_irq irl;
5dea2efb 85 MemoryRegion iomem;
c227f099 86} r2d_fpga_t;
b319feb7 87
d47ede60
AZ
88enum r2d_fpga_irq {
89 PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
90 SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
91 NR_IRQS
92};
93
94static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
95 [CF_IDE] = { 1, 1<<9 },
96 [CF_CD] = { 2, 1<<8 },
97 [PCI_INTA] = { 9, 1<<14 },
98 [PCI_INTB] = { 10, 1<<13 },
99 [PCI_INTC] = { 3, 1<<12 },
100 [PCI_INTD] = { 0, 1<<11 },
101 [SM501] = { 4, 1<<10 },
102 [KEY] = { 5, 1<<6 },
103 [RTC_A] = { 6, 1<<5 },
104 [RTC_T] = { 7, 1<<4 },
105 [SDCARD] = { 8, 1<<7 },
106 [EXT] = { 11, 1<<0 },
107 [TP] = { 12, 1<<15 },
108};
109
c227f099 110static void update_irl(r2d_fpga_t *fpga)
d47ede60
AZ
111{
112 int i, irl = 15;
113 for (i = 0; i < NR_IRQS; i++)
114 if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
115 if (irqtab[i].irl < irl)
116 irl = irqtab[i].irl;
117 qemu_set_irq(fpga->irl, irl ^ 15);
118}
119
120static void r2d_fpga_irq_set(void *opaque, int n, int level)
121{
c227f099 122 r2d_fpga_t *fpga = opaque;
d47ede60
AZ
123 if (level)
124 fpga->irlmon |= irqtab[n].msk;
125 else
126 fpga->irlmon &= ~irqtab[n].msk;
127 update_irl(fpga);
128}
129
a8170e5e 130static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
b319feb7 131{
c227f099 132 r2d_fpga_t *s = opaque;
b319feb7 133
b319feb7 134 switch (addr) {
d47ede60
AZ
135 case PA_IRLMSK:
136 return s->irlmsk;
b319feb7
AJ
137 case PA_OUTPORT:
138 return s->outport;
139 case PA_POWOFF:
37cc0b44 140 return 0x00;
b319feb7
AJ
141 case PA_VERREG:
142 return 0x10;
143 }
144
145 return 0;
146}
147
148static void
a8170e5e 149r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
b319feb7 150{
c227f099 151 r2d_fpga_t *s = opaque;
b319feb7 152
b319feb7 153 switch (addr) {
d47ede60
AZ
154 case PA_IRLMSK:
155 s->irlmsk = value;
156 update_irl(s);
157 break;
b319feb7
AJ
158 case PA_OUTPORT:
159 s->outport = value;
160 break;
161 case PA_POWOFF:
37cc0b44
AJ
162 if (value & 1) {
163 qemu_system_shutdown_request();
164 }
165 break;
b319feb7
AJ
166 case PA_VERREG:
167 /* Discard writes */
168 break;
169 }
170}
171
5dea2efb
AK
172static const MemoryRegionOps r2d_fpga_ops = {
173 .old_mmio = {
174 .read = { r2d_fpga_read, r2d_fpga_read, NULL, },
175 .write = { r2d_fpga_write, r2d_fpga_write, NULL, },
176 },
177 .endianness = DEVICE_NATIVE_ENDIAN,
b319feb7
AJ
178};
179
5dea2efb 180static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
a8170e5e 181 hwaddr base, qemu_irq irl)
b319feb7 182{
c227f099 183 r2d_fpga_t *s;
b319feb7 184
7267c094 185 s = g_malloc0(sizeof(r2d_fpga_t));
d47ede60
AZ
186
187 s->irl = irl;
b319feb7 188
2c9b15ca 189 memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
5dea2efb 190 memory_region_add_subregion(sysmem, base, &s->iomem);
d47ede60 191 return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
b319feb7
AJ
192}
193
4f6493ff 194typedef struct ResetData {
868bac81 195 SuperHCPU *cpu;
4f6493ff
AJ
196 uint32_t vector;
197} ResetData;
198
199static void main_cpu_reset(void *opaque)
200{
201 ResetData *s = (ResetData *)opaque;
868bac81 202 CPUSH4State *env = &s->cpu->env;
4f6493ff 203
868bac81 204 cpu_reset(CPU(s->cpu));
4f6493ff
AJ
205 env->pc = s->vector;
206}
207
541dc0d4 208static struct QEMU_PACKED
73f19035
AJ
209{
210 int mount_root_rdonly;
211 int ramdisk_flags;
212 int orig_root_dev;
213 int loader_type;
214 int initrd_start;
215 int initrd_size;
216
217 char pad[232];
218
219 char kernel_cmdline[256];
220} boot_params;
221
5f072e1f 222static void r2d_init(QEMUMachineInitArgs *args)
0d78f544 223{
5f072e1f
EH
224 const char *cpu_model = args->cpu_model;
225 const char *kernel_filename = args->kernel_filename;
226 const char *kernel_cmdline = args->kernel_cmdline;
227 const char *initrd_filename = args->initrd_filename;
fd2f410b 228 SuperHCPU *cpu;
0b7ade1d 229 CPUSH4State *env;
4f6493ff 230 ResetData *reset_info;
0d78f544 231 struct SH7750State *s;
5dea2efb 232 MemoryRegion *sdram = g_new(MemoryRegion, 1);
d47ede60 233 qemu_irq *irq;
751c6a17 234 DriveInfo *dinfo;
c2f01775 235 int i;
8c106233
BC
236 DeviceState *dev;
237 SysBusDevice *busdev;
27a9d2ea 238 MemoryRegion *address_space_mem = get_system_memory();
29b358f9 239 PCIBus *pci_bus;
0d78f544 240
fd2f410b 241 if (cpu_model == NULL) {
0fd3ca30 242 cpu_model = "SH7751R";
fd2f410b 243 }
aaed909a 244
fd2f410b
AF
245 cpu = cpu_sh4_init(cpu_model);
246 if (cpu == NULL) {
aaed909a
FB
247 fprintf(stderr, "Unable to find CPU definition\n");
248 exit(1);
249 }
fd2f410b
AF
250 env = &cpu->env;
251
7267c094 252 reset_info = g_malloc0(sizeof(ResetData));
868bac81 253 reset_info->cpu = cpu;
4f6493ff
AJ
254 reset_info->vector = env->pc;
255 qemu_register_reset(main_cpu_reset, reset_info);
0d78f544
TS
256
257 /* Allocate memory space */
2c9b15ca 258 memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE);
c5705a77 259 vmstate_register_ram_global(sdram);
5dea2efb 260 memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
0d78f544 261 /* Register peripherals */
2f493fee 262 s = sh7750_init(cpu, address_space_mem);
5dea2efb 263 irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
8c106233
BC
264
265 dev = qdev_create(NULL, "sh_pci");
1356b98d 266 busdev = SYS_BUS_DEVICE(dev);
8c106233 267 qdev_init_nofail(dev);
29b358f9 268 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
8c106233
BC
269 sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
270 sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
271 sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
272 sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
273 sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
274 sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
d47ede60 275
27a9d2ea
RH
276 sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE,
277 irq[SM501], serial_hds[2]);
a4a771c0
AZ
278
279 /* onboard CF (True IDE mode, Master only). */
612b2bd0 280 dinfo = drive_get(IF_IDE, 0, 0);
6b2578d6
AF
281 dev = qdev_create(NULL, "mmio-ide");
282 busdev = SYS_BUS_DEVICE(dev);
283 sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
284 qdev_prop_set_uint32(dev, "shift", 1);
285 qdev_init_nofail(dev);
286 sysbus_mmio_map(busdev, 0, 0x14001000);
287 sysbus_mmio_map(busdev, 1, 0x1400080c);
288 mmio_ide_init_drives(dev, dinfo, NULL);
a4a771c0 289
56839a19 290 /* onboard flash memory */
45e7e4bc 291 dinfo = drive_get(IF_PFLASH, 0, 0);
cfe5f011 292 pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
612b2bd0
AJ
293 dinfo ? dinfo->bdrv : NULL, (16 * 1024),
294 FLASH_SIZE >> 16,
295 1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
01e0451a 296 0x555, 0x2aa, 0);
56839a19 297
c2f01775 298 /* NIC: rtl8139 on-board, and 2 slots. */
ab2da564 299 for (i = 0; i < nb_nics; i++)
29b358f9
DG
300 pci_nic_init_nofail(&nd_table[i], pci_bus,
301 "rtl8139", i==0 ? "2" : NULL);
c2f01775 302
9caa3ec1
AJ
303 /* USB keyboard */
304 usbdevice_create("keyboard");
305
0d78f544 306 /* Todo: register on board registers */
73f19035
AJ
307 memset(&boot_params, 0, sizeof(boot_params));
308
e8afa065 309 if (kernel_filename) {
73f19035
AJ
310 int kernel_size;
311
312 kernel_size = load_image_targphys(kernel_filename,
313 SDRAM_BASE + LINUX_LOAD_OFFSET,
314 INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
315 if (kernel_size < 0) {
316 fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
317 exit(1);
318 }
319
320 /* initialization which should be done by firmware */
321 stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
322 stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
4f6493ff 323 reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
0d78f544 324 }
73f19035
AJ
325
326 if (initrd_filename) {
327 int initrd_size;
328
329 initrd_size = load_image_targphys(initrd_filename,
330 SDRAM_BASE + INITRD_LOAD_OFFSET,
331 SDRAM_SIZE - INITRD_LOAD_OFFSET);
332
333 if (initrd_size < 0) {
334 fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
335 exit(1);
336 }
337
338 /* initialization which should be done by firmware */
339 boot_params.loader_type = 1;
340 boot_params.initrd_start = INITRD_LOAD_OFFSET;
341 boot_params.initrd_size = initrd_size;
342 }
343
344 if (kernel_cmdline) {
9310b9be
JM
345 /* I see no evidence that this .kernel_cmdline buffer requires
346 NUL-termination, so using strncpy should be ok. */
73f19035
AJ
347 strncpy(boot_params.kernel_cmdline, kernel_cmdline,
348 sizeof(boot_params.kernel_cmdline));
349 }
350
351 rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
352 SDRAM_BASE + BOOT_PARAMS_OFFSET);
0d78f544
TS
353}
354
f80f9ec9 355static QEMUMachine r2d_machine = {
4b32e168
AL
356 .name = "r2d",
357 .desc = "r2d-plus board",
358 .init = r2d_init,
0d78f544 359};
f80f9ec9
AL
360
361static void r2d_machine_init(void)
362{
363 qemu_register_machine(&r2d_machine);
364}
365
366machine_init(r2d_machine_init);